LLVM  10.0.0svn
ARCInstrInfo.h
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1 //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
15 
16 #include "ARCRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "ARCGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class ARCSubtarget;
25 
26 class ARCInstrInfo : public ARCGenInstrInfo {
27  const ARCRegisterInfo RI;
28  virtual void anchor();
29 
30 public:
31  ARCInstrInfo();
32 
33  const ARCRegisterInfo &getRegisterInfo() const { return RI; }
34 
35  /// If the specified machine instruction is a direct
36  /// load from a stack slot, return the virtual or physical register number of
37  /// the destination along with the FrameIndex of the loaded stack slot. If
38  /// not, return 0. This predicate must return 0 if the instruction has
39  /// any side effects other than loading from the stack slot.
40  unsigned isLoadFromStackSlot(const MachineInstr &MI,
41  int &FrameIndex) const override;
42 
43  /// If the specified machine instruction is a direct
44  /// store to a stack slot, return the virtual or physical register number of
45  /// the source reg along with the FrameIndex of the loaded stack slot. If
46  /// not, return 0. This predicate must return 0 if the instruction has
47  /// any side effects other than storing to the stack slot.
48  unsigned isStoreToStackSlot(const MachineInstr &MI,
49  int &FrameIndex) const override;
50 
51  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
52 
54  MachineBasicBlock *&FBB,
56  bool AllowModify) const override;
57 
60  const DebugLoc &dl,
61  int *BytesAdded = nullptr) const override;
62 
63  unsigned removeBranch(MachineBasicBlock &MBB,
64  int *BytesRemoved = nullptr) const override;
65 
67  const DebugLoc &dl, unsigned DestReg, unsigned SrcReg,
68  bool KillSrc) const override;
69 
71  MachineBasicBlock::iterator MI, unsigned SrcReg,
72  bool isKill, int FrameIndex,
73  const TargetRegisterClass *RC,
74  const TargetRegisterInfo *TRI) const override;
75 
77  MachineBasicBlock::iterator MI, unsigned DestReg,
78  int FrameIndex, const TargetRegisterClass *RC,
79  const TargetRegisterInfo *TRI) const override;
80 
81  bool
83 
84 
85  bool isPostIncrement(const MachineInstr &MI) const override;
86 
87  // ARC-specific
88  bool isPreIncrement(const MachineInstr &MI) const;
89 
90  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
91  unsigned &BasePos,
92  unsigned &OffsetPos) const override;
93 
94  // Emit code before MBBI to load immediate value into physical register Reg.
95  // Returns an iterator to the new instruction.
98  unsigned Reg, uint64_t Value) const;
99 };
100 
101 } // end namespace llvm
102 
103 #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
const ARCRegisterInfo & getRegisterInfo() const
Definition: ARCInstrInfo.h:33
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &dl, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
unsigned Reg
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Return the inverse opcode of the specified Branch instruction.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isPostIncrement(const MachineInstr &MI) const override
#define I(x, y, z)
Definition: MD5.cpp:58
LLVM Value Representation.
Definition: Value.h:73
IRTranslator LLVM IR MI
bool isPreIncrement(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...