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ARMMCCodeEmitter.cpp
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1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51  const MCInstrInfo &MCII;
52  MCContext &CTX;
53  bool IsLittleEndian;
54 
55 public:
56  ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57  : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58  }
59  ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60  ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61  ~ARMMCCodeEmitter() override = default;
62 
63  bool isThumb(const MCSubtargetInfo &STI) const {
64  return STI.getFeatureBits()[ARM::ModeThumb];
65  }
66 
67  bool isThumb2(const MCSubtargetInfo &STI) const {
68  return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69  }
70 
71  bool isTargetMachO(const MCSubtargetInfo &STI) const {
72  const Triple &TT = STI.getTargetTriple();
73  return TT.isOSBinFormatMachO();
74  }
75 
76  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78  // getBinaryCodeForInstr - TableGen'erated function for getting the
79  // binary encoding for an instruction.
80  uint64_t getBinaryCodeForInstr(const MCInst &MI,
82  const MCSubtargetInfo &STI) const;
83 
84  /// getMachineOpValue - Return binary encoding of operand. If the machine
85  /// operand requires relocation, record the relocation and return zero.
86  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
88  const MCSubtargetInfo &STI) const;
89 
90  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91  /// the specified operand. This is used for operands with :lower16: and
92  /// :upper16: prefixes.
93  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
95  const MCSubtargetInfo &STI) const;
96 
97  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98  unsigned &Reg, unsigned &Imm,
100  const MCSubtargetInfo &STI) const;
101 
102  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103  /// BL branch target.
104  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
106  const MCSubtargetInfo &STI) const;
107 
108  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109  /// BLX branch target.
110  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
112  const MCSubtargetInfo &STI) const;
113 
114  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
117  const MCSubtargetInfo &STI) const;
118 
119  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
122  const MCSubtargetInfo &STI) const;
123 
124  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
127  const MCSubtargetInfo &STI) const;
128 
129  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130  /// branch target.
131  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
133  const MCSubtargetInfo &STI) const;
134 
135  /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136  /// immediate Thumb2 direct branch target.
137  uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139  const MCSubtargetInfo &STI) const;
140 
141  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142  /// branch target.
143  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145  const MCSubtargetInfo &STI) const;
146  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
148  const MCSubtargetInfo &STI) const;
149  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
151  const MCSubtargetInfo &STI) const;
152 
153  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154  /// ADR label target.
155  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
157  const MCSubtargetInfo &STI) const;
158  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
160  const MCSubtargetInfo &STI) const;
161  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
163  const MCSubtargetInfo &STI) const;
164 
165  uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
167  const MCSubtargetInfo &STI) const;
168 
169  /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170  /// operand.
171  uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
173  const MCSubtargetInfo &STI) const;
174 
175  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176  /// operand.
177  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
179  const MCSubtargetInfo &STI) const;
180 
181  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
184  const MCSubtargetInfo &STI) const;
185 
186  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187  /// operand.
188  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
190  const MCSubtargetInfo &STI) const;
191 
192  /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193  /// operand.
194  uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
196  const MCSubtargetInfo &STI) const;
197 
198  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199  /// operand.
200  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
202  const MCSubtargetInfo &STI) const;
203 
204  /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205  /// operand.
206  template<unsigned Bits, unsigned Shift>
207  uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
209  const MCSubtargetInfo &STI) const;
210 
211  /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212  /// operand.
213  uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
215  const MCSubtargetInfo &STI) const;
216 
217  /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218  /// operand.
219  template<int shift>
220  uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
222  const MCSubtargetInfo &STI) const;
223 
224  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225  /// operand as needed by load/store instructions.
226  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
228  const MCSubtargetInfo &STI) const;
229 
230  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
233  const MCSubtargetInfo &STI) const {
235  switch (Mode) {
236  default: llvm_unreachable("Unknown addressing sub-mode!");
237  case ARM_AM::da: return 0;
238  case ARM_AM::ia: return 1;
239  case ARM_AM::db: return 2;
240  case ARM_AM::ib: return 3;
241  }
242  }
243 
244  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245  ///
246  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247  switch (ShOpc) {
248  case ARM_AM::no_shift:
249  case ARM_AM::lsl: return 0;
250  case ARM_AM::lsr: return 1;
251  case ARM_AM::asr: return 2;
252  case ARM_AM::ror:
253  case ARM_AM::rrx: return 3;
254  default:
255  llvm_unreachable("Invalid ShiftOpc!");
256  }
257  }
258 
259  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
261  SmallVectorImpl<MCFixup> &Fixups,
262  const MCSubtargetInfo &STI) const;
263 
264  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
266  SmallVectorImpl<MCFixup> &Fixups,
267  const MCSubtargetInfo &STI) const;
268 
269  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
271  SmallVectorImpl<MCFixup> &Fixups,
272  const MCSubtargetInfo &STI) const;
273 
274  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
276  SmallVectorImpl<MCFixup> &Fixups,
277  const MCSubtargetInfo &STI) const;
278 
279  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280  /// operand.
281  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
282  SmallVectorImpl<MCFixup> &Fixups,
283  const MCSubtargetInfo &STI) const;
284 
285  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
287  SmallVectorImpl<MCFixup> &Fixups,
288  const MCSubtargetInfo &STI) const;
289 
290  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
292  SmallVectorImpl<MCFixup> &Fixups,
293  const MCSubtargetInfo &STI) const;
294 
295  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
297  SmallVectorImpl<MCFixup> &Fixups,
298  const MCSubtargetInfo &STI) const;
299 
300  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
302  SmallVectorImpl<MCFixup> &Fixups,
303  const MCSubtargetInfo &STI) const;
304 
305  /// getCCOutOpValue - Return encoding of the 's' bit.
306  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
307  SmallVectorImpl<MCFixup> &Fixups,
308  const MCSubtargetInfo &STI) const {
309  // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310  // '1' respectively.
311  return MI.getOperand(Op).getReg() == ARM::CPSR;
312  }
313 
314  unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315  SmallVectorImpl<MCFixup> &Fixups,
316  const MCSubtargetInfo &ST) const {
317  const MCOperand &MO = MI.getOperand(Op);
318 
319  // Support for fixups (MCFixup)
320  if (MO.isExpr()) {
321  const MCExpr *Expr = MO.getExpr();
322  // Fixups resolve to plain values that need to be encoded.
324  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325  return 0;
326  }
327 
328  // Immediate is already in its encoded format
329  return MO.getImm();
330  }
331 
332  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
334  SmallVectorImpl<MCFixup> &Fixups,
335  const MCSubtargetInfo &STI) const {
336  const MCOperand &MO = MI.getOperand(Op);
337 
338  // Support for fixups (MCFixup)
339  if (MO.isExpr()) {
340  const MCExpr *Expr = MO.getExpr();
341  // Fixups resolve to plain values that need to be encoded.
343  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
344  return 0;
345  }
346  unsigned SoImm = MO.getImm();
347  unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
348  assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349  return Encoded;
350  }
351 
352  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
353  SmallVectorImpl<MCFixup> &Fixups,
354  const MCSubtargetInfo &STI) const;
355  template<unsigned Bits, unsigned Shift>
356  unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
357  SmallVectorImpl<MCFixup> &Fixups,
358  const MCSubtargetInfo &STI) const;
359  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
360  SmallVectorImpl<MCFixup> &Fixups,
361  const MCSubtargetInfo &STI) const;
362 
363  /// getSORegOpValue - Return an encoded so_reg shifted register value.
364  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
365  SmallVectorImpl<MCFixup> &Fixups,
366  const MCSubtargetInfo &STI) const;
367  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
368  SmallVectorImpl<MCFixup> &Fixups,
369  const MCSubtargetInfo &STI) const;
370  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
371  SmallVectorImpl<MCFixup> &Fixups,
372  const MCSubtargetInfo &STI) const;
373 
374  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
375  SmallVectorImpl<MCFixup> &Fixups,
376  const MCSubtargetInfo &STI) const {
377  return 64 - MI.getOperand(Op).getImm();
378  }
379 
380  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
381  SmallVectorImpl<MCFixup> &Fixups,
382  const MCSubtargetInfo &STI) const;
383 
384  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
385  SmallVectorImpl<MCFixup> &Fixups,
386  const MCSubtargetInfo &STI) const;
387  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
388  SmallVectorImpl<MCFixup> &Fixups,
389  const MCSubtargetInfo &STI) const;
390  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
391  SmallVectorImpl<MCFixup> &Fixups,
392  const MCSubtargetInfo &STI) const;
393  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
394  SmallVectorImpl<MCFixup> &Fixups,
395  const MCSubtargetInfo &STI) const;
396  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
397  SmallVectorImpl<MCFixup> &Fixups,
398  const MCSubtargetInfo &STI) const;
399 
400  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
401  SmallVectorImpl<MCFixup> &Fixups,
402  const MCSubtargetInfo &STI) const;
403  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
404  SmallVectorImpl<MCFixup> &Fixups,
405  const MCSubtargetInfo &STI) const;
406  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
407  SmallVectorImpl<MCFixup> &Fixups,
408  const MCSubtargetInfo &STI) const;
409  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
410  SmallVectorImpl<MCFixup> &Fixups,
411  const MCSubtargetInfo &STI) const;
412 
413  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
414  SmallVectorImpl<MCFixup> &Fixups,
415  const MCSubtargetInfo &STI) const;
416  template <uint8_t shift, bool invert>
417  unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
418  SmallVectorImpl<MCFixup> &Fixups,
419  const MCSubtargetInfo &STI) const {
420  static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421  const MCOperand MO = MI.getOperand(Op);
422  return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift;
423  }
424 
425  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
426  unsigned EncodedValue,
427  const MCSubtargetInfo &STI) const;
428  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
429  unsigned EncodedValue,
430  const MCSubtargetInfo &STI) const;
431  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
432  unsigned EncodedValue,
433  const MCSubtargetInfo &STI) const;
434  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
435  unsigned EncodedValue,
436  const MCSubtargetInfo &STI) const;
437 
438  unsigned VFPThumb2PostEncoder(const MCInst &MI,
439  unsigned EncodedValue,
440  const MCSubtargetInfo &STI) const;
441 
442  uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
443  SmallVectorImpl<MCFixup> &Fixups,
444  const MCSubtargetInfo &STI) const;
445 
446  void EmitByte(unsigned char C, raw_ostream &OS) const {
447  OS << (char)C;
448  }
449 
450  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
451  // Output the constant in little endian byte order.
452  for (unsigned i = 0; i != Size; ++i) {
453  unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
454  EmitByte((Val >> Shift) & 0xff, OS);
455  }
456  }
457 
458  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
459  SmallVectorImpl<MCFixup> &Fixups,
460  const MCSubtargetInfo &STI) const override;
461 
462  template <bool isNeg, ARM::Fixups fixup>
463  uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
464  SmallVectorImpl<MCFixup> &Fixups,
465  const MCSubtargetInfo &STI) const;
466 
467  uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
468  SmallVectorImpl<MCFixup> &Fixups,
469  const MCSubtargetInfo &STI) const;
470 
471  uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
472  SmallVectorImpl<MCFixup> &Fixups,
473  const MCSubtargetInfo &STI) const;
474  uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
475  SmallVectorImpl<MCFixup> &Fixups,
476  const MCSubtargetInfo &STI) const;
477  template <unsigned size>
478  uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
479  SmallVectorImpl<MCFixup> &Fixups,
480  const MCSubtargetInfo &STI) const;
481 };
482 
483 } // end anonymous namespace
484 
485 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
486 /// instructions, and rewrite them to their Thumb2 form if we are currently in
487 /// Thumb2 mode.
488 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
489  unsigned EncodedValue,
490  const MCSubtargetInfo &STI) const {
491  if (isThumb2(STI)) {
492  // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
493  // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
494  // set to 1111.
495  unsigned Bit24 = EncodedValue & 0x01000000;
496  unsigned Bit28 = Bit24 << 4;
497  EncodedValue &= 0xEFFFFFFF;
498  EncodedValue |= Bit28;
499  EncodedValue |= 0x0F000000;
500  }
501 
502  return EncodedValue;
503 }
504 
505 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
506 /// instructions, and rewrite them to their Thumb2 form if we are currently in
507 /// Thumb2 mode.
508 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
509  unsigned EncodedValue,
510  const MCSubtargetInfo &STI) const {
511  if (isThumb2(STI)) {
512  EncodedValue &= 0xF0FFFFFF;
513  EncodedValue |= 0x09000000;
514  }
515 
516  return EncodedValue;
517 }
518 
519 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
520 /// instructions, and rewrite them to their Thumb2 form if we are currently in
521 /// Thumb2 mode.
522 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
523  unsigned EncodedValue,
524  const MCSubtargetInfo &STI) const {
525  if (isThumb2(STI)) {
526  EncodedValue &= 0x00FFFFFF;
527  EncodedValue |= 0xEE000000;
528  }
529 
530  return EncodedValue;
531 }
532 
533 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
534 /// if we are in Thumb2.
535 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
536  unsigned EncodedValue,
537  const MCSubtargetInfo &STI) const {
538  if (isThumb2(STI)) {
539  EncodedValue |= 0xC000000; // Set bits 27-26
540  }
541 
542  return EncodedValue;
543 }
544 
545 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
546 /// them to their Thumb2 form if we are currently in Thumb2 mode.
547 unsigned ARMMCCodeEmitter::
548 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
549  const MCSubtargetInfo &STI) const {
550  if (isThumb2(STI)) {
551  EncodedValue &= 0x0FFFFFFF;
552  EncodedValue |= 0xE0000000;
553  }
554  return EncodedValue;
555 }
556 
557 /// getMachineOpValue - Return binary encoding of operand. If the machine
558 /// operand requires relocation, record the relocation and return zero.
559 unsigned ARMMCCodeEmitter::
560 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
561  SmallVectorImpl<MCFixup> &Fixups,
562  const MCSubtargetInfo &STI) const {
563  if (MO.isReg()) {
564  unsigned Reg = MO.getReg();
565  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
566 
567  // In NEON, Q registers are encoded as 2x their register number,
568  // because they're using the same indices as the D registers they
569  // overlap. In MVE, there are no 64-bit vector instructions, so
570  // the encodings all refer to Q-registers by their literal
571  // register number.
572 
573  if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
574  return RegNo;
575 
576  switch (Reg) {
577  default:
578  return RegNo;
579  case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
580  case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
581  case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
582  case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
583  return 2 * RegNo;
584  }
585  } else if (MO.isImm()) {
586  return static_cast<unsigned>(MO.getImm());
587  } else if (MO.isFPImm()) {
588  return static_cast<unsigned>(APFloat(MO.getFPImm())
589  .bitcastToAPInt().getHiBits(32).getLimitedValue());
590  }
591 
592  llvm_unreachable("Unable to encode MCOperand!");
593 }
594 
595 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
596 bool ARMMCCodeEmitter::
597 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
598  unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
599  const MCSubtargetInfo &STI) const {
600  const MCOperand &MO = MI.getOperand(OpIdx);
601  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
602 
603  Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
604 
605  int32_t SImm = MO1.getImm();
606  bool isAdd = true;
607 
608  // Special value for #-0
609  if (SImm == INT32_MIN) {
610  SImm = 0;
611  isAdd = false;
612  }
613 
614  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
615  if (SImm < 0) {
616  SImm = -SImm;
617  isAdd = false;
618  }
619 
620  Imm = SImm;
621  return isAdd;
622 }
623 
624 /// getBranchTargetOpValue - Helper function to get the branch target operand,
625 /// which is either an immediate or requires a fixup.
626 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
627  unsigned FixupKind,
628  SmallVectorImpl<MCFixup> &Fixups,
629  const MCSubtargetInfo &STI) {
630  const MCOperand &MO = MI.getOperand(OpIdx);
631 
632  // If the destination is an immediate, we have nothing to do.
633  if (MO.isImm()) return MO.getImm();
634  assert(MO.isExpr() && "Unexpected branch target type!");
635  const MCExpr *Expr = MO.getExpr();
636  MCFixupKind Kind = MCFixupKind(FixupKind);
637  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
638 
639  // All of the information is in the fixup.
640  return 0;
641 }
642 
643 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
644 // determined by negating them and XOR'ing them with bit 23.
645 static int32_t encodeThumbBLOffset(int32_t offset) {
646  offset >>= 1;
647  uint32_t S = (offset & 0x800000) >> 23;
648  uint32_t J1 = (offset & 0x400000) >> 22;
649  uint32_t J2 = (offset & 0x200000) >> 21;
650  J1 = (~J1 & 0x1);
651  J2 = (~J2 & 0x1);
652  J1 ^= S;
653  J2 ^= S;
654 
655  offset &= ~0x600000;
656  offset |= J1 << 22;
657  offset |= J2 << 21;
658 
659  return offset;
660 }
661 
662 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
663 uint32_t ARMMCCodeEmitter::
664 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
665  SmallVectorImpl<MCFixup> &Fixups,
666  const MCSubtargetInfo &STI) const {
667  const MCOperand MO = MI.getOperand(OpIdx);
668  if (MO.isExpr())
670  Fixups, STI);
671  return encodeThumbBLOffset(MO.getImm());
672 }
673 
674 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
675 /// BLX branch target.
676 uint32_t ARMMCCodeEmitter::
677 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
678  SmallVectorImpl<MCFixup> &Fixups,
679  const MCSubtargetInfo &STI) const {
680  const MCOperand MO = MI.getOperand(OpIdx);
681  if (MO.isExpr())
683  Fixups, STI);
684  return encodeThumbBLOffset(MO.getImm());
685 }
686 
687 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
688 uint32_t ARMMCCodeEmitter::
689 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
690  SmallVectorImpl<MCFixup> &Fixups,
691  const MCSubtargetInfo &STI) const {
692  const MCOperand MO = MI.getOperand(OpIdx);
693  if (MO.isExpr())
695  Fixups, STI);
696  return (MO.getImm() >> 1);
697 }
698 
699 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
700 uint32_t ARMMCCodeEmitter::
701 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
702  SmallVectorImpl<MCFixup> &Fixups,
703  const MCSubtargetInfo &STI) const {
704  const MCOperand MO = MI.getOperand(OpIdx);
705  if (MO.isExpr())
707  Fixups, STI);
708  return (MO.getImm() >> 1);
709 }
710 
711 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
712 uint32_t ARMMCCodeEmitter::
713 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
714  SmallVectorImpl<MCFixup> &Fixups,
715  const MCSubtargetInfo &STI) const {
716  const MCOperand MO = MI.getOperand(OpIdx);
717  if (MO.isExpr())
719  return (MO.getImm() >> 1);
720 }
721 
722 /// Return true if this branch has a non-always predication
723 static bool HasConditionalBranch(const MCInst &MI) {
724  int NumOp = MI.getNumOperands();
725  if (NumOp >= 2) {
726  for (int i = 0; i < NumOp-1; ++i) {
727  const MCOperand &MCOp1 = MI.getOperand(i);
728  const MCOperand &MCOp2 = MI.getOperand(i + 1);
729  if (MCOp1.isImm() && MCOp2.isReg() &&
730  (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
731  if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
732  return true;
733  }
734  }
735  }
736  return false;
737 }
738 
739 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
740 /// target.
742 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
743  SmallVectorImpl<MCFixup> &Fixups,
744  const MCSubtargetInfo &STI) const {
745  // FIXME: This really, really shouldn't use TargetMachine. We don't want
746  // coupling between MC and TM anywhere we can help it.
747  if (isThumb2(STI))
748  return
749  ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
750  return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
751 }
752 
753 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
754 /// target.
755 uint32_t ARMMCCodeEmitter::
756 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
757  SmallVectorImpl<MCFixup> &Fixups,
758  const MCSubtargetInfo &STI) const {
759  const MCOperand MO = MI.getOperand(OpIdx);
760  if (MO.isExpr()) {
761  if (HasConditionalBranch(MI))
763  ARM::fixup_arm_condbranch, Fixups, STI);
765  ARM::fixup_arm_uncondbranch, Fixups, STI);
766  }
767 
768  return MO.getImm() >> 2;
769 }
770 
771 uint32_t ARMMCCodeEmitter::
772 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
773  SmallVectorImpl<MCFixup> &Fixups,
774  const MCSubtargetInfo &STI) const {
775  const MCOperand MO = MI.getOperand(OpIdx);
776  if (MO.isExpr()) {
777  if (HasConditionalBranch(MI))
779  ARM::fixup_arm_condbl, Fixups, STI);
781  }
782 
783  return MO.getImm() >> 2;
784 }
785 
786 uint32_t ARMMCCodeEmitter::
787 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
788  SmallVectorImpl<MCFixup> &Fixups,
789  const MCSubtargetInfo &STI) const {
790  const MCOperand MO = MI.getOperand(OpIdx);
791  if (MO.isExpr())
792  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
793 
794  return MO.getImm() >> 1;
795 }
796 
797 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
798 /// immediate branch target.
799 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
800  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
801  const MCSubtargetInfo &STI) const {
802  unsigned Val = 0;
803  const MCOperand MO = MI.getOperand(OpIdx);
804 
805  if(MO.isExpr())
807  else
808  Val = MO.getImm() >> 1;
809 
810  bool I = (Val & 0x800000);
811  bool J1 = (Val & 0x400000);
812  bool J2 = (Val & 0x200000);
813  if (I ^ J1)
814  Val &= ~0x400000;
815  else
816  Val |= 0x400000;
817 
818  if (I ^ J2)
819  Val &= ~0x200000;
820  else
821  Val |= 0x200000;
822 
823  return Val;
824 }
825 
826 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
827 /// ADR label target.
828 uint32_t ARMMCCodeEmitter::
829 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
830  SmallVectorImpl<MCFixup> &Fixups,
831  const MCSubtargetInfo &STI) const {
832  const MCOperand MO = MI.getOperand(OpIdx);
833  if (MO.isExpr())
835  Fixups, STI);
836  int64_t offset = MO.getImm();
837  uint32_t Val = 0x2000;
838 
839  int SoImmVal;
840  if (offset == INT32_MIN) {
841  Val = 0x1000;
842  SoImmVal = 0;
843  } else if (offset < 0) {
844  Val = 0x1000;
845  offset *= -1;
846  SoImmVal = ARM_AM::getSOImmVal(offset);
847  if(SoImmVal == -1) {
848  Val = 0x2000;
849  offset *= -1;
850  SoImmVal = ARM_AM::getSOImmVal(offset);
851  }
852  } else {
853  SoImmVal = ARM_AM::getSOImmVal(offset);
854  if(SoImmVal == -1) {
855  Val = 0x1000;
856  offset *= -1;
857  SoImmVal = ARM_AM::getSOImmVal(offset);
858  }
859  }
860 
861  assert(SoImmVal != -1 && "Not a valid so_imm value!");
862 
863  Val |= SoImmVal;
864  return Val;
865 }
866 
867 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
868 /// target.
869 uint32_t ARMMCCodeEmitter::
870 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
871  SmallVectorImpl<MCFixup> &Fixups,
872  const MCSubtargetInfo &STI) const {
873  const MCOperand MO = MI.getOperand(OpIdx);
874  if (MO.isExpr())
876  Fixups, STI);
877  int32_t Val = MO.getImm();
878  if (Val == INT32_MIN)
879  Val = 0x1000;
880  else if (Val < 0) {
881  Val *= -1;
882  Val |= 0x1000;
883  }
884  return Val;
885 }
886 
887 /// getITMaskOpValue - Return the architectural encoding of an IT
888 /// predication mask, given the MCOperand format.
889 uint32_t ARMMCCodeEmitter::
890 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
891  SmallVectorImpl<MCFixup> &Fixups,
892  const MCSubtargetInfo &STI) const {
893  const MCOperand MaskMO = MI.getOperand(OpIdx);
894  assert(MaskMO.isImm() && "Unexpected operand type!");
895 
896  unsigned Mask = MaskMO.getImm();
897 
898  // IT masks are encoded as a sequence of replacement low-order bits
899  // for the condition code. So if the low bit of the starting
900  // condition code is 1, then we have to flip all the bits above the
901  // terminating bit (which is the lowest 1 bit).
902  assert(OpIdx > 0 && "IT mask appears first!");
903  const MCOperand CondMO = MI.getOperand(OpIdx-1);
904  assert(CondMO.isImm() && "Unexpected operand type!");
905  if (CondMO.getImm() & 1) {
906  unsigned LowBit = Mask & -Mask;
907  unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
908  Mask ^= BitsAboveLowBit;
909  }
910 
911  return Mask;
912 }
913 
914 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
915 /// target.
916 uint32_t ARMMCCodeEmitter::
917 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
918  SmallVectorImpl<MCFixup> &Fixups,
919  const MCSubtargetInfo &STI) const {
920  const MCOperand MO = MI.getOperand(OpIdx);
921  if (MO.isExpr())
923  Fixups, STI);
924  return MO.getImm();
925 }
926 
927 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
928 /// operand.
929 uint32_t ARMMCCodeEmitter::
930 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
932  const MCSubtargetInfo &STI) const {
933  // [Rn, Rm]
934  // {5-3} = Rm
935  // {2-0} = Rn
936  const MCOperand &MO1 = MI.getOperand(OpIdx);
937  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
938  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
939  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
940  return (Rm << 3) | Rn;
941 }
942 
943 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
944 /// operand.
945 uint32_t
946 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
947  SmallVectorImpl<MCFixup> &Fixups,
948  const MCSubtargetInfo &STI) const {
949  // {4-0} = szimm5
950  // The value we are trying to encode is an immediate between either the
951  // range of [1-7] or [1-15] depending on whether we are dealing with the
952  // u8/s8 or the u16/s16 variants respectively.
953  // This value is encoded as follows, if ShiftImm is the value within those
954  // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
955  // or 16.
956 
957  unsigned Size, ShiftImm;
958  switch(MI.getOpcode()) {
959  case ARM::MVE_VSHLL_imms16bh:
960  case ARM::MVE_VSHLL_imms16th:
961  case ARM::MVE_VSHLL_immu16bh:
962  case ARM::MVE_VSHLL_immu16th:
963  Size = 16;
964  break;
965  case ARM::MVE_VSHLL_imms8bh:
966  case ARM::MVE_VSHLL_imms8th:
967  case ARM::MVE_VSHLL_immu8bh:
968  case ARM::MVE_VSHLL_immu8th:
969  Size = 8;
970  break;
971  default:
972  llvm_unreachable("Use of operand not supported by this instruction");
973  }
974  ShiftImm = MI.getOperand(OpIdx).getImm();
975  return Size + ShiftImm;
976 }
977 
978 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
979 uint32_t ARMMCCodeEmitter::
980 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
981  SmallVectorImpl<MCFixup> &Fixups,
982  const MCSubtargetInfo &STI) const {
983  // {17-13} = reg
984  // {12} = (U)nsigned (add == '1', sub == '0')
985  // {11-0} = imm12
986  unsigned Reg, Imm12;
987  bool isAdd = true;
988  // If The first operand isn't a register, we have a label reference.
989  const MCOperand &MO = MI.getOperand(OpIdx);
990  if (!MO.isReg()) {
991  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
992  Imm12 = 0;
993 
994  if (MO.isExpr()) {
995  const MCExpr *Expr = MO.getExpr();
996  isAdd = false ; // 'U' bit is set as part of the fixup.
997 
999  if (isThumb2(STI))
1001  else
1003  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1004 
1005  ++MCNumCPRelocations;
1006  } else {
1007  Reg = ARM::PC;
1008  int32_t Offset = MO.getImm();
1009  if (Offset == INT32_MIN) {
1010  Offset = 0;
1011  isAdd = false;
1012  } else if (Offset < 0) {
1013  Offset *= -1;
1014  isAdd = false;
1015  }
1016  Imm12 = Offset;
1017  }
1018  } else
1019  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
1020 
1021  uint32_t Binary = Imm12 & 0xfff;
1022  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1023  if (isAdd)
1024  Binary |= (1 << 12);
1025  Binary |= (Reg << 13);
1026  return Binary;
1027 }
1028 
1029 template<unsigned Bits, unsigned Shift>
1030 uint32_t ARMMCCodeEmitter::
1031 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1032  SmallVectorImpl<MCFixup> &Fixups,
1033  const MCSubtargetInfo &STI) const {
1034  // FIXME: The immediate operand should have already been encoded like this
1035  // before ever getting here. The encoder method should just need to combine
1036  // the MI operands for the register and the offset into a single
1037  // representation for the complex operand in the .td file. This isn't just
1038  // style, unfortunately. As-is, we can't represent the distinct encoding
1039  // for #-0.
1040 
1041  // {Bits} = (U)nsigned (add == '1', sub == '0')
1042  // {(Bits-1)-0} = immediate
1043  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044  bool isAdd = Imm >= 0;
1045 
1046  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047  if (Imm < 0)
1048  Imm = -(uint32_t)Imm;
1049 
1050  Imm >>= Shift;
1051 
1052  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054  if (isAdd)
1055  Binary |= (1U << Bits);
1056  return Binary;
1057 }
1058 
1059 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1060 /// operand.
1061 uint32_t ARMMCCodeEmitter::
1062 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1063  SmallVectorImpl<MCFixup> &Fixups,
1064  const MCSubtargetInfo &STI) const {
1065  // {6-3} Rn
1066  // {2-0} Qm
1067  const MCOperand &M0 = MI.getOperand(OpIdx);
1068  const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1069 
1070  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1071  unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1072 
1073  assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1074 
1075  return (Rn << 3) | Qm;
1076 }
1077 
1078 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1079 /// operand.
1080 template<int shift>
1081 uint32_t ARMMCCodeEmitter::
1082 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1083  SmallVectorImpl<MCFixup> &Fixups,
1084  const MCSubtargetInfo &STI) const {
1085  // {10-8} Qm
1086  // {7-0} Imm
1087  const MCOperand &M0 = MI.getOperand(OpIdx);
1088  const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1089 
1090  unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1091  int32_t Imm = M1.getImm();
1092 
1093  bool isAdd = Imm >= 0;
1094 
1095  Imm >>= shift;
1096 
1097  if (!isAdd)
1098  Imm = -(uint32_t)Imm;
1099 
1100  Imm &= 0x7f;
1101 
1102  if (isAdd)
1103  Imm |= 0x80;
1104 
1105  assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1106 
1107  return (Qm << 8) | Imm;
1108 }
1109 
1110 /// getT2AddrModeImm8s4OpValue - Return encoding info for
1111 /// 'reg +/- imm8<<2' operand.
1112 uint32_t ARMMCCodeEmitter::
1113 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1114  SmallVectorImpl<MCFixup> &Fixups,
1115  const MCSubtargetInfo &STI) const {
1116  // {12-9} = reg
1117  // {8} = (U)nsigned (add == '1', sub == '0')
1118  // {7-0} = imm8
1119  unsigned Reg, Imm8;
1120  bool isAdd = true;
1121  // If The first operand isn't a register, we have a label reference.
1122  const MCOperand &MO = MI.getOperand(OpIdx);
1123  if (!MO.isReg()) {
1124  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1125  Imm8 = 0;
1126  isAdd = false ; // 'U' bit is set as part of the fixup.
1127 
1128  assert(MO.isExpr() && "Unexpected machine operand type!");
1129  const MCExpr *Expr = MO.getExpr();
1131  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1132 
1133  ++MCNumCPRelocations;
1134  } else
1135  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1136 
1137  // FIXME: The immediate operand should have already been encoded like this
1138  // before ever getting here. The encoder method should just need to combine
1139  // the MI operands for the register and the offset into a single
1140  // representation for the complex operand in the .td file. This isn't just
1141  // style, unfortunately. As-is, we can't represent the distinct encoding
1142  // for #-0.
1143  uint32_t Binary = (Imm8 >> 2) & 0xff;
1144  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1145  if (isAdd)
1146  Binary |= (1 << 8);
1147  Binary |= (Reg << 9);
1148  return Binary;
1149 }
1150 
1151 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1152 /// 'reg +/- imm7<<2' operand.
1153 uint32_t
1154 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1155  SmallVectorImpl<MCFixup> &Fixups,
1156  const MCSubtargetInfo &STI) const {
1157  // {11-8} = reg
1158  // {7} = (A)dd (add == '1', sub == '0')
1159  // {6-0} = imm7
1160  unsigned Reg, Imm7;
1161  // If The first operand isn't a register, we have a label reference.
1162  bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1163 
1164  // FIXME: The immediate operand should have already been encoded like this
1165  // before ever getting here. The encoder method should just need to combine
1166  // the MI operands for the register and the offset into a single
1167  // representation for the complex operand in the .td file. This isn't just
1168  // style, unfortunately. As-is, we can't represent the distinct encoding
1169  // for #-0.
1170  uint32_t Binary = (Imm7 >> 2) & 0xff;
1171  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1172  if (isAdd)
1173  Binary |= (1 << 7);
1174  Binary |= (Reg << 8);
1175  return Binary;
1176 }
1177 
1178 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1179 /// 'reg + imm8<<2' operand.
1180 uint32_t ARMMCCodeEmitter::
1181 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1182  SmallVectorImpl<MCFixup> &Fixups,
1183  const MCSubtargetInfo &STI) const {
1184  // {11-8} = reg
1185  // {7-0} = imm8
1186  const MCOperand &MO = MI.getOperand(OpIdx);
1187  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1188  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1189  unsigned Imm8 = MO1.getImm();
1190  return (Reg << 8) | Imm8;
1191 }
1192 
1193 uint32_t
1194 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1195  SmallVectorImpl<MCFixup> &Fixups,
1196  const MCSubtargetInfo &STI) const {
1197  // {20-16} = imm{15-12}
1198  // {11-0} = imm{11-0}
1199  const MCOperand &MO = MI.getOperand(OpIdx);
1200  if (MO.isImm())
1201  // Hi / lo 16 bits already extracted during earlier passes.
1202  return static_cast<unsigned>(MO.getImm());
1203 
1204  // Handle :upper16: and :lower16: assembly prefixes.
1205  const MCExpr *E = MO.getExpr();
1206  MCFixupKind Kind;
1207  if (E->getKind() == MCExpr::Target) {
1208  const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1209  E = ARM16Expr->getSubExpr();
1210 
1211  if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1212  const int64_t Value = MCE->getValue();
1213  if (Value > UINT32_MAX)
1214  report_fatal_error("constant value truncated (limited to 32-bit)");
1215 
1216  switch (ARM16Expr->getKind()) {
1218  return (int32_t(Value) & 0xffff0000) >> 16;
1220  return (int32_t(Value) & 0x0000ffff);
1221  default: llvm_unreachable("Unsupported ARMFixup");
1222  }
1223  }
1224 
1225  switch (ARM16Expr->getKind()) {
1226  default: llvm_unreachable("Unsupported ARMFixup");
1230  break;
1234  break;
1235  }
1236 
1237  Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1238  return 0;
1239  }
1240  // If the expression doesn't have :upper16: or :lower16: on it,
1241  // it's just a plain immediate expression, previously those evaluated to
1242  // the lower 16 bits of the expression regardless of whether
1243  // we have a movt or a movw, but that led to misleadingly results.
1244  // This is disallowed in the AsmParser in validateInstruction()
1245  // so this should never happen.
1246  llvm_unreachable("expression without :upper16: or :lower16:");
1247 }
1248 
1249 uint32_t ARMMCCodeEmitter::
1250 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1251  SmallVectorImpl<MCFixup> &Fixups,
1252  const MCSubtargetInfo &STI) const {
1253  const MCOperand &MO = MI.getOperand(OpIdx);
1254  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1255  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1256  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1257  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1258  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1259  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1261  unsigned SBits = getShiftOp(ShOp);
1262 
1263  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1264  // amount. However, it would be an easy mistake to make so check here.
1265  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1266 
1267  // {16-13} = Rn
1268  // {12} = isAdd
1269  // {11-0} = shifter
1270  // {3-0} = Rm
1271  // {4} = 0
1272  // {6-5} = type
1273  // {11-7} = imm
1274  uint32_t Binary = Rm;
1275  Binary |= Rn << 13;
1276  Binary |= SBits << 5;
1277  Binary |= ShImm << 7;
1278  if (isAdd)
1279  Binary |= 1 << 12;
1280  return Binary;
1281 }
1282 
1283 uint32_t ARMMCCodeEmitter::
1284 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1285  SmallVectorImpl<MCFixup> &Fixups,
1286  const MCSubtargetInfo &STI) const {
1287  // {13} 1 == imm12, 0 == Rm
1288  // {12} isAdd
1289  // {11-0} imm12/Rm
1290  const MCOperand &MO = MI.getOperand(OpIdx);
1291  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1292  unsigned Imm = MO1.getImm();
1293  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1294  bool isReg = MO.getReg() != 0;
1295  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1296  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1297  if (isReg) {
1299  Binary <<= 7; // Shift amount is bits [11:7]
1300  Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1301  Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1302  }
1303  return Binary | (isAdd << 12) | (isReg << 13);
1304 }
1305 
1306 uint32_t ARMMCCodeEmitter::
1307 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1308  SmallVectorImpl<MCFixup> &Fixups,
1309  const MCSubtargetInfo &STI) const {
1310  // {4} isAdd
1311  // {3-0} Rm
1312  const MCOperand &MO = MI.getOperand(OpIdx);
1313  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1314  bool isAdd = MO1.getImm() != 0;
1315  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1316 }
1317 
1318 uint32_t ARMMCCodeEmitter::
1319 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1320  SmallVectorImpl<MCFixup> &Fixups,
1321  const MCSubtargetInfo &STI) const {
1322  // {9} 1 == imm8, 0 == Rm
1323  // {8} isAdd
1324  // {7-4} imm7_4/zero
1325  // {3-0} imm3_0/Rm
1326  const MCOperand &MO = MI.getOperand(OpIdx);
1327  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1328  unsigned Imm = MO1.getImm();
1329  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1330  bool isImm = MO.getReg() == 0;
1332  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1333  if (!isImm)
1334  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1335  return Imm8 | (isAdd << 8) | (isImm << 9);
1336 }
1337 
1338 uint32_t ARMMCCodeEmitter::
1339 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1340  SmallVectorImpl<MCFixup> &Fixups,
1341  const MCSubtargetInfo &STI) const {
1342  // {13} 1 == imm8, 0 == Rm
1343  // {12-9} Rn
1344  // {8} isAdd
1345  // {7-4} imm7_4/zero
1346  // {3-0} imm3_0/Rm
1347  const MCOperand &MO = MI.getOperand(OpIdx);
1348  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1349  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1350 
1351  // If The first operand isn't a register, we have a label reference.
1352  if (!MO.isReg()) {
1353  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1354 
1355  assert(MO.isExpr() && "Unexpected machine operand type!");
1356  const MCExpr *Expr = MO.getExpr();
1358  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1359 
1360  ++MCNumCPRelocations;
1361  return (Rn << 9) | (1 << 13);
1362  }
1363  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1364  unsigned Imm = MO2.getImm();
1365  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1366  bool isImm = MO1.getReg() == 0;
1368  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1369  if (!isImm)
1370  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1371  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1372 }
1373 
1374 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1375 uint32_t ARMMCCodeEmitter::
1376 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1377  SmallVectorImpl<MCFixup> &Fixups,
1378  const MCSubtargetInfo &STI) const {
1379  // [SP, #imm]
1380  // {7-0} = imm8
1381  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1382  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1383  "Unexpected base register!");
1384 
1385  // The immediate is already shifted for the implicit zeroes, so no change
1386  // here.
1387  return MO1.getImm() & 0xff;
1388 }
1389 
1390 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1391 uint32_t ARMMCCodeEmitter::
1392 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1393  SmallVectorImpl<MCFixup> &Fixups,
1394  const MCSubtargetInfo &STI) const {
1395  // [Rn, #imm]
1396  // {7-3} = imm5
1397  // {2-0} = Rn
1398  const MCOperand &MO = MI.getOperand(OpIdx);
1399  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1400  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1401  unsigned Imm5 = MO1.getImm();
1402  return ((Imm5 & 0x1f) << 3) | Rn;
1403 }
1404 
1405 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1406 uint32_t ARMMCCodeEmitter::
1407 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1408  SmallVectorImpl<MCFixup> &Fixups,
1409  const MCSubtargetInfo &STI) const {
1410  const MCOperand MO = MI.getOperand(OpIdx);
1411  if (MO.isExpr())
1413  return (MO.getImm() >> 2);
1414 }
1415 
1416 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1417 uint32_t ARMMCCodeEmitter::
1418 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1419  SmallVectorImpl<MCFixup> &Fixups,
1420  const MCSubtargetInfo &STI) const {
1421  // {12-9} = reg
1422  // {8} = (U)nsigned (add == '1', sub == '0')
1423  // {7-0} = imm8
1424  unsigned Reg, Imm8;
1425  bool isAdd;
1426  // If The first operand isn't a register, we have a label reference.
1427  const MCOperand &MO = MI.getOperand(OpIdx);
1428  if (!MO.isReg()) {
1429  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1430  Imm8 = 0;
1431  isAdd = false; // 'U' bit is handled as part of the fixup.
1432 
1433  assert(MO.isExpr() && "Unexpected machine operand type!");
1434  const MCExpr *Expr = MO.getExpr();
1435  MCFixupKind Kind;
1436  if (isThumb2(STI))
1438  else
1440  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1441 
1442  ++MCNumCPRelocations;
1443  } else {
1444  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1445  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1446  }
1447 
1448  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1449  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1450  if (isAdd)
1451  Binary |= (1 << 8);
1452  Binary |= (Reg << 9);
1453  return Binary;
1454 }
1455 
1456 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1457 uint32_t ARMMCCodeEmitter::
1458 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1459  SmallVectorImpl<MCFixup> &Fixups,
1460  const MCSubtargetInfo &STI) const {
1461  // {12-9} = reg
1462  // {8} = (U)nsigned (add == '1', sub == '0')
1463  // {7-0} = imm8
1464  unsigned Reg, Imm8;
1465  bool isAdd;
1466  // If The first operand isn't a register, we have a label reference.
1467  const MCOperand &MO = MI.getOperand(OpIdx);
1468  if (!MO.isReg()) {
1469  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1470  Imm8 = 0;
1471  isAdd = false; // 'U' bit is handled as part of the fixup.
1472 
1473  assert(MO.isExpr() && "Unexpected machine operand type!");
1474  const MCExpr *Expr = MO.getExpr();
1475  MCFixupKind Kind;
1476  if (isThumb2(STI))
1478  else
1480  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1481 
1482  ++MCNumCPRelocations;
1483  } else {
1484  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1485  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1486  }
1487 
1488  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1489  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1490  if (isAdd)
1491  Binary |= (1 << 8);
1492  Binary |= (Reg << 9);
1493  return Binary;
1494 }
1495 
1496 unsigned ARMMCCodeEmitter::
1497 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1498  SmallVectorImpl<MCFixup> &Fixups,
1499  const MCSubtargetInfo &STI) const {
1500  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1501  // shifted. The second is Rs, the amount to shift by, and the third specifies
1502  // the type of the shift.
1503  //
1504  // {3-0} = Rm.
1505  // {4} = 1
1506  // {6-5} = type
1507  // {11-8} = Rs
1508  // {7} = 0
1509 
1510  const MCOperand &MO = MI.getOperand(OpIdx);
1511  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1512  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1514 
1515  // Encode Rm.
1516  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1517 
1518  // Encode the shift opcode.
1519  unsigned SBits = 0;
1520  unsigned Rs = MO1.getReg();
1521  if (Rs) {
1522  // Set shift operand (bit[7:4]).
1523  // LSL - 0001
1524  // LSR - 0011
1525  // ASR - 0101
1526  // ROR - 0111
1527  switch (SOpc) {
1528  default: llvm_unreachable("Unknown shift opc!");
1529  case ARM_AM::lsl: SBits = 0x1; break;
1530  case ARM_AM::lsr: SBits = 0x3; break;
1531  case ARM_AM::asr: SBits = 0x5; break;
1532  case ARM_AM::ror: SBits = 0x7; break;
1533  }
1534  }
1535 
1536  Binary |= SBits << 4;
1537 
1538  // Encode the shift operation Rs.
1539  // Encode Rs bit[11:8].
1540  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1541  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1542 }
1543 
1544 unsigned ARMMCCodeEmitter::
1545 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1546  SmallVectorImpl<MCFixup> &Fixups,
1547  const MCSubtargetInfo &STI) const {
1548  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1549  // shifted. The second is the amount to shift by.
1550  //
1551  // {3-0} = Rm.
1552  // {4} = 0
1553  // {6-5} = type
1554  // {11-7} = imm
1555 
1556  const MCOperand &MO = MI.getOperand(OpIdx);
1557  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1559 
1560  // Encode Rm.
1561  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1562 
1563  // Encode the shift opcode.
1564  unsigned SBits = 0;
1565 
1566  // Set shift operand (bit[6:4]).
1567  // LSL - 000
1568  // LSR - 010
1569  // ASR - 100
1570  // ROR - 110
1571  // RRX - 110 and bit[11:8] clear.
1572  switch (SOpc) {
1573  default: llvm_unreachable("Unknown shift opc!");
1574  case ARM_AM::lsl: SBits = 0x0; break;
1575  case ARM_AM::lsr: SBits = 0x2; break;
1576  case ARM_AM::asr: SBits = 0x4; break;
1577  case ARM_AM::ror: SBits = 0x6; break;
1578  case ARM_AM::rrx:
1579  Binary |= 0x60;
1580  return Binary;
1581  }
1582 
1583  // Encode shift_imm bit[11:7].
1584  Binary |= SBits << 4;
1585  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1586  assert(Offset < 32 && "Offset must be in range 0-31!");
1587  return Binary | (Offset << 7);
1588 }
1589 
1590 
1591 unsigned ARMMCCodeEmitter::
1592 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1593  SmallVectorImpl<MCFixup> &Fixups,
1594  const MCSubtargetInfo &STI) const {
1595  const MCOperand &MO1 = MI.getOperand(OpNum);
1596  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1597  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1598 
1599  // Encoded as [Rn, Rm, imm].
1600  // FIXME: Needs fixup support.
1601  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1602  Value <<= 4;
1603  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1604  Value <<= 2;
1605  Value |= MO3.getImm();
1606 
1607  return Value;
1608 }
1609 
1610 template<unsigned Bits, unsigned Shift>
1611 unsigned ARMMCCodeEmitter::
1612 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1613  SmallVectorImpl<MCFixup> &Fixups,
1614  const MCSubtargetInfo &STI) const {
1615  const MCOperand &MO1 = MI.getOperand(OpNum);
1616  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617 
1618  // FIXME: Needs fixup support.
1619  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620 
1621  // If the immediate is B bits long, we need B+1 bits in order
1622  // to represent the (inverse of the) sign bit.
1623  Value <<= (Bits + 1);
1624  int32_t tmp = (int32_t)MO2.getImm();
1625  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626  tmp = 0;
1627  } else if (tmp < 0) {
1628  tmp = abs(tmp);
1629  } else {
1630  Value |= (1U << Bits); // Set the ADD bit
1631  }
1632  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633  return Value;
1634 }
1635 
1636 unsigned ARMMCCodeEmitter::
1637 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1638  SmallVectorImpl<MCFixup> &Fixups,
1639  const MCSubtargetInfo &STI) const {
1640  const MCOperand &MO1 = MI.getOperand(OpNum);
1641 
1642  // FIXME: Needs fixup support.
1643  unsigned Value = 0;
1644  int32_t tmp = (int32_t)MO1.getImm();
1645  if (tmp < 0)
1646  tmp = abs(tmp);
1647  else
1648  Value |= 256; // Set the ADD bit
1649  Value |= tmp & 255;
1650  return Value;
1651 }
1652 
1653 unsigned ARMMCCodeEmitter::
1654 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1655  SmallVectorImpl<MCFixup> &Fixups,
1656  const MCSubtargetInfo &STI) const {
1657  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1658  // shifted. The second is the amount to shift by.
1659  //
1660  // {3-0} = Rm.
1661  // {4} = 0
1662  // {6-5} = type
1663  // {11-7} = imm
1664 
1665  const MCOperand &MO = MI.getOperand(OpIdx);
1666  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1668 
1669  // Encode Rm.
1670  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1671 
1672  // Encode the shift opcode.
1673  unsigned SBits = 0;
1674  // Set shift operand (bit[6:4]).
1675  // LSL - 000
1676  // LSR - 010
1677  // ASR - 100
1678  // ROR - 110
1679  switch (SOpc) {
1680  default: llvm_unreachable("Unknown shift opc!");
1681  case ARM_AM::lsl: SBits = 0x0; break;
1682  case ARM_AM::lsr: SBits = 0x2; break;
1683  case ARM_AM::asr: SBits = 0x4; break;
1685  case ARM_AM::ror: SBits = 0x6; break;
1686  }
1687 
1688  Binary |= SBits << 4;
1689  if (SOpc == ARM_AM::rrx)
1690  return Binary;
1691 
1692  // Encode shift_imm bit[11:7].
1693  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1694 }
1695 
1696 unsigned ARMMCCodeEmitter::
1697 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1698  SmallVectorImpl<MCFixup> &Fixups,
1699  const MCSubtargetInfo &STI) const {
1700  // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1701  // msb of the mask.
1702  const MCOperand &MO = MI.getOperand(Op);
1703  uint32_t v = ~MO.getImm();
1704  uint32_t lsb = countTrailingZeros(v);
1705  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1706  assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1707  return lsb | (msb << 5);
1708 }
1709 
1710 unsigned ARMMCCodeEmitter::
1711 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1712  SmallVectorImpl<MCFixup> &Fixups,
1713  const MCSubtargetInfo &STI) const {
1714  // VLDM/VSTM/VSCCLRM:
1715  // {12-8} = Vd
1716  // {7-0} = Number of registers
1717  //
1718  // LDM/STM:
1719  // {15-0} = Bitfield of GPRs.
1720  unsigned Reg = MI.getOperand(Op).getReg();
1721  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1722  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1723 
1724  unsigned Binary = 0;
1725 
1726  if (SPRRegs || DPRRegs) {
1727  // VLDM/VSTM/VSCCLRM
1728  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1729  unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1730  Binary |= (RegNo & 0x1f) << 8;
1731 
1732  // Ignore VPR
1733  if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1734  --NumRegs;
1735  if (SPRRegs)
1736  Binary |= NumRegs;
1737  else
1738  Binary |= NumRegs * 2;
1739  } else {
1740  const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1741  assert(std::is_sorted(MI.begin() + Op, MI.end(),
1742  [&](const MCOperand &LHS, const MCOperand &RHS) {
1743  return MRI.getEncodingValue(LHS.getReg()) <
1744  MRI.getEncodingValue(RHS.getReg());
1745  }));
1746  for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1747  unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1748  Binary |= 1 << RegNo;
1749  }
1750  }
1751 
1752  return Binary;
1753 }
1754 
1755 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1756 /// with the alignment operand.
1757 unsigned ARMMCCodeEmitter::
1758 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1759  SmallVectorImpl<MCFixup> &Fixups,
1760  const MCSubtargetInfo &STI) const {
1761  const MCOperand &Reg = MI.getOperand(Op);
1762  const MCOperand &Imm = MI.getOperand(Op + 1);
1763 
1764  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1765  unsigned Align = 0;
1766 
1767  switch (Imm.getImm()) {
1768  default: break;
1769  case 2:
1770  case 4:
1771  case 8: Align = 0x01; break;
1772  case 16: Align = 0x02; break;
1773  case 32: Align = 0x03; break;
1774  }
1775 
1776  return RegNo | (Align << 4);
1777 }
1778 
1779 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1780 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1781 unsigned ARMMCCodeEmitter::
1782 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1783  SmallVectorImpl<MCFixup> &Fixups,
1784  const MCSubtargetInfo &STI) const {
1785  const MCOperand &Reg = MI.getOperand(Op);
1786  const MCOperand &Imm = MI.getOperand(Op + 1);
1787 
1788  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1789  unsigned Align = 0;
1790 
1791  switch (Imm.getImm()) {
1792  default: break;
1793  case 8:
1794  case 16:
1795  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1796  case 2: Align = 0x00; break;
1797  case 4: Align = 0x03; break;
1798  }
1799 
1800  return RegNo | (Align << 4);
1801 }
1802 
1803 
1804 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1805 /// alignment operand for use in VLD-dup instructions. This is the same as
1806 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1807 /// different for VLD4-dup.
1808 unsigned ARMMCCodeEmitter::
1809 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1810  SmallVectorImpl<MCFixup> &Fixups,
1811  const MCSubtargetInfo &STI) const {
1812  const MCOperand &Reg = MI.getOperand(Op);
1813  const MCOperand &Imm = MI.getOperand(Op + 1);
1814 
1815  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1816  unsigned Align = 0;
1817 
1818  switch (Imm.getImm()) {
1819  default: break;
1820  case 2:
1821  case 4:
1822  case 8: Align = 0x01; break;
1823  case 16: Align = 0x03; break;
1824  }
1825 
1826  return RegNo | (Align << 4);
1827 }
1828 
1829 unsigned ARMMCCodeEmitter::
1830 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1831  SmallVectorImpl<MCFixup> &Fixups,
1832  const MCSubtargetInfo &STI) const {
1833  const MCOperand &MO = MI.getOperand(Op);
1834  if (MO.getReg() == 0) return 0x0D;
1835  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1836 }
1837 
1838 unsigned ARMMCCodeEmitter::
1839 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1840  SmallVectorImpl<MCFixup> &Fixups,
1841  const MCSubtargetInfo &STI) const {
1842  return 8 - MI.getOperand(Op).getImm();
1843 }
1844 
1845 unsigned ARMMCCodeEmitter::
1846 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1847  SmallVectorImpl<MCFixup> &Fixups,
1848  const MCSubtargetInfo &STI) const {
1849  return 16 - MI.getOperand(Op).getImm();
1850 }
1851 
1852 unsigned ARMMCCodeEmitter::
1853 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1854  SmallVectorImpl<MCFixup> &Fixups,
1855  const MCSubtargetInfo &STI) const {
1856  return 32 - MI.getOperand(Op).getImm();
1857 }
1858 
1859 unsigned ARMMCCodeEmitter::
1860 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1861  SmallVectorImpl<MCFixup> &Fixups,
1862  const MCSubtargetInfo &STI) const {
1863  return 64 - MI.getOperand(Op).getImm();
1864 }
1865 
1866 void ARMMCCodeEmitter::
1867 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1868  SmallVectorImpl<MCFixup> &Fixups,
1869  const MCSubtargetInfo &STI) const {
1870  // Pseudo instructions don't get encoded.
1871  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1872  uint64_t TSFlags = Desc.TSFlags;
1873  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1874  return;
1875 
1876  int Size;
1877  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1878  Size = Desc.getSize();
1879  else
1880  llvm_unreachable("Unexpected instruction size!");
1881 
1882  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1883  // Thumb 32-bit wide instructions need to emit the high order halfword
1884  // first.
1885  if (isThumb(STI) && Size == 4) {
1886  EmitConstant(Binary >> 16, 2, OS);
1887  EmitConstant(Binary & 0xffff, 2, OS);
1888  } else
1889  EmitConstant(Binary, Size, OS);
1890  ++MCNumEmitted; // Keep track of the # of mi's emitted.
1891 }
1892 
1893 template <bool isNeg, ARM::Fixups fixup>
1894 uint32_t
1895 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1896  SmallVectorImpl<MCFixup> &Fixups,
1897  const MCSubtargetInfo &STI) const {
1898  const MCOperand MO = MI.getOperand(OpIdx);
1899  if (MO.isExpr())
1900  return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1901  return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1902 }
1903 
1904 uint32_t
1905 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1906  SmallVectorImpl<MCFixup> &Fixups,
1907  const MCSubtargetInfo &STI) const {
1908  const MCOperand MO = MI.getOperand(OpIdx);
1909  const MCOperand BranchMO = MI.getOperand(0);
1910 
1911  if (MO.isExpr()) {
1912  assert(BranchMO.isExpr());
1913  const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1914  MO.getExpr(), BranchMO.getExpr(), CTX);
1916  Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1917  return 0;
1918  }
1919 
1920  assert(MO.isImm() && BranchMO.isImm());
1921  int Diff = MO.getImm() - BranchMO.getImm();
1922  assert(Diff == 4 || Diff == 2);
1923 
1924  return Diff == 4;
1925 }
1926 
1927 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1928  SmallVectorImpl<MCFixup> &Fixups,
1929  const MCSubtargetInfo &STI)const {
1930  const MCOperand MO = MI.getOperand(OpIdx);
1931  assert(MO.isImm() && "Unexpected operand type!");
1932 
1933  int Value = MO.getImm();
1934  int Imm = 0;
1935 
1936  // VPT Masks are actually encoded as a series of invert/don't invert bits,
1937  // rather than true/false bits.
1938  unsigned PrevBit = 0;
1939  for (int i = 3; i >= 0; --i) {
1940  unsigned Bit = (Value >> i) & 1;
1941 
1942  // Check if we are at the end of the mask.
1943  if ((Value & ~(~0U << i)) == 0) {
1944  Imm |= (1 << i);
1945  break;
1946  }
1947 
1948  // Convert the bit in the mask based on the previous bit.
1949  if (Bit != PrevBit)
1950  Imm |= (1 << i);
1951 
1952  PrevBit = Bit;
1953  }
1954 
1955  return Imm;
1956 }
1957 
1958 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1959  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1960  const MCSubtargetInfo &STI) const {
1961 
1962  const MCOperand MO = MI.getOperand(OpIdx);
1963  assert(MO.isImm() && "Unexpected operand type!");
1964 
1965  switch (MO.getImm()) {
1966  default:
1967  assert(0 && "Unexpected Condition!");
1968  return 0;
1969  case ARMCC::HS:
1970  case ARMCC::EQ:
1971  return 0;
1972  case ARMCC::HI:
1973  case ARMCC::NE:
1974  return 1;
1975  case ARMCC::GE:
1976  return 4;
1977  case ARMCC::LT:
1978  return 5;
1979  case ARMCC::GT:
1980  return 6;
1981  case ARMCC::LE:
1982  return 7;
1983  }
1984 }
1985 
1986 uint32_t ARMMCCodeEmitter::
1987 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1988  SmallVectorImpl<MCFixup> &Fixups,
1989  const MCSubtargetInfo &STI) const {
1990  const MCOperand &MO = MI.getOperand(OpIdx);
1991  assert(MO.isImm() && "Unexpected operand type!");
1992  return countTrailingZeros((uint64_t)MO.getImm());
1993 }
1994 
1995 template <unsigned start>
1996 uint32_t ARMMCCodeEmitter::
1997 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
1998  SmallVectorImpl<MCFixup> &Fixups,
1999  const MCSubtargetInfo &STI) const {
2000  const MCOperand MO = MI.getOperand(OpIdx);
2001  assert(MO.isImm() && "Unexpected operand type!");
2002 
2003  int Value = MO.getImm();
2004  return Value - start;
2005 }
2006 
2007 #include "ARMGenMCCodeEmitter.inc"
2008 
2010  const MCRegisterInfo &MRI,
2011  MCContext &Ctx) {
2012  return new ARMMCCodeEmitter(MCII, Ctx, true);
2013 }
2014 
2016  const MCRegisterInfo &MRI,
2017  MCContext &Ctx) {
2018  return new ARMMCCodeEmitter(MCII, Ctx, false);
2019 }
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t CallInst * C
iterator end()
Definition: MCInst.h:194
iterator begin()
Definition: MCInst.h:192
bool isImm() const
Definition: MCInst.h:58
SI Whole Quad Mode
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: ARMMCExpr.h:51
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
STATISTIC(NumFunctions, "Total number of functions")
static Lanai::Fixups FixupKind(const MCExpr *Expr)
static bool isThumb(const MCSubtargetInfo &STI)
const Triple & getTargetTriple() const
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:65
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:554
unsigned char getAM3Offset(unsigned AM3Opc)
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
int64_t getImm() const
Definition: MCInst.h:75
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
unsigned const MachineRegisterInfo * MRI
unsigned getSORegOffset(unsigned Op)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isFPImm() const
Definition: MCInst.h:59
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
This file declares a class to represent arbitrary precision floating point values and provide a varie...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
bool isExpr() const
Definition: MCInst.h:60
unsigned getNumOperands() const
Definition: MCInst.h:181
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:93
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
static int32_t encodeThumbBLOffset(int32_t offset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
ExprKind getKind() const
Definition: MCExpr.h:72
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
unsigned getAM2Offset(unsigned AM2Opc)
SMLoc getLoc() const
Definition: MCInst.h:177
ShiftOpc getSORegShOp(unsigned Op)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: ARMMCExpr.h:54
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1223
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:320
LLVM Value Representation.
Definition: Value.h:73
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:258
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
Target specific expression.
Definition: MCExpr.h:42
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Function Alias Analysis false
double getFPImm() const
Definition: MCInst.h:85
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:600