LLVM  10.0.0svn
Go to the documentation of this file.
1 //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // Hexagon specific code to select Hexagon machine instructions for
9 // SelectionDAG operations.
10 //===----------------------------------------------------------------------===//
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/StringRef.h"
20 #include "llvm/Support/CodeGen.h"
22 #include <vector>
24 namespace llvm {
25 class MachineFunction;
26 class HexagonInstrInfo;
27 class HexagonRegisterInfo;
28 class HexagonTargetLowering;
31  const HexagonSubtarget *HST;
32  const HexagonInstrInfo *HII;
33  const HexagonRegisterInfo *HRI;
34 public:
37  : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
38  HRI(nullptr) {}
41  // Reset the subtarget each time through.
42  HST = &MF.getSubtarget<HexagonSubtarget>();
43  HII = HST->getInstrInfo();
44  HRI = HST->getRegisterInfo();
46  return true;
47  }
49  bool ComplexPatternFuncMutatesDAG() const override {
50  return true;
51  }
52  void PreprocessISelDAG() override;
53  void EmitFunctionEntryCode() override;
55  void Select(SDNode *N) override;
57  // Complex Pattern Selectors.
58  inline bool SelectAddrGA(SDValue &N, SDValue &R);
59  inline bool SelectAddrGP(SDValue &N, SDValue &R);
60  inline bool SelectAnyImm(SDValue &N, SDValue &R);
61  inline bool SelectAnyInt(SDValue &N, SDValue &R);
62  bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
63  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
64  uint32_t LogAlign);
65  bool SelectAddrFI(SDValue &N, SDValue &R);
66  bool DetectUseSxtw(SDValue &N, SDValue &R);
68  inline bool SelectAnyImm0(SDValue &N, SDValue &R);
69  inline bool SelectAnyImm1(SDValue &N, SDValue &R);
70  inline bool SelectAnyImm2(SDValue &N, SDValue &R);
71  inline bool SelectAnyImm3(SDValue &N, SDValue &R);
73  StringRef getPassName() const override {
74  return "Hexagon DAG->DAG Pattern Instruction Selection";
75  }
77  // Generate a machine instruction node corresponding to the circ/brev
78  // load intrinsic.
80  // Given the circ/brev load intrinsic and the already generated machine
81  // instruction, generate the appropriate store (that is a part of the
82  // intrinsic's functionality).
85  void SelectFrameIndex(SDNode *N);
86  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
87  /// inline asm expressions.
89  unsigned ConstraintID,
90  std::vector<SDValue> &OutOps) override;
92  bool SelectBrevLdIntrinsic(SDNode *IntN);
93  bool SelectNewCircIntrinsic(SDNode *IntN);
94  void SelectLoad(SDNode *N);
95  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
96  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
97  void SelectStore(SDNode *N);
98  void SelectSHL(SDNode *N);
99  void SelectZeroExtend(SDNode *N);
100  void SelectIntrinsicWChain(SDNode *N);
102  void SelectConstant(SDNode *N);
103  void SelectConstantFP(SDNode *N);
104  void SelectV65Gather(SDNode *N);
105  void SelectV65GatherPred(SDNode *N);
106  void SelectHVXDualOutput(SDNode *N);
107  void SelectAddSubCarry(SDNode *N);
108  void SelectVAlign(SDNode *N);
109  void SelectVAlignAddr(SDNode *N);
110  void SelectTypecast(SDNode *N);
111  void SelectP2D(SDNode *N);
112  void SelectD2P(SDNode *N);
113  void SelectQ2V(SDNode *N);
114  void SelectV2Q(SDNode *N);
116  // Include the declarations autogenerated from the selection patterns.
117  #define GET_DAGISEL_DECL
118  #include "HexagonGenDAGISel.inc"
120 private:
121  // This is really only to get access to ReplaceNode (which is a protected
122  // member). Any other members used by HvxSelector can be moved around to
123  // make them accessible).
124  friend struct HvxSelector;
126  SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
127  SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
128  return SDValue(U, 0);
129  }
131  void SelectHvxShuffle(SDNode *N);
132  void SelectHvxRor(SDNode *N);
133  void SelectHvxVAlign(SDNode *N);
135  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
136  bool isAlignedMemNode(const MemSDNode *N) const;
137  bool isSmallStackStore(const StoreSDNode *N) const;
138  bool isPositiveHalfWord(const SDNode *N) const;
139  bool hasOneUse(const SDNode *N) const;
141  // DAG preprocessing functions.
142  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
143  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
144  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
145  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
147  SmallDenseMap<SDNode *,int> RootWeights;
148  SmallDenseMap<SDNode *,int> RootHeights;
149  SmallDenseMap<const Value *,int> GAUsesInFunction;
150  int getWeight(SDNode *N);
151  int getHeight(SDNode *N);
152  SDValue getMultiplierForSHL(SDNode *N);
153  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
154  unsigned getUsesInFunction(const Value *V);
155  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
156  void rebalanceAddressTrees();
157 }; // end HexagonDAGToDAGISel
158 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectAddrFI(SDValue &N, SDValue &R)
MachineFunction * MF
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const HexagonRegisterInfo * getRegisterInfo() const override
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circlar buffer intrinsics.
bool SelectBrevLdIntrinsic(SDNode *IntN)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
This class is used to represent ISD::STORE nodes.
CodeGenOpt::Level OptLevel
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool SelectAnyImm0(SDValue &N, SDValue &R)
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void SelectZeroExtend(SDNode *N)
bool SelectAnyImm2(SDValue &N, SDValue &R)
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectAddrGA(SDValue &N, SDValue &R)
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, uint32_t LogAlign)
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel)
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign)
bool SelectAnyImm3(SDValue &N, SDValue &R)
bool SelectAnyImm1(SDValue &N, SDValue &R)
bool SelectAddrGP(SDValue &N, SDValue &R)
static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS)
#define N
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
bool SelectAnyImm(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
LLVM Value Representation.
Definition: Value.h:74
const HexagonInstrInfo * getInstrInfo() const override
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This class is used to represent ISD::LOAD nodes.