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HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 
16 #include "HexagonDepArch.h"
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
20 #include "HexagonRegisterInfo.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/StringRef.h"
27 #include <memory>
28 #include <string>
29 #include <vector>
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "HexagonGenSubtargetInfo.inc"
33 
34 namespace llvm {
35 
36 class MachineInstr;
37 class SDep;
38 class SUnit;
39 class TargetMachine;
40 class Triple;
41 
43  virtual void anchor();
44 
45  bool UseHVX64BOps = false;
46  bool UseHVX128BOps = false;
47 
48  bool UseLongCalls = false;
49  bool UseMemops = false;
50  bool UsePackets = false;
51  bool UseNewValueJumps = false;
52  bool UseNewValueStores = false;
53  bool UseSmallData = false;
54  bool UseZRegOps = false;
55 
56  bool HasMemNoShuf = false;
57  bool EnableDuplex = false;
58  bool ReservedR19 = false;
59  bool NoreturnStackElim = false;
60 
61 public:
65  /// True if the target should use Back-Skip-Back scheduling. This is the
66  /// default for V60.
68 
70  void apply(ScheduleDAGInstrs *DAG) override;
71  };
73  void apply(ScheduleDAGInstrs *DAG) override;
74  };
76  void apply(ScheduleDAGInstrs *DAG) override;
77  private:
78  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
79  const SUnit &Inst1, const SUnit &Inst2) const;
80  };
82  void apply(ScheduleDAGInstrs *DAG) override;
83  };
84 
85 private:
86  std::string CPUString;
87  HexagonInstrInfo InstrInfo;
89  HexagonTargetLowering TLInfo;
91  HexagonFrameLowering FrameLowering;
92  InstrItineraryData InstrItins;
93 
94 public:
96  const TargetMachine &TM);
97 
98  /// getInstrItins - Return the instruction itineraries based on subtarget
99  /// selection.
100  const InstrItineraryData *getInstrItineraryData() const override {
101  return &InstrItins;
102  }
103  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
104  const HexagonRegisterInfo *getRegisterInfo() const override {
105  return &RegInfo;
106  }
107  const HexagonTargetLowering *getTargetLowering() const override {
108  return &TLInfo;
109  }
110  const HexagonFrameLowering *getFrameLowering() const override {
111  return &FrameLowering;
112  }
114  return &TSInfo;
115  }
116 
118  StringRef FS);
119 
120  /// ParseSubtargetFeatures - Parses features string setting specified
121  /// subtarget options. Definition of function is auto generated by tblgen.
123 
124  bool hasV5Ops() const {
126  }
127  bool hasV5OpsOnly() const {
129  }
130  bool hasV55Ops() const {
132  }
133  bool hasV55OpsOnly() const {
135  }
136  bool hasV60Ops() const {
138  }
139  bool hasV60OpsOnly() const {
141  }
142  bool hasV62Ops() const {
144  }
145  bool hasV62OpsOnly() const {
147  }
148  bool hasV65Ops() const {
150  }
151  bool hasV65OpsOnly() const {
153  }
154  bool hasV66Ops() const {
156  }
157  bool hasV66OpsOnly() const {
159  }
160 
161  bool useLongCalls() const { return UseLongCalls; }
162  bool useMemops() const { return UseMemops; }
163  bool usePackets() const { return UsePackets; }
164  bool useNewValueJumps() const { return UseNewValueJumps; }
165  bool useNewValueStores() const { return UseNewValueStores; }
166  bool useSmallData() const { return UseSmallData; }
167  bool useZRegOps() const { return UseZRegOps; }
168 
169  bool useHVXOps() const {
170  return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
171  }
172  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
173  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
174 
175  bool hasMemNoShuf() const { return HasMemNoShuf; }
176  bool hasReservedR19() const { return ReservedR19; }
177  bool usePredicatedCalls() const;
178 
179  bool noreturnStackElim() const { return NoreturnStackElim; }
180 
181  bool useBSBScheduling() const { return UseBSBScheduling; }
182  bool enableMachineScheduler() const override;
183 
184  // Always use the TargetLowering default scheduler.
185  // FIXME: This will use the vliw scheduler which is probably just hurting
186  // compiler time and will be removed eventually anyway.
187  bool enableMachineSchedDefaultSched() const override { return false; }
188 
189  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
190  bool enablePostRAScheduler() const override { return true; }
191 
192  bool enableSubRegLiveness() const override;
193 
194  const std::string &getCPUString () const { return CPUString; }
195 
197  return HexagonArchVersion;
198  }
199 
200  void getPostRAMutations(
201  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
202  const override;
203 
204  void getSMSMutations(
205  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
206  const override;
207 
208  /// Enable use of alias analysis during code generation (during MI
209  /// scheduling, DAGCombine, etc.).
210  bool useAA() const override;
211 
212  /// Perform target specific adjustments to the latency of a schedule
213  /// dependency.
214  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
215 
216  unsigned getVectorLength() const {
217  assert(useHVXOps());
218  if (useHVX64BOps())
219  return 64;
220  if (useHVX128BOps())
221  return 128;
222  llvm_unreachable("Invalid HVX vector length settings");
223  }
224 
226  static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
227  return makeArrayRef(Types);
228  }
229 
230  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
231  if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
232  return false;
233  MVT ElemTy = VecTy.getVectorElementType();
234  if (!IncludeBool && ElemTy == MVT::i1)
235  return false;
236 
237  unsigned HwLen = getVectorLength();
238  unsigned NumElems = VecTy.getVectorNumElements();
239  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
240 
241  if (IncludeBool && ElemTy == MVT::i1) {
242  // Special case for the v512i1, etc.
243  if (8*HwLen == NumElems)
244  return true;
245  // Boolean HVX vector types are formed from regular HVX vector types
246  // by replacing the element type with i1.
247  for (MVT T : ElemTypes)
248  if (NumElems * T.getSizeInBits() == 8*HwLen)
249  return true;
250  return false;
251  }
252 
253  unsigned VecWidth = VecTy.getSizeInBits();
254  if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
255  return false;
256  return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
257  }
258 
259  unsigned getTypeAlignment(MVT Ty) const {
260  if (isHVXVectorType(Ty, true))
261  return getVectorLength();
262  return Ty.getSizeInBits() / 8;
263  }
264 
265  unsigned getL1CacheLineSize() const;
266  unsigned getL1PrefetchDistance() const;
267 
268 private:
269  // Helper function responsible for increasing the latency only.
270  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
271  const;
272  void restoreLatency(SUnit *Src, SUnit *Dst) const;
273  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
274  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
275  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
276 };
277 
278 } // end namespace llvm
279 
280 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
AntiDepBreakMode getAntiDepBreakMode() const override
bool noreturnStackElim() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isVector() const
Return true if this is a vector value type.
Hexagon::ArchEnum HexagonArchVersion
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
Mutate the DAG as a postpass after normal DAG building.
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
const Hexagon::ArchEnum & getHexagonArchVersion() const
const HexagonFrameLowering * getFrameLowering() const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
bool enablePostRAScheduler() const override
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
const HexagonRegisterInfo * getRegisterInfo() const override
Hexagon::ArchEnum HexagonHVXVersion
unsigned getSizeInBits() const
const HexagonTargetLowering * getTargetLowering() const override
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
const std::string & getCPUString() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
MVT getVectorElementType() const
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Scheduling dependency.
Definition: ScheduleDAG.h:49
Move duplicate certain instructions close to their use
Definition: Localizer.cpp:27
Machine Value Type.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
CodeGenOpt::Level OptLevel
void apply(ScheduleDAGInstrs *DAG) override
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1172
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
bool enableMachineScheduler() const override
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool enableMachineSchedDefaultSched() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getVectorLength() const
unsigned getTypeAlignment(MVT Ty) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool useNewValueStores() const
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242