14 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H 15 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H 39 class MachineFrameInfo;
40 class MachineFunction;
42 class MachineLoopInfo;
44 struct MCSchedClassDesc;
46 class PseudoSourceValue;
47 class RegPressureTracker;
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
70 unsigned OperandIndex,
SUnit *
SU)
71 :
VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
136 bool CanHandleTerminators =
false;
139 bool TrackLaneMasks =
false;
206 void addChainDependency(
SUnit *SUa,
SUnit *SUb,
212 addChainDependency(SU,
Entry, Latency);
244 std::vector<std::pair<MachineInstr *, MachineInstr *>>;
257 bool RemoveKillFlags =
false);
292 virtual void finishBlock();
301 unsigned regioninstrs);
304 virtual void exitRegion();
314 bool TrackLaneMasks =
false);
323 void addSchedBarrierDeps();
329 virtual void schedule() = 0;
335 void dumpNode(
const SUnit &SU)
const override;
336 void dump()
const override;
339 std::string getGraphNodeLabel(
const SUnit *SU)
const override;
342 std::string getDAGName()
const override;
349 bool canAddEdge(
SUnit *SuccSU,
SUnit *PredSU);
360 void addPhysRegDataDeps(
SUnit *SU,
unsigned OperIdx);
361 void addPhysRegDeps(
SUnit *SU,
unsigned OperIdx);
362 void addVRegDefDeps(
SUnit *SU,
unsigned OperIdx);
363 void addVRegUseDeps(
SUnit *SU,
unsigned OperIdx);
386 const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
388 SUnits.emplace_back(MI, (
unsigned)SUnits.size());
389 assert((Addr ==
nullptr || Addr == &SUnits[0]) &&
390 "SUnits std::vector reallocated on the fly!");
391 return &SUnits.back();
397 if (I == MISUnitMap.end())
404 #endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries...
const_iterator end(StringRef path)
Get end iterator over path.
A common definition of LaneBitmask for use in TableGen and CodeGen.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
This class represents lattice values for constants.
Record a physical register access.
LivePhysRegs LiveRegs
Set of live physical registers for updating kill flags.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
unsigned getSparseSetIndex() const
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
Provide an instruction scheduling machine model to CodeGen passes.
'undef' values are things that do not have specified contents.
An individual mapping from virtual register number to SUnit.
static unsigned getInt(StringRef R)
Get an unsigned integer, including error checks.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
DbgValueVector DbgValues
Remember instruction that precedes DBG_VALUE.
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
MachineBasicBlock::iterator begin() const
Returns an iterator to the top of the current scheduling region.
ValueType getValue() const
static void addEdge(SmallVectorImpl< LazyCallGraph::Edge > &Edges, DenseMap< LazyCallGraph::Node *, int > &EdgeIndexMap, LazyCallGraph::Node &N, LazyCallGraph::Edge::Kind EK)
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.
SUnit * getSUnit(MachineInstr *MI) const
Returns an existing SUnit for this MI, or nullptr.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
PointerIntPair - This class implements a pair of a pointer and small integer.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Summarize the scheduling resources required for an instruction of a particular scheduling class...
virtual bool doMBBSchedRegionsTopDown() const
If this method returns true, handling of the scheduling regions themselves (in case of a scheduling b...
Track the current register pressure at some position in the instruction stream, and remember the high...
const TargetSchedModel * getSchedModel() const
Gets the machine model for instruction scheduling.
const MCSchedClassDesc * SchedClass
nullptr or resolved SchedClass.
const MachineFrameInfo & MFI
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
The two locations may or may not alias. This is the least precise result.
PhysRegSUOper(SUnit *su, int op, unsigned R)
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)
Reg2SUnitsMap Defs
Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instr...
const MachineLoopInfo * MLI
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
virtual void finalizeSchedule()
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
A set of physical registers with utility functions to track liveness when walking backward/forward th...
void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency)
Adds dependencies as needed from all SUs in list to SU.
Mapping from virtual register to SUnit including an operand index.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
MachineBasicBlock::iterator end() const
Returns an iterator to the bottom of the current scheduling region.
SUnit * newSUnit(MachineInstr *MI)
Creates a new SUnit and return a ptr to it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
UnderlyingObject(ValueType V, bool MayAlias)
MachineBasicBlock * BB
The block in which to insert instructions.
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
unsigned getSparseSetIndex() const
Scheduling unit. This is a node in the scheduling DAG.
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...