85 if (&Subtarget == &NewSubtarget)
88 Names2InstrOpCodes.clear();
90 Names2RegMasks.clear();
91 Names2SubRegIndices.clear();
92 Names2TargetIndices.clear();
93 Names2DirectTargetFlags.clear();
94 Names2BitmaskTargetFlags.clear();
95 Names2MMOTargetFlags.clear();
97 initNames2RegClasses();
101void PerTargetMIParsingState::initNames2Regs() {
102 if (!Names2Regs.empty())
106 Names2Regs.insert(std::make_pair(
"noreg", 0));
108 assert(
TRI &&
"Expected target register info");
110 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
115 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
122 auto RegInfo = Names2Regs.find(
RegName);
123 if (RegInfo == Names2Regs.end())
125 Reg = RegInfo->getValue();
131 const auto *
TRI = Subtarget.getRegisterInfo();
132 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
139void PerTargetMIParsingState::initNames2InstrOpCodes() {
140 if (!Names2InstrOpCodes.
empty())
143 assert(
TII &&
"Expected target instruction info");
144 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
150 initNames2InstrOpCodes();
151 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
152 if (InstrInfo == Names2InstrOpCodes.end())
154 OpCode = InstrInfo->getValue();
158void PerTargetMIParsingState::initNames2RegMasks() {
159 if (!Names2RegMasks.
empty())
162 assert(
TRI &&
"Expected target register info");
166 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
168 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
172 initNames2RegMasks();
173 auto RegMaskInfo = Names2RegMasks.find(Identifier);
174 if (RegMaskInfo == Names2RegMasks.end())
176 return RegMaskInfo->getValue();
179void PerTargetMIParsingState::initNames2SubRegIndices() {
180 if (!Names2SubRegIndices.
empty())
183 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
184 Names2SubRegIndices.
insert(
185 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
189 initNames2SubRegIndices();
190 auto SubRegInfo = Names2SubRegIndices.find(Name);
191 if (SubRegInfo == Names2SubRegIndices.end())
193 return SubRegInfo->getValue();
196void PerTargetMIParsingState::initNames2TargetIndices() {
197 if (!Names2TargetIndices.
empty())
200 assert(
TII &&
"Expected target instruction info");
201 auto Indices =
TII->getSerializableTargetIndices();
202 for (
const auto &
I : Indices)
207 initNames2TargetIndices();
208 auto IndexInfo = Names2TargetIndices.find(Name);
209 if (IndexInfo == Names2TargetIndices.end())
211 Index = IndexInfo->second;
215void PerTargetMIParsingState::initNames2DirectTargetFlags() {
216 if (!Names2DirectTargetFlags.
empty())
220 assert(
TII &&
"Expected target instruction info");
221 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
222 for (
const auto &
I : Flags)
223 Names2DirectTargetFlags.
insert(
229 initNames2DirectTargetFlags();
230 auto FlagInfo = Names2DirectTargetFlags.find(Name);
231 if (FlagInfo == Names2DirectTargetFlags.end())
233 Flag = FlagInfo->second;
237void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
238 if (!Names2BitmaskTargetFlags.
empty())
242 assert(
TII &&
"Expected target instruction info");
243 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
244 for (
const auto &
I : Flags)
245 Names2BitmaskTargetFlags.
insert(
251 initNames2BitmaskTargetFlags();
252 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
253 if (FlagInfo == Names2BitmaskTargetFlags.end())
255 Flag = FlagInfo->second;
259void PerTargetMIParsingState::initNames2MMOTargetFlags() {
260 if (!Names2MMOTargetFlags.
empty())
264 assert(
TII &&
"Expected target instruction info");
265 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
266 for (
const auto &
I : Flags)
272 initNames2MMOTargetFlags();
273 auto FlagInfo = Names2MMOTargetFlags.find(Name);
274 if (FlagInfo == Names2MMOTargetFlags.end())
276 Flag = FlagInfo->second;
280void PerTargetMIParsingState::initNames2RegClasses() {
281 if (!Names2RegClasses.
empty())
285 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
286 const auto *RC =
TRI->getRegClass(
I);
292void PerTargetMIParsingState::initNames2RegBanks() {
293 if (!Names2RegBanks.empty())
296 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
304 Names2RegBanks.insert(
305 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
311 auto RegClassInfo = Names2RegClasses.find(Name);
312 if (RegClassInfo == Names2RegClasses.end())
314 return RegClassInfo->getValue();
318 auto RegBankInfo = Names2RegBanks.find(Name);
319 if (RegBankInfo == Names2RegBanks.end())
321 return RegBankInfo->getValue();
334 Info->
VReg =
MRI.createIncompleteVirtualRegister();
335 I.first->second = Info;
337 return *
I.first->second;
346 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
347 I.first->second = Info;
349 return *
I.first->second;
357 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
365 for (
const auto &Arg :
F.args())
367 for (
const auto &BB :
F) {
369 for (
const auto &
I : BB)
384struct ParsedMachineOperand {
388 std::optional<unsigned> TiedDefIdx;
392 std::optional<unsigned> &TiedDefIdx)
393 : Operand(Operand), Begin(Begin),
End(
End), TiedDefIdx(TiedDefIdx) {
396 "Only used register operands can be tied");
403 StringRef
Source, CurrentSource;
405 PerFunctionMIParsingState &PFS;
407 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
410 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
415 void lex(
unsigned SkipChar = 0);
428 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
429 bool parseBasicBlocks();
431 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
433 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
435 bool parseStandaloneStackObject(
int &FI);
436 bool parseStandaloneMDNode(MDNode *&Node);
439 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
440 bool parseBasicBlock(MachineBasicBlock &
MBB,
441 MachineBasicBlock *&AddFalthroughFrom);
442 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
443 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
446 bool parseVirtualRegister(VRegInfo *&Info);
447 bool parseNamedVirtualRegister(VRegInfo *&Info);
448 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
449 bool parseRegisterFlag(
RegState &Flags);
450 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
451 bool parseSubRegisterIndex(
unsigned &SubReg);
452 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
453 bool parseRegisterOperand(MachineOperand &Dest,
454 std::optional<unsigned> &TiedDefIdx,
456 bool parseImmediateOperand(MachineOperand &Dest);
457 bool parseSymbolicInlineAsmOperand(
unsigned OpIdx, MachineOperand &Dest);
462 bool parseTypedImmediateOperand(MachineOperand &Dest);
463 bool parseFPImmediateOperand(MachineOperand &Dest);
465 bool parseMBBOperand(MachineOperand &Dest);
466 bool parseStackFrameIndex(
int &FI);
467 bool parseStackObjectOperand(MachineOperand &Dest);
468 bool parseFixedStackFrameIndex(
int &FI);
469 bool parseFixedStackObjectOperand(MachineOperand &Dest);
471 bool parseGlobalAddressOperand(MachineOperand &Dest);
472 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
473 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
474 bool parseJumpTableIndexOperand(MachineOperand &Dest);
475 bool parseExternalSymbolOperand(MachineOperand &Dest);
476 bool parseMCSymbolOperand(MachineOperand &Dest);
478 bool parseDIExpression(MDNode *&Expr);
479 bool parseDILocation(MDNode *&Expr);
480 bool parseMetadataOperand(MachineOperand &Dest);
481 bool parseCFIOffset(
int &
Offset);
482 bool parseCFIUnsigned(
unsigned &
Value);
483 bool parseCFIRegister(
unsigned &
Reg);
485 bool parseCFIEscapeValues(std::string&
Values);
486 bool parseCFIOperand(MachineOperand &Dest);
487 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
488 bool parseBlockAddressOperand(MachineOperand &Dest);
489 bool parseIntrinsicOperand(MachineOperand &Dest);
490 bool parsePredicateOperand(MachineOperand &Dest);
491 bool parseShuffleMaskOperand(MachineOperand &Dest);
492 bool parseTargetIndexOperand(MachineOperand &Dest);
493 bool parseDbgInstrRefOperand(MachineOperand &Dest);
494 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
495 bool parseLaneMaskOperand(MachineOperand &Dest);
496 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
497 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
498 MachineOperand &Dest,
499 std::optional<unsigned> &TiedDefIdx);
500 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
501 const unsigned OpIdx,
502 MachineOperand &Dest,
503 std::optional<unsigned> &TiedDefIdx);
504 bool parseOffset(int64_t &
Offset);
505 bool parseIRBlockAddressTaken(BasicBlock *&BB);
507 bool parseAddrspace(
unsigned &Addrspace);
508 bool parseSectionID(std::optional<MBBSectionID> &SID);
509 bool parseBBID(std::optional<UniqueBBID> &BBID);
510 bool parseCallFrameSize(
unsigned &CallFrameSize);
511 bool parseMaxBytesForAlignment(
unsigned &MaxBytesForAlignment);
513 bool parseOperandsOffset(MachineOperand &
Op);
516 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
517 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
520 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
521 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
522 bool parseHeapAllocMarker(MDNode *&Node);
523 bool parsePCSections(MDNode *&Node);
524 bool parseMMRA(MDNode *&Node);
526 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
527 MachineOperand &Dest,
const MIRFormatter &MF);
554 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
556 bool assignRegisterTies(MachineInstr &
MI,
560 const MCInstrDesc &MCID);
566 MCSymbol *getOrCreateMCSymbol(StringRef Name);
570 bool parseStringConstant(std::string &Result);
580void MIParser::lex(
unsigned SkipChar) {
582 CurrentSource.substr(SkipChar), Token,
586bool MIParser::error(
const Twine &
Msg) {
return error(Token.location(),
Msg); }
621 return "<unknown token>";
626 if (Token.isNot(TokenKind))
633 if (Token.isNot(TokenKind))
640bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
646 return error(
"Unknown Section ID");
649 const StringRef &S = Token.stringValue();
650 if (S ==
"Exception")
652 else if (S ==
"Cold")
655 return error(
"Unknown Section ID");
662bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
664 return error(
"expected 'bb_id'");
667 unsigned CloneID = 0;
670 auto Parts = S.
split(
'.');
671 if (Parts.first.getAsInteger(10, BaseID) ||
672 Parts.second.getAsInteger(10, CloneID))
673 return error(
"Unknown BB ID");
677 return error(
"Unknown BB ID");
682 return error(
"Unknown Clone ID");
686 return error(
"Unknown Clone ID");
690 BBID = {BaseID, CloneID};
695bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
700 return error(
"Unknown call frame size");
701 CallFrameSize =
Value;
708bool MIParser::parseMaxBytesForAlignment(
unsigned &MaxBytesForAlignment) {
712 return error(
"expected an integer literal after 'max-bytes-for-alignment'");
716 MaxBytesForAlignment =
Value;
723 std::optional<UniqueBBID> BBID;
732bool MIParser::parseBasicBlockDefinition(
738 auto Loc = Token.location();
739 auto Name = Token.stringValue();
741 bool MachineBlockAddressTaken =
false;
742 bool LabelMustBeEmitted =
false;
744 bool IsLandingPad =
false;
745 bool IsInlineAsmBrIndirectTarget =
false;
746 bool IsEHFuncletEntry =
false;
747 bool IsEHScopeEntry =
false;
748 bool IsCleanupFuncletEntry =
false;
749 bool IsEHContTarget =
false;
750 std::optional<MBBSectionID> SectionID;
752 unsigned MaxBytesForAlignment = 0;
753 std::optional<UniqueBBID> BBID;
754 unsigned CallFrameSize = 0;
759 switch (Token.kind()) {
761 MachineBlockAddressTaken =
true;
765 LabelMustBeEmitted =
true;
769 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
777 IsInlineAsmBrIndirectTarget =
true;
781 IsEHFuncletEntry =
true;
785 IsEHScopeEntry =
true;
789 IsCleanupFuncletEntry =
true;
793 IsEHContTarget =
true;
801 if (parseMaxBytesForAlignment(MaxBytesForAlignment))
807 if (parseIRBlock(BB, MF.getFunction()))
812 if (parseSectionID(SectionID))
820 if (parseCallFrameSize(CallFrameSize))
835 MF.getFunction().getValueSymbolTable()->lookup(Name));
838 "' is not defined in the function '" +
841 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
843 bool WasInserted = MBBSlots.
insert(std::make_pair(ID,
MBB)).second;
845 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
849 else if (MaxBytesForAlignment)
850 return error(
Loc,
"'max-bytes-for-alignment' requires 'align'");
852 if (MachineBlockAddressTaken)
854 if (LabelMustBeEmitted)
856 if (AddressTakenIRBlock)
872bool MIParser::parseBasicBlockDefinitions(
878 if (Token.isErrorOrEOF())
879 return Token.isError();
881 return error(
"expected a basic block definition before instructions");
882 unsigned BraceDepth = 0;
884 if (parseBasicBlockDefinition(MBBSlots))
886 bool IsAfterNewline =
false;
890 Token.isErrorOrEOF())
893 return error(
"basic block definition should be located at the start of "
896 IsAfterNewline =
true;
899 IsAfterNewline =
false;
904 return error(
"extraneous closing brace ('}')");
910 if (!Token.isError() && BraceDepth)
911 return error(
"expected '}'");
912 }
while (!Token.isErrorOrEOF());
913 return Token.isError();
921 if (Token.isNewlineOrEOF())
925 return error(
"expected a named register");
927 if (parseNamedRegister(
Reg))
935 return error(
"expected a lane mask");
937 "Use correct get-function for lane mask");
940 return error(
"invalid lane mask value");
954 if (Token.isNewlineOrEOF())
958 return error(
"expected a machine basic block reference");
967 return error(
"expected an integer literal after '('");
1001 bool ExplicitSuccessors =
false;
1004 if (parseBasicBlockSuccessors(
MBB))
1006 ExplicitSuccessors =
true;
1008 if (parseBasicBlockLiveins(
MBB))
1015 if (!Token.isNewlineOrEOF())
1016 return error(
"expected line break at the end of a list");
1021 bool IsInBundle =
false;
1045 return error(
"nested instruction bundles are not allowed");
1054 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1059 if (!ExplicitSuccessors) {
1066 if (IsFallthrough) {
1067 AddFalthroughFrom = &
MBB;
1076bool MIParser::parseBasicBlocks() {
1081 if (Token.isErrorOrEOF())
1082 return Token.isError();
1091 if (AddFalthroughFrom) {
1095 AddFalthroughFrom =
nullptr;
1097 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1110 while (Token.isRegister() || Token.isRegisterFlag()) {
1111 auto Loc = Token.location();
1112 std::optional<unsigned> TiedDefIdx;
1113 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1116 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1125 if (Token.isError() || parseInstruction(OpCode, Flags))
1138 auto Loc = Token.location();
1139 std::optional<unsigned> TiedDefIdx;
1140 if (parseMachineOperandAndTargetFlags(OpCode,
Operands.size(), MO, TiedDefIdx))
1143 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1148 return error(
"expected ',' before the next machine operand");
1152 MCSymbol *PreInstrSymbol =
nullptr;
1154 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1156 MCSymbol *PostInstrSymbol =
nullptr;
1158 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1160 MDNode *HeapAllocMarker =
nullptr;
1162 if (parseHeapAllocMarker(HeapAllocMarker))
1164 MDNode *PCSections =
nullptr;
1166 if (parsePCSections(PCSections))
1171 unsigned CFIType = 0;
1175 return error(
"expected an integer literal after 'cfi-type'");
1193 unsigned InstrNum = 0;
1197 return error(
"expected an integer literal after 'debug-instr-number'");
1214 if (parseDILocation(Node))
1217 return error(
"expected a metadata node after 'debug-location'");
1221 return error(
"referenced metadata is not a DILocation");
1228 while (!Token.isNewlineOrEOF()) {
1230 if (parseMachineMemoryOperand(
MemOp))
1233 if (Token.isNewlineOrEOF())
1238 return error(
"expected ',' before the next machine memory operand");
1243 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1244 if (!
MCID.isVariadic()) {
1250 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1251 MI->setFlags(Flags);
1255 for (
const auto &Operand :
Operands)
1256 MI->addOperand(MF, Operand.Operand);
1261 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1262 if (PostInstrSymbol)
1263 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1264 if (HeapAllocMarker)
1265 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1267 MI->setPCSections(MF, PCSections);
1269 MI->setMMRAMetadata(MF, MMRA);
1271 MI->setCFIType(MF, CFIType);
1273 MI->setDeactivationSymbol(MF, DS);
1274 if (!MemOperands.
empty())
1275 MI->setMemRefs(MF, MemOperands);
1277 MI->setDebugInstrNum(InstrNum);
1284 return error(
"expected a machine basic block reference");
1290 "expected end of string after the machine basic block reference");
1294bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1297 return error(
"expected a named register");
1298 if (parseNamedRegister(
Reg))
1302 return error(
"expected end of string after the register reference");
1306bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1309 return error(
"expected a virtual register");
1310 if (parseVirtualRegister(Info))
1314 return error(
"expected end of string after the register reference");
1318bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1322 return error(
"expected either a named or virtual register");
1325 if (parseRegister(
Reg, Info))
1330 return error(
"expected end of string after the register reference");
1334bool MIParser::parseStandaloneStackObject(
int &FI) {
1337 return error(
"expected a stack object");
1338 if (parseStackFrameIndex(FI))
1341 return error(
"expected end of string after the stack object reference");
1345bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1351 if (parseDIExpression(Node))
1354 if (parseDILocation(Node))
1357 return error(
"expected a metadata node");
1360 return error(
"expected end of string after the metadata node");
1366 return MO.
isDef() ?
"implicit-def" :
"implicit";
1371 assert(
Reg.isPhysical() &&
"expected phys reg");
1399 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1400 assert(
TRI &&
"Expected target register info");
1401 for (
const auto &
I : ImplicitOperands) {
1405 Twine(
"missing implicit register operand '") +
1412bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1487 return error(
"expected a machine instruction");
1488 StringRef InstrName = Token.stringValue();
1489 if (PFS.Target.parseInstrName(InstrName, OpCode))
1490 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1498 if (PFS.Target.getRegisterByName(Name,
Reg))
1499 return error(
Twine(
"unknown register name '") + Name +
"'");
1503bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1508 Info = &PFS.getVRegInfoNamed(Name);
1512bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1514 return parseNamedVirtualRegister(Info);
1519 Info = &PFS.getVRegInfo(ID);
1524 switch (Token.kind()) {
1529 return parseNamedRegister(
Reg);
1532 if (parseVirtualRegister(Info))
1542bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1544 return error(
"expected '_', register class, or register bank name");
1553 switch (RegInfo.
Kind) {
1559 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1568 return error(
Loc,
"register class specification on generic register");
1576 RegBank = PFS.Target.getRegBank(Name);
1578 return error(
Loc,
"expected '_', register class, or register bank name");
1583 switch (RegInfo.
Kind) {
1589 return error(
Loc,
"conflicting generic register banks");
1595 return error(
Loc,
"register bank specification on normal register");
1600bool MIParser::parseRegisterFlag(
RegState &Flags) {
1602 switch (Token.kind()) {
1636 if (OldFlags == Flags)
1639 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1644bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
1648 return error(
"expected a subregister index after '.'");
1649 auto Name = Token.stringValue();
1650 SubReg = PFS.Target.getSubRegIndex(Name);
1652 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1657bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1661 return error(
"expected an integer literal after 'tied-def'");
1676 unsigned DefIdx = *
Operands[
I].TiedDefIdx;
1679 Twine(
"use of invalid tied-def operand index '" +
1680 Twine(DefIdx) +
"'; instruction has only ") +
1682 const auto &DefOperand =
Operands[DefIdx].Operand;
1683 if (!DefOperand.isReg() || !DefOperand.isDef())
1686 Twine(
"use of invalid tied-def operand index '") +
1687 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1688 " isn't a defined register");
1690 for (
const auto &TiedPair : TiedRegisterPairs) {
1691 if (TiedPair.first == DefIdx)
1693 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1694 " is already tied with another register operand");
1696 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1700 for (
const auto &TiedPair : TiedRegisterPairs)
1701 MI.tieOperands(TiedPair.first, TiedPair.second);
1706 std::optional<unsigned> &TiedDefIdx,
1709 while (Token.isRegisterFlag()) {
1710 if (parseRegisterFlag(Flags))
1715 if (!Token.isRegister())
1716 return error(
"expected a register after register flags");
1719 if (parseRegister(
Reg, RegInfo))
1722 unsigned SubReg = 0;
1724 if (parseSubRegisterIndex(SubReg))
1727 return error(
"subregister index expects a virtual register");
1731 return error(
"register class specification expects a virtual register");
1733 if (parseRegisterClassOrBank(*RegInfo))
1742 return error(
"tied-def not supported for defs");
1744 if (parseRegisterTiedDefIndex(Idx))
1749 return error(
"unexpected type on physical register");
1753 if (parseLowLevelType(Token.location(), Ty))
1755 :
error(
"expected tied-def or low-level type after '('");
1762 return error(
"inconsistent type for generic virtual register");
1772 return error(
"generic virtual registers must have a type");
1777 return error(
"cannot have a killed def operand");
1780 return error(
"cannot have a dead use operand");
1797 const APSInt &
Int = Token.integerValue();
1798 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1800 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1803 return error(
"integer literal is too large to be an immediate operand");
1808bool MIParser::parseSymbolicInlineAsmOperand(
unsigned OpIdx,
1812 "expected symbolic inline asm operand");
1816 unsigned ExtraInfo = 0;
1821 StringRef FlagName = Token.stringValue();
1829 .
Case(
"attdialect", 0)
1833 return error(
"unknown inline asm extra info flag '" + FlagName +
"'");
1844 StringRef KindStr = Token.stringValue();
1855 if (K == InvalidKind)
1856 return error(
"unknown inline asm operand kind '" + KindStr +
"'");
1867 return error(
"expected ':' after 'tiedto'");
1870 return error(
"expected '$N' operand number after 'tiedto:'");
1872 if (Token.stringValue().getAsInteger(10, OperandNo))
1873 return error(
"invalid operand number in tiedto constraint");
1876 F.setMatchingOp(OperandNo);
1888 "expected register class or memory constraint name after ':'");
1890 StringRef ConstraintStr = Token.stringValue();
1891 if (
F.isMemKind()) {
1925 return error(
"unknown memory constraint '" + ConstraintStr +
"'");
1926 F.setMemConstraint(
CC);
1927 }
else if (
F.isRegDefKind() ||
F.isRegUseKind() ||
1928 F.isRegDefEarlyClobberKind()) {
1930 PFS.Target.getRegClass(ConstraintStr.
lower());
1932 return error(
"unknown register class '" + ConstraintStr +
"'");
1933 F.setRegClass(RC->
getID());
1943 if (!
F.isRegDefKind() && !
F.isRegUseKind() && !
F.isRegDefEarlyClobberKind())
1944 return error(
"only a register operand can be 'foldable'");
1946 F.setRegMayBeFolded(
true);
1954bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1955 const unsigned OpIdx,
1959 auto Loc = Token.location();
1965 Len += Token.range().size();
1974 Src =
StringRef(
Loc, Len + Token.stringValue().size());
1979 ->
bool { return error(Loc, Msg); }))
1991 auto Source = StringValue.
str();
1996 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
2002 return ::parseIRConstant(
2003 Loc, StringValue, PFS,
C,
2023 return NumElts != 0 && (HasVScale || NumElts != 1) &&
isUInt<16>(NumElts);
2037 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2040 bool Scalar = Token.range().starts_with(
"s");
2041 if (Scalar || Token.range().starts_with(
"i")) {
2050 return error(
"invalid size for scalar type");
2057 if (Token.range().starts_with(
"p")) {
2061 return error(
"invalid address space number");
2068 if (Token.range().starts_with(
"f") || Token.range().starts_with(
"bf")) {
2071 return error(
"invalid size for scalar type");
2073 if (Token.range().starts_with(
"bf") && ScalarSize != 16)
2074 return error(
"invalid size for bfloat");
2077 :
LLT::floatIEEE(ScalarSize);
2084 return error(
Loc,
"expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, "
2085 "or <vscale x M x pA> for GlobalISel type, "
2086 "where t = {'s', 'i', 'f', 'bf'}");
2095 "expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
2099 auto GetError = [
this, &HasVScale,
Loc]() {
2101 return error(
Loc,
"expected <vscale x M x tN> for vector type, where t = "
2102 "{'s', 'i', 'f', 'bf', 'p'}");
2103 return error(
Loc,
"expected <M x tN> for vector type, where t = {'s', 'i', "
2109 uint64_t NumElements = Token.integerValue().getZExtValue();
2111 return error(
"invalid number of vector elements");
2119 StringRef VectorTyDigits = Token.range();
2128 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2130 Scalar = Token.range().starts_with(
"s");
2131 if (Scalar || Token.range().starts_with(
"i")) {
2134 return error(
"invalid size for scalar element in vector");
2136 }
else if (Token.range().starts_with(
"p")) {
2140 return error(
"invalid address space number");
2143 }
else if (Token.range().starts_with(
"f")) {
2146 return error(
"invalid size for float element in vector");
2148 }
else if (Token.range().starts_with(
"bf")) {
2151 return error(
"invalid size for bfloat element in vector");
2173 return error(
"a typed immediate operand should start with one of 'i', "
2174 "'s', 'f', 'bf', or 'p'");
2177 "expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
2179 auto Loc = Token.location();
2183 !(Token.range() ==
"true" || Token.range() ==
"false"))
2184 return error(
"expected an integer literal");
2194 auto Loc = Token.location();
2198 return error(
"expected a floating point literal");
2209 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2211 if (!isxdigit(S[2]))
2214 APInt A(V.size()*4, V, 16);
2218 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2229 return ErrCB(Token.
location(),
"expected unsigned integer");
2232 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2240 if (
A.getBitWidth() > 32)
2241 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2242 Result =
A.getZExtValue();
2248bool MIParser::getUnsigned(
unsigned &Result) {
2249 return ::getUnsigned(
2261 auto MBBInfo = PFS.MBBSlots.find(
Number);
2262 if (MBBInfo == PFS.MBBSlots.end())
2263 return error(
Twine(
"use of undefined machine basic block #") +
2265 MBB = MBBInfo->second;
2268 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2270 " isn't '" + Token.stringValue() +
"'");
2283bool MIParser::parseStackFrameIndex(
int &FI) {
2288 auto ObjectInfo = PFS.StackObjectSlots.find(ID);
2289 if (ObjectInfo == PFS.StackObjectSlots.end())
2290 return error(
Twine(
"use of undefined stack object '%stack.") +
Twine(ID) +
2293 if (
const auto *Alloca =
2294 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2295 Name = Alloca->getName();
2296 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2297 return error(
Twine(
"the name of the stack object '%stack.") +
Twine(ID) +
2298 "' isn't '" + Token.stringValue() +
"'");
2300 FI = ObjectInfo->second;
2306 if (parseStackFrameIndex(FI))
2312bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2317 auto ObjectInfo = PFS.FixedStackObjectSlots.find(ID);
2318 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2319 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2322 FI = ObjectInfo->second;
2326bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2328 if (parseFixedStackFrameIndex(FI))
2337 switch (Token.
kind()) {
2342 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2343 Token.
range() +
"'");
2352 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2353 Twine(GVIdx) +
"'");
2362bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2363 return ::parseGlobalValue(
2376 if (parseOperandsOffset(Dest))
2381bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2388 return error(
"use of undefined constant '%const." +
Twine(ID) +
"'");
2391 if (parseOperandsOffset(Dest))
2401 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(ID);
2402 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2403 return error(
"use of undefined jump table '%jump-table." +
Twine(ID) +
"'");
2411 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2414 if (parseOperandsOffset(Dest))
2424 if (parseOperandsOffset(Dest))
2429bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2432 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2433 if (SubRegIndex == 0)
2434 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2440bool MIParser::parseMDNode(
MDNode *&Node) {
2443 auto Loc = Token.location();
2446 return error(
"expected metadata id after '!'");
2450 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(ID);
2451 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2452 NodeInfo = PFS.MachineMetadataNodes.find(ID);
2453 if (NodeInfo == PFS.MachineMetadataNodes.end())
2454 return error(
Loc,
"use of undefined metadata '!" +
Twine(ID) +
"'");
2457 Node = NodeInfo->second.get();
2461bool MIParser::parseDIExpression(
MDNode *&Expr) {
2464 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2466 CurrentSource = CurrentSource.substr(
Read);
2473bool MIParser::parseDILocation(
MDNode *&
Loc) {
2477 bool HaveLine =
false;
2479 unsigned Column = 0;
2481 MDNode *InlinedAt =
nullptr;
2482 bool ImplicitCode =
false;
2485 MDNode *IRLayers =
nullptr;
2493 if (Token.stringValue() ==
"line") {
2498 Token.integerValue().isSigned())
2499 return error(
"expected unsigned integer");
2500 Line = Token.integerValue().getZExtValue();
2505 if (Token.stringValue() ==
"column") {
2510 Token.integerValue().isSigned())
2511 return error(
"expected unsigned integer");
2512 Column = Token.integerValue().getZExtValue();
2516 if (Token.stringValue() ==
"scope") {
2521 return error(
"expected metadata node");
2523 return error(
"expected DIScope node");
2526 if (Token.stringValue() ==
"inlinedAt") {
2534 if (parseDILocation(InlinedAt))
2537 return error(
"expected metadata node");
2540 return error(
"expected DILocation node");
2543 if (Token.stringValue() ==
"isImplicitCode") {
2548 return error(
"expected true/false");
2552 if (Token.stringValue() ==
"true")
2553 ImplicitCode =
true;
2554 else if (Token.stringValue() ==
"false")
2555 ImplicitCode =
false;
2557 return error(
"expected true/false");
2561 if (Token.stringValue() ==
"atomGroup") {
2566 Token.integerValue().isSigned())
2567 return error(
"expected unsigned integer");
2568 AtomGroup = Token.integerValue().getZExtValue();
2572 if (Token.stringValue() ==
"atomRank") {
2577 Token.integerValue().isSigned())
2578 return error(
"expected unsigned integer");
2579 AtomRank = Token.integerValue().getZExtValue();
2583 if (Token.stringValue() ==
"irlayers") {
2588 return error(
"expected metadata node");
2590 return error(
"expected DILayerLocList node");
2594 return error(
Twine(
"invalid DILocation argument '") +
2595 Token.stringValue() +
"'");
2603 return error(
"DILocation requires line number");
2605 return error(
"DILocation requires a scope");
2608 InlinedAt, ImplicitCode, AtomGroup, AtomRank, IRLayers);
2618 if (parseDIExpression(Node))
2625bool MIParser::parseCFIOffset(
int &
Offset) {
2627 return error(
"expected a cfi offset");
2628 if (Token.integerValue().getSignificantBits() > 32)
2629 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2630 Offset = (int)Token.integerValue().getExtValue();
2635bool MIParser::parseCFIUnsigned(
unsigned &
Value) {
2642bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2644 return error(
"expected a cfi register");
2646 if (parseNamedRegister(LLVMReg))
2648 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2649 assert(
TRI &&
"Expected target register info");
2650 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2652 return error(
"invalid DWARF register");
2653 Reg = (unsigned)DwarfReg;
2658bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2660 return error(
"expected a cfi address space literal");
2661 if (Token.integerValue().isSigned())
2662 return error(
"expected an unsigned integer (cfi address space)");
2668bool MIParser::parseCFIEscapeValues(std::string &
Values) {
2671 return error(
"expected a hexadecimal literal");
2675 if (
Value > UINT8_MAX)
2676 return error(
"expected a 8-bit integer (too large)");
2684 auto Kind = Token.kind();
2692 if (parseCFIRegister(
Reg))
2707 CFIIndex = MF.addFrameInst(
2711 if (parseCFIRegister(
Reg))
2717 if (parseCFIOffset(
Offset))
2723 if (parseCFIOffset(
Offset))
2725 CFIIndex = MF.addFrameInst(
2747 if (parseCFIRegister(
Reg))
2755 if (parseCFIRegister(
Reg))
2762 parseCFIRegister(Reg2))
2785 PACSym = getOrCreateMCSymbol(Token.stringValue());
2787 CFIIndex = MF.addFrameInst(
2791 if (parseCFIOffset(
Offset))
2793 CFIIndex = MF.addFrameInst(
2796 return error(
"expected '<mcsymbol ...>' or integer offset for "
2797 "cfi_set_ra_state");
2802 unsigned Reg, R1,
R2;
2803 unsigned R1Size, R2Size;
2808 parseCFIUnsigned(R2Size))
2812 nullptr,
Reg, R1, R1Size,
R2, R2Size));
2816 std::vector<MCCFIInstruction::VectorRegisterWithLane> VectorRegisters;
2821 unsigned Lane,
Size;
2824 parseCFIUnsigned(
Size))
2826 VectorRegisters.push_back({VR, Lane,
Size});
2830 nullptr,
Reg, std::move(VectorRegisters)));
2834 unsigned Reg, MaskReg;
2835 unsigned RegSize, MaskRegSize;
2841 parseCFIUnsigned(MaskRegSize) || expectAndConsume(
MIToken::comma) ||
2850 unsigned Reg, SpillReg, MaskReg;
2851 unsigned SpillRegLaneSize, MaskRegSize;
2854 parseCFIRegister(SpillReg) || expectAndConsume(
MIToken::comma) ||
2855 parseCFIUnsigned(SpillRegLaneSize) ||
2857 expectAndConsume(
MIToken::comma) || parseCFIUnsigned(MaskRegSize))
2861 nullptr,
Reg, SpillReg, SpillRegLaneSize, MaskReg, MaskRegSize));
2866 if (parseCFIEscapeValues(
Values))
2880 switch (Token.kind()) {
2883 F.getValueSymbolTable()->lookup(Token.stringValue()));
2885 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2889 unsigned SlotNumber = 0;
2892 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2894 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2895 Twine(SlotNumber) +
"'");
2911 return error(
"expected a global value");
2917 return error(
"expected an IR function reference");
2923 return error(
"expected an IR block reference");
2924 if (parseIRBlock(BB, *
F))
2930 if (parseOperandsOffset(Dest))
2939 return error(
"expected syntax intrinsic(@llvm.whatever)");
2942 return error(
"expected syntax intrinsic(@llvm.whatever)");
2944 std::string
Name = std::string(Token.stringValue());
2948 return error(
"expected ')' to terminate intrinsic name");
2953 return error(
"unknown intrinsic name");
2965 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2968 return error(
"whatever");
2991 return error(
"invalid floating-point predicate");
3006 return error(
"invalid integer predicate");
3012 return error(
"predicate should be terminated by ')'.");
3022 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
3029 const APSInt &
Int = Token.integerValue();
3032 return error(
"expected integer constant");
3039 return error(
"shufflemask should be terminated by ')'.");
3041 if (ShufMask.
size() < 2)
3042 return error(
"shufflemask should have > 1 element");
3054 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3057 return error(
"expected unsigned integer for instruction index");
3058 uint64_t InstrIdx = Token.integerValue().getZExtValue();
3059 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
3060 "Instruction reference's instruction index is too large");
3064 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3067 return error(
"expected unsigned integer for operand index");
3068 uint64_t OpIdx = Token.integerValue().getZExtValue();
3069 assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
3070 "Instruction reference's operand index is too large");
3074 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3086 return error(
"expected the name of the target index");
3088 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
3089 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
3094 if (parseOperandsOffset(Dest))
3099bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
3100 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
3105 uint32_t *
Mask = MF.allocateRegMask();
3109 return error(
"expected a named register");
3111 if (parseNamedRegister(
Reg))
3135 return error(
"expected a valid lane mask value");
3137 "Use correct get-function for lane mask.");
3151bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
3153 uint32_t *
Mask = MF.allocateRegMask();
3159 return error(
"expected a named register");
3161 if (parseNamedRegister(
Reg))
3176bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
3178 std::optional<unsigned> &TiedDefIdx) {
3179 switch (Token.kind()) {
3194 return parseRegisterOperand(Dest, TiedDefIdx);
3198 return parseImmediateOperand(Dest);
3206 return parseFPImmediateOperand(Dest);
3208 return parseMBBOperand(Dest);
3210 return parseStackObjectOperand(Dest);
3212 return parseFixedStackObjectOperand(Dest);
3215 return parseGlobalAddressOperand(Dest);
3217 return parseConstantPoolIndexOperand(Dest);
3219 return parseJumpTableIndexOperand(Dest);
3221 return parseExternalSymbolOperand(Dest);
3223 return parseMCSymbolOperand(Dest);
3225 return parseSubRegisterIndexOperand(Dest);
3228 return parseMetadataOperand(Dest);
3251 return parseCFIOperand(Dest);
3253 return parseBlockAddressOperand(Dest);
3255 return parseIntrinsicOperand(Dest);
3257 return parseTargetIndexOperand(Dest);
3259 return parseLaneMaskOperand(Dest);
3261 return parseLiveoutRegisterMaskOperand(Dest);
3264 return parsePredicateOperand(Dest);
3266 return parseShuffleMaskOperand(Dest);
3268 return parseDbgInstrRefOperand(Dest);
3272 bool IsInlineAsm =
OpCode == TargetOpcode::INLINEASM ||
3273 OpCode == TargetOpcode::INLINEASM_BR;
3275 return parseSymbolicInlineAsmOperand(OpIdx, Dest);
3278 if (
const auto *RegMask = PFS.Target.getRegMask(Id)) {
3282 }
else if (Id ==
"CustomRegMask") {
3283 return parseCustomRegisterMaskOperand(Dest);
3285 return parseTypedImmediateOperand(Dest);
3289 const auto *
TII = MF.getSubtarget().getInstrInfo();
3290 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3291 return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter);
3297 return error(
"expected a machine operand");
3302bool MIParser::parseMachineOperandAndTargetFlags(
3303 const unsigned OpCode,
const unsigned OpIdx,
MachineOperand &Dest,
3304 std::optional<unsigned> &TiedDefIdx) {
3306 bool HasTargetFlags =
false;
3308 HasTargetFlags =
true;
3313 return error(
"expected the name of the target flag");
3314 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3315 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3316 return error(
"use of undefined target flag '" + Token.stringValue() +
3323 return error(
"expected the name of the target flag");
3324 unsigned BitFlag = 0;
3325 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3326 return error(
"use of undefined target flag '" + Token.stringValue() +
3335 auto Loc = Token.location();
3336 if (parseMachineOperand(OpCode, OpIdx, Dest, TiedDefIdx))
3338 if (!HasTargetFlags)
3341 return error(
Loc,
"register operands can't have target flags");
3346bool MIParser::parseOffset(int64_t &
Offset) {
3353 return error(
"expected an integer literal after '" + Sign +
"'");
3354 if (Token.integerValue().getSignificantBits() > 64)
3355 return error(
"expected 64-bit integer (too large)");
3356 Offset = Token.integerValue().getExtValue();
3363bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3367 return error(
"expected basic block after 'ir_block_address_taken'");
3369 if (parseIRBlock(BB, MF.getFunction()))
3376bool MIParser::parseAlignment(
uint64_t &Alignment) {
3380 return error(
"expected an integer literal after 'align'");
3381 if (getUint64(Alignment))
3386 return error(
"expected a power-of-2 literal after 'align'");
3391bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3395 return error(
"expected an integer literal after 'addrspace'");
3412 switch (Token.
kind()) {
3418 unsigned SlotNumber = 0;
3446 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3450bool MIParser::parseIRValue(
const Value *&V) {
3451 return ::parseIRValue(
3457bool MIParser::getUint64(
uint64_t &Result) {
3458 if (Token.hasIntegerValue()) {
3459 if (Token.integerValue().getActiveBits() > 64)
3460 return error(
"expected 64-bit integer (too large)");
3461 Result = Token.integerValue().getZExtValue();
3468 if (
A.getBitWidth() > 64)
3469 return error(
"expected 64-bit integer (too large)");
3476bool MIParser::getHexUint(
APInt &Result) {
3477 return ::getHexUint(Token, Result);
3481 const auto OldFlags =
Flags;
3482 switch (Token.kind()) {
3497 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3498 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3506 if (OldFlags == Flags)
3509 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3515 switch (Token.kind()) {
3517 PSV = MF.getPSVManager().getStack();
3520 PSV = MF.getPSVManager().getGOT();
3523 PSV = MF.getPSVManager().getJumpTable();
3526 PSV = MF.getPSVManager().getConstantPool();
3530 if (parseFixedStackFrameIndex(FI))
3532 PSV = MF.getPSVManager().getFixedStack(FI);
3538 if (parseStackFrameIndex(FI))
3540 PSV = MF.getPSVManager().getFixedStack(FI);
3546 switch (Token.kind()) {
3552 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3556 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3557 MF.createExternalSymbolName(Token.stringValue()));
3561 "expected a global value or an external symbol after 'call-entry'");
3566 const auto *
TII = MF.getSubtarget().getInstrInfo();
3567 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3568 if (Formatter->parseCustomPseudoSourceValue(
3569 Token.stringValue(), MF, PFS, PSV,
3571 return error(Loc, Msg);
3575 return error(
"unable to parse target custom pseudo source value");
3592 if (parseMemoryPseudoSourceValue(PSV))
3605 return error(
"expected an IR value reference");
3606 const Value *
V =
nullptr;
3609 if (V && !
V->getType()->isPointerTy())
3610 return error(
"expected a pointer IR value");
3625 return error(
"expected '(' in syncscope");
3628 if (parseStringConstant(SSN))
3631 SSID =
Context.getOrInsertSyncScopeID(SSN);
3633 return error(
"expected ')' in syncscope");
3639bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3658 return error(
"expected an atomic scope, ordering or a size specification");
3665 while (Token.isMemoryOperandFlag()) {
3666 if (parseMemoryOperandFlag(Flags))
3670 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3671 return error(
"expected 'load' or 'store' memory operation");
3672 if (Token.stringValue() ==
"load")
3686 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3691 if (parseOptionalAtomicOrdering(Order))
3694 if (parseOptionalAtomicOrdering(FailureOrder))
3700 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3701 "memory operation");
3706 if (getUint64(
Size))
3717 if (parseLowLevelType(Token.location(), MemoryType))
3730 if (Token.stringValue() != Word)
3731 return error(
Twine(
"expected '") + Word +
"'");
3734 if (parseMachinePointerInfo(Ptr))
3743 MDNode *MemCacheHint =
nullptr;
3745 switch (Token.kind()) {
3751 if (Ptr.
Offset & (Alignment - 1)) {
3756 return error(
"specified alignment is more aligned than offset");
3802 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3803 "'!noalias' or '!range' or '!mem.cache_hint' or "
3804 "'!noalias.addrspace'");
3809 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3811 Order, FailureOrder);
3815bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3818 "Invalid token for a pre- post-instruction symbol!");
3821 return error(
"expected a symbol after 'pre-instr-symbol'");
3822 Symbol = getOrCreateMCSymbol(Token.stringValue());
3828 return error(
"expected ',' before the next machine operand");
3833bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3835 "Invalid token for a heap alloc marker!");
3840 return error(
"expected a MDNode after 'heap-alloc-marker'");
3845 return error(
"expected ',' before the next machine operand");
3850bool MIParser::parsePCSections(
MDNode *&Node) {
3852 "Invalid token for a PC sections!");
3857 return error(
"expected a MDNode after 'pcsections'");
3862 return error(
"expected ',' before the next machine operand");
3867bool MIParser::parseMMRA(
MDNode *&Node) {
3876 return error(
"expected ',' before the next machine operand");
3886 for (
const auto &BB :
F) {
3892 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3899 return Slots2BasicBlocks.
lookup(Slot);
3902const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3903 if (Slots2BasicBlocks.empty())
3909 if (&
F == &MF.getFunction())
3910 return getIRBlock(Slot);
3922 return MF.getContext().getOrCreateSymbol(Name);
3925bool MIParser::parseStringConstant(std::string &Result) {
3927 return error(
"expected string constant");
3928 Result = std::string(Token.stringValue());
3936 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3941 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3947 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3953 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3959 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3965 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3970 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3976 return MIParser(PFS,
Error, Src).parsePrefetchTarget(
Target);
3980 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3992 return ::parseIRValue(Token, PFS, V, ErrorCallback);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(GsymDataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static bool verifyVectorElementCount(uint64_t NumElts, bool HasVScale)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
MachineRegisterInfo & MRI
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
Get the array size.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static constexpr BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
Return the entry for the specified key, or a default constructed value if no such entry exists.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT bfloat16()
static LLT floatIEEE(unsigned SizeInBits)
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createLLVMVectorOffset(MCSymbol *L, unsigned Register, unsigned RegisterSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, int64_t Offset, SMLoc Loc={})
.cfi_llvm_vector_offset Previous value of Register is saved at Offset from CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createLLVMVectorRegisters(MCSymbol *L, unsigned Register, ArrayRef< VectorRegisterWithLane > VectorRegisters, SMLoc Loc={})
.cfi_llvm_vector_registers Previous value of Register is saved in lanes of vector registers.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createSetRAState(MCSymbol *L, unsigned State, MCSymbol *PACSym=nullptr, SMLoc Loc={})
.cfi_set_ra_state AArch64 set RA sign state,
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createLLVMVectorRegisterMask(MCSymbol *L, unsigned Register, unsigned SpillRegister, unsigned SpillRegisterLaneSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, SMLoc Loc={})
.cfi_llvm_vector_register_mask Previous value of Register is saved in SpillRegister,...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction createLLVMRegisterPair(MCSymbol *L, unsigned Register, unsigned R1, unsigned R1SizeInBits, unsigned R2, unsigned R2SizeInBits, SMLoc Loc={})
.cfi_llvm_register_pair Previous value of Register is saved in R1:R2.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
unsigned getID() const
getID() - Return the register class ID number.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
void setIsCleanupFuncletEntry(bool V=true)
Indicates if this is the entry block of a cleanup funclet.
void setLabelMustBeEmitted()
Set this block to reflect that, regardless how we flow to it, we need its label be emitted.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setMaxBytesForAlignment(unsigned MaxBytes)
Set the maximum amount of padding allowed for aligning the basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHContTarget(bool V=true)
Indicates if this is a target of Windows EH Continuation Guard.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void noteNewVirtualRegister(Register Reg)
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
LLVM_ABI SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr bool empty() const
Check if the string is empty.
LLVM_ABI std::string lower() const
bool consume_front(char Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
LLVM_ABI bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RelativeUniformCounterPtr Values
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
LLVM_ABI bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
LLVM_ABI bool parsePrefetchTarget(PerFunctionMIParsingState &PFS, CallsiteID &Target, StringRef Src, SMDiagnostic &Error)
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Value
LLVM_ABI bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
LLVM_ABI bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
LLVM_ABI bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
LLVM_ABI bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
@ End
Run the machine verifier once, at the end of the pipeline.
LLVM_ABI bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
MCRegisterClass TargetRegisterClass
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_cleanup_funclet_entry
@ kw_cfi_llvm_register_pair
@ kw_cfi_llvm_vector_offset
@ kw_inlineasm_br_indirect_target
@ kw_cfi_llvm_vector_registers
@ kw_label_must_be_emitted
@ kw_cfi_llvm_vector_register_mask
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_max_bytes_for_alignment
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
LLVM_ABI VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
LLVM_ABI const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
LLVM_ABI PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
LLVM_ABI VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
LLVM_ABI bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
LLVM_ABI bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
LLVM_ABI const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
LLVM_ABI bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
LLVM_ABI unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
LLVM_ABI bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
LLVM_ABI void setTarget(const TargetSubtargetInfo &NewSubtarget)
LLVM_ABI bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
LLVM_ABI bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
LLVM_ABI bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
LLVM_ABI const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
LLVM_ABI const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.