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ARMUnwindOpAsm.cpp
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1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the unwind opcode assembler for ARM exception handling
10 // table.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMUnwindOpAsm.h"
15 #include "llvm/Support/ARMEHABI.h"
16 #include "llvm/Support/LEB128.h"
18 #include <cassert>
19 
20 using namespace llvm;
21 
22 namespace {
23 
24  /// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
25  /// with MSB to LSB per uint32_t ordering. For example, the first byte will
26  /// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
27  /// 7, 6, 5, 4, 11, 10, 9, 8, and so on.
28  class UnwindOpcodeStreamer {
29  private:
31  size_t Pos = 3;
32 
33  public:
34  UnwindOpcodeStreamer(SmallVectorImpl<uint8_t> &V) : Vec(V) {}
35 
36  /// Emit the byte in MSB to LSB per uint32_t order.
37  void EmitByte(uint8_t elem) {
38  Vec[Pos] = elem;
39  Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
40  }
41 
42  /// Emit the size prefix.
43  void EmitSize(size_t Size) {
44  size_t SizeInWords = (Size + 3) / 4;
45  assert(SizeInWords <= 0x100u &&
46  "Only 256 additional words are allowed for unwind opcodes");
47  EmitByte(static_cast<uint8_t>(SizeInWords - 1));
48  }
49 
50  /// Emit the personality index prefix.
51  void EmitPersonalityIndex(unsigned PI) {
53  "Invalid personality prefix");
54  EmitByte(ARM::EHABI::EHT_COMPACT | PI);
55  }
56 
57  /// Fill the rest of bytes with FINISH opcode.
58  void FillFinishOpcode() {
59  while (Pos < Vec.size())
61  }
62  };
63 
64 } // end anonymous namespace
65 
67  if (RegSave == 0u) {
68  // That's the special case for RA PAC.
70  return;
71  }
72 
73  // One byte opcode to save register r14 and r11-r4
74  if (RegSave & (1u << 4)) {
75  // The one byte opcode will always save r4, thus we can't use the one byte
76  // opcode when r4 is not in .save directive.
77 
78  // Compute the consecutive registers from r4 to r11.
79  uint32_t Mask = RegSave & 0xff0u;
80  uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4.
81  // Mask off non-consecutive registers. Keep r4.
82  Mask &= ~(0xffffffe0u << Range);
83 
84  // Emit this opcode when the mask covers every registers.
85  uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
86  if (UnmaskedReg == 0u) {
87  // Pop r[4 : (4 + n)]
89  RegSave &= 0x000fu;
90  } else if (UnmaskedReg == (1u << 14)) {
91  // Pop r[14] + r[4 : (4 + n)]
93  RegSave &= 0x000fu;
94  }
95  }
96 
97  // Two bytes opcode to save register r15-r4
98  if ((RegSave & 0xfff0u) != 0)
99  EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
100 
101  // Opcode to save register r3-r0
102  if ((RegSave & 0x000fu) != 0)
103  EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
104 }
105 
106 /// Emit unwind opcodes for .vsave directives
108  // We only have 4 bits to save the offset in the opcode so look at the lower
109  // and upper 16 bits separately.
110  for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
111  while (Regs) {
112  // Now look for a run of set bits. Remember the MSB and LSB of the run.
113  auto RangeMSB = 32 - countLeadingZeros(Regs);
114  auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
115  auto RangeLSB = RangeMSB - RangeLen;
116 
117  int Opcode = RangeLSB >= 16
120 
121  EmitInt16(Opcode | ((RangeLSB % 16) << 4) | (RangeLen - 1));
122 
123  // Zero out bits we're done with.
124  Regs &= ~(-1u << RangeLSB);
125  }
126  }
127 }
128 
129 /// Emit unwind opcodes to copy address from source register to $sp.
132 }
133 
134 /// Emit unwind opcodes to add $sp with an offset.
136  if (Offset > 0x200) {
137  uint8_t Buff[16];
139  size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1);
140  emitBytes(Buff, ULEBSize + 1);
141  } else if (Offset > 0) {
142  if (Offset > 0x100) {
143  EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | 0x3fu);
144  Offset -= 0x100;
145  }
147  static_cast<uint8_t>((Offset - 4) >> 2));
148  } else if (Offset < 0) {
149  while (Offset < -0x100) {
150  EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP | 0x3fu);
151  Offset += 0x100;
152  }
154  static_cast<uint8_t>(((-Offset) - 4) >> 2));
155  }
156 }
157 
158 void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
159  SmallVectorImpl<uint8_t> &Result) {
160  UnwindOpcodeStreamer OpStreamer(Result);
161 
162  if (HasPersonality) {
163  // User-specifed personality routine: [ SIZE , OP1 , OP2 , ... ]
164  PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX;
165  size_t TotalSize = Ops.size() + 1;
166  size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
167  Result.resize(RoundUpSize);
168  OpStreamer.EmitSize(RoundUpSize);
169  } else {
170  // If no personalityindex is specified, select ane
171  if (PersonalityIndex == ARM::EHABI::NUM_PERSONALITY_INDEX)
172  PersonalityIndex = (Ops.size() <= 3) ? ARM::EHABI::AEABI_UNWIND_CPP_PR0
174  if (PersonalityIndex == ARM::EHABI::AEABI_UNWIND_CPP_PR0) {
175  // __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
176  assert(Ops.size() <= 3 && "too many opcodes for __aeabi_unwind_cpp_pr0");
177  Result.resize(4);
178  OpStreamer.EmitPersonalityIndex(PersonalityIndex);
179  } else {
180  // __aeabi_unwind_cpp_pr{1,2}: [ {0x81,0x82} , SIZE , OP1 , OP2 , ... ]
181  size_t TotalSize = Ops.size() + 2;
182  size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
183  Result.resize(RoundUpSize);
184  OpStreamer.EmitPersonalityIndex(PersonalityIndex);
185  OpStreamer.EmitSize(RoundUpSize);
186  }
187  }
188 
189  // Copy the unwind opcodes
190  for (size_t i = OpBegins.size() - 1; i > 0; --i)
191  for (size_t j = OpBegins[i - 1], end = OpBegins[i]; j < end; ++j)
192  OpStreamer.EmitByte(Ops[j]);
193 
194  // Emit the padding finish opcodes if the size is not multiple of 4.
195  OpStreamer.FillFinishOpcode();
196 
197  // Reset the assembler state
198  Reset();
199 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
i
i
Definition: README.txt:29
ARMEHABI.h
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4
@ UNWIND_OPCODE_POP_REG_RANGE_R4
Definition: ARMEHABI.h:64
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::ARM::EHABI::UNWIND_OPCODE_SET_VSP
@ UNWIND_OPCODE_SET_VSP
Definition: ARMEHABI.h:60
llvm::ARM::EHABI::UNWIND_OPCODE_INC_VSP_ULEB128
@ UNWIND_OPCODE_INC_VSP_ULEB128
Definition: ARMEHABI.h:85
llvm::ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4_R14
@ UNWIND_OPCODE_POP_REG_RANGE_R4_R14
Definition: ARMEHABI.h:68
llvm::countLeadingOnes
unsigned countLeadingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the most significant bit to the first zero bit.
Definition: MathExtras.h:509
llvm::ARM::EHABI::AEABI_UNWIND_CPP_PR1
@ AEABI_UNWIND_CPP_PR1
Definition: ARMEHABI.h:128
llvm::ARM::EHABI::EHT_COMPACT
@ EHT_COMPACT
Definition: ARMEHABI.h:30
llvm::ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD
@ UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD
Definition: ARMEHABI.h:114
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
ARMUnwindOpAsm.h
llvm::ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK
@ UNWIND_OPCODE_POP_REG_MASK
Definition: ARMEHABI.h:81
llvm::UnwindOpcodeAssembler::Finalize
void Finalize(unsigned &PersonalityIndex, SmallVectorImpl< uint8_t > &Result)
Finalize the unwind opcode sequence for emitBytes()
Definition: ARMUnwindOpAsm.cpp:158
llvm::ARM::EHABI::UNWIND_OPCODE_POP_RA_AUTH_CODE
@ UNWIND_OPCODE_POP_RA_AUTH_CODE
Definition: ARMEHABI.h:76
llvm::ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4
@ UNWIND_OPCODE_POP_REG_MASK_R4
Definition: ARMEHABI.h:55
LEB128.h
llvm::countTrailingOnes
unsigned countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
Definition: MathExtras.h:525
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::UnwindOpcodeAssembler::EmitSetSP
void EmitSetSP(uint16_t Reg)
Emit unwind opcodes to copy address from source register to $sp.
Definition: ARMUnwindOpAsm.cpp:130
llvm::ARM::EHABI::AEABI_UNWIND_CPP_PR0
@ AEABI_UNWIND_CPP_PR0
Definition: ARMEHABI.h:127
llvm::UnwindOpcodeAssembler::EmitSPOffset
void EmitSPOffset(int64_t Offset)
Emit unwind opcodes to add $sp with an offset.
Definition: ARMUnwindOpAsm.cpp:135
llvm::ARM::EHABI::UNWIND_OPCODE_FINISH
@ UNWIND_OPCODE_FINISH
Definition: ARMEHABI.h:72
uint32_t
j
return j(j<< 16)
llvm::UnwindOpcodeAssembler::EmitRegSave
void EmitRegSave(uint32_t RegSave)
Emit unwind opcodes for .save directives.
Definition: ARMUnwindOpAsm.cpp:66
uint16_t
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::UnwindOpcodeAssembler::EmitVFPRegSave
void EmitVFPRegSave(uint32_t VFPRegSave)
Emit unwind opcodes for .vsave directives.
Definition: ARMUnwindOpAsm.cpp:107
llvm::ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16
@ UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16
Definition: ARMEHABI.h:110
llvm::ARM::EHABI::UNWIND_OPCODE_INC_VSP
@ UNWIND_OPCODE_INC_VSP
Definition: ARMEHABI.h:42
llvm::encodeULEB128
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
llvm::SmallVectorImpl< uint8_t >
llvm::ARM::EHABI::UNWIND_OPCODE_DEC_VSP
@ UNWIND_OPCODE_DEC_VSP
Definition: ARMEHABI.h:46
llvm::ARM::EHABI::NUM_PERSONALITY_INDEX
@ NUM_PERSONALITY_INDEX
Definition: ARMEHABI.h:131
llvm::UnwindOpcodeAssembler::Reset
void Reset()
Reset the unwind opcode assembler.
Definition: ARMUnwindOpAsm.h:37