#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"

Classes
struct	llvm::AMDGPU::HazardContext
struct	llvm::AMDGPU::ClassMatch
struct	llvm::AMDGPU::HazardSide
struct	llvm::AMDGPU::WindowSpec
struct	llvm::AMDGPU::ConsumerTarget
struct	llvm::AMDGPU::HazardAntiHintRule

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU
namespace	llvm::AMDGPU::HazardClass

Typedefs
using	llvm::AMDGPU::HazardClassMask = uint32_t
using	llvm::AMDGPU::RulePredicate = bool (*)(const HazardContext &)
using	llvm::AMDGPU::InstPredicate = bool (*)(const MachineInstr &, const HazardContext &)
using	llvm::AMDGPU::AdvanceForRawWindowFn

Enumerations
enum	: HazardClassMask { llvm::AMDGPU::HazardClass::None = 0 , llvm::AMDGPU::HazardClass::CTRL = 1u << 0 , llvm::AMDGPU::HazardClass::VALU = 1u << 1 , llvm::AMDGPU::HazardClass::TRANS = 1u << 2 , llvm::AMDGPU::HazardClass::SALU = 1u << 3 , llvm::AMDGPU::HazardClass::DS = 1u << 4 , llvm::AMDGPU::HazardClass::VMEM = 1u << 5 , llvm::AMDGPU::HazardClass::SMEM = 1u << 6 , llvm::AMDGPU::HazardClass::WMMA = 1u << 7 , llvm::AMDGPU::HazardClass::MFMA = 1u << 8 , llvm::AMDGPU::HazardClass::EXP = 1u << 9 , llvm::AMDGPU::HazardClass::Load = 1u << 10 , llvm::AMDGPU::HazardClass::WritesVGPR = 1u << 11 , llvm::AMDGPU::HazardClass::RawVALU = 1u << 12 , llvm::AMDGPU::HazardClass::LDSDMA = 1u << 13 }
enum class	llvm::AMDGPU::HazardOperand : uint8_t { llvm::AMDGPU::None , llvm::AMDGPU::Def , llvm::AMDGPU::Src0 , llvm::AMDGPU::Src1 , llvm::AMDGPU::Src2 , llvm::AMDGPU::Src0Src1 , llvm::AMDGPU::Idx , llvm::AMDGPU::Vaddr , llvm::AMDGPU::AnySrc , llvm::AMDGPU::AnyUse }
enum class	llvm::AMDGPU::AntiHintDirection : uint8_t { llvm::AMDGPU::OneDirectional , llvm::AMDGPU::Symmetric }
enum class	llvm::AMDGPU::Lifetime : uint8_t { llvm::AMDGPU::WindowBudget , llvm::AMDGPU::RegisterCount }

Functions
void	llvm::AMDGPU::applyAntiHintRules (MachineFunction &MF, const HazardContext &Ctx)

Classes

Namespaces