LLVM
15.0.0git
|
Namespaces | |
CPol | |
DepCtr | |
DPP | |
ElfNote | |
EncValues | |
Exp | |
HSAMD | |
Hwreg | |
ImplicitArg | |
IsaInfo | |
MTBUFFormat | |
PALMD | |
SDWA | |
SendMsg | |
Swizzle | |
UfmtGFX10 | |
UfmtGFX11 | |
VGPRIndexMode | |
VOP3PEncoding | |
Classes | |
struct | CustomOperand |
struct | CustomOperandVal |
struct | D16ImageDimIntrinsic |
struct | GcnBufferFormatInfo |
struct | ImageDimIntrinsicInfo |
struct | IsaVersion |
Instruction set architecture version. More... | |
struct | MAIInstInfo |
struct | MIMGBaseOpcodeInfo |
struct | MIMGBiasMappingInfo |
struct | MIMGDimInfo |
struct | MIMGG16MappingInfo |
struct | MIMGInfo |
struct | MIMGLZMappingInfo |
struct | MIMGMIPMappingInfo |
struct | MIMGOffsetMappingInfo |
struct | MTBUFInfo |
struct | MUBUFInfo |
struct | RsrcIntrinsic |
struct | SIModeRegisterDefaults |
struct | SMInfo |
struct | VOPC64DPPInfo |
struct | VOPInfo |
struct | Waitcnt |
Represents the counter values to wait for in an s_waitcnt instruction. More... | |
Variables | |
const uint64_t | RSRC_DATA_FORMAT = 0xf00000000000LL |
const uint64_t | RSRC_ELEMENT_SIZE_SHIFT = (32 + 19) |
const uint64_t | RSRC_INDEX_STRIDE_SHIFT = (32 + 21) |
const uint64_t | RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23) |
const int | OPR_ID_UNKNOWN = -1 |
const int | OPR_ID_UNSUPPORTED = -2 |
const int | OPR_ID_DUPLICATE = -3 |
const int | OPR_VAL_INVALID = -4 |
Enumerator | |
---|---|
FEATURE_NONE | |
FEATURE_FMA | |
FEATURE_LDEXP | |
FEATURE_FP64 | |
FEATURE_FAST_FMA_F32 | |
FEATURE_FAST_DENORMAL_F32 | |
FEATURE_WAVE32 | |
FEATURE_XNACK | |
FEATURE_SRAMECC |
Definition at line 121 of file TargetParser.h.
enum llvm::AMDGPU::Fixups |
Enumerator | |
---|---|
fixup_si_sopp_br | 16-bit PC relative fixup for SOPP branch instructions. |
LastTargetFixupKind | |
NumTargetFixupKinds |
Definition at line 16 of file AMDGPUFixupKinds.h.
enum llvm::AMDGPU::GPUKind : uint32_t |
GPU kinds supported by the AMDGPU target.
Definition at line 38 of file TargetParser.h.
enum llvm::AMDGPU::OperandType : unsigned |
Definition at line 149 of file SIDefines.h.
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static |
Definition at line 35 of file AMDGPUMemoryUtils.cpp.
References llvm::append_range(), F, I, llvm::SetVector< T, Vector, Set >::insert(), and llvm::Value::users().
Referenced by replaceConstantUsesInFunction().
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits | ( | const MCSubtargetInfo & | ST, |
uint64_t | ByteOffset | ||
) |
Convert ByteOffset
to dwords if the subtarget uses dword SMRD immediate offsets.
Definition at line 2202 of file AMDGPUBaseInfo.cpp.
References assert(), hasSMEMByteOffset(), isDwordAligned(), and llvm::ARM_MB::ST.
Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().
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static |
Definition at line 1171 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Hwreg::Opr.
Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().
unsigned llvm::AMDGPU::decodeExpcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1021 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by decodeWaitcnt().
unsigned llvm::AMDGPU::decodeLgkmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1026 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by decodeWaitcnt().
unsigned llvm::AMDGPU::decodeVmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1013 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by decodeWaitcnt().
Waitcnt llvm::AMDGPU::decodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Encoded | ||
) |
Definition at line 1038 of file AMDGPUBaseInfo.cpp.
References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, llvm::IndexedInstrProf::Version, and llvm::AMDGPU::Waitcnt::VmCnt.
void llvm::AMDGPU::decodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned & | Vmcnt, | ||
unsigned & | Expcnt, | ||
unsigned & | Lgkmcnt | ||
) |
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt
for given isa Version
, and writes decoded values into Vmcnt
, Expcnt
and Lgkmcnt
respectively.
Vmcnt
, Expcnt
and Lgkmcnt
are decoded as follows: Vmcnt
= Waitcnt
[3:0] (pre-gfx9) Vmcnt
= Waitcnt
[15:14,3:0] (gfx9,10) Vmcnt
= Waitcnt
[15:10] (gfx11+) Expcnt
= Waitcnt
[6:4] (pre-gfx11) Expcnt
= Waitcnt
[2:0] (gfx11+) Lgkmcnt
= Waitcnt
[11:8] (pre-gfx10) Lgkmcnt
= Waitcnt
[13:8] (gfx10) Lgkmcnt
= Waitcnt
[9:4] (gfx11+)
Definition at line 1031 of file AMDGPUBaseInfo.cpp.
References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and llvm::IndexedInstrProf::Version.
Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().
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static |
Definition at line 1195 of file AMDGPUBaseInfo.cpp.
References encodeCustomOperandVal(), llvm::AMDGPU::Hwreg::Opr, OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, and OPR_ID_UNSUPPORTED.
Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().
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static |
Definition at line 1188 of file AMDGPUBaseInfo.cpp.
References OPR_VAL_INVALID.
Referenced by encodeCustomOperand().
unsigned llvm::AMDGPU::encodeExpcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Expcnt | ||
) |
Waitcnt
with encoded Expcnt
for given isa Version
. Definition at line 1055 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by encodeWaitcnt().
unsigned llvm::AMDGPU::encodeLgkmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Lgkmcnt | ||
) |
Waitcnt
with encoded Lgkmcnt
for given isa Version
. Definition at line 1061 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by encodeWaitcnt().
unsigned llvm::AMDGPU::encodeVmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Vmcnt | ||
) |
Waitcnt
with encoded Vmcnt
for given isa Version
. Definition at line 1046 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by encodeWaitcnt().
unsigned llvm::AMDGPU::encodeWaitcnt | ( | const IsaVersion & | Version, |
const Waitcnt & | Decoded | ||
) |
Definition at line 1076 of file AMDGPUBaseInfo.cpp.
References encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, llvm::IndexedInstrProf::Version, and llvm::AMDGPU::Waitcnt::VmCnt.
unsigned llvm::AMDGPU::encodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Vmcnt, | ||
unsigned | Expcnt, | ||
unsigned | Lgkmcnt | ||
) |
Encodes Vmcnt
, Expcnt
and Lgkmcnt
into Waitcnt for given isa Version
.
Vmcnt
, Expcnt
and Lgkmcnt
are encoded as follows: Waitcnt[2:0] = Expcnt
(gfx11+) Waitcnt[3:0] = Vmcnt
(pre-gfx9) Waitcnt[3:0] = Vmcnt
[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt
(pre-gfx11) Waitcnt[9:4] = Lgkmcnt
(gfx11+) Waitcnt[11:8] = Lgkmcnt
(pre-gfx10) Waitcnt[13:8] = Lgkmcnt
(gfx10) Waitcnt[15:10] = Vmcnt
(gfx11+) Waitcnt[15:14] = Vmcnt
[5:4] (gfx9,10)
Vmcnt
, Expcnt
and Lgkmcnt
for given isa Version
. Definition at line 1067 of file AMDGPUBaseInfo.cpp.
References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and llvm::IndexedInstrProf::Version.
Referenced by encodeWaitcnt().
void llvm::AMDGPU::fillValidArchListAMDGCN | ( | SmallVectorImpl< StringRef > & | Values | ) |
Definition at line 182 of file TargetParser.cpp.
void llvm::AMDGPU::fillValidArchListR600 | ( | SmallVectorImpl< StringRef > & | Values | ) |
Definition at line 188 of file TargetParser.cpp.
std::vector< GlobalVariable * > llvm::AMDGPU::findVariablesToLower | ( | Module & | M, |
const Function * | F | ||
) |
Definition at line 108 of file AMDGPUMemoryUtils.cpp.
References F, llvm::AMDGPUAS::LOCAL_ADDRESS, M, and shouldLowerLDSToStruct().
LLVM_READONLY int llvm::AMDGPU::getAddr64Inst | ( | uint16_t | Opcode | ) |
LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp | ( | const MIMGBaseOpcodeInfo * | BaseOpcode, |
const MIMGDimInfo * | Dim, | ||
bool | IsA16, | ||
bool | IsG16Supported | ||
) |
Definition at line 219 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, and llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().
Align llvm::AMDGPU::getAlign | ( | DataLayout const & | DL, |
const GlobalVariable * | GV | ||
) |
Definition at line 30 of file AMDGPUMemoryUtils.cpp.
References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().
unsigned llvm::AMDGPU::getAmdhsaCodeObjectVersion | ( | ) |
Definition at line 153 of file AMDGPUBaseInfo.cpp.
References AmdhsaCodeObjectVersion.
Referenced by allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateSpecialInputSGPRs(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), intrinsicToAttrMask(), and llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr().
unsigned llvm::AMDGPU::getArchAttrAMDGCN | ( | GPUKind | AK | ) |
Definition at line 170 of file TargetParser.cpp.
unsigned llvm::AMDGPU::getArchAttrR600 | ( | GPUKind | AK | ) |
Definition at line 176 of file TargetParser.cpp.
Definition at line 140 of file TargetParser.cpp.
Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().
Definition at line 146 of file TargetParser.cpp.
Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().
LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp | ( | uint16_t | Opcode | ) |
std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset | ( | MachineRegisterInfo & | MRI, |
Register | Reg | ||
) |
Returns base register and constant offset.
Definition at line 19 of file AMDGPUGlobalISelUtils.cpp.
References llvm::sampleprof::Base, llvm::tgtok::Def, llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::mi_match(), and MRI.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().
LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::verifyInstruction().
Definition at line 246 of file TargetParser.cpp.
References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), parseArchR600(), and T.
LLVM_READONLY int llvm::AMDGPU::getCommuteOrig | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
LLVM_READONLY int llvm::AMDGPU::getCommuteRev | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 895 of file AMDGPUBaseInfo.cpp.
References AMDHSA_BITS_SET, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), isGFX90A(), llvm::amdhsa::kernel_descriptor_t::kernel_code_properties, llvm::FeatureBitset::test(), and llvm::IndexedInstrProf::Version.
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static |
Definition at line 1140 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Hwreg::Opr.
Referenced by llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().
LLVM_READONLY int llvm::AMDGPU::getDPPOp32 | ( | uint16_t | Opcode | ) |
unsigned llvm::AMDGPU::getExpcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 993 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV | ( | uint16_t | Opcode | ) |
Opcode
of an SV (VADDR) form. LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS | ( | uint16_t | Opcode | ) |
Opcode
of an SS (SADDR) form. Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS | ( | uint16_t | Opcode | ) |
Opcode
of an SS (SADDR) form. Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS | ( | uint16_t | Opcode | ) |
Opcode
of an SVS (SADDR + VADDR) form. Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo | ( | uint8_t | BitsPerComp, |
uint8_t | NumComponents, | ||
uint8_t | NumFormat, | ||
const MCSubtargetInfo & | STI | ||
) |
Definition at line 2343 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX11Plus().
Referenced by getBufferFormatWithCompCount().
const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo | ( | uint8_t | Format, |
const MCSubtargetInfo & | STI | ||
) |
Definition at line 2356 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX11Plus().
LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp | ( | uint16_t | Opcode | ) |
Opcode
of a VADDR form. LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp | ( | uint16_t | Opcode | ) |
Opcode
of a SADDR form. Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().
Definition at line 1605 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_PS, F, and getIntegerAttribute().
Referenced by generateEndPgm().
Definition at line 1612 of file AMDGPUBaseInfo.cpp.
References F, and getIntegerAttribute().
Referenced by generateEndPgm().
unsigned llvm::AMDGPU::getHostcallImplicitArgPosition | ( | ) |
Definition at line 174 of file AMDGPUBaseInfo.cpp.
References AmdhsaCodeObjectVersion, llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET, and llvm_unreachable.
Optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 105 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::AMDHSA, AmdhsaCodeObjectVersion, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::Triple::getOS(), llvm::MCSubtargetInfo::getTargetTriple(), llvm::None, and llvm::report_fatal_error().
Referenced by llvm::createAMDGPUAsmBackend(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), isHsaAbiVersion2(), isHsaAbiVersion3(), isHsaAbiVersion4(), isHsaAbiVersion5(), llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().
LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst | ( | uint16_t | Opcode | ) |
Check if Opcode
is an Addr64 opcode.
Opcode
if it is an Addr64 opcode, otherwise -1. const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode | ( | unsigned | BaseOpcode, |
unsigned | Dim | ||
) |
Referenced by simplifyAMDGCNImageIntrinsic().
const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicInfo | ( | unsigned | Intr | ) |
Definition at line 1601 of file AMDGPUBaseInfo.cpp.
References F, and getIntegerAttribute().
Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().
F's
Name
attribute.Default
if attribute is not present.Default
and emits error if requested value cannot be converted to integer. Definition at line 947 of file AMDGPUBaseInfo.cpp.
References llvm::LLVMContext::emitError(), and F.
Referenced by llvm::GCNSubtarget::getBaseMaxNumSGPRs(), llvm::GCNSubtarget::getBaseMaxNumVGPRs(), getHasColorExport(), getHasDepthExport(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), getInitialPSInputAddr(), and llvm::AMDGPUTTIImpl::getUnrollingPreferences().
std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute | ( | const Function & | F, |
StringRef | Name, | ||
std::pair< int, int > | Default, | ||
bool | OnlyFirstRequired = false |
||
) |
F's
Name
attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired
is false).Default
if attribute is not present.Default
and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired
is false and "second" value is not present. Definition at line 962 of file AMDGPUBaseInfo.cpp.
References llvm::LLVMContext::emitError(), and F.
Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().
AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion | ( | StringRef | GPU | ) |
Definition at line 193 of file TargetParser.cpp.
References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_NONE, and parseArchAMDGCN().
Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPUInstPrinter::printWaitFlag(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().
unsigned llvm::AMDGPU::getLgkmcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 997 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().
LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM | ( | unsigned | Opc | ) |
Returns true if MAI operation is a double precision GEMM.
Definition at line 387 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by isDGEMM().
LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL | ( | unsigned | Opc | ) |
LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp | ( | unsigned | Opc, |
unsigned | NewChannels | ||
) |
Definition at line 211 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.
LLVM_READONLY int llvm::AMDGPU::getMCOpcode | ( | uint16_t | Opcode, |
unsigned | Gen | ||
) |
Definition at line 400 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().
unsigned llvm::AMDGPU::getMCReg | ( | unsigned | Reg, |
const MCSubtargetInfo & | STI | ||
) |
If Reg
is a pseudo reg, return the correct hardware register given STI
otherwise return Reg
.
Definition at line 1861 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, and llvm::Triple::r600.
Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().
LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::pseudoToMCOpcode(), and updateOperand().
const LLVM_READONLY MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 206 of file AMDGPUBaseInfo.cpp.
References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.
const LLVM_READONLY MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcodeInfo | ( | unsigned | BaseOpcode | ) |
const LLVM_READONLY MIMGBiasMappingInfo* llvm::AMDGPU::getMIMGBiasMappingInfo | ( | unsigned | Bias | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfo | ( | unsigned | DimEnum | ) |
const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByAsmSuffix | ( | StringRef | AsmSuffix | ) |
const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByEncoding | ( | uint8_t | DimEnc | ) |
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().
const LLVM_READONLY MIMGG16MappingInfo* llvm::AMDGPU::getMIMGG16MappingInfo | ( | unsigned | G | ) |
const LLVM_READONLY MIMGInfo* llvm::AMDGPU::getMIMGInfo | ( | unsigned | Opc | ) |
const LLVM_READONLY MIMGLZMappingInfo* llvm::AMDGPU::getMIMGLZMappingInfo | ( | unsigned | L | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
const LLVM_READONLY MIMGMIPMappingInfo* llvm::AMDGPU::getMIMGMIPMappingInfo | ( | unsigned | MIP | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
const LLVM_READONLY MIMGOffsetMappingInfo* llvm::AMDGPU::getMIMGOffsetMappingInfo | ( | unsigned | Offset | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode | ( | unsigned | BaseOpcode, |
unsigned | MIMGEncoding, | ||
unsigned | VDataDwords, | ||
unsigned | VAddrDwords | ||
) |
Definition at line 199 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().
LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 298 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMTBUFElements | ( | unsigned | Opc | ) |
Definition at line 308 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset | ( | unsigned | Opc | ) |
Definition at line 323 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc | ( | unsigned | Opc | ) |
Definition at line 318 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr | ( | unsigned | Opc | ) |
Definition at line 313 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode | ( | unsigned | BaseOpc, |
unsigned | Elements | ||
) |
Definition at line 303 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 328 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFElements | ( | unsigned | Opc | ) |
Definition at line 338 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset | ( | unsigned | Opc | ) |
Definition at line 353 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc | ( | unsigned | Opc | ) |
Definition at line 348 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr | ( | unsigned | Opc | ) |
Definition at line 343 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv | ( | unsigned | Opc | ) |
Definition at line 358 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode | ( | unsigned | BaseOpc, |
unsigned | Elements | ||
) |
Definition at line 333 of file AMDGPUBaseInfo.cpp.
References Info.
unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition | ( | ) |
Definition at line 157 of file AMDGPUBaseInfo.cpp.
References AmdhsaCodeObjectVersion, llvm_unreachable, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.
LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx | ( | uint16_t | Opcode, |
uint16_t | NamedIdx | ||
) |
Referenced by llvm::SITargetLowering::AddIMGInit(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), decodeOperand_AVLdSt_Any(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), frameIndexMayFold(), getFlatScratchSpillOpcode(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::getRegClass(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIInstrInfo::hasModifiers(), insertNamedMCOperand(), IsAGPROperand(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isOperandLegal(), isSendMsgTraceDataOrGDS(), isValidDPP8(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), AMDGPUMCInstLower::lower(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), nodesHaveSameOperandValue(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIInstrInfo::removeModOperands(), tryConstantFoldOp(), updateOperand(), and llvm::SIInstrInfo::verifyInstruction().
unsigned llvm::AMDGPU::getNumFlatOffsetBits | ( | const MCSubtargetInfo & | ST, |
bool | Signed | ||
) |
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition at line 2237 of file AMDGPUBaseInfo.cpp.
References isGFX10(), Signed, and llvm::ARM_MB::ST.
Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().
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Definition at line 905 of file AMDGPUBaseInfo.h.
References getOperandSize(), and llvm::MCInstrDesc::OpInfo.
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Definition at line 860 of file AMDGPUBaseInfo.h.
References llvm_unreachable, OPERAND_KIMM16, OPERAND_KIMM32, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2INT32, and llvm::MCOperandInfo::OperandType.
Referenced by getOperandSize().
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Definition at line 1114 of file AMDGPUBaseInfo.cpp.
References Context, and llvm::Test.
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Definition at line 1121 of file AMDGPUBaseInfo.cpp.
References Context, llvm::AMDGPU::CustomOperand< T >::Encoding, and llvm::Test.
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Definition at line 1099 of file AMDGPUBaseInfo.cpp.
References Cond, Context, llvm::ARM::InvalidIdx, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and llvm::Test.
unsigned llvm::AMDGPU::getRegBitWidth | ( | const MCRegisterClass & | RC | ) |
Get the size in bits of a register from the register class RC
.
Definition at line 2037 of file AMDGPUBaseInfo.cpp.
References llvm::MCRegisterClass::getID(), and getRegBitWidth().
unsigned llvm::AMDGPU::getRegBitWidth | ( | unsigned | RCID | ) |
Get the size in bits of a register from the register class RC
.
Definition at line 1932 of file AMDGPUBaseInfo.cpp.
References llvm_unreachable.
Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().
unsigned llvm::AMDGPU::getRegOperandSize | ( | const MCRegisterInfo * | MRI, |
const MCInstrDesc & | Desc, | ||
unsigned | OpNo | ||
) |
Get size of register operand.
Definition at line 2041 of file AMDGPUBaseInfo.cpp.
References assert(), getRegBitWidth(), MRI, llvm::MCInstrDesc::NumOperands, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
LLVM_READONLY int llvm::AMDGPU::getSDWAOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer | ( | unsigned | Opc | ) |
Definition at line 363 of file AMDGPUBaseInfo.cpp.
References Info.
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset | ||
) |
Definition at line 2228 of file AMDGPUBaseInfo.cpp.
References convertSMRDOffsetUnits(), isCI(), isDwordAligned(), llvm::isUInt< 32 >(), llvm::None, and llvm::ARM_MB::ST.
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset, | ||
bool | IsBuffer | ||
) |
ByteOffset
in the SMRD offset field, or None if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets. Definition at line 2211 of file AMDGPUBaseInfo.cpp.
References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isLegalSMRDEncodedUnsignedOffset(), llvm::None, and llvm::ARM_MB::ST.
LLVM_READONLY int llvm::AMDGPU::getSOPKOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation | ( | uint16_t | Opcode | ) |
int llvm::AMDGPU::getTotalNumVGPRs | ( | bool | has90AInsts, |
int32_t | ArgNumAGPR, | ||
int32_t | ArgNumVGPR | ||
) |
Definition at line 1790 of file AMDGPUBaseInfo.cpp.
References llvm::alignTo(), and llvm::max().
Referenced by llvm::AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs().
LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP | ( | uint16_t | Opcode | ) |
Referenced by findPossibleVCMPVCMPXOptimization(), and optimizeVCMPSaveExecSequence().
unsigned llvm::AMDGPU::getVmcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 987 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().
LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle | ( | unsigned | Opc | ) |
Definition at line 368 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle | ( | unsigned | Opc | ) |
Definition at line 373 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle | ( | unsigned | Opc | ) |
Definition at line 378 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getVOPe32 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding(), and tryAddToFoldList().
LLVM_READONLY int llvm::AMDGPU::getVOPe64 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().
unsigned llvm::AMDGPU::getWaitcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 1001 of file AMDGPUBaseInfo.cpp.
References llvm::IndexedInstrProf::Version.
Referenced by encodeWaitcnt().
bool llvm::AMDGPU::hasArchitectedFlatScratch | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1778 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().
bool llvm::AMDGPU::hasAtomicFaddRtnForTy | ( | const GCNSubtarget & | Subtarget, |
const LLT & | Ty | ||
) |
Definition at line 72 of file AMDGPUGlobalISelUtils.cpp.
References llvm::LLT::fixed_vector(), llvm::GCNSubtarget::hasAtomicFaddRtnInsts(), llvm::GCNSubtarget::hasGFX90AInsts(), and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().
bool llvm::AMDGPU::hasG16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1685 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().
bool llvm::AMDGPU::hasGFX10_3Insts | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1766 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().
bool llvm::AMDGPU::hasGFX10A16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1681 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::hasMAIInsts | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1782 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::hasMIMG_R128 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1677 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::hasPackedD16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1689 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), isCI(), and isSI().
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().
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Definition at line 2176 of file AMDGPUBaseInfo.cpp.
References isGCN3Encoding(), isGFX10Plus(), and llvm::ARM_MB::ST.
Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().
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Definition at line 2180 of file AMDGPUBaseInfo.cpp.
References isGFX9Plus(), and llvm::ARM_MB::ST.
Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().
bool llvm::AMDGPU::hasSRAMECC | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1673 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::hasVOPD | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1786 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().
bool llvm::AMDGPU::hasXNACK | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1669 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
void llvm::AMDGPU::initDefaultAMDKernelCodeT | ( | amd_kernel_code_t & | Header, |
const MCSubtargetInfo * | STI | ||
) |
Definition at line 859 of file AMDGPUBaseInfo.cpp.
References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, amd_kernel_code_t::amd_kernel_code_version_major, amd_kernel_code_t::amd_kernel_code_version_minor, amd_kernel_code_t::amd_machine_kind, amd_kernel_code_t::amd_machine_version_major, amd_kernel_code_t::amd_machine_version_minor, amd_kernel_code_t::amd_machine_version_stepping, amd_kernel_code_t::call_convention, amd_kernel_code_t::code_properties, amd_kernel_code_t::compute_pgm_resource_registers, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), amd_kernel_code_t::group_segment_alignment, amd_kernel_code_t::kernarg_segment_alignment, amd_kernel_code_t::kernel_code_entry_byte_offset, amd_kernel_code_t::private_segment_alignment, S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, llvm::FeatureBitset::test(), llvm::IndexedInstrProf::Version, and amd_kernel_code_t::wavefront_size.
Definition at line 2149 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, F, and llvm::CallingConv::SPIR_KERNEL.
Referenced by llvm::GCNTTIImpl::isSourceOfDivergence(), and llvm::AMDGPUInstrInfo::isUniformMMO().
bool llvm::AMDGPU::isCI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1698 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().
bool llvm::AMDGPU::isClobberedInFunction | ( | const LoadInst * | Load, |
MemorySSA * | MSSA, | ||
AAResults * | AA | ||
) |
Check is a Load
is clobbered in its function.
Definition at line 171 of file AMDGPUMemoryUtils.cpp.
References llvm::dbgs(), llvm::tgtok::Def, llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::MemoryPhi::incoming_values(), llvm::SmallSet< T, N, C >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), LLVM_DEBUG, and llvm::SPII::Load.
LLVM_READNONE bool llvm::AMDGPU::isCompute | ( | CallingConv::ID | cc | ) |
Definition at line 1635 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, and isGraphics().
Referenced by llvm::SIProgramInfo::getPGMRSrc1(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().
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Definition at line 2198 of file AMDGPUBaseInfo.cpp.
Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().
LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC | ( | CallingConv::ID | CC | ) |
Definition at line 1639 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, and llvm::CallingConv::SPIR_KERNEL.
Referenced by llvm::SITargetLowering::CanLowerReturn(), INITIALIZE_PASS(), isModuleEntryFunctionCC(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), mustPreserveGV(), promoteAllocasToVector(), recursivelyVisitUsers(), llvm::AMDGPUPropagateAttributesEarlyPass::run(), and llvm::SIMachineFunctionInfo::usesAGPRs().
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Definition at line 406 of file AMDGPU.h.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.
Referenced by llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), and llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg().
LLVM_READNONE bool llvm::AMDGPU::isFoldableLiteralV216 | ( | int32_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2136 of file AMDGPUBaseInfo.cpp.
References assert(), llvm::isInt< 16 >(), and llvm::isUInt< 16 >().
Referenced by updateOperand().
bool llvm::AMDGPU::isGCN3Encoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1754 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by hasSMEMByteOffset().
bool llvm::AMDGPU::isGFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1726 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by getGcnBufferFormatInfo(), getNumFlatOffsetBits(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().
bool llvm::AMDGPU::isGFX10_AEncoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1758 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::isGFX10_BEncoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1762 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by isGFX10Before1030().
bool llvm::AMDGPU::isGFX10Before1030 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1750 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX10_BEncoding().
bool llvm::AMDGPU::isGFX10Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1730 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX11Plus().
Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), and llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding().
bool llvm::AMDGPU::isGFX11 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1734 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by isGFX11Plus().
bool llvm::AMDGPU::isGFX11Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1738 of file AMDGPUBaseInfo.cpp.
References isGFX11().
Referenced by llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt(), llvm::AMDGPU::SendMsg::decodeMsg(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs(), getGcnBufferFormatInfo(), llvm::AMDGPU::SendMsg::getMsgIdMask(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormat(), isGFX10Plus(), llvm::AMDGPUDisassembler::isGFX11Plus(), isNotGFX11Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::SendMsg::isValidMsgOp(), llvm::AMDGPU::SendMsg::isValidMsgStream(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPU::SendMsg::msgRequiresOp(), and llvm::AMDGPU::SendMsg::msgSupportsStream().
bool llvm::AMDGPU::isGFX8_GFX9_GFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1714 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX8Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1718 of file AMDGPUBaseInfo.cpp.
References isGFX9Plus(), and isVI().
bool llvm::AMDGPU::isGFX9 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1706 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9Plus(), and isNotGFX10Plus().
bool llvm::AMDGPU::isGFX90A | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1770 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getDefaultAmdhsaKernelDescriptor(), and llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().
bool llvm::AMDGPU::isGFX940 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1774 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
bool llvm::AMDGPU::isGFX9_GFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1710 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX9Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1722 of file AMDGPUBaseInfo.cpp.
References isGFX10Plus(), and isGFX9().
Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), and llvm::AMDGPUDisassembler::isGFX9Plus().
bool llvm::AMDGPU::isGlobalSegment | ( | const GlobalValue * | GV | ) |
Definition at line 933 of file AMDGPUBaseInfo.cpp.
References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.
LLVM_READNONE bool llvm::AMDGPU::isGraphics | ( | CallingConv::ID | cc | ) |
Definition at line 1631 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, and isShader().
Referenced by isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().
bool llvm::AMDGPU::isGroupSegment | ( | const GlobalValue * | GV | ) |
Definition at line 929 of file AMDGPUBaseInfo.cpp.
References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.
bool llvm::AMDGPU::isHsaAbiVersion2 | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 124 of file AMDGPUBaseInfo.cpp.
References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2, and getHsaAbiVersion().
Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), llvm::AMDGPUAsmPrinter::emitEndOfAsmFile(), llvm::AMDGPUAsmPrinter::emitFunctionBodyEnd(), and llvm::AMDGPUAsmPrinter::emitFunctionBodyStart().
bool llvm::AMDGPU::isHsaAbiVersion3 | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 130 of file AMDGPUBaseInfo.cpp.
References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, and getHsaAbiVersion().
Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), and isHsaAbiVersion3AndAbove().
bool llvm::AMDGPU::isHsaAbiVersion3AndAbove | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 148 of file AMDGPUBaseInfo.cpp.
References isHsaAbiVersion3(), isHsaAbiVersion4(), and isHsaAbiVersion5().
Referenced by llvm::AMDGPUAsmPrinter::emitFunctionEntryLabel().
bool llvm::AMDGPU::isHsaAbiVersion4 | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 136 of file AMDGPUBaseInfo.cpp.
References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, and getHsaAbiVersion().
Referenced by isHsaAbiVersion3AndAbove().
bool llvm::AMDGPU::isHsaAbiVersion5 | ( | const MCSubtargetInfo * | STI | ) |
Definition at line 142 of file AMDGPUBaseInfo.cpp.
References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, and getHsaAbiVersion().
Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), and isHsaAbiVersion3AndAbove().
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Is this literal inlinable, and not one of the values intended for floating point values.
Definition at line 912 of file AMDGPUBaseInfo.h.
Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), isInlinableIntLiteralV216(), isInlinableLiteral16(), isInlinableLiteral32(), isInlinableLiteral64(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().
LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteralV216 | ( | int32_t | Literal | ) |
Definition at line 2125 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral(), llvm::isInt< 16 >(), and llvm::isUInt< 16 >().
Referenced by llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 | ( | int16_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2091 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral().
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 | ( | int32_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2065 of file AMDGPUBaseInfo.cpp.
References f(), llvm::FloatToBits(), and isInlinableIntLiteral().
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIRegisterInfo::eliminateFrameIndex(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 | ( | int64_t | Literal, |
bool | HasInv2Pi | ||
) |
Is this literal inlinable.
Definition at line 2048 of file AMDGPUBaseInfo.cpp.
References llvm::DoubleToBits(), and isInlinableIntLiteral().
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 | ( | int32_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2110 of file AMDGPUBaseInfo.cpp.
References assert(), isInlinableLiteral16(), llvm::isInt< 16 >(), and llvm::isUInt< 16 >().
Referenced by llvm::SIInstrInfo::isInlineConstant().
bool llvm::AMDGPU::isIntrinsicSourceOfDivergence | ( | unsigned | IntrID | ) |
Definition at line 2339 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().
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Definition at line 786 of file AMDGPUBaseInfo.h.
References llvm::CallingConv::AMDGPU_KERNEL, and llvm::CallingConv::SPIR_KERNEL.
Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::SITargetLowering::LowerReturn().
Definition at line 1665 of file AMDGPUBaseInfo.cpp.
References isModuleEntryFunctionCC().
Referenced by shouldLowerLDSToStruct().
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Definition at line 979 of file AMDGPUBaseInfo.h.
References DC, llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, and llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.
Referenced by llvm::SIInstrInfo::expandMovDPP64(), and llvm::SIInstrInfo::verifyInstruction().
LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | EncodedOffset, | ||
bool | IsBuffer | ||
) |
Definition at line 2190 of file AMDGPUBaseInfo.cpp.
References hasSMRDSignedImmOffset(), and llvm::ARM_MB::ST.
LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | EncodedOffset | ||
) |
Definition at line 2184 of file AMDGPUBaseInfo.cpp.
References hasSMEMByteOffset(), llvm::isUInt< 8 >(), and llvm::ARM_MB::ST.
Referenced by getSMRDEncodedOffset().
bool llvm::AMDGPU::isLegalSMRDImmOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset | ||
) |
ByteOffset
should be the offset in bytes and not the encoded offset. Definition at line 63 of file AMDGPUGlobalISelUtils.cpp.
References assert(), and llvm::BitmaskEnumDetail::Mask().
Referenced by llvm::AMDGPULegalizerInfo::legalizeShuffleVector().
LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC | ( | CallingConv::ID | CC | ) |
Definition at line 1656 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, and isEntryFunctionCC().
Referenced by isKernelCC().
bool llvm::AMDGPU::isNotGFX10Plus | ( | const MCSubtargetInfo & | STI | ) |
bool llvm::AMDGPU::isNotGFX11Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1742 of file AMDGPUBaseInfo.cpp.
References isGFX11Plus().
bool llvm::AMDGPU::isReadOnlySegment | ( | const GlobalValue * | GV | ) |
Definition at line 937 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().
Given a Def
clobbering a load from Ptr
according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
Definition at line 141 of file AMDGPUMemoryUtils.cpp.
References llvm::tgtok::Def, and I.
Referenced by isClobberedInFunction().
bool llvm::AMDGPU::isSGPR | ( | unsigned | Reg, |
const MCRegisterInfo * | TRI | ||
) |
Is Reg - scalar register.
Definition at line 1797 of file AMDGPUBaseInfo.cpp.
References llvm::MCRegisterClass::contains(), llvm::AMDGPU::CPol::SCC, and TRI.
LLVM_READNONE bool llvm::AMDGPU::isShader | ( | CallingConv::ID | cc | ) |
Definition at line 1616 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.
Referenced by llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::SITargetLowering::LowerCall(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().
bool llvm::AMDGPU::isSI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1694 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().
bool llvm::AMDGPU::isSISrcFPOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Is this floating-point operand?
Definition at line 1894 of file AMDGPUBaseInfo.cpp.
References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
bool llvm::AMDGPU::isSISrcInlinableOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Does this operand support only inlinable literals?
Definition at line 1923 of file AMDGPUBaseInfo.cpp.
References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
bool llvm::AMDGPU::isSISrcOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Can this operand also contain immediate values?
Definition at line 1887 of file AMDGPUBaseInfo.cpp.
References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_SRC_FIRST, OPERAND_SRC_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIInstrInfo::isOperandLegal().
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Definition at line 1152 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Hwreg::Opr.
Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().
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Definition at line 1092 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::CustomOperand< T >::Cond, Context, and llvm::AMDGPU::CustomOperand< T >::Name.
bool llvm::AMDGPU::isVI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 1702 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().
LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP | ( | unsigned | Opc | ) |
Definition at line 383 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), and llvm::AMDGPUDisassembler::getInstruction().
const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsic | ( | unsigned | Intr | ) |
const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsic | ( | unsigned | Intr | ) |
LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg | ( | unsigned | Reg | ) |
Convert hardware register Reg
to a pseudo register.
Definition at line 1877 of file AMDGPUBaseInfo.cpp.
References MAP_REG2REG.
AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN | ( | StringRef | CPU | ) |
Definition at line 152 of file TargetParser.cpp.
References GK_NONE.
Referenced by getCanonicalArchName(), llvm::AMDGPUTargetStreamer::getElfMach(), and getIsaVersion().
AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 | ( | StringRef | CPU | ) |
Definition at line 161 of file TargetParser.cpp.
References GK_NONE.
Referenced by getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().
void llvm::AMDGPU::replaceConstantUsesInFunction | ( | ConstantExpr * | C, |
const Function * | F | ||
) |
Replace all uses of constant C
with instructions in F
.
Definition at line 55 of file AMDGPUMemoryUtils.cpp.
References collectFunctionUses(), llvm::convertConstantExprsToInstructions(), F, and I.
TT
, false otherwise. Definition at line 943 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::r600.
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().
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Definition at line 64 of file AMDGPUMemoryUtils.cpp.
References llvm::append_range(), assert(), F, llvm::Value::getName(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), isKernelCC(), llvm::MipsISD::Ret, and llvm::Value::users().
Referenced by findVariablesToLower().
bool llvm::AMDGPU::splitMUBUFOffset | ( | uint32_t | Imm, |
uint32_t & | SOffset, | ||
uint32_t & | ImmOffset, | ||
const GCNSubtarget * | Subtarget, | ||
Align | Alignment | ||
) |
Definition at line 2252 of file AMDGPUBaseInfo.cpp.
References llvm::alignDown(), llvm::GCNSubtarget::getGeneration(), High, llvm::RISCVMatInt::Imm, llvm::Low, and llvm::AMDGPUSubtarget::SEA_ISLANDS.
Referenced by setBufferOffsets().
Definition at line 25 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand().
Definition at line 23 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand(), and getOprIdx().
Definition at line 24 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand(), and getOprIdx().
Definition at line 26 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperandVal().
Definition at line 1301 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat(), and llvm::SIInstrInfo::getScratchRsrcWords23().
Definition at line 1302 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
Definition at line 1303 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
Definition at line 1304 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().