LLVM  14.0.0git
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llvm::AMDGPU Namespace Reference

Namespaces

 CPol
 
 DPP
 
 ElfNote
 
 EncValues
 
 Exp
 
 HSAMD
 
 Hwreg
 
 IsaInfo
 
 MTBUFFormat
 
 PALMD
 
 SDWA
 
 SendMsg
 
 Swizzle
 
 VGPRIndexMode
 
 VOP3PEncoding
 

Classes

struct  D16ImageDimIntrinsic
 
struct  GcnBufferFormatInfo
 
struct  ImageDimIntrinsicInfo
 
struct  IsaVersion
 Instruction set architecture version. More...
 
struct  MIMGBaseOpcodeInfo
 
struct  MIMGBiasMappingInfo
 
struct  MIMGDimInfo
 
struct  MIMGG16MappingInfo
 
struct  MIMGInfo
 
struct  MIMGLZMappingInfo
 
struct  MIMGMIPMappingInfo
 
struct  MTBUFInfo
 
struct  MUBUFInfo
 
struct  RsrcIntrinsic
 
struct  SIModeRegisterDefaults
 
struct  SMInfo
 
struct  VOPInfo
 
struct  Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction. More...
 

Enumerations

enum  GPUKind : uint32_t {
  GK_NONE = 0, GK_R600 = 1, GK_R630 = 2, GK_RS880 = 3,
  GK_RV670 = 4, GK_RV710 = 5, GK_RV730 = 6, GK_RV770 = 7,
  GK_CEDAR = 8, GK_CYPRESS = 9, GK_JUNIPER = 10, GK_REDWOOD = 11,
  GK_SUMO = 12, GK_BARTS = 13, GK_CAICOS = 14, GK_CAYMAN = 15,
  GK_TURKS = 16, GK_R600_FIRST = GK_R600, GK_R600_LAST = GK_TURKS, GK_GFX600 = 32,
  GK_GFX601 = 33, GK_GFX602 = 34, GK_GFX700 = 40, GK_GFX701 = 41,
  GK_GFX702 = 42, GK_GFX703 = 43, GK_GFX704 = 44, GK_GFX705 = 45,
  GK_GFX801 = 50, GK_GFX802 = 51, GK_GFX803 = 52, GK_GFX805 = 53,
  GK_GFX810 = 54, GK_GFX900 = 60, GK_GFX902 = 61, GK_GFX904 = 62,
  GK_GFX906 = 63, GK_GFX908 = 64, GK_GFX909 = 65, GK_GFX90A = 66,
  GK_GFX90C = 67, GK_GFX1010 = 71, GK_GFX1011 = 72, GK_GFX1012 = 73,
  GK_GFX1013 = 74, GK_GFX1030 = 75, GK_GFX1031 = 76, GK_GFX1032 = 77,
  GK_GFX1033 = 78, GK_GFX1034 = 79, GK_GFX1035 = 80, GK_AMDGCN_FIRST = GK_GFX600,
  GK_AMDGCN_LAST = GK_GFX1035
}
 GPU kinds supported by the AMDGPU target. More...
 
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0, FEATURE_FMA = 1 << 1, FEATURE_LDEXP = 1 << 2, FEATURE_FP64 = 1 << 3,
  FEATURE_FAST_FMA_F32 = 1 << 4, FEATURE_FAST_DENORMAL_F32 = 1 << 5, FEATURE_WAVE32 = 1 << 6, FEATURE_XNACK = 1 << 7,
  FEATURE_SRAMECC = 1 << 8
}
 
enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType : unsigned {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32_DEFERRED,
  OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_IMM_V2FP32,
  OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16,
  OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2FP16,
  OPERAND_REG_INLINE_C_V2INT32, OPERAND_REG_INLINE_C_V2FP32, OPERAND_KIMM32, OPERAND_KIMM16,
  OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32,
  OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT32,
  OPERAND_REG_INLINE_AC_V2FP32, OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
  OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
  OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, OPERAND_INPUT_MODS, OPERAND_SDWA_VOPC_DST
}
 

Functions

StringRef getArchNameAMDGCN (GPUKind AK)
 
StringRef getArchNameR600 (GPUKind AK)
 
StringRef getCanonicalArchName (const Triple &T, StringRef Arch)
 
GPUKind parseArchAMDGCN (StringRef CPU)
 
GPUKind parseArchR600 (StringRef CPU)
 
unsigned getArchAttrAMDGCN (GPUKind AK)
 
unsigned getArchAttrR600 (GPUKind AK)
 
void fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
 
void fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
 
IsaVersion getIsaVersion (StringRef GPU)
 
bool isFlatGlobalAddrSpace (unsigned AS)
 
std::pair< Register, unsigned > getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg)
 Returns base register and constant offset. More...
 
bool isLegalVOP3PShuffleMask (ArrayRef< int > Mask)
 
const RsrcIntrinsic * lookupRsrcIntrinsic (unsigned Intr)
 
const D16ImageDimIntrinsic * lookupD16ImageDimIntrinsic (unsigned Intr)
 
const ImageDimIntrinsicInfo * getImageDimIntrinsicInfo (unsigned Intr)
 
const ImageDimIntrinsicInfo * getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp32 (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getIfAddr64Inst (uint16_t Opcode)
 Check if Opcode is an Addr64 opcode. More...
 
LLVM_READONLY int getMUBUFNoLdsInst (uint16_t Opcode)
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalSaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalVaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXNoSDstOp (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSTfromSS (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSSfromSV (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSVfromSS (uint16_t Opcode)
 
Optional< uint8_t > getHsaAbiVersion (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion2 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion3 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion4 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion3Or4 (const MCSubtargetInfo *STI)
 
int getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode (unsigned Opc)
 
int getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
unsigned getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
 
int getMTBUFBaseOpcode (unsigned Opc)
 
int getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int getMTBUFElements (unsigned Opc)
 
bool getMTBUFHasVAddr (unsigned Opc)
 
bool getMTBUFHasSrsrc (unsigned Opc)
 
bool getMTBUFHasSoffset (unsigned Opc)
 
int getMUBUFBaseOpcode (unsigned Opc)
 
int getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int getMUBUFElements (unsigned Opc)
 
bool getMUBUFHasVAddr (unsigned Opc)
 
bool getMUBUFHasSrsrc (unsigned Opc)
 
bool getMUBUFHasSoffset (unsigned Opc)
 
bool getMUBUFIsBufferInv (unsigned Opc)
 
bool getSMEMIsBuffer (unsigned Opc)
 
bool getVOP1IsSingle (unsigned Opc)
 
bool getVOP2IsSingle (unsigned Opc)
 
bool getVOP3IsSingle (unsigned Opc)
 
int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getVmcntBitMask (const IsaVersion &Version)
 
unsigned getExpcntBitMask (const IsaVersion &Version)
 
unsigned getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned getWaitcntBitMask (const IsaVersion &Version)
 
unsigned decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
Waitcnt decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool getHasColorExport (const Function &F)
 
bool getHasDepthExport (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isGraphics (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::ID CC)
 
bool isModuleEntryFunctionCC (CallingConv::ID CC)
 
bool hasXNACK (const MCSubtargetInfo &STI)
 
bool hasSRAMECC (const MCSubtargetInfo &STI)
 
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool hasGFX10A16 (const MCSubtargetInfo &STI)
 
bool hasG16 (const MCSubtargetInfo &STI)
 
bool hasPackedD16 (const MCSubtargetInfo &STI)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
bool isGFX9 (const MCSubtargetInfo &STI)
 
bool isGFX9Plus (const MCSubtargetInfo &STI)
 
bool isGFX10 (const MCSubtargetInfo &STI)
 
bool isGFX10Plus (const MCSubtargetInfo &STI)
 
bool isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool isGFX10_AEncoding (const MCSubtargetInfo &STI)
 
bool isGFX10_BEncoding (const MCSubtargetInfo &STI)
 
bool hasGFX10_3Insts (const MCSubtargetInfo &STI)
 
bool isGFX90A (const MCSubtargetInfo &STI)
 
bool hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
 
bool isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this operand support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableIntLiteralV216 (int32_t Literal)
 
bool isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isArgPassedInSGPR (const Argument *A)
 
static bool hasSMEMByteOffset (const MCSubtargetInfo &ST)
 
static bool hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
 
bool isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
 
static bool isDwordAligned (uint64_t ByteOffset)
 
uint64_t convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets. More...
 
Optional< int64_t > getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
 
Optional< int64_t > getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned getNumFlatOffsetBits (const MCSubtargetInfo &ST, bool Signed)
 For FLAT segment the offset must be positive; MSB is ignored and forced to zero. More...
 
bool splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
const GcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
 
const GcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READONLY int getSOPPWithRelaxation (uint16_t Opcode)
 
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfo (unsigned DimEnum)
 
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding (uint8_t DimEnc)
 
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
 
const LLVM_READONLY MIMGLZMappingInfo * getMIMGLZMappingInfo (unsigned L)
 
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo (unsigned MIP)
 
const LLVM_READONLY MIMGBiasMappingInfo * getMIMGBiasMappingInfo (unsigned Bias)
 
const LLVM_READONLY MIMGG16MappingInfo * getMIMGG16MappingInfo (unsigned G)
 
const LLVM_READONLY MIMGInfo * getMIMGInfo (unsigned Opc)
 
LLVM_READNONE bool isKernel (CallingConv::ID CC)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 
LLVM_READNONE bool isInlinableIntLiteral (int64_t Literal)
 Is this literal inlinable, and not one of the values intended for floating point values. More...
 
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
LLVM_READNONE bool isLegal64BitDPPControl (unsigned DC)
 
bool isKernelCC (const Function *Func)
 
Align getAlign (DataLayout const &DL, const GlobalVariable *GV)
 
static void collectFunctionUses (User *U, const Function *F, SetVector< Instruction * > &InstUsers)
 
void replaceConstantUsesInFunction (ConstantExpr *C, const Function *F)
 Replace all uses of constant C with instructions in F. More...
 
static bool shouldLowerLDSToStruct (const GlobalVariable &GV, const Function *F)
 
std::vector< GlobalVariable * > findVariablesToLower (Module &M, const Function *F)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 

Enumeration Type Documentation

◆ ArchFeatureKind

enum llvm::AMDGPU::ArchFeatureKind : uint32_t
Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 
FEATURE_WAVE32 
FEATURE_XNACK 
FEATURE_SRAMECC 

Definition at line 112 of file TargetParser.h.

◆ Fixups

enum llvm::AMDGPU::Fixups
Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ GPUKind

enum llvm::AMDGPU::GPUKind : uint32_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE 
GK_R600 
GK_R630 
GK_RS880 
GK_RV670 
GK_RV710 
GK_RV730 
GK_RV770 
GK_CEDAR 
GK_CYPRESS 
GK_JUNIPER 
GK_REDWOOD 
GK_SUMO 
GK_BARTS 
GK_CAICOS 
GK_CAYMAN 
GK_TURKS 
GK_R600_FIRST 
GK_R600_LAST 
GK_GFX600 
GK_GFX601 
GK_GFX602 
GK_GFX700 
GK_GFX701 
GK_GFX702 
GK_GFX703 
GK_GFX704 
GK_GFX705 
GK_GFX801 
GK_GFX802 
GK_GFX803 
GK_GFX805 
GK_GFX810 
GK_GFX900 
GK_GFX902 
GK_GFX904 
GK_GFX906 
GK_GFX908 
GK_GFX909 
GK_GFX90A 
GK_GFX90C 
GK_GFX1010 
GK_GFX1011 
GK_GFX1012 
GK_GFX1013 
GK_GFX1030 
GK_GFX1031 
GK_GFX1032 
GK_GFX1033 
GK_GFX1034 
GK_GFX1035 
GK_AMDGCN_FIRST 
GK_AMDGCN_LAST 

Definition at line 36 of file TargetParser.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned
Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_IMM_FP16_DEFERRED 
OPERAND_REG_IMM_FP32_DEFERRED 
OPERAND_REG_IMM_V2FP16 
OPERAND_REG_IMM_V2INT16 
OPERAND_REG_IMM_V2INT32 
OPERAND_REG_IMM_V2FP32 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT32 
OPERAND_REG_INLINE_C_V2FP32 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 
OPERAND_REG_INLINE_AC_INT16 

Operands with an AccVGPR register or inline constant.

OPERAND_REG_INLINE_AC_INT32 
OPERAND_REG_INLINE_AC_FP16 
OPERAND_REG_INLINE_AC_FP32 
OPERAND_REG_INLINE_AC_FP64 
OPERAND_REG_INLINE_AC_V2INT16 
OPERAND_REG_INLINE_AC_V2FP16 
OPERAND_REG_INLINE_AC_V2INT32 
OPERAND_REG_INLINE_AC_V2FP32 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_REG_INLINE_AC_FIRST 
OPERAND_REG_INLINE_AC_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 

Definition at line 143 of file SIDefines.h.

◆ TargetIndex

enum llvm::AMDGPU::TargetIndex
Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 338 of file AMDGPU.h.

Function Documentation

◆ collectFunctionUses()

static void llvm::AMDGPU::collectFunctionUses ( User *  U,
const Function *  F,
SetVector< Instruction * > &  InstUsers 
)
static

Definition at line 36 of file AMDGPULDSUtils.cpp.

References llvm::append_range(), F, I, llvm::SetVector< T, Vector, Set >::insert(), and llvm::Value::users().

Referenced by replaceConstantUsesInFunction().

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits ( const MCSubtargetInfo &  ST,
uint64_t  ByteOffset 
)

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 1890 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), isDwordAligned(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 937 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 941 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by decodeWaitcnt().

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 925 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by decodeWaitcnt().

◆ decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt ( const IsaVersion &  Version,
unsigned  Encoded 
)

Definition at line 953 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, Version, and llvm::AMDGPU::Waitcnt::VmCnt.

◆ decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned &  Vmcnt,
unsigned &  Expcnt,
unsigned &  Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9 only) Vmcnt = Waitcnt[3:0] | Waitcnt[15:14] (gfx9+ only) Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8] (pre-gfx10 only) Lgkmcnt = Waitcnt[13:8] (gfx10+ only)

Definition at line 946 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 972 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 977 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by encodeWaitcnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 961 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion &  Version,
const Waitcnt &  Decoded 
)

Definition at line 992 of file AMDGPUBaseInfo.cpp.

References encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, Version, and llvm::AMDGPU::Waitcnt::VmCnt.

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion &  Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt (pre-gfx9 only) Waitcnt[3:0] = Vmcnt[3:0] (gfx9+ only) Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt (pre-gfx10 only) Waitcnt[13:8] = Lgkmcnt (gfx10+ only) Waitcnt[15:14] = Vmcnt[5:4] (gfx9+ only)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 983 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and Version.

Referenced by encodeWaitcnt().

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > &  Values)

Definition at line 176 of file TargetParser.cpp.

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > &  Values)

Definition at line 182 of file TargetParser.cpp.

◆ findVariablesToLower()

std::vector< GlobalVariable * > llvm::AMDGPU::findVariablesToLower ( Module &  M,
const Function *  F 
)

Definition at line 109 of file AMDGPULDSUtils.cpp.

References F, llvm::AMDGPUAS::LOCAL_ADDRESS, M, and shouldLowerLDSToStruct().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)

◆ getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp ( const MIMGBaseOpcodeInfo *  BaseOpcode,
const MIMGDimInfo *  Dim,
bool  IsA16,
bool  IsG16Supported 
)

Definition at line 159 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getAlign()

Align llvm::AMDGPU::getAlign ( DataLayout const &  DL,
const GlobalVariable *  GV 
)

Definition at line 31 of file AMDGPULDSUtils.cpp.

References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind  AK)

Definition at line 164 of file TargetParser.cpp.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind  AK)

Definition at line 170 of file TargetParser.cpp.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind  AK)

Definition at line 134 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind  AK)

Definition at line 140 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)

◆ getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset ( MachineRegisterInfo &  MRI,
Register  Reg 
)

Returns base register and constant offset.

Definition at line 17 of file AMDGPUGlobalISelUtils.cpp.

References llvm::sampleprof::Base, llvm::tgtok::Def, llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::mi_match(), MRI, and Offset.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName ( const Triple &  T,
StringRef  Arch 
)

Definition at line 234 of file TargetParser.cpp.

References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), and parseArchR600().

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getDefaultAmdhsaKernelDescriptor()

amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor ( const MCSubtargetInfo *  STI)

Definition at line 803 of file AMDGPUBaseInfo.cpp.

References AMDHSA_BITS_SET, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), isGFX90A(), llvm::amdhsa::kernel_descriptor_t::kernel_code_properties, llvm::FeatureBitset::test(), and Version.

◆ getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32 ( uint16_t  Opcode)

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion &  Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 904 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV ( uint16_t  Opcode)
Returns
SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS ( uint16_t  Opcode)
Returns
ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS ( uint16_t  Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getGcnBufferFormatInfo() [1/2]

const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t  BitsPerComp,
uint8_t  NumComponents,
uint8_t  NumFormat,
const MCSubtargetInfo &  STI 
)

Definition at line 2030 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus().

Referenced by getBufferFormatWithCompCount().

◆ getGcnBufferFormatInfo() [2/2]

const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t  Format,
const MCSubtargetInfo &  STI 
)

Definition at line 2040 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp ( uint16_t  Opcode)
Returns
SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

◆ getGlobalVaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp ( uint16_t  Opcode)
Returns
VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport ( const Function &  F)

Definition at line 1359 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, F, and getIntegerAttribute().

Referenced by generateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport ( const Function &  F)

Definition at line 1366 of file AMDGPUBaseInfo.cpp.

References F, and getIntegerAttribute().

Referenced by generateEndPgm().

◆ getHsaAbiVersion()

Optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion ( const MCSubtargetInfo *  STI)
Returns
HSA OS ABI Version identification.

Definition at line 91 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, AmdhsaCodeObjectVersion, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::Triple::getOS(), llvm::MCSubtargetInfo::getTargetTriple(), llvm::None, and llvm::report_fatal_error().

Referenced by llvm::createAMDGPUAsmBackend(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), isHsaAbiVersion2(), isHsaAbiVersion3(), isHsaAbiVersion4(), llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst ( uint16_t  Opcode)

Check if Opcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

◆ getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode ( unsigned  BaseOpcode,
unsigned  Dim 
)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned  Intr)

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::GCNTTIImpl::instCombineIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), and llvm::AMDGPUInstructionSelector::select().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function &  F)

Definition at line 1355 of file AMDGPUBaseInfo.cpp.

References F, and getIntegerAttribute().

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function &  F,
StringRef  Name,
int  Default 
)
Returns
Integer value requested using F's Name attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

Definition at line 855 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), and F.

Referenced by llvm::GCNSubtarget::getBaseMaxNumSGPRs(), llvm::GCNSubtarget::getBaseMaxNumVGPRs(), getHasColorExport(), getHasDepthExport(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), getInitialPSInputAddr(), and llvm::AMDGPUTTIImpl::getUnrollingPreferences().

◆ getIntegerPairAttribute()

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function &  F,
StringRef  Name,
std::pair< int, int >  Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 870 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), and F.

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef  GPU)

Definition at line 187 of file TargetParser.cpp.

References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_NONE, and parseArchAMDGCN().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::emitStartOfAsmFile(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPUInstPrinter::printWaitFlag(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion &  Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 908 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( unsigned  Opc,
unsigned  NewChannels 
)

Definition at line 151 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)

Definition at line 318 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo &  STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 1555 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, and llvm::Triple::r600.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().

◆ getMIMGBaseOpcode()

const LLVM_READONLY MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode ( unsigned  Opc)

Definition at line 146 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.

◆ getMIMGBaseOpcodeInfo()

const LLVM_READONLY MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned  BaseOpcode)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGBiasMappingInfo()

const LLVM_READONLY MIMGBiasMappingInfo* llvm::AMDGPU::getMIMGBiasMappingInfo ( unsigned  Bias)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfo()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfo ( unsigned  DimEnum)

◆ getMIMGDimInfoByAsmSuffix()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef  AsmSuffix)

◆ getMIMGDimInfoByEncoding()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t  DimEnc)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGG16MappingInfo()

const LLVM_READONLY MIMGG16MappingInfo* llvm::AMDGPU::getMIMGG16MappingInfo ( unsigned  G)

◆ getMIMGInfo()

const LLVM_READONLY MIMGInfo* llvm::AMDGPU::getMIMGInfo ( unsigned  Opc)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

const LLVM_READONLY MIMGLZMappingInfo* llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned  L)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGMIPMappingInfo()

const LLVM_READONLY MIMGMIPMappingInfo* llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned  MIP)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode ( unsigned  BaseOpcode,
unsigned  MIMGEncoding,
unsigned  VDataDwords,
unsigned  VAddrDwords 
)

Definition at line 139 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode ( unsigned  Opc)

Definition at line 230 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements ( unsigned  Opc)

Definition at line 240 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset ( unsigned  Opc)

Definition at line 255 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc ( unsigned  Opc)

Definition at line 250 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr ( unsigned  Opc)

Definition at line 245 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode ( unsigned  BaseOpc,
unsigned  Elements 
)

Definition at line 235 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned  Opc)

Definition at line 260 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements ( unsigned  Opc)

Definition at line 270 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned  Opc)

Definition at line 285 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned  Opc)

Definition at line 280 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned  Opc)

Definition at line 275 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv ( unsigned  Opc)

Definition at line 290 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFNoLdsInst()

LLVM_READONLY int llvm::AMDGPU::getMUBUFNoLdsInst ( uint16_t  Opcode)

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode ( unsigned  BaseOpc,
unsigned  Elements 
)

Definition at line 265 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)

Referenced by llvm::SITargetLowering::AddIMGInit(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), decodeOperand_AVLdSt_Any(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), frameIndexMayFold(), getFlatScratchSpillOpcode(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::getRegClass(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIInstrInfo::hasModifiers(), insertNamedMCOperand(), IsAGPROperand(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isImmOperandLegal(), isInlineConstantIfFolded(), llvm::SIInstrInfo::isOperandLegal(), isSendMsgTraceDataOrGDS(), isValidDPP8(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), AMDGPUMCInstLower::lower(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), nodesHaveSameOperandValue(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), removeModOperands(), tryConstantFoldOp(), updateOperand(), and llvm::SIInstrInfo::verifyInstruction().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits ( const MCSubtargetInfo &  ST,
bool  Signed 
)

For FLAT segment the offset must be positive; MSB is ignored and forced to zero.

Returns
The number of bits available for the offset field in flat instructions.

Definition at line 1925 of file AMDGPUBaseInfo.cpp.

References isGFX10(), Signed, and llvm::ARM_MB::ST.

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)
inline

Definition at line 842 of file AMDGPUBaseInfo.h.

References getOperandSize(), and llvm::MCInstrDesc::OpInfo.

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo &  OpInfo)
inline

Definition at line 797 of file AMDGPUBaseInfo.h.

References llvm_unreachable, OPERAND_KIMM16, OPERAND_KIMM32, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2INT32, and llvm::MCOperandInfo::OperandType.

Referenced by getOperandSize().

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass &  RC)

Get the size in bits of a register from the register class RC.

Definition at line 1725 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

Get the size in bits of a register from the register class RC.

Definition at line 1620 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo *  MRI,
const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Get size of register operand.

Definition at line 1729 of file AMDGPUBaseInfo.cpp.

References assert(), getRegBitWidth(), MRI, llvm::MCInstrDesc::NumOperands, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t  Opcode)

◆ getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer ( unsigned  Opc)

Definition at line 295 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getSMRDEncodedLiteralOffset32()

Optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 ( const MCSubtargetInfo &  ST,
int64_t  ByteOffset 
)
Returns
The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 1916 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), isDwordAligned(), llvm::isUInt< 32 >(), llvm::None, and llvm::ARM_MB::ST.

◆ getSMRDEncodedOffset()

Optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo &  ST,
int64_t  ByteOffset,
bool  IsBuffer 
)
Returns
The encoding that will be used for ByteOffset in the SMRD offset field, or None if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 1899 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isLegalSMRDEncodedUnsignedOffset(), llvm::None, and llvm::ARM_MB::ST.

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

Referenced by shrinkScalarCompare().

◆ getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation ( uint16_t  Opcode)

◆ getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp ( uint16_t  Opcode)

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion &  Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 895 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle ( unsigned  Opc)

Definition at line 300 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle ( unsigned  Opc)

Definition at line 305 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle ( unsigned  Opc)

Definition at line 310 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding(), and tryAddToFoldList().

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion &  Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 912 of file AMDGPUBaseInfo.cpp.

References Version.

Referenced by encodeWaitcnt().

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch ( const MCSubtargetInfo &  STI)

Definition at line 1489 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ hasG16()

bool llvm::AMDGPU::hasG16 ( const MCSubtargetInfo &  STI)

Definition at line 1435 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts ( const MCSubtargetInfo &  STI)

Definition at line 1481 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ hasGFX10A16()

bool llvm::AMDGPU::hasGFX10A16 ( const MCSubtargetInfo &  STI)

Definition at line 1431 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo &  STI)

Definition at line 1427 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo &  STI)

Definition at line 1439 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasSMEMByteOffset()

static bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo &  ST)
static

Definition at line 1864 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), isGFX10Plus(), and llvm::ARM_MB::ST.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().

◆ hasSMRDSignedImmOffset()

static bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo &  ST)
static

Definition at line 1868 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC ( const MCSubtargetInfo &  STI)

Definition at line 1423 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo &  STI)

Definition at line 1419 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t &  Header,
const MCSubtargetInfo *  STI 
)

Definition at line 767 of file AMDGPUBaseInfo.cpp.

References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, amd_kernel_code_t::amd_kernel_code_version_major, amd_kernel_code_t::amd_kernel_code_version_minor, amd_kernel_code_t::amd_machine_kind, amd_kernel_code_t::amd_machine_version_major, amd_kernel_code_t::amd_machine_version_minor, amd_kernel_code_t::amd_machine_version_stepping, amd_kernel_code_t::call_convention, amd_kernel_code_t::code_properties, amd_kernel_code_t::compute_pgm_resource_registers, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), amd_kernel_code_t::group_segment_alignment, amd_kernel_code_t::kernarg_segment_alignment, amd_kernel_code_t::kernel_code_entry_byte_offset, amd_kernel_code_t::private_segment_alignment, S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, llvm::FeatureBitset::test(), Version, and amd_kernel_code_t::wavefront_size.

◆ isArgPassedInSGPR()

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument *  A)

Definition at line 1837 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, F, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::GCNTTIImpl::isSourceOfDivergence(), and llvm::AMDGPUInstrInfo::isUniformMMO().

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo &  STI)

Definition at line 1447 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), and llvm::AMDGPU::Hwreg::isValidHwreg().

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)

Definition at line 1389 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, cc, and isGraphics().

Referenced by llvm::SIProgramInfo::getPGMRSrc1(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

◆ isDwordAligned()

static bool llvm::AMDGPU::isDwordAligned ( uint64_t  ByteOffset)
static

Definition at line 1886 of file AMDGPUBaseInfo.cpp.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID  CC)

Definition at line 1393 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::SITargetLowering::CanLowerReturn(), INITIALIZE_PASS(), isModuleEntryFunctionCC(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), mustPreserveGV(), promoteAllocasToVector(), recursivelyVisitUsers(), llvm::AMDGPUPropagateAttributesEarlyPass::run(), and llvm::SIMachineFunctionInfo::usesAGPRs().

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned  AS)
inline

Definition at line 406 of file AMDGPU.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), and llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg().

◆ isFoldableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isFoldableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1824 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), and llvm::Literal.

Referenced by updateOperand().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo &  STI)

Definition at line 1469 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by hasSMEMByteOffset().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo &  STI)

Definition at line 1463 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), getNumFlatOffsetBits(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10Plus(), and llvm::AMDGPU::Hwreg::isValidHwreg().

◆ isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding ( const MCSubtargetInfo &  STI)

Definition at line 1473 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding ( const MCSubtargetInfo &  STI)

Definition at line 1477 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), and llvm::AMDGPU::Hwreg::isValidHwreg().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus ( const MCSubtargetInfo &  STI)

Definition at line 1467 of file AMDGPUBaseInfo.cpp.

References isGFX10().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), getGcnBufferFormatInfo(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding(), llvm::AMDGPU::Hwreg::isValidHwreg(), and llvm::AMDGPU::SendMsg::isValidMsgId().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo &  STI)

Definition at line 1455 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9Plus(), llvm::AMDGPU::Hwreg::isValidHwreg(), and llvm::AMDGPU::SendMsg::isValidMsgId().

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A ( const MCSubtargetInfo &  STI)

Definition at line 1485 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getDefaultAmdhsaKernelDescriptor(), and llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus ( const MCSubtargetInfo &  STI)

Definition at line 1459 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX9().

Referenced by hasSMRDSignedImmOffset(), llvm::AMDGPUDisassembler::isGFX9Plus(), and llvm::AMDGPU::SendMsg::isValidMsgId().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue *  GV)

Definition at line 841 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.

◆ isGraphics()

LLVM_READNONE bool llvm::AMDGPU::isGraphics ( CallingConv::ID  cc)

Definition at line 1385 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, cc, and isShader().

Referenced by isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue *  GV)

Definition at line 837 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

◆ isHsaAbiVersion2()

bool llvm::AMDGPU::isHsaAbiVersion2 ( const MCSubtargetInfo *  STI)
Returns
True if HSA OS ABI Version identification is 2, false otherwise.

Definition at line 108 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2, and getHsaAbiVersion().

Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), llvm::AMDGPUAsmPrinter::emitEndOfAsmFile(), llvm::AMDGPUAsmPrinter::emitFunctionBodyEnd(), and llvm::AMDGPUAsmPrinter::emitFunctionBodyStart().

◆ isHsaAbiVersion3()

bool llvm::AMDGPU::isHsaAbiVersion3 ( const MCSubtargetInfo *  STI)
Returns
True if HSA OS ABI Version identification is 3, false otherwise.

Definition at line 114 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, and getHsaAbiVersion().

Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), and isHsaAbiVersion3Or4().

◆ isHsaAbiVersion3Or4()

bool llvm::AMDGPU::isHsaAbiVersion3Or4 ( const MCSubtargetInfo *  STI)
Returns
True if HSA OS ABI Version identification is 3 or 4, false otherwise.

Definition at line 126 of file AMDGPUBaseInfo.cpp.

References isHsaAbiVersion3(), and isHsaAbiVersion4().

Referenced by llvm::AMDGPUAsmPrinter::emitFunctionEntryLabel(), and llvm::AMDGPUAsmPrinter::emitStartOfAsmFile().

◆ isHsaAbiVersion4()

bool llvm::AMDGPU::isHsaAbiVersion4 ( const MCSubtargetInfo *  STI)
Returns
True if HSA OS ABI Version identification is 4, false otherwise.

Definition at line 120 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, and getHsaAbiVersion().

Referenced by isHsaAbiVersion3Or4().

◆ isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t  Literal)
inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line 849 of file AMDGPUBaseInfo.h.

References llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), isInlinableIntLiteralV216(), isInlinableLiteral16(), isInlinableLiteral32(), isInlinableLiteral64(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().

◆ isInlinableIntLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteralV216 ( int32_t  Literal)

Definition at line 1813 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1779 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1753 of file AMDGPUBaseInfo.cpp.

References f(), llvm::FloatToBits(), isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::isInlineConstant(), and shrinkScalarLogicOp().

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

Is this literal inlinable.

Definition at line 1736 of file AMDGPUBaseInfo.cpp.

References llvm::DoubleToBits(), isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1798 of file AMDGPUBaseInfo.cpp.

References assert(), isInlinableLiteral16(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned  IntrID)
Returns
true if the intrinsic is divergent

Definition at line 2026 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC)
inline

Definition at line 732 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::SITargetLowering::LowerReturn().

◆ isKernelCC()

bool llvm::AMDGPU::isKernelCC ( const Function *  Func)

Definition at line 27 of file AMDGPULDSUtils.cpp.

References isModuleEntryFunctionCC().

Referenced by shouldLowerLDSToStruct().

◆ isLegal64BitDPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegal64BitDPPControl ( unsigned  DC)
inline

Definition at line 916 of file AMDGPUBaseInfo.h.

References DC, llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, and llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset ( const MCSubtargetInfo &  ST,
int64_t  EncodedOffset,
bool  IsBuffer 
)

Definition at line 1878 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset(), and llvm::ARM_MB::ST.

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset ( const MCSubtargetInfo &  ST,
int64_t  EncodedOffset 
)

Definition at line 1872 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset(), llvm::isUInt< 8 >(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedOffset().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo &  ST,
int64_t  ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

◆ isLegalVOP3PShuffleMask()

bool llvm::AMDGPU::isLegalVOP3PShuffleMask ( ArrayRef< int >  Mask)

Definition at line 61 of file AMDGPUGlobalISelUtils.cpp.

References assert(), and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::AMDGPULegalizerInfo::legalizeShuffleVector().

◆ isModuleEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC ( CallingConv::ID  CC)

Definition at line 1410 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, and isEntryFunctionCC().

Referenced by isKernelCC().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue *  GV)

Definition at line 845 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isRegIntersect()

bool llvm::AMDGPU::isRegIntersect ( unsigned  Reg0,
unsigned  Reg1,
const MCRegisterInfo *  TRI 
)

Is there any intersection between registers.

Definition at line 1500 of file AMDGPUBaseInfo.cpp.

References TRI.

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( unsigned  Reg,
const MCRegisterInfo *  TRI 
)

Is Reg - scalar register.

Definition at line 1493 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), llvm::AMDGPU::CPol::SCC, and TRI.

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)

Definition at line 1370 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, and cc.

Referenced by llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::SITargetLowering::LowerCall(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo &  STI)

Definition at line 1443 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), and llvm::AMDGPU::Hwreg::isValidHwreg().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Is this floating-point operand?

Definition at line 1582 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Does this operand support only inlinable literals?

Definition at line 1611 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Can this operand also contain immediate values?

Definition at line 1575 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_SRC_FIRST, OPERAND_SRC_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIInstrInfo::isOperandLegal().

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo &  STI)

Definition at line 1451 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), llvm::AMDGPU::Hwreg::isValidHwreg(), and llvm::AMDGPU::SendMsg::isValidMsgId().

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned  Intr)

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned  Intr)

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::SITargetLowering::getTgtMemIntrinsic().

◆ mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg ( unsigned  Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 1567 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef  CPU)

Definition at line 146 of file TargetParser.cpp.

References GK_NONE.

Referenced by getCanonicalArchName(), llvm::AMDGPUTargetStreamer::getElfMach(), and getIsaVersion().

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef  CPU)

Definition at line 155 of file TargetParser.cpp.

References GK_NONE.

Referenced by getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().

◆ replaceConstantUsesInFunction()

void llvm::AMDGPU::replaceConstantUsesInFunction ( ConstantExpr *  C,
const Function *  F 
)

Replace all uses of constant C with instructions in F.

Definition at line 56 of file AMDGPULDSUtils.cpp.

References collectFunctionUses(), llvm::convertConstantExprsToInstructions(), F, and I.

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple &  TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 851 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::r600.

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().

◆ shouldLowerLDSToStruct()

static bool llvm::AMDGPU::shouldLowerLDSToStruct ( const GlobalVariable &  GV,
const Function *  F 
)
static

Definition at line 65 of file AMDGPULDSUtils.cpp.

References llvm::append_range(), assert(), F, llvm::Value::getName(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), isKernelCC(), llvm::MipsISD::Ret, and llvm::Value::users().

Referenced by findVariablesToLower().

◆ splitMUBUFOffset()

bool llvm::AMDGPU::splitMUBUFOffset ( uint32_t  Imm,
uint32_t &  SOffset,
uint32_t &  ImmOffset,
const GCNSubtarget *  Subtarget,
Align  Alignment 
)

Definition at line 1940 of file AMDGPUBaseInfo.cpp.

References llvm::alignDown(), llvm::GCNSubtarget::getGeneration(), High, llvm::AMDGPUSubtarget::SEA_ISLANDS, and llvm::Align::value().

Referenced by setBufferOffsets().

Variable Documentation

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 1249 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat(), and llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 1250 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 1251 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 1252 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

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