Namespaces
namespace	Barrier
namespace	CPol
namespace	DefaultBufferSizes
namespace	DepCtr
namespace	DPP
namespace	DWARFAS
namespace	ElfNote
namespace	EncValues
namespace	Exp
namespace	GenericVersion
	Generic target versions emitted by this version of LLVM.
namespace	HazardClass
namespace	HSAMD
namespace	HWEncoding
namespace	Hwreg
namespace	impl
namespace	ImplicitArg
namespace	IsaInfo
namespace	MFMAScaleFormats
namespace	MTBUFFormat
namespace	PALMD
namespace	SDWA
namespace	SendMsg
namespace	Swizzle
namespace	SyntheticAperture
namespace	UCVersion
namespace	UfmtGFX10
namespace	UfmtGFX11
namespace	VGPRIndexMode
namespace	VirtRegFlag
namespace	VOP3PEncoding
namespace	VOPD
namespace	WaitEvent
namespace	WMMA
namespace	WMMAMods

Classes
struct	AMDGPUBlockingCyclesInfo
class	AMDGPUMCInstrAnalysis
struct	AMDGPUMCKernelCodeT
struct	CanBeVOPD
struct	ClassMatch
class	ClusterDimsAttr
struct	CoExecInfo
	Co-execution characteristics for a multi-cycle instruction. More...
struct	CoExecSlotInfo
	Per-slot info: which instruction classes may co-execute here. More...
struct	ConsumerTarget
struct	CustomOperand
struct	CustomOperandVal
struct	DPMACCInstructionInfo
struct	EncodingField
struct	EncodingFields
struct	FP4FP8DstByteSelInfo
struct	FuncInfo
struct	GcnBufferFormatInfo
struct	GVUsesInfoTy
struct	HardwareLimits
	Represents the hardware counter limits for different wait count types. More...
struct	HazardAntiHintRule
struct	HazardContext
struct	HazardSide
class	HWEvents
	Bit mask of hardware events. More...
struct	ImageDimIntrinsicInfo
struct	Incoming
	Incoming for lane mask phi as machine instruction, incoming register `Reg` and incoming block `Block` are taken from machine instruction. More...
struct	InfoSectionData
class	IntrinsicLaneMaskAnalyzer
struct	IsaVersion
	Instruction set architecture version. More...
class	LaneMaskConstants
class	LoopFinder
	Helper class that detects loops which require us to lower an i1 COPY into bitwise manipulation. More...
struct	MAIInstInfo
struct	MCKernelDescriptor
struct	MFMA_F8F6F4_Info
struct	MIMGBaseOpcodeInfo
struct	MIMGBiasMappingInfo
struct	MIMGDimInfo
struct	MIMGG16MappingInfo
struct	MIMGInfo
struct	MIMGLZMappingInfo
struct	MIMGMIPMappingInfo
struct	MIMGOffsetMappingInfo
struct	MTBUFInfo
struct	MUBUFInfo
class	PhiIncomingAnalysis
	Helper class that determines the relationship between incoming values of a phi in the control flow graph to determine where an incoming value can simply be taken as a scalar lane mask as-is, and where it needs to be merged with another, previously defined lane mask. More...
class	PhiLoweringHelper
struct	PredicateMapping
class	RegBankLegalizeHelper
struct	RegBankLegalizeRule
class	RegBankLegalizeRules
struct	RegBankLLTMapping
struct	RsrcIntrinsic
class	SetOfRulesForOpcode
struct	SMInfo
class	TargetID
struct	True16D16Info
struct	VOP3PHasNoOpSelHiInfo
struct	VOPC64DPPInfo
struct	VOPCDPPAsmOnlyInfo
struct	VOPDComponentInfo
struct	VOPDInfo
struct	VOPDXYInfo
struct	VOPInfo
struct	VOPTrue16Info
class	Waitcnt
	Represents the counter values to wait for in an s_waitcnt instruction. More...
struct	WaterfallInfo
	Holds waterfall loop information: the set of SGPR operand registers that need waterfalling, and an instruction range [Start, End) to wrap in the loop. More...
struct	WindowSpec
struct	WMMAInstInfo
struct	WMMAOpcodeMappingInfo

Typedefs
using	AMDGPUFeatureBitset = Bitset<NUM_FEATURES>
using	R600FeatureBitset = Bitset<R600_NUM_FEATURES>
using	CoExecMaskT = CoExecMask
using	FunctionVariableMap = MapVector<Function , DenseSet<GlobalVariable >>
using	VariableFunctionMap = DenseMap<GlobalVariable , DenseSet<Function >>
using	HazardClassMask = uint32_t
using	RulePredicate = bool (*)(const HazardContext &)
using	InstPredicate = bool (*)(const MachineInstr &, const HazardContext &)
using	AdvanceForRawWindowFn
using	TargetIDSetting = AMDGPU::TargetIDSetting
using	TargetID = AMDGPU::TargetID
template<unsigned Bit, unsigned D = 0>
using	EncodingBit = EncodingField<Bit, Bit, D>

Enumerations
enum class	FlatAddrSpace : unsigned { FLAT , FlatGlobal , FlatScratch }
enum class	AsyncStages : uint32_t { NONE = 0 , TENSOR = 1u << 0 , GLOBAL_LOAD_ASYNC_TO_LDS = 1u << 1 , GLOBAL_LOAD_ASYNC_TO_LDS_MCAST = 1u << 2 , GLOBAL_STORE_ASYNC_FROM_LDS = 1u << 3 , RESERVED_4 = 1u << 4 , BUFFER_GLOBAL_LOAD = 1u << 5 , RESERVED_6 = 1u << 6 , RESERVED_7 = 1u << 7 , RESERVED_8 = 1u << 8 , RESERVED_9 = 1u << 9 , RESERVED_10 = 1u << 10 , RESERVED , ALL = (1u << 11) - 1 }
	Bit mask of the async stages tracked by the asyncmark / wait_asyncmark intrinsics. More...
enum class	InfoKind : uint8_t { INFO_FUNC = 1 , INFO_FLAGS = 2 , INFO_NUM_SGPR = 3 , INFO_NUM_VGPR = 4 , INFO_NUM_AGPR = 5 , INFO_PRIVATE_SEGMENT_SIZE = 6 , INFO_USE = 7 , INFO_CALL = 8 , INFO_INDIRECT_CALL = 9 , INFO_TYPEID = 10 }
	Entry kind values for the .amdgpu.info section. More...
enum class	FuncInfoFlags : uint32_t { FUNC_USES_VCC = 1U << 0 , FUNC_USES_FLAT_SCRATCH = 1U << 1 , FUNC_HAS_DYN_STACK = 1U << 2 , LLVM_MARK_AS_BITMASK_ENUM =(FUNC_HAS_DYN_STACK) }
	Per-function flags packed into INFO_FLAGS entries. More...
enum	GPUKind : uint8_t { GK_NONE = 0 }
	GPU kinds supported by the AMDGPU target. More...
enum	AMDGPUFeature : unsigned
	One enumerator per frontend-visible feature bit; NUM_FEATURES is the count. More...
enum	R600Feature : unsigned
	One enumerator per frontend-visible R600 feature bit; R600_NUM_FEATURES is the count. More...
enum	FeatureError : uint32_t { NO_ERROR = 0 , INVALID_FEATURE_COMBINATION , UNSUPPORTED_TARGET_FEATURE }
enum	{ FIXED_NUM_SGPRS_FOR_INIT_BUG = 96 }
enum class	TargetIDSetting { Unsupported , Any , Off , On }
enum	TargetIndex { TI_CONSTDATA_START , TI_SCRATCH_RSRC_DWORD0 , TI_SCRATCH_RSRC_DWORD1 , TI_SCRATCH_RSRC_DWORD2 , TI_SCRATCH_RSRC_DWORD3 }
enum class	CoExecMask : uint16_t { None = 0 , CTRL = 1 << 0 , VALU = 1 << 1 , TRANS = 1 << 2 , SALU = 1 << 3 , DS = 1 << 4 , VMEM = 1 << 5 , SMEM = 1 << 6 , WMMA = 1 << 7 , All = 0xFFFF , MEM = DS \| VMEM \| SMEM , StageE0 = CTRL , StageE = CTRL \| SALU \| MEM , StageI = CTRL \| SALU \| MEM \| VALU \| TRANS , StageIS = StageI \| WMMA , StageV = CTRL \| SALU \| MEM \| WMMA , StageTR = All & ~TRANS }
	Bitmask for instruction types allowed to co-execute at a stage. More...
enum class	InstructionFlavor : uint8_t { WMMA , SingleCycleVALU , TRANS , MultiCycleVALU , VMEM , SMEM , DS , SALU , DMA , Fence , Other , NUM_FLAVORS }
	Classification of instructions by execution characteristics. More...
enum class	CoExecStageType : uint8_t { NONE = 0 , E0 , E , I , IS , V , TR }
	Stage type for co-execution (for annotation/display). More...
enum class	AMDGPUSchedReason : uint8_t { None , Stall , MemoryPipeline , CritResourceBalance , CritResourceDep , NUM_REASONS }
	AMDGPU-specific scheduling decision reasons. More...
enum class	SchedulingPhase { Initial , PreRAReentry , PostRA }
enum	IGLPStrategyID : int { MFMASmallGemmOptID = 0 , MFMASmallGemmSingleWaveOptID = 1 , MFMAExpInterleaveID = 2 , MFMAExpSimpleInterleaveID = 3 }
	Operand 0 immediate for IGLP_OPT pseudo instructions. More...
enum class	SchedGroupMask { NONE = 0u , ALU = 1u << 0 , VALU = 1u << 1 , SALU = 1u << 2 , MFMA = 1u << 3 , VMEM = 1u << 4 , VMEM_READ = 1u << 5 , VMEM_WRITE = 1u << 6 , DS = 1u << 7 , DS_READ = 1u << 8 , DS_WRITE = 1u << 9 , TRANS = 1u << 10 , LDSDMA = 1u << 11 , ALL }
enum	UniformityLLTOpPredicateID { _ , S1 , S16 , S32 , S64 , S128 , UniS1 , UniS16 , UniS32 , UniS64 , UniS128 , UniBF16 , DivS1 , DivS16 , DivS32 , DivS64 , DivS128 , DivAnyTy , P0 , P1 , P2 , P3 , P4 , P5 , P8 , Ptr32 , Ptr64 , Ptr128 , UniP0 , UniP1 , UniP2 , UniP3 , UniP4 , UniP5 , UniP6 , UniP8 , UniPtr32 , UniPtr64 , UniPtr128 , DivP0 , DivP1 , DivP2 , DivP3 , DivP4 , DivP5 , DivPtr32 , DivPtr64 , DivPtr128 , V2S16 , V2S32 , V2S64 , V3S32 , V4S32 , V32S32 , UniV2S16 , UniV2S32 , UniV4S32 , UniV2S64 , UniV3S32 , UniV6S32 , UniV8S16 , UniV8S32 , UniV16S16 , UniV16S32 , UniV32S16 , UniV32S32 , DivV2S16 , DivV2S32 , DivV4S32 , DivV2S64 , DivV3S32 , DivV4S16 , DivV8S16 , DivV8S32 , DivV16S16 , DivV16S32 , DivV6S32 , DivV32S16 , DivV32S32 , B32 , B64 , B96 , B128 , B160 , B256 , B512 , BRC , UniB32 , UniB64 , UniB96 , UniB128 , UniB160 , UniB256 , UniB512 , UniBRC , DivB32 , DivB64 , DivB96 , DivB128 , DivB160 , DivB256 , DivB512 , DivBRC }
enum	RegBankLLTMappingApplyID { InvalidMapping , None , IntrId , Imm , Vcc , VgprAnyTy , AgprAnyTy , VgprOrAgprAnyTy , Sgpr16 , Sgpr32 , Sgpr64 , Sgpr128 , SgprP0 , SgprP1 , SgprP2 , SgprP3 , SgprP4 , SgprP5 , SgprP6 , SgprP8 , SgprPtr32 , SgprPtr64 , SgprPtr128 , SgprV2S16 , SgprV4S32 , SgprV2S32 , SgprB32 , SgprB64 , SgprB96 , SgprB128 , SgprB256 , SgprB512 , SgprBRC , Vgpr16 , Vgpr32 , Vgpr64 , Vgpr128 , VgprP0 , VgprP1 , VgprP2 , VgprP3 , VgprP4 , VgprP5 , VgprPtr32 , VgprPtr64 , VgprPtr128 , VgprV2S16 , VgprV2S32 , VgprV3S32 , VgprB32 , VgprB64 , VgprB96 , VgprB128 , VgprB160 , VgprB256 , VgprB512 , VgprBRC , VgprV4S16 , VgprV8S16 , VgprV16S16 , VgprV4S32 , VgprV8S32 , VgprV2S64 , UniInVcc , UniInVgprS16 , UniInVgprS32 , UniInVgprS64 , UniInVgprV2S16 , UniInVgprV2S32 , UniInVgprV3S32 , UniInVgprV4S32 , UniInVgprV2S64 , UniInVgprV6S32 , UniInVgprV8S16 , UniInVgprV8S32 , UniInVgprV16S16 , UniInVgprV16S32 , UniInVgprV32S16 , UniInVgprV32S32 , UniInVgprB32 , UniInVgprB64 , UniInVgprB96 , UniInVgprB128 , UniInVgprB160 , UniInVgprB256 , UniInVgprB512 , Sgpr32Trunc , Sgpr32ToVgprDst , Sgpr64ToVgprDst , Sgpr32_WF , SgprV4S32_WF , SgprP0Call_WF , SgprP4Call_WF , SgprB32_M0 , SgprB32_ReadFirstLane , SgprB64_ReadFirstLane , SgprV4S32_ReadFirstLane , SgprV8S32_ReadFirstLane , Sgpr32AExt , Sgpr32AExtBoolInReg , Sgpr32SExt , Sgpr32ZExt , Vgpr32AExt , Vgpr32SExt , Vgpr32ZExt , VgprV6S32 , VgprV16S32 , VgprV32S16 , VgprV32S32 }
enum	LoweringMethodID { DoNotLower , VccExtToSel , UniExtToSel , UnpackBitShift , UnpackMinMax , S_BFE , V_BFE , VgprToVccCopy , UniMAD64 , UniMul64 , DivSMulToMAD , SplitTo32 , SplitTo32Mul , ScalarizeToS16 , SplitTo32Select , SplitTo32SExtInReg , S_BUF_to_BUF , Ext32To64 , UniCstExt , CtPop64To32 , SplitLoad , WidenLoad , WidenMMOToS32 , UnpackAExt , VerifyAllSgpr , ApplyAllVgpr , UnmergeToShiftTrunc , AextToS32InIncomingBlockGPHI , VerifyAllSgprGPHI , VerifyAllSgprOrVgprGPHI , ApplyINTRIN_IMAGE , ApplyBVH_INTERSECT_RAY , SplitBitCount64To32 , ExtrVecEltToSel , ExtrVecEltTo32 , InsVecEltToSel , InsVecEltTo32 , AbsToNegMax , AbsToS32 , DynStackAlloc , DeletePrefetch , LowerSetRounding , LowerGetRounding }
enum	FastRulesTypes { NoFastRules , Standard , StandardB , Vector }
enum class	ScanOptions { DPP , Iterative , None }
enum class	AntiHintRule { None , MFMAWAW , MFMAWAR , WMMAWARAB , SWMMACWARIndex , WMMAWAW , TransWAR , MemAddrWAR , VAVdstWAR , All }
enum class	CarriedLatency { Off , Fence , All }
enum class	LDSLoweringKind { module , table , kernel , hybrid }
enum	InstCounterType { LOAD_CNT = 0 , DS_CNT , EXP_CNT , STORE_CNT , NUM_NORMAL_INST_CNTS , SAMPLE_CNT = NUM_NORMAL_INST_CNTS , BVH_CNT , KM_CNT , X_CNT , ASYNC_CNT , TENSOR_CNT , NUM_EXTENDED_INST_CNTS , VA_VDST_RD = NUM_EXTENDED_INST_CNTS , VA_VDST_WR , VM_VSRC , NUM_EXPERT_INST_CNTS , NUM_INST_CNTS = NUM_EXPERT_INST_CNTS }
enum class	HazardOperand : uint8_t { None , Def , Src0 , Src1 , Src2 , Src0Src1 , Idx , Vaddr , AnySrc , AnyUse }
enum class	AntiHintDirection : uint8_t { OneDirectional , Symmetric }
enum class	Lifetime : uint8_t { WindowBudget , RegisterCount }
enum	Fixups { fixup_si_sopp_br = FirstTargetFixupKind , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	OperandType : unsigned { OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET , OPERAND_REG_IMM_INT64 , OPERAND_REG_IMM_INT16 , OPERAND_REG_IMM_FP32 , OPERAND_REG_IMM_FP64 , OPERAND_REG_IMM_BF16 , OPERAND_REG_IMM_FP16 , OPERAND_REG_IMM_NOINLINE_FP16 , OPERAND_REG_IMM_V2BF16 , OPERAND_REG_IMM_V2FP16 , OPERAND_REG_IMM_V2FP16_SPLAT , OPERAND_REG_IMM_V2INT16 , OPERAND_REG_IMM_V2INT64 , OPERAND_REG_IMM_NOINLINE_V2FP16 , OPERAND_REG_IMM_V2INT32 , OPERAND_REG_IMM_V2FP32 , OPERAND_REG_IMM_V2FP64 , OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_INT32 , OPERAND_REG_INLINE_C_INT64 , OPERAND_REG_INLINE_C_BF16 , OPERAND_REG_INLINE_C_FP16 , OPERAND_REG_INLINE_C_FP32 , OPERAND_REG_INLINE_C_FP64 , OPERAND_REG_INLINE_C_V2INT16 , OPERAND_REG_INLINE_C_V2BF16 , OPERAND_REG_INLINE_C_V2FP16 , OPERAND_INLINE_SPLIT_BARRIER_INT32 , OPERAND_KIMM32 , OPERAND_KIMM16 , OPERAND_KIMM64 , OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_FP32 , OPERAND_REG_INLINE_AC_FP64 , OPERAND_INLINE_C_AV64_PSEUDO , OPERAND_INPUT_MODS , OPERAND_SDWA_VOPC_DST , OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP64 , OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64 , OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO , OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST , OPERAND_KIMM_FIRST = OPERAND_KIMM32 , OPERAND_KIMM_LAST = OPERAND_KIMM64 }
enum	AsmComments : MachineInstr::AsmPrinterFlagTy { SGPR_SPILL = MachineInstr::TAsmComments }
enum	AMDGPUFltRounds : int8_t { TowardZero = static_cast<int8_t>(RoundingMode::TowardZero) , NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven) , TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive) , TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative) , NearestTiesToAwayUnsupported , Dynamic = static_cast<int8_t>(RoundingMode::Dynamic) , NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven , NearestTiesToEvenF32_TowardPositiveF64 = 8 , NearestTiesToEvenF32_TowardNegativeF64 = 9 , NearestTiesToEvenF32_TowardZeroF64 = 10 , TowardPositiveF32_NearestTiesToEvenF64 = 11 , TowardPositiveF32_TowardPositiveF64 = TowardPositive , TowardPositiveF32_TowardNegativeF64 = 12 , TowardPositiveF32_TowardZeroF64 = 13 , TowardNegativeF32_NearestTiesToEvenF64 = 14 , TowardNegativeF32_TowardPositiveF64 = 15 , TowardNegativeF32_TowardNegativeF64 = TowardNegative , TowardNegativeF32_TowardZeroF64 = 16 , TowardZeroF32_NearestTiesToEvenF64 = 17 , TowardZeroF32_TowardPositiveF64 = 18 , TowardZeroF32_TowardNegativeF64 = 19 , TowardZeroF32_TowardZeroF64 = TowardZero , Invalid = static_cast<int8_t>(RoundingMode::Invalid) }
	Return values used for llvm.get.rounding. More...
enum	{ AMDHSA_COV4 = 4 , AMDHSA_COV5 = 5 , AMDHSA_COV6 = 6 }
enum class	FPType { None , FP4 , FP8 }
enum class	WMMAVariant { Unknown = 0 , IU8_16x16x64 , F8F6F4_16x16x128 , F8F6F4_16x16x128_BothF4 , FP8BF8_16x16x64 , F16BF16_16x16x32 , FP8BF8_16x16x128 , F4_32x16x128 }
	Normalized WMMA or SWMMAC family used to select co-execution rules. More...

Functions
bool	isFlatGlobalAddrSpace (unsigned AS)
bool	isExtendedGlobalAddrSpace (unsigned AS)
bool	isConstantAddressSpace (unsigned AS)
constexpr int	mapToDWARFAddrSpace (unsigned LLVMAddrSpace)
	If `LLVMAddressSpace` has a corresponding DWARF encoding, return it; otherwise return the sentinel value -1 to indicate no such mapping exists.
constexpr int64_t	getNullPointerValue (unsigned AS)
	Get the null pointer value for the given address space.
	LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE ()
constexpr bool	isValidAsyncStageMask (int64_t Mask)
constexpr AsyncStages	asyncStagesFromMaskOperand (int64_t Mask)
auto	asyncStages (AsyncStages Mask)
unsigned	getAsyncStageIndex (AsyncStages Stage)
StringRef	getAsyncStageName (AsyncStages Stage)
raw_ostream &	operator<< (raw_ostream &OS, AsyncStages Mask)
	Print the stages named by `Mask` as a '\|'-separated list, or "all" if it names every stage.
LLVM_ABI StringRef	getArchFamilyNameAMDGCN (GPUKind AK)
LLVM_ABI Triple::SubArchType	getSubArch (GPUKind AK)
LLVM_ABI Triple::SubArchType	getSubArchFromGPUName (StringRef CPU)
	Returns the preferred subarch for a GPU name `CPU`, or NoSubArch if unrecognized.
LLVM_ABI Triple::SubArchType	getMajorSubArch (Triple::SubArchType SubArch)
LLVM_ABI bool	isSubArchCompatible (const Triple &A, const Triple &B)
	Return true if subarch `A` is compatible with subarch `B`, i.e.
LLVM_ABI bool	isSubArchCompatible (Triple::SubArchType A, Triple::SubArchType B)
LLVM_ABI bool	isCPUValidForSubArch (Triple::SubArchType SubArch, GPUKind AK)
	Return true if the GPU `AK` is usable with the triple subarch `SubArch`.
LLVM_ABI bool	isCPUValidForSubArch (Triple::SubArchType SubArch, StringRef CPU)
	Convenience overload of isCPUValidForSubArch taking a GPU name `CPU`, which is parsed via parseArchAMDGCN.
LLVM_ABI bool	isPseudoTarget (GPUKind AK)
	Return true if `AK` is a pseudo target (e.g.
LLVM_ABI bool	isPseudoTarget (StringRef CPU)
	Convenience overload of isPseudoTarget taking a GPU name `CPU`, which is parsed via parseArchAMDGCN.
LLVM_ABI std::string	mergeSubArch (const Triple &A, const Triple &B)
	Returns the effective triple appropriate to use when linking `B` into `A` by merging the subarches in case of inexact match.
LLVM_ABI StringRef	getArchNameAMDGCN (GPUKind AK)
LLVM_ABI StringRef	getArchNameR600 (GPUKind AK)
LLVM_ABI StringRef	getArchNameFromSubArch (Triple::SubArchType SubArch)
	Returns the canonical GPU name for an AMDGPU subarch, e.g.
LLVM_ABI StringRef	getSubArchName (Triple::SubArchType SubArch)
	Returns the triple subarch name for an AMDGPU subarch, e.g.
LLVM_ABI StringRef	getCanonicalArchName (const Triple &T, StringRef Arch)
LLVM_ABI GPUKind	parseArchAMDGCN (StringRef CPU)
LLVM_ABI GPUKind	parseArchR600 (StringRef CPU)
LLVM_ABI GPUKind	getGPUKindFromSubArch (Triple::SubArchType SubArch)
LLVM_ABI const AMDGPUFeatureBitset &	getFeatureBitset (GPUKind AK)
	Returns `AK's` feature bitset, or an empty bitset if unknown.
LLVM_ABI const AMDGPUFeatureBitset &	getFeatureBitset (Triple::SubArchType SubArch)
	Convenience overload of getFeatureBitset taking a triple subarch, which is mapped via getGPUKindFromSubArch.
LLVM_ABI const R600FeatureBitset &	getFeatureBitsetR600 (GPUKind AK)
	Returns R600 GPU `AK's` feature bitset, or an empty bitset if unknown.
LLVM_ABI void	getFeatureNames (const AMDGPUFeatureBitset &Features, SmallVectorImpl< StringRef > &Names)
	Appends the feature name of each bit set in `Features` to `Names`.
LLVM_ABI void	fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values, Triple::SubArchType SubArch=Triple::NoSubArch)
	Append the valid AMDGCN GPU names to `Values`.
LLVM_ABI void	fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
LLVM_ABI IsaVersion	getIsaVersion (StringRef GPU)
LLVM_ABI IsaVersion	getIsaVersion (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getTotalNumSGPRs (GPUKind AK)
LLVM_ABI unsigned	getTotalNumSGPRs (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getAddressableNumSGPRs (GPUKind AK)
LLVM_ABI unsigned	getAddressableNumSGPRs (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getSGPRAllocGranule (GPUKind AK)
LLVM_ABI unsigned	getSGPRAllocGranule (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getVGPRAllocGranule (GPUKind AK, bool IsWave32)
LLVM_ABI unsigned	getVGPRAllocGranule (Triple::SubArchType SubArch, bool IsWave32)
LLVM_ABI unsigned	getTotalNumVGPRs (GPUKind AK, bool IsWave32)
LLVM_ABI unsigned	getTotalNumVGPRs (Triple::SubArchType SubArch, bool IsWave32)
LLVM_ABI unsigned	getAddressableNumVGPRs (GPUKind AK, bool IsWave32)
LLVM_ABI unsigned	getAddressableNumVGPRs (Triple::SubArchType SubArch, bool IsWave32)
LLVM_ABI unsigned	getMaxHWAddressableLocalMemorySize (GPUKind AK)
	LDS size queries.
LLVM_ABI unsigned	getMaxHWAddressableLocalMemorySize (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getLocalMemorySize (GPUKind AK, bool FullSIMDMode)
LLVM_ABI unsigned	getLocalMemorySize (Triple::SubArchType SubArch, bool FullSIMDMode)
LLVM_ABI unsigned	getAddressableLocalMemorySize (GPUKind AK, bool FullSIMDMode)
LLVM_ABI unsigned	getAddressableLocalMemorySize (Triple::SubArchType SubArch, bool FullSIMDMode)
LLVM_ABI unsigned	getLDSBankCount (GPUKind AK)
LLVM_ABI unsigned	getLDSBankCount (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getLDSAllocGranule (GPUKind AK)
LLVM_ABI unsigned	getLDSAllocGranule (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getLDSEncodingGranule (GPUKind AK)
LLVM_ABI unsigned	getLDSEncodingGranule (Triple::SubArchType SubArch)
constexpr unsigned	getNumWorkGroupSIMDs (bool FullSIMDMode)
constexpr unsigned	getMinWavesPerEU ()
LLVM_ABI std::optional< unsigned >	getBufferResourceNumRecordsWidth (GPUKind AK)
LLVM_ABI std::optional< unsigned >	getBufferResourceNumRecordsWidth (Triple::SubArchType SubArch)
LLVM_ABI unsigned	getMaxWavesPerEU (GPUKind AK)
LLVM_ABI unsigned	getMaxWavesPerEU (Triple::SubArchType SubArch)
constexpr unsigned	getMinFlatWorkGroupSize ()
constexpr unsigned	getMaxFlatWorkGroupSize ()
LLVM_ABI std::pair< FeatureError, StringRef >	fillAMDGPUFeatureMap (StringRef GPU, const Triple &T, StringMap< bool > &Features)
	Fills Features map with default values for given target GPU.
raw_ostream &	operator<< (raw_ostream &OS, const TargetID &TargetID)
static bool	addrspacesMayAlias (unsigned AS1, unsigned AS2)
static uint64_t	getRedzoneSizeForScale (int AsanScale)
static uint64_t	getMinRedzoneSizeForGlobal (int AsanScale)
uint64_t	getRedzoneSizeForGlobal (int Scale, uint64_t SizeInBytes)
	Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.
static size_t	TypeStoreSizeToSizeIndex (uint32_t TypeSize)
static Instruction *	genAMDGPUReportBlock (Module &M, IRBuilder<> &IRB, Value *Cond, bool Recover)
static Value *	createSlowPathCmp (Module &M, IRBuilder<> &IRB, Type IntptrTy, Value AddrLong, Value *ShadowValue, uint32_t TypeStoreSize, int AsanScale)
static Instruction *	generateCrashCode (Module &M, IRBuilder<> &IRB, Type IntptrTy, Instruction InsertBefore, Value Addr, bool IsWrite, size_t AccessSizeIndex, Value SizeArgument, bool Recover)
static Value *	memToShadow (Module &M, IRBuilder<> &IRB, Type IntptrTy, Value Shadow, int AsanScale, uint32_t AsanOffset)
static void	instrumentAddressImpl (Module &M, IRBuilder<> &IRB, Instruction OrigIns, Instruction InsertBefore, Value Addr, Align Alignment, uint32_t TypeStoreSize, bool IsWrite, Value SizeArgument, bool UseCalls, bool Recover, int AsanScale, int AsanOffset)
void	instrumentAddress (Module &M, IRBuilder<> &IRB, Instruction OrigIns, Instruction InsertBefore, Value Addr, Align Alignment, TypeSize TypeStoreSize, bool IsWrite, Value SizeArgument, bool UseCalls, bool Recover, int Scale, int Offset)
	Instrument the memory operand Addr.
void	getInterestingMemoryOperands (Module &M, Instruction *I, SmallVectorImpl< InterestingMemoryOperand > &Interesting)
	Get all the memory operands from the instruction that needs to be instrumented.
StringRef	getFlavorName (InstructionFlavor F)
InstructionFlavor	classifyFlavor (const MachineInstr &MI, const SIInstrInfo &SII)
	Classify `MI` into the execution flavor that drives both the scheduler's slot preferences and the hazard recognizer's co-execution masks.
CoExecMaskT	getCoExecMask (InstructionFlavor F)
	Map a flavor to the co-execution class it occupies in a window slot.
const char *	getStageTypeName (CoExecStageType T)
const char *	getCoExecMaskName (CoExecMaskT Mask)
	Return a human-readable name for a mask holding a single instruction class, as produced by getCoExecMask().
CoExecInfo	getMFMACoExecInfo (unsigned Opcode)
	Get co-execution info for a gfx950 MFMA instruction.
CoExecInfo	getCoExecInfo (const MachineInstr &MI, const SIInstrInfo &TII)
	Get co-execution info for a WMMA instruction, selecting the per-cycle slot pattern from the opcode (and operand formats for the F8F6F4 variants).
StringRef	getReasonName (AMDGPUSchedReason R)
bool	isUnscaledIEEEDivFmas (const MachineInstr &MI, const MachineRegisterInfo &MRI)
	Return whether div.fmas can use ordinary FMA without changing denormals.
std::pair< Register, unsigned >	getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg, GISelValueTracking *ValueTracking=nullptr, bool CheckNUW=false)
	Returns base register and constant offset.
void	buildReadAnyLane (MachineIRBuilder &B, Register SgprDst, Register VgprSrc, const RegisterBankInfo &RBI)
void	buildReadFirstLane (MachineIRBuilder &B, Register SgprDst, Register VgprSrc, const RegisterBankInfo &RBI)
static HWEvents	getExpertSchedulingEventType (const MachineInstr &Inst, const SIInstrInfo &TII)
HWEvents	getSimplifiedVMEMEventsFor (const MachineInstr &Inst, const SIInstrInfo &TII)
static HWEvents	getEventsForImpl (const MachineInstr &Inst, const GCNSubtarget &ST, const SIInstrInfo &TII, bool TgSplit)
HWEvents	getEventsFor (const MachineInstr &Inst, const GCNSubtarget &ST, bool IsExpertMode, bool TgSplit)
bool	isUniformMMO (const MachineMemOperand *MMO)
Intrinsic::ID	getIntrinsicID (const MachineInstr &I)
	Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
const RsrcIntrinsic *	lookupRsrcIntrinsic (unsigned Intr)
const ImageDimIntrinsicInfo *	getImageDimIntrinsicInfo (unsigned Intr)
const ImageDimIntrinsicInfo *	getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)
Align	getAlign (const DataLayout &DL, const GlobalVariable *GV)
unsigned	getSyntheticApertureNumber (unsigned AS)
void	copyMetadataForWidenedLoad (LoadInst &Dest, const LoadInst &Source)
static TargetExtType *	getTargetExtType (const GlobalVariable &GV)
TargetExtType *	isNamedBarrier (const GlobalVariable &GV)
unsigned	getNumNamedBarriersDeclared (const DataLayout &DL, const GlobalVariable &GV)
bool	isDynamicLDS (const GlobalVariable &GV)
bool	isLDSVariableToLower (const GlobalVariable &GV)
bool	eliminateGVConstantExprUsesFromAllInstructions (Module &M, function_ref< bool(const GlobalVariable &)> Filter)
	Iterates over all GlobalVariables in `M`, and whenever `Filter` returns true, replace all constant users of the GV with instructions.
void	getUsesOfGVByFunction (const CallGraph &CG, Module &M, function_ref< bool(const GlobalVariable &)> Filter, FunctionVariableMap &Kernels, FunctionVariableMap &Functions)
	Finds uses of Global Variables on a per-function basis.
GVUsesInfoTy	getTransitiveUsesOfGV (const CallGraph &CG, Module &M, function_ref< bool(const GlobalVariable &)> Filter)
	Collects all uses of Global Variables in `M` using getUsesOfGVByFunction.
GVUsesInfoTy	getTransitiveUsesOfLDSForLowering (const CallGraph &CG, Module &M)
	Collects all uses of LDS Global Variables in `M` using getUsesOfGVByFunction, with isLDSVariableToLower as the filter.
void	removeFnAttrFromReachable (CallGraph &CG, Function *KernelRoot, ArrayRef< StringRef > FnAttrs)
	Strip FnAttr attribute from any functions where we may have introduced its use.
bool	isReallyAClobber (const Value Ptr, MemoryDef Def, AAResults *AA)
	Given a `Def` clobbering a load from `Ptr` according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
bool	isClobberedInFunction (const LoadInst Load, MemorySSA MSSA, AAResults *AA)
	Check is a `Load` is clobbered in its function.
bool	isAnyPtr (LLT Ty, unsigned Width)
StringRef	getSchedStrategy (const AMDGPUOptions &CLOpts, const Function &F)
bool	isExpertSchedulingMode (const GCNSubtarget &ST, const Function &F)
	Return whether expert scheduling mode is available and enabled for `F`.
iota_range< InstCounterType >	inst_counter_types (InstCounterType MaxCounter)
StringLiteral	getInstCounterName (InstCounterType T)
Waitcnt	decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
unsigned	encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
Waitcnt	decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)
Waitcnt	decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)
unsigned	encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
unsigned	encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
std::optional< AMDGPU::InstCounterType >	counterTypeForInstr (unsigned Opcode)
	Determine if `MI` is a gfx12+ single-counter S_WAIT_*CNT instruction, and if so, which counter it is waiting on.
void	applyAntiHintRules (MachineFunction &MF, const HazardContext &Ctx)
void	printAMDGPUMCExpr (const MCExpr Expr, raw_ostream &OS, const MCAsmInfo MAI)
const MCExpr *	foldAMDGPUMCExpr (const MCExpr *Expr, MCContext &Ctx)
static AMDGPUMCExpr::Specifier	getSpecifier (const MCSymbolRefExpr *SRE)
LLVM_READONLY bool	isLitExpr (const MCExpr *Expr)
LLVM_READONLY int64_t	getLitValue (const MCExpr *Expr)
LLVM_READONLY AMDGPUMCExpr::VariantKind	getExprKind (const MCExpr *Expr)
LLVM_READONLY int32_t	getVOPe64 (uint32_t Opcode)
LLVM_READONLY int32_t	getVOPe32 (uint32_t Opcode)
LLVM_READONLY int32_t	getSDWAOp (uint32_t Opcode)
LLVM_READONLY int32_t	getDPPOp32 (uint32_t Opcode)
LLVM_READONLY int32_t	getDPPOp64 (uint32_t Opcode)
LLVM_READONLY int32_t	getBasicFromSDWAOp (uint32_t Opcode)
LLVM_READONLY int32_t	getCommuteRev (uint32_t Opcode)
LLVM_READONLY int32_t	getCommuteOrig (uint32_t Opcode)
LLVM_READONLY int32_t	getAddr64Inst (uint32_t Opcode)
LLVM_READONLY int32_t	getIfAddr64Inst (uint32_t Opcode)
	Check if `Opcode` is an Addr64 opcode.
LLVM_READONLY int32_t	getSOPKOp (uint32_t Opcode)
LLVM_READONLY int32_t	getGlobalSaddrOp (uint32_t Opcode)
LLVM_READONLY int32_t	getGlobalVaddrOp (uint32_t Opcode)
LLVM_READONLY int32_t	getFlatScratchInstSTfromSS (uint32_t Opcode)
LLVM_READONLY int32_t	getFlatScratchInstSVfromSVS (uint32_t Opcode)
LLVM_READONLY int32_t	getFlatScratchInstSSfromSV (uint32_t Opcode)
LLVM_READONLY int32_t	getFlatScratchInstSVfromSS (uint32_t Opcode)
LLVM_READONLY int32_t	getMFMAEarlyClobberOp (uint32_t Opcode)
LLVM_READONLY int32_t	getAGPRFormOp (uint32_t Opcode)
LLVM_READONLY int32_t	getVCMPXOpFromVCMP (uint32_t Opcode)
Register	createLaneMaskReg (MachineRegisterInfo *MRI, MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs)
uint32_t	decodeFltRoundToHWConversionTable (uint32_t FltRounds)
	Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
template<size_t N>
static StringRef	getNameFromOperandTable (const CustomOperand(&Table)[N], unsigned Encoding, const MCSubtargetInfo &STI)
	Map from the encoding of a sendmsg/hwreg asm operand to it's name.
template<size_t N>
static int64_t	getEncodingFromOperandTable (const CustomOperand(&Table)[N], StringRef Name, const MCSubtargetInfo &STI)
	Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.
bool	hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
bool	isHsaAbi (const MCSubtargetInfo &STI)
unsigned	getAMDHSACodeObjectVersion (const Module &M)
unsigned	getDefaultAMDHSACodeObjectVersion ()
unsigned	getAMDHSACodeObjectVersion (unsigned ABIVersion)
uint8_t	getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)
unsigned	getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
int	getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords, bool IndexedRsrc, bool IndexedSamp)
const MIMGBaseOpcodeInfo *	getMIMGBaseOpcode (unsigned Opc)
int	getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
unsigned	getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo BaseOpcode, const MIMGDimInfo Dim, bool IsA16, bool IsG16Supported)
int	getMTBUFBaseOpcode (unsigned Opc)
int	getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
int	getMTBUFElements (unsigned Opc)
bool	getMTBUFHasVAddr (unsigned Opc)
bool	getMTBUFHasSrsrc (unsigned Opc)
bool	getMTBUFHasSoffset (unsigned Opc)
int	getMUBUFBaseOpcode (unsigned Opc)
int	getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
int	getMUBUFElements (unsigned Opc)
bool	getMUBUFHasVAddr (unsigned Opc)
bool	getMUBUFHasSrsrc (unsigned Opc)
bool	getMUBUFHasSoffset (unsigned Opc)
bool	getMUBUFIsBufferInv (unsigned Opc)
bool	getMUBUFTfe (unsigned Opc)
bool	getSMEMIsBuffer (unsigned Opc)
bool	getVOP1IsSingle (unsigned Opc)
bool	getVOP2IsSingle (unsigned Opc)
bool	getVOP3IsSingle (unsigned Opc)
bool	isVOPC64DPP (unsigned Opc)
bool	isVOPCAsmOnly (unsigned Opc)
bool	getMAIIsDGEMM (unsigned Opc)
	Returns true if MAI operation is a double precision GEMM.
bool	getMAIIsGFX940XDL (unsigned Opc)
bool	getWMMAIsXDL (unsigned Opc)
bool	getHasMatrixScale (unsigned Opc)
uint8_t	mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)
const MFMA_F8F6F4_Info *	getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
uint8_t	wmmaScaleF8F6F4FormatToNumRegs (unsigned Fmt)
const MFMA_F8F6F4_Info *	getWMMA_F8F6F4_WithFormatArgs (unsigned FmtA, unsigned FmtB, unsigned F8F8Opcode)
bool	isValidWMMAScaleFmtCombination (unsigned AFmt, unsigned AScale, unsigned BFmt, unsigned BScale)
unsigned	getVOPDEncodingFamily (const MCSubtargetInfo &ST)
CanBeVOPD	getCanBeVOPD (unsigned Opc, unsigned EncodingFamily, bool VOPD3)
unsigned	getVOPDOpcode (unsigned Opc, bool VOPD3)
bool	isVOPD (unsigned Opc)
bool	isMAC (unsigned Opc)
bool	isPermlane16 (unsigned Opc)
bool	isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)
bool	isGenericAtomic (unsigned Opc)
bool	isAsyncStore (unsigned Opc)
bool	isTensorStore (unsigned Opc)
unsigned	getTemporalHintType (const MCInstrDesc TID)
bool	isTrue16Inst (unsigned Opc)
bool	hasNoOpSelHi (unsigned Opc)
	Returns true if this VOP3P opcode has no op_sel_hi field, in which case those bits are encoded as zero instead of defaulting to one.
FPType	getFPDstSelType (unsigned Opc)
bool	isDPMACCInstruction (unsigned Opc)
unsigned	mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
int32_t	getMCOpcode (uint32_t Opcode, unsigned Gen)
unsigned	getBitOp2 (unsigned Opc)
int	getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily, bool VOPD3)
std::pair< unsigned, unsigned >	getVOPDComponents (unsigned VOPDOpcode)
VOPD::InstInfo	getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)
VOPD::InstInfo	getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)
TargetID	createAMDGPUTargetID (const MCSubtargetInfo &STI, StringRef FeatureString)
	Construct TargetID from MCSubtargetInfo.
void	initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo &STI)
bool	isReadOnlySegment (const GlobalValue *GV)
bool	shouldEmitConstantsToTextSection (const Triple &TT)
static bool	isValidRegPrefix (char C)
std::tuple< char, unsigned, unsigned >	parseAsmPhysRegName (StringRef TupleString)
	Returns a valid charcode or 0 in the first entry if this is a valid physical register name.
std::tuple< char, unsigned, unsigned >	parseAsmConstraintPhysReg (StringRef Constraint)
	Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.
std::pair< unsigned, unsigned >	getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
std::optional< std::pair< unsigned, std::optional< unsigned > > >	getIntegerPairAttribute (const Function &F, StringRef Name, bool OnlyFirstRequired)
SmallVector< unsigned >	getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)
std::optional< SmallVector< unsigned > >	getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size)
	Similar to the function above, but returns std::nullopt if any error occurs.
SmallVector< unsigned >	getMaxNumWorkGroups (const Function &F)
bool	hasValueInRangeLikeMetadata (const MDNode &MD, int64_t Val)
	Checks if `Val` is inside `MD`, a !range-like metadata.
unsigned	getVmcntBitMask (const IsaVersion &Version)
unsigned	getLoadcntBitMask (const IsaVersion &Version)
unsigned	getSamplecntBitMask (const IsaVersion &Version)
unsigned	getBvhcntBitMask (const IsaVersion &Version)
unsigned	getExpcntBitMask (const IsaVersion &Version)
unsigned	getLgkmcntBitMask (const IsaVersion &Version)
unsigned	getDscntBitMask (const IsaVersion &Version)
unsigned	getKmcntBitMask (const IsaVersion &Version)
unsigned	getXcntBitMask (const IsaVersion &Version)
unsigned	getAsynccntBitMask (const IsaVersion &Version)
unsigned	getStorecntBitMask (const IsaVersion &Version)
unsigned	getBarrierMemberCountBitMask (const IsaVersion &Version)
unsigned	getWaitcntBitMask (const IsaVersion &Version)
unsigned	decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeStorecnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeDscnt (const IsaVersion &Version, unsigned Waitcnt)
void	decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
	Decodes Vmcnt, Expcnt and Lgkmcnt from given `Waitcnt` for given isa `Version`, and writes decoded values into `Vmcnt`, `Expcnt` and `Lgkmcnt` respectively.
unsigned	encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned	encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned	encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
unsigned	encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
	Encodes `Vmcnt`, `Expcnt` and `Lgkmcnt` into Waitcnt for given isa `Version`.
static unsigned	getCombinedCountBitMask (const IsaVersion &Version, bool IsStore)
static unsigned	encodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
static unsigned	encodeStorecnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static unsigned	encodeDscnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
unsigned	encodeLoadcntDscnt (const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
unsigned	encodeStorecntDscnt (const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
static bool	isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
static bool	decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
static int	encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
static int	encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned	getInitialPSInputAddr (const Function &F)
bool	getHasColorExport (const Function &F)
bool	getHasDepthExport (const Function &F)
unsigned	getDynamicVGPRBlockSize (const Function &F)
bool	hasMIMG_R128 (const MCSubtargetInfo &STI)
bool	hasA16 (const MCSubtargetInfo &STI)
bool	hasG16 (const MCSubtargetInfo &STI)
bool	hasPackedD16 (const MCSubtargetInfo &STI)
bool	hasGDS (const MCSubtargetInfo &STI)
unsigned	getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)
unsigned	getMaxNumUserSGPRs (const MCSubtargetInfo &STI)
bool	isSI (const MCSubtargetInfo &STI)
bool	isCI (const MCSubtargetInfo &STI)
bool	isVI (const MCSubtargetInfo &STI)
bool	isGFX9 (const MCSubtargetInfo &STI)
bool	isGFX9_GFX10 (const MCSubtargetInfo &STI)
bool	isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)
bool	isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
bool	isGFX8Plus (const MCSubtargetInfo &STI)
bool	isGFX9Plus (const MCSubtargetInfo &STI)
bool	isNotGFX9Plus (const MCSubtargetInfo &STI)
bool	hasPopsExitingWaveID (const MCSubtargetInfo &STI)
bool	hasPrivateApertureRegs (const MCSubtargetInfo &STI)
bool	isGFX10 (const MCSubtargetInfo &STI)
bool	isGFX10_GFX11 (const MCSubtargetInfo &STI)
bool	isGFX10Plus (const MCSubtargetInfo &STI)
bool	isGFX11 (const MCSubtargetInfo &STI)
bool	isGFX11Plus (const MCSubtargetInfo &STI)
bool	isGFX12 (const MCSubtargetInfo &STI)
bool	isGFX12Plus (const MCSubtargetInfo &STI)
bool	isNotGFX12Plus (const MCSubtargetInfo &STI)
bool	isGFX1250 (const MCSubtargetInfo &STI)
bool	isFullSIMDMode (const MCSubtargetInfo &STI)
bool	isGFX1250Plus (const MCSubtargetInfo &STI)
bool	isGFX13 (const MCSubtargetInfo &STI)
bool	isGFX13Plus (const MCSubtargetInfo &STI)
bool	supportsWGP (const MCSubtargetInfo &STI)
bool	isNotGFX11Plus (const MCSubtargetInfo &STI)
bool	isNotGFX10Plus (const MCSubtargetInfo &STI)
bool	isGFX10Before1030 (const MCSubtargetInfo &STI)
bool	isGCN3Encoding (const MCSubtargetInfo &STI)
bool	isGFX10_BEncoding (const MCSubtargetInfo &STI)
bool	hasGFX10_3Insts (const MCSubtargetInfo &STI)
bool	isGFX10_3_GFX11 (const MCSubtargetInfo &STI)
bool	isGFX90A (const MCSubtargetInfo &STI)
bool	isGFX940 (const MCSubtargetInfo &STI)
bool	hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
bool	hasMAIInsts (const MCSubtargetInfo &STI)
bool	hasVOPD (const MCSubtargetInfo &STI)
bool	hasDPPSrc1SGPR (const MCSubtargetInfo &STI)
unsigned	hasKernargPreload (const MCSubtargetInfo &STI)
uint32_t	getTotalNumVGPRs (bool has90AInsts, uint32_t ArgNumAGPR, uint32_t ArgNumVGPR)
bool	isSGPR (MCRegister Reg, const MCRegisterInfo *TRI)
	Is Reg - scalar register.
bool	isRsrcIndexReg (MCRegister Reg, const MCRegisterInfo &MRI)
bool	isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister	getMCReg (MCRegister Reg, const MCSubtargetInfo &STI)
	If `Reg` is a pseudo reg, return the correct hardware register given `STI` otherwise return `Reg`.
MCRegister	mc2PseudoReg (MCRegister Reg)
	Convert hardware register `Reg` to a pseudo register.
bool	isInlineValue (MCRegister Reg)
bool	isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this a KImm operand?
bool	isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this floating-point operand?
unsigned	getRegBitWidth (unsigned RCID)
	Get the size in bits of a register from the register class `RC`.
unsigned	getRegBitWidth (const MCRegisterClass &RC)
	Get the size in bits of a register from the register class `RC`.
bool	isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
	Is this literal inlinable.
bool	isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
bool	isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi, bool *IsBF16)
bool	isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)
bool	isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)
std::optional< unsigned >	getInlineEncodingV216 (bool IsFloat, uint32_t Literal)
std::optional< unsigned >	getInlineEncodingV2I16 (uint32_t Literal)
std::optional< unsigned >	getInlineEncodingV2BF16 (uint32_t Literal)
std::optional< unsigned >	getInlineEncodingV2F16 (uint32_t Literal)
std::optional< unsigned >	getPKFMACF16InlineEncoding (uint32_t Literal, bool IsGFX11Plus)
bool	isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)
bool	isInlinableLiteralV2I16 (uint32_t Literal)
bool	isInlinableLiteralV2BF16 (uint32_t Literal)
bool	isInlinableLiteralV2F16 (uint32_t Literal)
bool	isPKFMACF16InlineConstant (uint32_t Literal, bool IsGFX11Plus)
bool	isValid32BitLiteral (uint64_t Val, bool IsFP64)
int64_t	encode32BitLiteral (int64_t Imm, OperandType Type, bool IsLit)
bool	isArgPassedInSGPR (const Argument *A)
bool	isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)
static bool	hasSMEMByteOffset (const MCSubtargetInfo &ST)
bool	isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool	isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
static bool	isDwordAligned (uint64_t ByteOffset)
uint64_t	convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
	Convert `ByteOffset` to dwords if the subtarget uses dword SMRD immediate offsets.
std::optional< int64_t >	getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
std::optional< int64_t >	getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned	getNumFlatOffsetBits (const MCSubtargetInfo &ST)
	For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool	isIntrinsicSourceOfDivergence (unsigned IntrID)
bool	isIntrinsicAlwaysUniform (unsigned IntrID)
bool	isTriviallyUniform (const Value V, const Instruction CtxI)
	Return true if we can easily prove that `V` is uniform at `CtxI`.
bool	isTriviallyUniform (const Use &U)
	Return true if we can easily prove that use `U` is uniform.
bool	isLDSDMAIntrinsic (unsigned IntrID)
std::optional< unsigned >	getExponentOnlyScaleArgIdx (unsigned IntrID)
const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
const MCRegisterClass *	getVGPRPhysRegClass (MCRegister Reg, const MCRegisterInfo &MRI)
unsigned	getVGPREncodingMSBs (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister	getVGPRWithMSBs (MCRegister Reg, unsigned MSBs, const MCRegisterInfo &MRI)
	If `Reg` is a low VGPR return a corresponding high VGPR with `MSBs` set.
static std::optional< unsigned >	convertSetRegImmToVgprMSBs (uint64_t Imm, uint64_t Simm16, bool HasSetregVGPRMSBFixup)
std::optional< unsigned >	convertSetRegImmToVgprMSBs (const MachineInstr &MI, bool HasSetregVGPRMSBFixup)
std::optional< unsigned >	convertSetRegImmToVgprMSBs (const MCInst &MI, bool HasSetregVGPRMSBFixup)
std::pair< const AMDGPU::OpName , const AMDGPU::OpName >	getVGPRLoweringOperandTables (const MCInstrDesc &Desc)
bool	supportsScaleOffset (const MCInstrInfo &MII, unsigned Opcode)
static bool	hasAny64BitVGPROperands (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool	isDPALU_DPP32BitOpc (unsigned Opc)
bool	isDPALU_DPP (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool	isPackedSingleSGPRFP32Inst (unsigned Opc)
	The opcode is a packed fp32 instruction which only reads low 32 bits of a scalar operand and propagates it to high channel.
bool	isPackedSingleSGPR64BitInst (unsigned Opc)
	The opcode is a packed 64-bit instruction which only reads low 64 bits of a scalar operand and propagates it to high channel.
bool	isSingleSGPRReadInst (unsigned Opc)
	Packed instructions that read a single SGPR for SGPR operands, except for 64-bit elements which read two SGPRs.
std::optional< APFloat >	evaluateRcp (const APFloat &Val)
	Evaluate the constant-folded result of v_rcp for `Val`, accounting for the hardware's denormal flushing on f32/f64 and its approximate rounding.
LLVM_READONLY bool	hasNamedOperand (uint32_t Opcode, OpName NamedIdx)
LLVM_READONLY int32_t	getSOPPWithRelaxation (uint32_t Opcode)
LLVM_READONLY const MIMGBaseOpcodeInfo *	getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfo (unsigned DimEnum)
LLVM_READONLY StringRef	getMIMGDimInfoStr (StringTable::Offset)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByEncoding (uint8_t DimEnc)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
LLVM_READONLY const MIMGLZMappingInfo *	getMIMGLZMappingInfo (unsigned L)
LLVM_READONLY const MIMGMIPMappingInfo *	getMIMGMIPMappingInfo (unsigned MIP)
LLVM_READONLY const MIMGBiasMappingInfo *	getMIMGBiasMappingInfo (unsigned Bias)
LLVM_READONLY const MIMGOffsetMappingInfo *	getMIMGOffsetMappingInfo (unsigned Offset)
LLVM_READONLY const MIMGG16MappingInfo *	getMIMGG16MappingInfo (unsigned G)
LLVM_READONLY const MIMGInfo *	getMIMGInfo (unsigned Opc)
template<typename InstT>
std::pair< unsigned, unsigned >	getWMMAMatrixFmts (const InstT &MI)
template<typename InstT>
bool	isWMMAAnyF8 (const InstT &MI)
template<typename InstT>
bool	isWMMABothF4 (const InstT &MI)
bool	isTgSplitEnabled (const Function &F)
LLVM_READNONE constexpr bool	isShader (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isGraphics (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isCompute (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isEntryFunctionCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isChainCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isModuleEntryFunctionCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool	isKernel (CallingConv::ID CC)
bool	isKernel (const Function &F)
LLVM_READNONE constexpr bool	canGuaranteeTCO (CallingConv::ID CC)
LLVM_READNONE constexpr bool	mayTailCallThisCC (CallingConv::ID CC)
	Return true if we might ever do TCO for calls with this calling convention.
constexpr bool	isSISrcOperand (const MCOperandInfo &OpInfo)
	Is this an AMDGPU specific source operand?
bool	isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
constexpr bool	isBF16SrcOperand (const MCOperandInfo &OpInfo)
	Is this a scalar (i.e. not packed) bf16 source operand?
LLVM_READNONE unsigned	getOperandSize (const MCOperandInfo &OpInfo)
LLVM_READNONE unsigned	getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
LLVM_READNONE bool	isInlinableIntLiteral (int64_t Literal)
	Is this literal inlinable, and not one of the values intended for floating point values.
LLVM_READNONE bool	isLegalDPALU_DPPControl (const MCSubtargetInfo &ST, unsigned DC)
APInt	getExponentOnlyScaleDemandedBits ()
constexpr std::pair< unsigned, unsigned >	getShiftMask (unsigned Value)
	Deduce the least significant bit aligned shift and mask values for a binary Complement `Value` (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.
const MCExpr *	maskShiftSet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
	Provided with the MCExpr * `Val`, uint32 `Mask` and `Shift`, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext `Ctx`.
const MCExpr *	maskShiftGet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
	Provided with the MCExpr * `Val`, uint32 `Mask` and `Shift`, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext `Ctx`.

Variables
constexpr unsigned	NumAsyncStages = BitWidth<AsyncStages>
	The number of stages, which is also the number of bits in a stage mask.
constexpr StringLiteral	AsyncStageNames [NumAsyncStages]
	The name of each stage, indexed by the position of its bit.
constexpr unsigned	MaxCoExecStages = 32
	Max stages: INT8 16x16x64 = 17 cycles, round up for safety.
static constexpr LaneMaskConstants	LaneMaskConstants32
static constexpr LaneMaskConstants	LaneMaskConstants64
static constexpr unsigned	NamedBarrierTypeSizeInBytes = 1
const uint64_t	RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t	RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
const uint64_t	RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
const uint64_t	RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
static constexpr uint32_t	ExtendedFltRoundOffset = 4
	Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
static constexpr uint32_t	F32FltRoundOffset = 0
	Offset in mode register of f32 rounding mode.
static constexpr uint32_t	F64FltRoundOffset = 2
	Offset in mode register of f64/f16 rounding mode.
const uint64_t	FltRoundConversionTable
const uint64_t	FltRoundToHWConversionTable
const int	OPR_ID_UNKNOWN = -1
const int	OPR_ID_UNSUPPORTED = -2
const int	OPR_ID_DUPLICATE = -3
const int	OPR_VAL_INVALID = -4

Typedef Documentation

◆ AdvanceForRawWindowFn

using llvm::AMDGPU::AdvanceForRawWindowFn

Initial value:

 unsigned (*)(const MachineInstr &Producer,
                                           HazardClassMask ReaderClass,
                                           const HazardContext &Ctx)

Definition at line 102 of file GCNPreRAAntiHints.h.

◆ AMDGPUFeatureBitset

using llvm::AMDGPU::AMDGPUFeatureBitset = Bitset<NUM_FEATURES>

Definition at line 52 of file AMDGPUTargetParser.h.

◆ CoExecMaskT

using llvm::AMDGPU::CoExecMaskT = CoExecMask

Definition at line 72 of file AMDGPUCoExecInfo.h.

◆ EncodingBit

template<unsigned Bit, unsigned D = 0>

using llvm::AMDGPU::EncodingBit = EncodingField<Bit, Bit, D>

Definition at line 334 of file AMDGPUBaseInfo.h.

◆ FunctionVariableMap

using llvm::AMDGPU::FunctionVariableMap = MapVector<Function *, DenseSet<GlobalVariable *>>

Definition at line 36 of file AMDGPUMemoryUtils.h.

◆ HazardClassMask

using llvm::AMDGPU::HazardClassMask = uint32_t

Definition at line 27 of file GCNPreRAAntiHints.h.

◆ InstPredicate

using llvm::AMDGPU::InstPredicate = bool (*)(const MachineInstr &, const HazardContext &)

Definition at line 98 of file GCNPreRAAntiHints.h.

◆ R600FeatureBitset

using llvm::AMDGPU::R600FeatureBitset = Bitset<R600_NUM_FEATURES>

Definition at line 61 of file AMDGPUTargetParser.h.

◆ RulePredicate

using llvm::AMDGPU::RulePredicate = bool (*)(const HazardContext &)

Definition at line 95 of file GCNPreRAAntiHints.h.

◆ TargetID

using llvm::AMDGPU::TargetID = AMDGPU::TargetID

Definition at line 161 of file AMDGPUBaseInfo.h.

◆ TargetIDSetting

using llvm::AMDGPU::TargetIDSetting = AMDGPU::TargetIDSetting

Definition at line 160 of file AMDGPUBaseInfo.h.

◆ VariableFunctionMap

using llvm::AMDGPU::VariableFunctionMap = DenseMap<GlobalVariable *, DenseSet<Function *>>

Definition at line 37 of file AMDGPUMemoryUtils.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
AMDHSA_COV4
AMDHSA_COV5
AMDHSA_COV6

Definition at line 70 of file AMDGPUBaseInfo.h.

◆ anonymous enum

anonymous enum

Enumerator
FIXED_NUM_SGPRS_FOR_INIT_BUG

Definition at line 169 of file AMDGPUTargetParser.h.

◆ AMDGPUFeature

enum llvm::AMDGPU::AMDGPUFeature : unsigned

One enumerator per frontend-visible feature bit; NUM_FEATURES is the count.

Definition at line 47 of file AMDGPUTargetParser.h.

◆ AMDGPUFltRounds

enum llvm::AMDGPU::AMDGPUFltRounds : int8_t

Return values used for llvm.get.rounding.

When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.

Enumerator
TowardZero
NearestTiesToEven
TowardPositive
TowardNegative
NearestTiesToAwayUnsupported
Dynamic
NearestTiesToEvenF32_NearestTiesToEvenF64
NearestTiesToEvenF32_TowardPositiveF64
NearestTiesToEvenF32_TowardNegativeF64
NearestTiesToEvenF32_TowardZeroF64
TowardPositiveF32_NearestTiesToEvenF64
TowardPositiveF32_TowardPositiveF64
TowardPositiveF32_TowardNegativeF64
TowardPositiveF32_TowardZeroF64
TowardNegativeF32_NearestTiesToEvenF64
TowardNegativeF32_TowardPositiveF64
TowardNegativeF32_TowardNegativeF64
TowardNegativeF32_TowardZeroF64
TowardZeroF32_NearestTiesToEvenF64
TowardZeroF32_TowardPositiveF64
TowardZeroF32_TowardNegativeF64
TowardZeroF32_TowardZeroF64
Invalid

Definition at line 101 of file SIModeRegisterDefaults.h.

◆ AMDGPUSchedReason

enum class llvm::AMDGPU::AMDGPUSchedReason : uint8_t

strong

AMDGPU-specific scheduling decision reasons.

These provide more granularity than the generic CandReason enum for debugging purposes.

Enumerator
None
Stall
MemoryPipeline
CritResourceBalance
CritResourceDep
NUM_REASONS

Definition at line 30 of file AMDGPUCoExecSchedStrategy.h.

◆ AntiHintDirection

enum class llvm::AMDGPU::AntiHintDirection : uint8_t

strong

Enumerator
OneDirectional
Symmetric

Definition at line 64 of file GCNPreRAAntiHints.h.

◆ AntiHintRule

enum class llvm::AMDGPU::AntiHintRule

strong

Enumerator
None
MFMAWAW
MFMAWAR
WMMAWARAB
SWMMACWARIndex
WMMAWAW
TransWAR
MemAddrWAR
VAVdstWAR
All

Definition at line 29 of file AMDGPUSubtarget.h.

◆ AsmComments

enum llvm::AMDGPU::AsmComments : MachineInstr::AsmPrinterFlagTy

Enumerator
SGPR_SPILL

Definition at line 2050 of file SIInstrInfo.h.

◆ AsyncStages

enum class llvm::AMDGPU::AsyncStages : uint32_t

strong

Bit mask of the async stages tracked by the asyncmark / wait_asyncmark intrinsics.

Each stage has its own independent sequence of marks. A single stage is a mask with exactly one bit set.

The bit of each stage is part of the IR, so do not renumber them. Some values are RESERVED for later use.

Enumerator
NONE
TENSOR
GLOBAL_LOAD_ASYNC_TO_LDS
GLOBAL_LOAD_ASYNC_TO_LDS_MCAST
GLOBAL_STORE_ASYNC_FROM_LDS
RESERVED_4
BUFFER_GLOBAL_LOAD
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10
RESERVED
ALL

Definition at line 37 of file AMDGPUAsyncStages.h.

◆ CarriedLatency

enum class llvm::AMDGPU::CarriedLatency

strong

Enumerator
Off
Fence
All

Definition at line 42 of file AMDGPUSubtarget.h.

◆ CoExecMask

enum class llvm::AMDGPU::CoExecMask : uint16_t

strong

Bitmask for instruction types allowed to co-execute at a stage.

Enumerator
None
CTRL
VALU
TRANS
SALU
DS
VMEM
SMEM
WMMA
All
MEM
StageE0
StageE
StageI
StageIS
StageV
StageTR

Definition at line 45 of file AMDGPUCoExecInfo.h.

◆ CoExecStageType

enum class llvm::AMDGPU::CoExecStageType : uint8_t

strong

Stage type for co-execution (for annotation/display).

Enumerator
NONE
E0
E
I
IS
V
TR

Definition at line 165 of file AMDGPUCoExecInfo.h.

◆ FastRulesTypes

enum llvm::AMDGPU::FastRulesTypes

Enumerator
NoFastRules
Standard
StandardB
Vector

Definition at line 357 of file AMDGPURegBankLegalizeRules.h.

◆ FeatureError

enum llvm::AMDGPU::FeatureError : uint32_t

Enumerator
NO_ERROR
INVALID_FEATURE_COMBINATION
UNSUPPORTED_TARGET_FEATURE

Definition at line 76 of file AMDGPUTargetParser.h.

◆ Fixups

enum llvm::AMDGPU::Fixups

Enumerator
fixup_si_sopp_br	16-bit PC relative fixup for SOPP branch instructions.
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ FlatAddrSpace

enum class llvm::AMDGPU::FlatAddrSpace : unsigned

strong

Enumerator
FLAT
FlatGlobal
FlatScratch

Definition at line 112 of file AMDGPUAddrSpace.h.

◆ FPType

enum class llvm::AMDGPU::FPType

strong

Enumerator
None
FP4
FP8

Definition at line 72 of file AMDGPUBaseInfo.h.

◆ FuncInfoFlags

enum class llvm::AMDGPU::FuncInfoFlags : uint32_t

strong

Per-function flags packed into INFO_FLAGS entries.

Enumerator
FUNC_USES_VCC
FUNC_USES_FLAT_SCRATCH
FUNC_HAS_DYN_STACK
LLVM_MARK_AS_BITMASK_ENUM

Definition at line 64 of file AMDGPUObjLinkingInfo.h.

◆ GPUKind

enum llvm::AMDGPU::GPUKind : uint8_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE

Definition at line 35 of file AMDGPUTargetParser.h.

◆ HazardOperand

enum class llvm::AMDGPU::HazardOperand : uint8_t

strong

Enumerator
None
Def
Src0
Src1
Src2
Src0Src1
Idx
Vaddr
AnySrc
AnyUse

Definition at line 51 of file GCNPreRAAntiHints.h.

◆ IGLPStrategyID

enum llvm::AMDGPU::IGLPStrategyID : int

Operand 0 immediate for IGLP_OPT pseudo instructions.

Enumerator
MFMASmallGemmOptID
MFMASmallGemmSingleWaveOptID
MFMAExpInterleaveID
MFMAExpSimpleInterleaveID

Definition at line 23 of file AMDGPUIGroupLP.h.

◆ InfoKind

enum class llvm::AMDGPU::InfoKind : uint8_t

strong

Entry kind values for the .amdgpu.info section.

Entries that appear between an INFO_FUNC and the next INFO_FUNC (or end of section) belong to the function scope opened by that INFO_FUNC.

Enumerator
INFO_FUNC	Opens a new function scope. Payload is an 8-byte symbol reference (relocated) identifying the function. All subsequent entries until the next INFO_FUNC belong to this function.
INFO_FLAGS	Bitfield of FuncInfoFlags properties for the function. [u32].
INFO_NUM_SGPR	Number of SGPRs explicitly used by the function. [u32].
INFO_NUM_VGPR	Number of architectural VGPRs used by the function. [u32].
INFO_NUM_AGPR	Number of accumulator VGPRs (AGPRs) used by the function. [u32].
INFO_PRIVATE_SEGMENT_SIZE	Private (scratch) memory size in bytes required by the function. [u32].
INFO_USE	Dependency edge: the function uses the resource identified by the 8-byte relocated symbol (e.g. an LDS variable or named barrier).
INFO_CALL	Direct call edge: the function calls the callee identified by the 8-byte relocated symbol.
INFO_INDIRECT_CALL	Indirect call edge: the function contains an indirect call whose callee is expected to match the type-ID string at the given .amdgpu.strtab offset. [u32]
INFO_TYPEID	Function type ID: tags an address-taken function with a type-ID string (at the given .amdgpu.strtab offset) so the linker can match it against INFO_INDIRECT_CALL entries. [u32]

Definition at line 32 of file AMDGPUObjLinkingInfo.h.

◆ InstCounterType

enum llvm::AMDGPU::InstCounterType

Enumerator
LOAD_CNT
DS_CNT
EXP_CNT
STORE_CNT
NUM_NORMAL_INST_CNTS
SAMPLE_CNT
BVH_CNT
KM_CNT
X_CNT
ASYNC_CNT
TENSOR_CNT
NUM_EXTENDED_INST_CNTS
VA_VDST_RD
VA_VDST_WR
VM_VSRC
NUM_EXPERT_INST_CNTS
NUM_INST_CNTS

Definition at line 28 of file AMDGPUWaitcntUtils.h.

◆ InstructionFlavor

enum class llvm::AMDGPU::InstructionFlavor : uint8_t

strong

Classification of instructions by execution characteristics.

Used for scheduling decisions and co-execution slot preferences.

Enumerator
WMMA
SingleCycleVALU
TRANS
MultiCycleVALU
VMEM
SMEM
DS
SALU
DMA
Fence
Other
NUM_FLAVORS

Definition at line 80 of file AMDGPUCoExecInfo.h.

◆ LDSLoweringKind

enum class llvm::AMDGPU::LDSLoweringKind

strong

Enumerator
module
table
kernel
hybrid

Definition at line 44 of file AMDGPUSubtarget.h.

◆ Lifetime

enum class llvm::AMDGPU::Lifetime : uint8_t

strong

Enumerator
WindowBudget
RegisterCount

Definition at line 69 of file GCNPreRAAntiHints.h.

◆ LoweringMethodID

enum llvm::AMDGPU::LoweringMethodID

Enumerator
DoNotLower
VccExtToSel
UniExtToSel
UnpackBitShift
UnpackMinMax
S_BFE
V_BFE
VgprToVccCopy
UniMAD64
UniMul64
DivSMulToMAD
SplitTo32
SplitTo32Mul
ScalarizeToS16
SplitTo32Select
SplitTo32SExtInReg
S_BUF_to_BUF
Ext32To64
UniCstExt
CtPop64To32
SplitLoad
WidenLoad
WidenMMOToS32
UnpackAExt
VerifyAllSgpr
ApplyAllVgpr
UnmergeToShiftTrunc
AextToS32InIncomingBlockGPHI
VerifyAllSgprGPHI
VerifyAllSgprOrVgprGPHI
ApplyINTRIN_IMAGE
ApplyBVH_INTERSECT_RAY
SplitBitCount64To32
ExtrVecEltToSel
ExtrVecEltTo32
InsVecEltToSel
InsVecEltTo32
AbsToNegMax
AbsToS32
DynStackAlloc
DeletePrefetch
LowerSetRounding
LowerGetRounding

Definition at line 311 of file AMDGPURegBankLegalizeRules.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned

Enumerator
OPERAND_REG_IMM_INT32	Operands with register, 32-bit, or 64-bit immediate.
OPERAND_REG_IMM_INT64
OPERAND_REG_IMM_INT16
OPERAND_REG_IMM_FP32
OPERAND_REG_IMM_FP64
OPERAND_REG_IMM_BF16
OPERAND_REG_IMM_FP16
OPERAND_REG_IMM_NOINLINE_FP16
OPERAND_REG_IMM_V2BF16
OPERAND_REG_IMM_V2FP16
OPERAND_REG_IMM_V2FP16_SPLAT
OPERAND_REG_IMM_V2INT16
OPERAND_REG_IMM_V2INT64
OPERAND_REG_IMM_NOINLINE_V2FP16
OPERAND_REG_IMM_V2INT32
OPERAND_REG_IMM_V2FP32
OPERAND_REG_IMM_V2FP64
OPERAND_REG_INLINE_C_INT16	Operands with register or inline constant.
OPERAND_REG_INLINE_C_INT32
OPERAND_REG_INLINE_C_INT64
OPERAND_REG_INLINE_C_BF16
OPERAND_REG_INLINE_C_FP16
OPERAND_REG_INLINE_C_FP32
OPERAND_REG_INLINE_C_FP64
OPERAND_REG_INLINE_C_V2INT16
OPERAND_REG_INLINE_C_V2BF16
OPERAND_REG_INLINE_C_V2FP16
OPERAND_INLINE_SPLIT_BARRIER_INT32
OPERAND_KIMM32	Operand with 32-bit immediate that uses the constant bus.
OPERAND_KIMM16
OPERAND_KIMM64
OPERAND_REG_INLINE_AC_INT32	Operands with an AccVGPR register or inline constant.
OPERAND_REG_INLINE_AC_FP32
OPERAND_REG_INLINE_AC_FP64
OPERAND_INLINE_C_AV64_PSEUDO
OPERAND_INPUT_MODS
OPERAND_SDWA_VOPC_DST
OPERAND_REG_IMM_FIRST
OPERAND_REG_IMM_LAST
OPERAND_REG_INLINE_C_FIRST
OPERAND_REG_INLINE_C_LAST
OPERAND_REG_INLINE_AC_FIRST
OPERAND_REG_INLINE_AC_LAST
OPERAND_SRC_FIRST
OPERAND_SRC_LAST
OPERAND_KIMM_FIRST
OPERAND_KIMM_LAST

Definition at line 423 of file SIDefines.h.

◆ R600Feature

enum llvm::AMDGPU::R600Feature : unsigned

One enumerator per frontend-visible R600 feature bit; R600_NUM_FEATURES is the count.

Definition at line 56 of file AMDGPUTargetParser.h.

◆ RegBankLLTMappingApplyID

enum llvm::AMDGPU::RegBankLLTMappingApplyID

Enumerator
InvalidMapping
None
IntrId
Imm
Vcc
VgprAnyTy
AgprAnyTy
VgprOrAgprAnyTy
Sgpr16
Sgpr32
Sgpr64
Sgpr128
SgprP0
SgprP1
SgprP2
SgprP3
SgprP4
SgprP5
SgprP6
SgprP8
SgprPtr32
SgprPtr64
SgprPtr128
SgprV2S16
SgprV4S32
SgprV2S32
SgprB32
SgprB64
SgprB96
SgprB128
SgprB256
SgprB512
SgprBRC
Vgpr16
Vgpr32
Vgpr64
Vgpr128
VgprP0
VgprP1
VgprP2
VgprP3
VgprP4
VgprP5
VgprPtr32
VgprPtr64
VgprPtr128
VgprV2S16
VgprV2S32
VgprV3S32
VgprB32
VgprB64
VgprB96
VgprB128
VgprB160
VgprB256
VgprB512
VgprBRC
VgprV4S16
VgprV8S16
VgprV16S16
VgprV4S32
VgprV8S32
VgprV2S64
UniInVcc
UniInVgprS16
UniInVgprS32
UniInVgprS64
UniInVgprV2S16
UniInVgprV2S32
UniInVgprV3S32
UniInVgprV4S32
UniInVgprV2S64
UniInVgprV6S32
UniInVgprV8S16
UniInVgprV8S32
UniInVgprV16S16
UniInVgprV16S32
UniInVgprV32S16
UniInVgprV32S32
UniInVgprB32
UniInVgprB64
UniInVgprB96
UniInVgprB128
UniInVgprB160
UniInVgprB256
UniInVgprB512
Sgpr32Trunc
Sgpr32ToVgprDst
Sgpr64ToVgprDst
Sgpr32_WF
SgprV4S32_WF
SgprP0Call_WF
SgprP4Call_WF
SgprB32_M0
SgprB32_ReadFirstLane
SgprB64_ReadFirstLane
SgprV4S32_ReadFirstLane
SgprV8S32_ReadFirstLane
Sgpr32AExt
Sgpr32AExtBoolInReg
Sgpr32SExt
Sgpr32ZExt
Vgpr32AExt
Vgpr32SExt
Vgpr32ZExt
VgprV6S32
VgprV16S32
VgprV32S16
VgprV32S32

Definition at line 168 of file AMDGPURegBankLegalizeRules.h.

◆ ScanOptions

enum class llvm::AMDGPU::ScanOptions

strong

Enumerator
DPP
Iterative
None

Definition at line 27 of file AMDGPUSubtarget.h.

◆ SchedGroupMask

enum class llvm::AMDGPU::SchedGroupMask

strong

Enumerator
NONE
ALU
VALU
SALU
MFMA
VMEM
VMEM_READ
VMEM_WRITE
DS
DS_READ
DS_WRITE
TRANS
LDSDMA
ALL

Definition at line 32 of file AMDGPUIGroupLP.h.

◆ SchedulingPhase

enum class llvm::AMDGPU::SchedulingPhase

strong

Enumerator
Initial
PreRAReentry
PostRA

Definition at line 20 of file AMDGPUIGroupLP.h.

◆ TargetIDSetting

enum class llvm::AMDGPU::TargetIDSetting

strong

Enumerator
Unsupported
Any
Off
On

Definition at line 294 of file AMDGPUTargetParser.h.

◆ TargetIndex

enum llvm::AMDGPU::TargetIndex

Enumerator
TI_CONSTDATA_START
TI_SCRATCH_RSRC_DWORD0
TI_SCRATCH_RSRC_DWORD1
TI_SCRATCH_RSRC_DWORD2
TI_SCRATCH_RSRC_DWORD3

Definition at line 664 of file AMDGPU.h.

◆ UniformityLLTOpPredicateID

enum llvm::AMDGPU::UniformityLLTOpPredicateID

Enumerator
_
S1
S16
S32
S64
S128
UniS1
UniS16
UniS32
UniS64
UniS128
UniBF16
DivS1
DivS16
DivS32
DivS64
DivS128
DivAnyTy
P0
P1
P2
P3
P4
P5
P8
Ptr32
Ptr64
Ptr128
UniP0
UniP1
UniP2
UniP3
UniP4
UniP5
UniP6
UniP8
UniPtr32
UniPtr64
UniPtr128
DivP0
DivP1
DivP2
DivP3
DivP4
DivP5
DivPtr32
DivPtr64
DivPtr128
V2S16
V2S32
V2S64
V3S32
V4S32
V32S32
UniV2S16
UniV2S32
UniV4S32
UniV2S64
UniV3S32
UniV6S32
UniV8S16
UniV8S32
UniV16S16
UniV16S32
UniV32S16
UniV32S32
DivV2S16
DivV2S32
DivV4S32
DivV2S64
DivV3S32
DivV4S16
DivV8S16
DivV8S32
DivV16S16
DivV16S32
DivV6S32
DivV32S16
DivV32S32
B32
B64
B96
B128
B160
B256
B512
BRC
UniB32
UniB64
UniB96
UniB128
UniB160
UniB256
UniB512
UniBRC
DivB32
DivB64
DivB96
DivB128
DivB160
DivB256
DivB512
DivBRC

Definition at line 39 of file AMDGPURegBankLegalizeRules.h.

◆ WMMAVariant

enum class llvm::AMDGPU::WMMAVariant

strong

Normalized WMMA or SWMMAC family used to select co-execution rules.

Enumerator
Unknown
IU8_16x16x64
F8F6F4_16x16x128
F8F6F4_16x16x128_BothF4
FP8BF8_16x16x64
F16BF16_16x16x32
FP8BF8_16x16x128
F4_32x16x128

Definition at line 123 of file AMDGPUBaseInfo.h.

Function Documentation

◆ addrspacesMayAlias()

bool llvm::AMDGPU::addrspacesMayAlias	(	unsigned	AS1,
		unsigned	AS2 )

inlinestatic

Definition at line 672 of file AMDGPU.h.

References llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::GCNTTIImpl::addrspacesMayAlias(), llvm::AMDGPUAAResult::alias(), and llvm::GCNTTIImpl::isValidAddrSpaceCast().

◆ applyAntiHintRules()

void llvm::AMDGPU::applyAntiHintRules	(	MachineFunction &	MF,
		const HazardContext &	Ctx )

Definition at line 724 of file GCNPreRAAntiHints.cpp.

◆ asyncStages()

auto llvm::AMDGPU::asyncStages ( AsyncStages Mask )

inline

Returns: the single stages named by Mask, from the least significant bit up.

Definition at line 103 of file AMDGPUAsyncStages.h.

References I, llvm::make_filter_range(), llvm::map_range(), NumAsyncStages, and llvm::seq().

Referenced by operator<<().

◆ asyncStagesFromMaskOperand()

AsyncStages llvm::AMDGPU::asyncStagesFromMaskOperand ( int64_t Mask )

constexpr

Returns: the stages named by the stage mask operand Mask of the asyncmark / wait_asyncmark intrinsics and pseudos. The zero mask is the one exception to a set bit naming a stage: it names every stage rather than none.

Definition at line 96 of file AMDGPUAsyncStages.h.

References ALL, assert(), and isValidAsyncStageMask().

Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().

◆ buildReadAnyLane()

void llvm::AMDGPU::buildReadAnyLane	(	MachineIRBuilder &	B,
		Register	SgprDst,
		Register	VgprSrc,
		const RegisterBankInfo &	RBI )

Definition at line 195 of file AMDGPUGlobalISelUtils.cpp.

References B(), and buildReadLane().

◆ buildReadFirstLane()

void llvm::AMDGPU::buildReadFirstLane	(	MachineIRBuilder &	B,
		Register	SgprDst,
		Register	VgprSrc,
		const RegisterBankInfo &	RBI )

Definition at line 204 of file AMDGPUGlobalISelUtils.cpp.

References B(), and buildReadLane().

◆ canGuaranteeTCO()

LLVM_READNONE constexpr bool llvm::AMDGPU::canGuaranteeTCO ( CallingConv::ID CC )

constexpr

Definition at line 1482 of file AMDGPUBaseInfo.h.

References CC, and llvm::CallingConv::Fast.

Referenced by llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), and mayTailCallThisCC().

◆ classifyFlavor()

InstructionFlavor llvm::AMDGPU::classifyFlavor	(	const MachineInstr &	MI,
		const SIInstrInfo &	SII )

Classify MI into the execution flavor that drives both the scheduler's slot preferences and the hazard recognizer's co-execution masks.

Definition at line 374 of file AMDGPUCoExecSchedStrategy.cpp.

References DMA, DS, Fence, llvm::SIInstrInfo::getBlockingCycles(), llvm::SIInstrInfo::isDS(), llvm::SIInstrInfo::isLDSDMA(), llvm::SIInstrInfo::isMFMA(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSMRD(), llvm::SIInstrInfo::isSWMMAC(), llvm::SIInstrInfo::isTRANS(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVMEM(), llvm::SIInstrInfo::isWaitcnt(), llvm::SIInstrInfo::isWMMA(), MI, MultiCycleVALU, Opc, Other, SALU, SingleCycleVALU, SMEM, TRANS, VMEM, and WMMA.

Referenced by llvm::CandidateHeuristics::collectRegionSummary(), llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary(), llvm::CandidateHeuristics::getCarriedLatency(), llvm::GCNHazardRecognizer::getCoExecMaskForMI(), llvm::CandidateHeuristics::getStallCosts(), llvm::CandidateHeuristics::tryCriticalResourceDependency(), llvm::CandidateHeuristics::tryMemoryPipeline(), and llvm::CandidateHeuristics::updateForScheduling().

◆ convertSetRegImmToVgprMSBs() [1/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs	(	const MachineInstr &	MI,
		bool	HasSetregVGPRMSBFixup )

Returns: VGPR MSBs encoded in a S_SETREG_IMM32_B32 MI if it sets it. If HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is ignored.

Definition at line 3505 of file AMDGPUBaseInfo.cpp.

References assert(), convertSetRegImmToVgprMSBs(), and MI.

◆ convertSetRegImmToVgprMSBs() [2/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs	(	const MCInst &	MI,
		bool	HasSetregVGPRMSBFixup )

Returns: VGPR MSBs encoded in a S_SETREG_IMM32_B32 MI if it sets it. If HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is ignored.

Definition at line 3513 of file AMDGPUBaseInfo.cpp.

References assert(), convertSetRegImmToVgprMSBs(), and MI.

◆ convertSetRegImmToVgprMSBs() [3/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs	(	uint64_t	Imm,
		uint64_t	Simm16,
		bool	HasSetregVGPRMSBFixup )

static

Definition at line 3487 of file AMDGPUBaseInfo.cpp.

References llvm::countr_zero_constexpr(), llvm::AMDGPU::EncodingFields< HwregId, HwregOffset, HwregSize >::decode(), llvm::AMDGPU::Hwreg::DST_VGPR_MSB, llvm::AMDGPU::Hwreg::ID_MODE, Imm, llvm::maskTrailingOnes(), llvm::Offset, llvm::rotr(), llvm::Size, uint64_t, and llvm::AMDGPU::Hwreg::VGPR_MSB_MASK.

Referenced by convertSetRegImmToVgprMSBs(), convertSetRegImmToVgprMSBs(), llvm::AMDGPUAsmPrinter::emitInstruction(), and llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState().

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits	(	const MCSubtargetInfo &	ST,
		uint64_t	ByteOffset )

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 3289 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), isDwordAligned(), and uint64_t.

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ copyMetadataForWidenedLoad()

void llvm::AMDGPU::copyMetadataForWidenedLoad	(	LoadInst &	Dest,
		const LoadInst &	Source )

Definition at line 43 of file AMDGPUMemoryUtils.cpp.

References N, and llvm::Instruction::setMetadata().

◆ counterTypeForInstr()

std::optional< AMDGPU::InstCounterType > llvm::AMDGPU::counterTypeForInstr ( unsigned Opcode )

Determine if MI is a gfx12+ single-counter S_WAIT_*CNT instruction, and if so, which counter it is waiting on.

Definition at line 152 of file AMDGPUWaitcntUtils.cpp.

References ASYNC_CNT, BVH_CNT, DS_CNT, EXP_CNT, KM_CNT, LOAD_CNT, SAMPLE_CNT, STORE_CNT, TENSOR_CNT, and X_CNT.

Referenced by isWaitInstr().

◆ createAMDGPUTargetID()

TargetID llvm::AMDGPU::createAMDGPUTargetID	(	const MCSubtargetInfo &	STI,
		StringRef	FeatureString )

Construct TargetID from MCSubtargetInfo.

FeatureString is used to determine explicitly requested xnack/sramecc settings.

Definition at line 1087 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::TargetID::createFromSubtargetFeatures(), llvm::MCSubtargetInfo::getCPU(), and llvm::MCSubtargetInfo::getTargetTriple().

Referenced by llvm::AMDGPUTargetStreamer::initializeTargetID().

◆ createLaneMaskReg()

Register llvm::AMDGPU::createLaneMaskReg	(	MachineRegisterInfo *	MRI,
		MachineRegisterInfo::VRegAttrs	LaneMaskRegAttrs )

Definition at line 383 of file SILowerI1Copies.cpp.

References MRI.

Referenced by insertUndefLaneMask(), and llvm::AMDGPU::PhiLoweringHelper::mergeIncomingLaneMasks().

◆ createSlowPathCmp()

Value * llvm::AMDGPU::createSlowPathCmp	(	Module &	M,
		IRBuilder<> &	IRB,
		Type *	IntptrTy,
		Value *	AddrLong,
		Value *	ShadowValue,
		uint32_t	TypeStoreSize,
		int	AsanScale )

static

Definition at line 79 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateAnd(), llvm::IRBuilderBase::CreateICmpSGE(), llvm::IRBuilderBase::CreateIntCast(), and llvm::Value::getType().

Referenced by instrumentAddressImpl().

◆ decodeCustomOperand()

bool llvm::AMDGPU::decodeCustomOperand	(	const CustomOperandVal *	Opr,
		int	Size,
		unsigned	Code,
		int &	Idx,
		StringRef &	Name,
		unsigned &	Val,
		bool &	IsDefault,
		const MCSubtargetInfo &	STI )

static

Definition at line 1864 of file AMDGPUBaseInfo.cpp.

References Idx, and llvm::Size.

Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().

◆ decodeDscnt()

unsigned llvm::AMDGPU::decodeDscnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Dscnt from given Waitcnt for given isa Version.

Definition at line 1751 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeLoadcntDscnt(), and decodeStorecntDscnt().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 1731 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeFltRoundToHWConversionTable()

uint32_t llvm::AMDGPU::decodeFltRoundToHWConversionTable ( uint32_t FltRounds )

Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.

Definition at line 235 of file SIModeRegisterDefaults.cpp.

References FltRoundToHWConversionTable.

Referenced by llvm::SITargetLowering::lowerSET_ROUNDING().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 1736 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeLoadcnt()

unsigned llvm::AMDGPU::decodeLoadcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Loadcnt from given Waitcnt for given isa Version.

Definition at line 1741 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeLoadcntDscnt().

◆ decodeLoadcntDscnt()

Waitcnt llvm::AMDGPU::decodeLoadcntDscnt	(	const IsaVersion &	Version,
		unsigned	LoadcntDscnt )

Returns: Decoded Waitcnt structure from given LoadcntDscnt for given isa Version.

Definition at line 127 of file AMDGPUWaitcntUtils.cpp.

References decodeDscnt(), decodeLoadcnt(), DS_CNT, LOAD_CNT, llvm::AMDGPU::Waitcnt::set(), and llvm::Version.

◆ decodeStorecnt()

unsigned llvm::AMDGPU::decodeStorecnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Storecnt from given Waitcnt for given isa Version.

Definition at line 1746 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeStorecntDscnt().

◆ decodeStorecntDscnt()

Waitcnt llvm::AMDGPU::decodeStorecntDscnt	(	const IsaVersion &	Version,
		unsigned	StorecntDscnt )

Returns: Decoded Waitcnt structure from given StorecntDscnt for given isa Version.

Definition at line 134 of file AMDGPUWaitcntUtils.cpp.

References decodeDscnt(), decodeStorecnt(), DS_CNT, llvm::AMDGPU::Waitcnt::set(), STORE_CNT, and llvm::Version.

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt )

Returns: Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 1723 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Encoded )

Definition at line 114 of file AMDGPUWaitcntUtils.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), DS_CNT, EXP_CNT, LOAD_CNT, llvm::AMDGPU::Waitcnt::set(), and llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned &	Vmcnt,
		unsigned &	Expcnt,
		unsigned &	Lgkmcnt )

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9) Vmcnt = Waitcnt[15:14,3:0] (gfx9,10) Vmcnt = Waitcnt[15:10] (gfx11) Expcnt = Waitcnt[6:4] (pre-gfx11) Expcnt = Waitcnt[2:0] (gfx11) Lgkmcnt = Waitcnt[11:8] (pre-gfx10) Lgkmcnt = Waitcnt[13:8] (gfx10) Lgkmcnt = Waitcnt[9:4] (gfx11)

Definition at line 1756 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and llvm::Version.

◆ eliminateGVConstantExprUsesFromAllInstructions()

bool llvm::AMDGPU::eliminateGVConstantExprUsesFromAllInstructions	(	Module &	M,
		function_ref< bool(const GlobalVariable &)>	Filter )

Iterates over all GlobalVariables in M, and whenever Filter returns true, replace all constant users of the GV with instructions.

Definition at line 133 of file AMDGPUMemoryUtils.cpp.

References llvm::convertUsersOfConstantsToInstructions(), llvm::Filter, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ encode32BitLiteral()

LLVM_READNONE int64_t llvm::AMDGPU::encode32BitLiteral	(	int64_t	Imm,
		OperandType	Type,
		bool	IsLit )

◆ encodeCustomOperand()

int llvm::AMDGPU::encodeCustomOperand	(	const CustomOperandVal *	Opr,
		int	Size,
		const StringRef	Name,
		int64_t	InputVal,
		unsigned &	UsedOprMask,
		const MCSubtargetInfo &	STI )

static

Definition at line 1888 of file AMDGPUBaseInfo.cpp.

References encodeCustomOperandVal(), Idx, OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and llvm::Size.

Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().

◆ encodeCustomOperandVal()

int llvm::AMDGPU::encodeCustomOperandVal	(	const CustomOperandVal &	Op,
		int64_t	InputVal )

static

Definition at line 1881 of file AMDGPUBaseInfo.cpp.

References OPR_VAL_INVALID.

Referenced by encodeCustomOperand().

◆ encodeDscnt()

unsigned llvm::AMDGPU::encodeDscnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Dscnt )

static

Definition at line 1819 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Expcnt )

Returns: Waitcnt with encoded Expcnt for given isa Version.

Definition at line 1772 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Lgkmcnt )

Returns: Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 1778 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLoadcnt()

unsigned llvm::AMDGPU::encodeLoadcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Loadcnt )

static

Definition at line 1807 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeLoadcntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded )

Returns: Loadcnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa Version.

Definition at line 141 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeLoadcntDscnt(), llvm::AMDGPU::Waitcnt::get(), LOAD_CNT, and llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeLoadcntDscnt() [2/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt	(	const IsaVersion &	Version,
		unsigned	Loadcnt,
		unsigned	Dscnt )

Returns: Waitcnt with encoded Loadcnt and Dscnt for given isa Version.

Definition at line 1825 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeLoadcnt(), getCombinedCountBitMask(), and llvm::Version.

◆ encodeStorecnt()

unsigned llvm::AMDGPU::encodeStorecnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Storecnt )

static

Definition at line 1813 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeStorecntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded )

Returns: Storecnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa Version.

Definition at line 146 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeStorecntDscnt(), llvm::AMDGPU::Waitcnt::get(), STORE_CNT, and llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeStorecntDscnt() [2/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt	(	const IsaVersion &	Version,
		unsigned	Storecnt,
		unsigned	Dscnt )

Returns: Waitcnt with encoded Storecnt and Dscnt for given isa Version.

Definition at line 1833 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeStorecnt(), getCombinedCountBitMask(), and llvm::Version.

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Vmcnt )

Returns: Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 1763 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded )

Definition at line 122 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeWaitcnt(), EXP_CNT, llvm::AMDGPU::Waitcnt::get(), LOAD_CNT, and llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Vmcnt,
		unsigned	Expcnt,
		unsigned	Lgkmcnt )

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[2:0] = Expcnt (gfx11+) Waitcnt[3:0] = Vmcnt (pre-gfx9) Waitcnt[3:0] = Vmcnt[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt (pre-gfx11) Waitcnt[9:4] = Lgkmcnt (gfx11) Waitcnt[11:8] = Lgkmcnt (pre-gfx10) Waitcnt[13:8] = Lgkmcnt (gfx10) Waitcnt[15:10] = Vmcnt (gfx11) Waitcnt[15:14] = Vmcnt[5:4] (gfx9,10)

Returns: Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 1784 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and llvm::Version.

◆ evaluateRcp()

std::optional< APFloat > llvm::AMDGPU::evaluateRcp ( const APFloat & Val )

Evaluate the constant-folded result of v_rcp for Val, accounting for the hardware's denormal flushing on f32/f64 and its approximate rounding.

Returns std::nullopt if the hardware result is not guaranteed to match the exact reciprocal.

Definition at line 3761 of file AMDGPUBaseInfo.cpp.

References llvm::APFloatBase::BFloat(), llvm::APFloat::getOne(), llvm::APFloat::getSemantics(), llvm::APFloat::getZero(), llvm::APFloatBase::IEEEhalf(), llvm::APFloat::isDenormal(), and llvm::APFloat::isNegative().

Referenced by llvm::GCNTTIImpl::instCombineIntrinsic(), and llvm::AMDGPUTargetLowering::performRcpCombine().

◆ fillAMDGPUFeatureMap()

std::pair< FeatureError, StringRef > llvm::AMDGPU::fillAMDGPUFeatureMap	(	StringRef	GPU,
		const Triple &	T,
		StringMap< bool > &	Features )

Fills Features map with default values for given target GPU.

Features contains overriding target features and this function returns default target features with entries overridden by Features.

Definition at line 723 of file AMDGPUTargetParser.cpp.

References addGPUFeatures(), llvm::Triple::AMDHSA, fillAMDGCNFeatureMap(), fillValidArchListAMDGCN(), G, llvm_unreachable, NO_ERROR, parseArchAMDGCN(), parseArchR600(), and T.

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN	(	SmallVectorImpl< StringRef > &	Values,
		Triple::SubArchType	SubArch = Triple::NoSubArch )

Append the valid AMDGCN GPU names to Values.

If SubArch is not NoSubArch, only GPUs compatible with that subarch (see isCPUValidForSubArch) are appended.

Definition at line 340 of file AMDGPUTargetParser.cpp.

References A(), I, isCPUValidForSubArch(), llvm::Triple::NoSubArch, and llvm::Values.

Referenced by fillAMDGPUFeatureMap().

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > & Values )

Definition at line 357 of file AMDGPUTargetParser.cpp.

References A(), and llvm::Values.

◆ foldAMDGPUMCExpr()

const MCExpr * llvm::AMDGPU::foldAMDGPUMCExpr	(	const MCExpr *	Expr,
		MCContext &	Ctx )

Definition at line 741 of file AMDGPUMCExpr.cpp.

References knownBitsMapHelper(), and tryFoldHelper().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ genAMDGPUReportBlock()

Instruction * llvm::AMDGPU::genAMDGPUReportBlock	(	Module &	M,
		IRBuilder<> &	IRB,
		Value *	Cond,
		bool	Recover )

static

Definition at line 57 of file AMDGPUAsanInstrumentation.cpp.

References Cond, llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateIntrinsicWithoutFolding(), llvm::IRBuilderBase::CreateIsNotNull(), llvm::MDBuilder::createUnlikelyBranchWeights(), llvm::IRBuilderBase::GetInsertPoint(), llvm::IRBuilderBase::getInt64Ty(), llvm::IRBuilderBase::SetInsertPoint(), and llvm::SplitBlockAndInsertIfThen().

Referenced by instrumentAddressImpl().

◆ generateCrashCode()

Instruction * llvm::AMDGPU::generateCrashCode	(	Module &	M,
		IRBuilder<> &	IRB,
		Type *	IntptrTy,
		Instruction *	InsertBefore,
		Value *	Addr,
		bool	IsWrite,
		size_t	AccessSizeIndex,
		Value *	SizeArgument,
		bool	Recover )

static

Definition at line 97 of file AMDGPUAsanInstrumentation.cpp.

References Call, llvm::IRBuilderBase::CreateCall(), llvm::FunctionType::get(), llvm::IRBuilderBase::getVoidTy(), kAsanReportErrorTemplate, llvm::IRBuilderBase::SetInsertPoint(), and llvm::raw_svector_ostream::str().

Referenced by instrumentAddressImpl().

◆ getAddr64Inst()

LLVM_READONLY int32_t llvm::AMDGPU::getAddr64Inst ( uint32_t Opcode )

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getAddressableLocalMemorySize() [1/2]

unsigned llvm::AMDGPU::getAddressableLocalMemorySize	(	GPUKind	AK,
		bool	FullSIMDMode )

Returns: LDS in bytes a single work-group can allocate.

Definition at line 509 of file AMDGPUTargetParser.cpp.

References getLocalMemorySize(), and getMaxHWAddressableLocalMemorySize().

Referenced by getAddressableLocalMemorySize(), and llvm::GCNSubtarget::initializeSubtargetDependencies().

◆ getAddressableLocalMemorySize() [2/2]

unsigned llvm::AMDGPU::getAddressableLocalMemorySize	(	Triple::SubArchType	SubArch,
		bool	FullSIMDMode )

Definition at line 514 of file AMDGPUTargetParser.cpp.

References getAddressableLocalMemorySize(), and getGPUKindFromSubArch().

◆ getAddressableNumSGPRs() [1/2]

unsigned llvm::AMDGPU::getAddressableNumSGPRs ( GPUKind AK )

Definition at line 388 of file AMDGPUTargetParser.cpp.

References FIXED_NUM_SGPRS_FOR_INIT_BUG, getFeatureBitset(), getIsaVersion(), getSubArch(), test, and llvm::Version.

Referenced by llvm::GCNSubtarget::getAddressableNumSGPRs(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getSGPRAllocGranule(), and getSGPRAllocGranule().

◆ getAddressableNumSGPRs() [2/2]

unsigned llvm::AMDGPU::getAddressableNumSGPRs ( Triple::SubArchType SubArch )

Definition at line 400 of file AMDGPUTargetParser.cpp.

References FIXED_NUM_SGPRS_FOR_INIT_BUG, getFeatureBitset(), getGPUKindFromSubArch(), getIsaVersion(), test, and llvm::Version.

◆ getAddressableNumVGPRs() [1/2]

unsigned llvm::AMDGPU::getAddressableNumVGPRs	(	GPUKind	AK,
		bool	IsWave32 )

Returns: Number of VGPRs a single wave can address. On a target with a unified register file this covers the AGPRs as well. This does not account for dynamic VGPR mode, which caps allocation at a fixed number of blocks.

Definition at line 461 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), getTotalNumVGPRs(), and llvm::Bitset< NumBits >::test().

Referenced by getAddressableNumVGPRs(), and llvm::GCNSubtarget::getAddressableNumVGPRs().

◆ getAddressableNumVGPRs() [2/2]

unsigned llvm::AMDGPU::getAddressableNumVGPRs	(	Triple::SubArchType	SubArch,
		bool	IsWave32 )

Definition at line 476 of file AMDGPUTargetParser.cpp.

References getAddressableNumVGPRs(), and getGPUKindFromSubArch().

◆ getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp	(	const MIMGBaseOpcodeInfo *	BaseOpcode,
		const MIMGDimInfo *	Dim,
		bool	IsA16,
		bool	IsG16Supported )

Definition at line 342 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getAGPRFormOp()

LLVM_READONLY int32_t llvm::AMDGPU::getAGPRFormOp ( uint32_t Opcode )

Returns: Version of an instruction which uses AGPRs for coupled operands given an Opcode which uses VGPRs for coupled operands.

References LLVM_READONLY.

Referenced by getMFMANonMacAGPRFormOp().

◆ getAlign()

Align llvm::AMDGPU::getAlign	(	const DataLayout &	DL,
		const GlobalVariable *	GV )

Definition at line 29 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().

◆ getAMDHSACodeObjectVersion() [1/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( const Module & M )

Returns: Code object version from the IR module flag.

Definition at line 219 of file AMDGPUBaseInfo.cpp.

References llvm::mdconst::extract_or_null(), and getDefaultAMDHSACodeObjectVersion().

Referenced by llvm::AMDGPUAsmPrinter::doInitialization(), llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV4::emitKernel(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULowerKernelAttributesPass::run(), llvm::AMDGPUResourceUsageAnalysis::run(), llvm::AMDGPUResourceUsageAnalysisWrapperPass::runOnMachineFunction(), and llvm::AMDGPUDisassembler::setABIVersion().

◆ getAMDHSACodeObjectVersion() [2/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( unsigned ABIVersion )

Returns: Code object version from ELF's e_ident[EI_ABIVERSION].

Definition at line 232 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and getDefaultAMDHSACodeObjectVersion().

◆ getArchFamilyNameAMDGCN()

StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN ( GPUKind AK )

Definition at line 165 of file AMDGPUTargetParser.cpp.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind AK )

Definition at line 276 of file AMDGPUTargetParser.cpp.

Referenced by getCanonicalArchName(), llvm::AMDGPU::TargetID::print(), and llvm::AMDGPU::TargetID::printCanonicalTargetIDString().

◆ getArchNameFromSubArch()

StringRef llvm::AMDGPU::getArchNameFromSubArch ( Triple::SubArchType SubArch )

Returns the canonical GPU name for an AMDGPU subarch, e.g.

AMDGPUSubArch1030 -> "gfx1030", AMDGPUSubArch9 -> "gfx9-generic", AMDGPUSubArch6 -> "gfx600". Returns "" for NoSubArch or a non-AMDGPU subarch. The major-only subarches map to their generic/lowest representative, matching the default subtarget for an unspecified -mcpu.

Definition at line 281 of file AMDGPUTargetParser.cpp.

References llvm::Triple::FirstAMDGPUSubArch, and llvm::Triple::LastAMDGPUSubArch.

Referenced by createAMDGPUMCSubtargetInfo(), and getGPUOrDefault().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind AK )

Definition at line 300 of file AMDGPUTargetParser.cpp.

Referenced by getCanonicalArchName().

◆ getAsynccntBitMask()

unsigned llvm::AMDGPU::getAsynccntBitMask ( const IsaVersion & Version )

Returns: Asynccnt bit mask for given isa Version. Returns 0 for versions that do not support Asynccnt

Definition at line 1699 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getAsyncStageIndex()

unsigned llvm::AMDGPU::getAsyncStageIndex ( AsyncStages Stage )

inline

Returns: the position of the bit of the single stage Stage, for indexing per-stage data.

Definition at line 112 of file AMDGPUAsyncStages.h.

References assert(), llvm::countr_zero(), llvm::has_single_bit(), and llvm::to_underlying().

Referenced by getAsyncStageName().

◆ getAsyncStageName()

StringRef llvm::AMDGPU::getAsyncStageName ( AsyncStages Stage )

inline

Returns: the name of the single stage Stage.

Definition at line 118 of file AMDGPUAsyncStages.h.

References AsyncStageNames, and getAsyncStageIndex().

Referenced by operator<<().

◆ getBarrierMemberCountBitMask()

unsigned llvm::AMDGPU::getBarrierMemberCountBitMask ( const IsaVersion & Version )

Returns: barrier member count bit mask in M0 for given isa Version.

Definition at line 1707 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset	(	MachineRegisterInfo &	MRI,
		Register	Reg,
		GISelValueTracking *	ValueTracking = nullptr,
		bool	CheckNUW = false )

◆ getBasicFromSDWAOp()

LLVM_READONLY int32_t llvm::AMDGPU::getBasicFromSDWAOp ( uint32_t Opcode )

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getBitOp2()

unsigned llvm::AMDGPU::getBitOp2 ( unsigned Opc )

Definition at line 869 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getCanBeVOPD(), getVOPDFull(), and getVOPDOpcode().

◆ getBufferResourceNumRecordsWidth() [1/2]

std::optional< unsigned > llvm::AMDGPU::getBufferResourceNumRecordsWidth ( GPUKind AK )

Returns: Number of bits in the num_records field in a buffer resource, or nullopt if it is not known concretely.

Definition at line 529 of file AMDGPUTargetParser.cpp.

Referenced by getBufferResourceNumRecordsWidth().

◆ getBufferResourceNumRecordsWidth() [2/2]

std::optional< unsigned > llvm::AMDGPU::getBufferResourceNumRecordsWidth ( Triple::SubArchType SubArch )

Definition at line 537 of file AMDGPUTargetParser.cpp.

References getBufferResourceNumRecordsWidth(), and getGPUKindFromSubArch().

◆ getBvhcntBitMask()

unsigned llvm::AMDGPU::getBvhcntBitMask ( const IsaVersion & Version )

Returns: Bvhcnt bit mask for given isa Version. Returns 0 for versions that do not support BVHcnt

Definition at line 1675 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getCanBeVOPD()

LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD	(	unsigned	Opc,
		unsigned	EncodingFamily,
		bool	VOPD3 )

Definition at line 696 of file AMDGPUBaseInfo.cpp.

References getBitOp2(), llvm::InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key, llvm::AMDGPU::VOPDXYInfo::IsX, llvm::AMDGPU::VOPDXYInfo::IsY, and Opc.

Referenced by shouldScheduleVOPDAdjacent(), and tryMatchVOPDPairVariant().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName	(	const Triple &	T,
		StringRef	Arch )

Definition at line 598 of file AMDGPUTargetParser.cpp.

References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), parseArchR600(), and T.

◆ getCoExecInfo()

CoExecInfo llvm::AMDGPU::getCoExecInfo	(	const MachineInstr &	MI,
		const SIInstrInfo &	TII )

inline

Get co-execution info for a WMMA instruction, selecting the per-cycle slot pattern from the opcode (and operand formats for the F8F6F4 variants).

Definition at line 376 of file AMDGPUCoExecInfo.h.

References llvm::AMDGPU::CoExecInfo::build(), F16BF16_16x16x32, F4_32x16x128, F8F6F4_16x16x128, F8F6F4_16x16x128_BothF4, FP8BF8_16x16x128, FP8BF8_16x16x64, llvm::MachineOperand::getImm(), getMFMACoExecInfo(), IU8_16x16x64, llvm_unreachable, llvm::AMDGPU::WMMA::MATRIX_FMT_FP4, MI, Opc, TII, and Unknown.

◆ getCoExecMask()

CoExecMaskT llvm::AMDGPU::getCoExecMask ( InstructionFlavor F )

inline

Map a flavor to the co-execution class it occupies in a window slot.

Definition at line 131 of file AMDGPUCoExecInfo.h.

References CTRL, DMA, DS, F, Fence, llvm_unreachable, MultiCycleVALU, NUM_FLAVORS, Other, SALU, SingleCycleVALU, SMEM, TRANS, VALU, VMEM, and WMMA.

Referenced by llvm::GCNHazardRecognizer::getCoExecMaskForMI().

◆ getCoExecMaskName()

const char * llvm::AMDGPU::getCoExecMaskName ( CoExecMaskT Mask )

inline

Return a human-readable name for a mask holding a single instruction class, as produced by getCoExecMask().

Definition at line 197 of file AMDGPUCoExecInfo.h.

References CTRL, DS, llvm_unreachable, SALU, SMEM, TRANS, VALU, VMEM, and WMMA.

◆ getCombinedCountBitMask()

unsigned llvm::AMDGPU::getCombinedCountBitMask	(	const IsaVersion &	Version,
		bool	IsStore )

static

Definition at line 1793 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ getCommuteOrig()

LLVM_READONLY int32_t llvm::AMDGPU::getCommuteOrig ( uint32_t Opcode )

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCommuteRev()

LLVM_READONLY int32_t llvm::AMDGPU::getCommuteRev ( uint32_t Opcode )

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCompletionActionImplicitArgPosition()

unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition ( unsigned CodeObjectVersion )

Definition at line 297 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.

◆ getDefaultAMDHSACodeObjectVersion()

unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ( )

Returns: The default HSA code object version. This should only be used when we lack a more accurate CodeObjectVersion value (e.g. from the IR module flag or a .amdhsa_code_object_version directive)

Definition at line 228 of file AMDGPUBaseInfo.cpp.

References DefaultAMDHSACodeObjectVersion.

Referenced by getAMDHSACodeObjectVersion(), and getAMDHSACodeObjectVersion().

◆ getDefaultQueueImplicitArgPosition()

unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition ( unsigned CodeObjectVersion )

Definition at line 286 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.

◆ getDPPOp32()

LLVM_READONLY int32_t llvm::AMDGPU::getDPPOp32 ( uint32_t Opcode )

References LLVM_READONLY.

◆ getDPPOp64()

LLVM_READONLY int32_t llvm::AMDGPU::getDPPOp64 ( uint32_t Opcode )

References LLVM_READONLY.

◆ getDscntBitMask()

unsigned llvm::AMDGPU::getDscntBitMask ( const IsaVersion & Version )

Returns: Dscnt bit mask for given isa Version. Returns 0 for versions that do not support DScnt

Definition at line 1687 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getDynamicVGPRBlockSize()

unsigned llvm::AMDGPU::getDynamicVGPRBlockSize ( const Function & F )

Definition at line 2377 of file AMDGPUBaseInfo.cpp.

References BlockSize, and F.

Referenced by llvm::GCNSubtarget::computeOccupancy(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getELFABIVersion()

uint8_t llvm::AMDGPU::getELFABIVersion	(	const Triple &	OS,
		unsigned	CodeObjectVersion )

Returns: ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION].

Parameters

CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().

Definition at line 245 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, llvm::report_fatal_error(), and T.

Referenced by llvm::AMDGPUTargetELFStreamer::finish().

◆ getEncodingFromOperandTable()

template<size_t N>

int64_t llvm::AMDGPU::getEncodingFromOperandTable	(	const CustomOperand(&)	Table[N],
		StringRef	Name,
		const MCSubtargetInfo &	STI )

static

Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.

Definition at line 46 of file AMDGPUAsmUtils.cpp.

References N, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and llvm::Table.

Referenced by llvm::AMDGPU::Hwreg::getHwregId(), llvm::AMDGPU::SendMsg::getMsgId(), and llvm::AMDGPU::SendMsg::getMsgOpId().

◆ getEventsFor()

HWEvents llvm::AMDGPU::getEventsFor	(	const MachineInstr &	Inst,
		const GCNSubtarget &	ST,
		bool	IsExpertMode,
		bool	TgSplit )

Returns: A bitmask of HWEvent triggered by Inst

Definition at line 199 of file AMDGPUHWEvents.cpp.

References getEventsForImpl(), getExpertSchedulingEventType(), and TII.

◆ getEventsForImpl()

HWEvents llvm::AMDGPU::getEventsForImpl	(	const MachineInstr &	Inst,
		const GCNSubtarget &	ST,
		const SIInstrInfo &	TII,
		bool	TgSplit )

static

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion & Version )

Returns: Expcnt bit mask for given isa Version.

Definition at line 1679 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getExpertSchedulingEventType()

HWEvents llvm::AMDGPU::getExpertSchedulingEventType	(	const MachineInstr &	Inst,
		const SIInstrInfo &	TII )

static

Definition at line 23 of file AMDGPUHWEvents.cpp.

References llvm::MachineInstr::getOpcode(), isDPMACCInstruction(), and TII.

Referenced by getEventsFor().

◆ getExponentOnlyScaleArgIdx()

std::optional< unsigned > llvm::AMDGPU::getExponentOnlyScaleArgIdx ( unsigned IntrID )

Returns: the index of the f32 scale argument of a V_CVT_SCALEF32_* conversion to a narrow format, or std::nullopt for any other intrinsic. These instructions only read the bits of the scale given by getExponentOnlyScaleDemandedBits().

Definition at line 3412 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::GCNTTIImpl::instCombineIntrinsic().

◆ getExponentOnlyScaleDemandedBits()

APInt llvm::AMDGPU::getExponentOnlyScaleDemandedBits ( )

inline

Returns: the bits of an exponent-only scale argument that are read: the exponent field of the f32 value.

Definition at line 1809 of file AMDGPUBaseInfo.h.

References llvm::APInt::getBitsSet().

Referenced by simplifyExponentOnlyScaleArg().

◆ getExprKind()

AMDGPUMCExpr::VariantKind llvm::AMDGPU::getExprKind ( const MCExpr * Expr )

Definition at line 773 of file AMDGPUMCExpr.cpp.

References llvm::AMDGPUMCExpr::AGVK_None, llvm::dyn_cast(), and E.

◆ getFeatureBitset() [1/2]

const AMDGPUFeatureBitset & llvm::AMDGPU::getFeatureBitset ( GPUKind AK )

Returns AK's feature bitset, or an empty bitset if unknown.

Definition at line 315 of file AMDGPUTargetParser.cpp.

References DenseMapInfo< LocallyHashedType >::Empty.

Referenced by computeTargetIDFeatures(), getAddressableNumSGPRs(), getAddressableNumSGPRs(), getAddressableNumVGPRs(), getDefaultTargetIDFeatures(), getFeatureBitset(), getLDSAllocGranule(), getLDSEncodingGranule(), getLocalMemorySize(), getTotalNumVGPRs(), getVGPRAllocGranule(), isSramEccHardwiredOn(), and isXnackHardwiredOn().

◆ getFeatureBitset() [2/2]

const AMDGPUFeatureBitset & llvm::AMDGPU::getFeatureBitset ( Triple::SubArchType SubArch )

Convenience overload of getFeatureBitset taking a triple subarch, which is mapped via getGPUKindFromSubArch.

Definition at line 322 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), and getGPUKindFromSubArch().

◆ getFeatureBitsetR600()

const R600FeatureBitset & llvm::AMDGPU::getFeatureBitsetR600 ( GPUKind AK )

Returns R600 GPU AK's feature bitset, or an empty bitset if unknown.

Definition at line 326 of file AMDGPUTargetParser.cpp.

References DenseMapInfo< LocallyHashedType >::Empty.

◆ getFeatureNames()

void llvm::AMDGPU::getFeatureNames	(	const AMDGPUFeatureBitset &	Features,
		SmallVectorImpl< StringRef > &	Names )

Appends the feature name of each bit set in Features to Names.

Definition at line 332 of file AMDGPUTargetParser.cpp.

References I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::Bitset< NumBits >::test().

Referenced by addGPUFeatures().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSSfromSV ( uint32_t Opcode )

Returns: SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

References LLVM_READONLY.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSTfromSS ( uint32_t Opcode )

Returns: ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSVfromSS ( uint32_t Opcode )

Returns: SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getFlatScratchInstSVfromSVS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSVfromSVS ( uint32_t Opcode )

Returns: SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SVS (SADDR + VADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getFlavorName()

StringRef llvm::AMDGPU::getFlavorName ( InstructionFlavor F )

inline

Definition at line 95 of file AMDGPUCoExecInfo.h.

References DMA, DS, F, Fence, llvm_unreachable, MultiCycleVALU, NUM_FLAVORS, Other, SALU, SingleCycleVALU, SMEM, TRANS, VMEM, and WMMA.

Referenced by llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary(), and llvm::CandidateHeuristics::dumpRegionSummary().

◆ getFPDstSelType()

LLVM_READONLY FPType llvm::AMDGPU::getFPDstSelType ( unsigned Opc )

Definition at line 841 of file AMDGPUBaseInfo.cpp.

References FP4, FP8, None, and Opc.

Referenced by getDstSelForwardingOperand().

◆ getGcnBufferFormatInfo() [1/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	BitsPerComp,
		uint8_t	NumComponents,
		uint8_t	NumFormat,
		const MCSubtargetInfo &	STI )

Definition at line 3419 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by getBufferFormatWithCompCount(), and simplifyAMDGCNMemoryIntrinsicDemanded().

◆ getGcnBufferFormatInfo() [2/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	Format,
		const MCSubtargetInfo &	STI )

Definition at line 3430 of file AMDGPUBaseInfo.cpp.

References llvm::Format, isGFX10(), and isGFX11Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int32_t llvm::AMDGPU::getGlobalSaddrOp ( uint32_t Opcode )

Returns: SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

References LLVM_READONLY.

◆ getGlobalVaddrOp()

LLVM_READONLY int32_t llvm::AMDGPU::getGlobalVaddrOp ( uint32_t Opcode )

Returns: VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getGPUKindFromSubArch()

AMDGPU::GPUKind llvm::AMDGPU::getGPUKindFromSubArch ( Triple::SubArchType SubArch )

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport ( const Function & F )

Definition at line 2366 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, and F.

Referenced by generateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport ( const Function & F )

Definition at line 2373 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by generateEndPgm().

◆ getHasMatrixScale()

LLVM_READONLY bool llvm::AMDGPU::getHasMatrixScale ( unsigned Opc )

Definition at line 599 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition ( unsigned COV )

Returns: The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line 275 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.

◆ getIfAddr64Inst()

LLVM_READONLY int32_t llvm::AMDGPU::getIfAddr64Inst ( uint32_t Opcode )

Check if Opcode is an Addr64 opcode.

Returns: Opcode if it is an Addr64 opcode, otherwise -1.

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode	(	unsigned	BaseOpcode,
		unsigned	Dim )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned Intr )

Referenced by collectMergeableInsts(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::GCNTTIImpl::instCombineIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), optimizeSection(), and llvm::AMDGPUInstructionSelector::select().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function & F )

Definition at line 2361 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getInlineEncodingV216()

std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV216	(	bool	IsFloat,
		uint32_t	Literal )

Definition at line 3006 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and llvm::Signed.

Referenced by getInlineEncodingV2F16(), getInlineEncodingV2I16(), getPKFMACF16InlineEncoding(), and isInlinableLiteralV216().

◆ getInlineEncodingV2BF16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2BF16 ( uint32_t Literal )

Definition at line 3067 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and llvm::Signed.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2BF16().

◆ getInlineEncodingV2F16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2F16 ( uint32_t Literal )

Definition at line 3095 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2F16().

◆ getInlineEncodingV2I16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2I16 ( uint32_t Literal )

Definition at line 3061 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2I16().

◆ getInstCounterName()

StringLiteral llvm::AMDGPU::getInstCounterName ( InstCounterType T )

Definition at line 28 of file AMDGPUWaitcntUtils.cpp.

References ASYNC_CNT, BVH_CNT, DS_CNT, EXP_CNT, KM_CNT, llvm_unreachable, LOAD_CNT, NUM_INST_CNTS, SAMPLE_CNT, STORE_CNT, T, TENSOR_CNT, VA_VDST_RD, VA_VDST_WR, VM_VSRC, and X_CNT.

Referenced by llvm::AMDGPU::Waitcnt::print().

◆ getIntegerPairAttribute() [1/2]

std::optional< std::pair< unsigned, std::optional< unsigned > > > llvm::AMDGPU::getIntegerPairAttribute	(	const Function &	F,
		StringRef	Name,
		bool	OnlyFirstRequired = false )

Returns: A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).; std::nullopt if attribute is not present.; std::nullopt and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1561 of file AMDGPUBaseInfo.cpp.

References A(), and F.

◆ getIntegerPairAttribute() [2/2]

std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute	(	const Function &	F,
		StringRef	Name,
		std::pair< unsigned, unsigned >	Default,
		bool	OnlyFirstRequired = false )

Returns: A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).; Default if attribute is not present.; Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1552 of file AMDGPUBaseInfo.cpp.

References llvm::Default, F, and getIntegerPairAttribute().

Referenced by llvm::AMDGPUMachineFunctionInfo::AMDGPUMachineFunctionInfo(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), getIntegerPairAttribute(), llvm::GCNSubtarget::getMaxNumVectorRegs(), llvm::AMDGPUSubtarget::getWavesPerEU(), llvm::AMDGPUSubtarget::getWavesPerEU(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getIntegerVecAttribute() [1/2]

std::optional< SmallVector< unsigned > > llvm::AMDGPU::getIntegerVecAttribute	(	const Function &	F,
		StringRef	Name,
		unsigned	Size )

Similar to the function above, but returns std::nullopt if any error occurs.

Definition at line 1596 of file AMDGPUBaseInfo.cpp.

References A(), assert(), llvm::StringRef::empty(), F, llvm::Size, llvm::StringRef::split(), and llvm::utostr().

◆ getIntegerVecAttribute() [2/2]

SmallVector< unsigned > llvm::AMDGPU::getIntegerVecAttribute	(	const Function &	F,
		StringRef	Name,
		unsigned	Size,
		unsigned	DefaultVal )

Returns: Generate a vector of integer values requested using F's Name attribute.; A vector of size Size, with all elements set to DefaultVal, if any error occurs. The corresponding error will also be emitted.

Definition at line 1587 of file AMDGPUBaseInfo.cpp.

References F, getIntegerVecAttribute(), and llvm::Size.

Referenced by llvm::AMDGPU::ClusterDimsAttr::get(), getIntegerVecAttribute(), getMaxNumWorkGroups(), and processUse().

◆ getInterestingMemoryOperands()

void llvm::AMDGPU::getInterestingMemoryOperands	(	Module &	M,
		Instruction *	I,
		SmallVectorImpl< InterestingMemoryOperand > &	Interesting )

Get all the memory operands from the instruction that needs to be instrumented.

Definition at line 221 of file AMDGPUAsanInstrumentation.cpp.

References llvm::cast(), DL, llvm::dyn_cast(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::VectorType::get(), llvm::Value::getPointerAlignment(), llvm::Value::getType(), I, and llvm::isa().

◆ getIntrinsicID()

Intrinsic::ID llvm::AMDGPU::getIntrinsicID ( const MachineInstr & I )

Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But they are not actual instances of GIntrinsics, so we cannot use GIntrinsic::getIntrinsicID() on them.

Definition at line 24 of file AMDGPUInstrInfo.cpp.

References I.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPUInstructionSelector::select().

◆ getIsaVersion() [1/2]

◆ getIsaVersion() [2/2]

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( Triple::SubArchType SubArch )

Definition at line 369 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch().

◆ getKmcntBitMask()

unsigned llvm::AMDGPU::getKmcntBitMask ( const IsaVersion & Version )

Returns: Dscnt bit mask for given isa Version. Returns 0 for versions that do not support KMcnt

Definition at line 1691 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getLDSAllocGranule() [1/2]

unsigned llvm::AMDGPU::getLDSAllocGranule ( GPUKind AK )

Returns: Hardware LDS allocation granularity in bytes, used for occupancy.

Definition at line 541 of file AMDGPUTargetParser.cpp.

References assert(), getFeatureBitset(), llvm::Bitset< NumBits >::none(), and llvm::Bitset< NumBits >::test().

Referenced by getLDSAllocGranule(), and llvm::GCNSubtarget::initializeSubtargetDependencies().

◆ getLDSAllocGranule() [2/2]

unsigned llvm::AMDGPU::getLDSAllocGranule ( Triple::SubArchType SubArch )

Definition at line 565 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getLDSAllocGranule().

◆ getLDSBankCount() [1/2]

unsigned llvm::AMDGPU::getLDSBankCount ( GPUKind AK )

Returns: Number of LDS banks per compute unit.

Definition at line 520 of file AMDGPUTargetParser.cpp.

Referenced by getLDSBankCount().

◆ getLDSBankCount() [2/2]

unsigned llvm::AMDGPU::getLDSBankCount ( Triple::SubArchType SubArch )

Definition at line 525 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getLDSBankCount().

◆ getLDSEncodingGranule() [1/2]

unsigned llvm::AMDGPU::getLDSEncodingGranule ( GPUKind AK )

Returns: LDS size encoding granularity in bytes, used for program resource registers and metadata. This can differ from the allocation granularity. Returns zero if the target has no LDS encoding granularity feature.

Definition at line 569 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), and llvm::Bitset< NumBits >::test().

Referenced by EmitPALMetadataCommon(), getLDSEncodingGranule(), and getLDSEncodingGranule().

◆ getLDSEncodingGranule() [2/2]

unsigned llvm::AMDGPU::getLDSEncodingGranule ( Triple::SubArchType SubArch )

Definition at line 585 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getLDSEncodingGranule().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion & Version )

Returns: Lgkmcnt bit mask for given isa Version.

Definition at line 1683 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getLitValue()

int64_t llvm::AMDGPU::getLitValue ( const MCExpr * Expr )

Definition at line 767 of file AMDGPUMCExpr.cpp.

References assert(), llvm::cast(), and isLitExpr().

◆ getLoadcntBitMask()

unsigned llvm::AMDGPU::getLoadcntBitMask ( const IsaVersion & Version )

Returns: Loadcnt bit mask for given isa Version. Returns 0 for versions that do not support LOADcnt

Definition at line 1667 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getLocalMemorySize() [1/2]

unsigned llvm::AMDGPU::getLocalMemorySize	(	GPUKind	AK,
		bool	FullSIMDMode )

Returns: Total LDS in bytes available to work-groups sharing a physical block. FullSIMDMode selects full-SIMD mode (four SIMDs) when true and half-SIMD mode (two SIMDs) otherwise.

Definition at line 491 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), getMaxHWAddressableLocalMemorySize(), llvm::Size, and test.

Referenced by getAddressableLocalMemorySize(), getLocalMemorySize(), and llvm::GCNSubtarget::initializeSubtargetDependencies().

◆ getLocalMemorySize() [2/2]

unsigned llvm::AMDGPU::getLocalMemorySize	(	Triple::SubArchType	SubArch,
		bool	FullSIMDMode )

Definition at line 504 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getLocalMemorySize().

◆ getMAIIsDGEMM()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM ( unsigned Opc )

Returns true if MAI operation is a double precision GEMM.

Definition at line 584 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isDGEMM().

◆ getMAIIsGFX940XDL()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL ( unsigned Opc )

Definition at line 589 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isXDL().

◆ getMajorSubArch()

Triple::SubArchType llvm::AMDGPU::getMajorSubArch ( Triple::SubArchType SubArch )

Definition at line 187 of file AMDGPUTargetParser.cpp.

References llvm::Triple::FirstAMDGPUSubArch, llvm::Triple::LastAMDGPUSubArch, llvm::Triple::NoSubArch, and X.

Referenced by llvm::AMDGPUTargetMachine::AMDGPUTargetMachine(), computeDefaultGeneration(), llvm::GCNTargetMachine::getSubtargetImpl(), isSubArchCompatible(), mergeSubArch(), and llvm::AMDGPU::TargetID::providesFor().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp	(	unsigned	Opc,
		unsigned	NewChannels )

Definition at line 334 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::IndexedRsrc, llvm::AMDGPU::MIMGInfo::IndexedSamp, llvm::AMDGPU::MIMGInfo::MIMGEncoding, Opc, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMaxFlatWorkGroupSize()

unsigned llvm::AMDGPU::getMaxFlatWorkGroupSize ( )

constexpr

Returns: Maximum flat work group size.

Definition at line 283 of file AMDGPUTargetParser.h.

Referenced by annotateGroupSizeLoadWithRangeMD(), llvm::GCNSubtarget::getMaxFlatWorkGroupSize(), and llvm::R600Subtarget::getMaxFlatWorkGroupSize().

◆ getMaxHWAddressableLocalMemorySize() [1/2]

unsigned llvm::AMDGPU::getMaxHWAddressableLocalMemorySize ( GPUKind AK )

LDS size queries.

getMaxHWAddressableLocalMemorySize returns the architectural limit that one work-group can address. It is independent of execution mode.

getLocalMemorySize returns the LDS available to all work-groups sharing a physical block, which is the LDS capacity used to compute occupancy. In full-SIMD mode, a work-group runs on four SIMDs and the query returns the full physical block. In half-SIMD mode, it runs on two SIMDs and the query returns half the block.

getAddressableLocalMemorySize returns the amount one work-group can allocate:

min(getMaxHWAddressableLocalMemorySize(), getLocalMemorySize())

The physical LDS block belongs to a WGP on gfx10/11/12 and to a CU otherwise. On gfx6 and gfx10/11/12, the block is twice the address limit, so a work-group cannot address the entire block in full-SIMD mode.

The mode columns below show local/addressable LDS, in KiB:

GPU address limit full-SIMD half-SIMD gfx600 32 64/32 n/a (always full-SIMD) gfx900 64 64/64 n/a (always full-SIMD) gfx1030 64 128/64 64/64 gfx1250 320 320/320 n/a (always full-SIMD)

Returns: Maximum LDS in bytes a single work-group can address.

Definition at line 481 of file AMDGPUTargetParser.cpp.

Referenced by getAddressableLocalMemorySize(), getLocalMemorySize(), and getMaxHWAddressableLocalMemorySize().

◆ getMaxHWAddressableLocalMemorySize() [2/2]

unsigned llvm::AMDGPU::getMaxHWAddressableLocalMemorySize ( Triple::SubArchType SubArch )

Definition at line 487 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getMaxHWAddressableLocalMemorySize().

◆ getMaxNumUserSGPRs()

unsigned llvm::AMDGPU::getMaxNumUserSGPRs ( const MCSubtargetInfo & STI )

Definition at line 2420 of file AMDGPUBaseInfo.cpp.

References isGFX1250Plus().

Referenced by llvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(), getComputePGMRSrc2Reg(), llvm::GCNSubtarget::getMaxNumUserSGPRs(), and llvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().

◆ getMaxNumWorkGroups()

SmallVector< unsigned > llvm::AMDGPU::getMaxNumWorkGroups ( const Function & F )

Returns: The maximum number of workgroups for the function.

Definition at line 1633 of file AMDGPUBaseInfo.cpp.

References F, and getIntegerVecAttribute().

Referenced by llvm::GCNTTIImpl::collectKernelLaunchBounds(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getMaxWavesPerEU() [1/2]

unsigned llvm::AMDGPU::getMaxWavesPerEU ( GPUKind AK )

Returns: Maximum number of waves per execution unit without any kind of limitation.

Definition at line 589 of file AMDGPUTargetParser.cpp.

Referenced by getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumVGPRs(), llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs(), and llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs().

◆ getMaxWavesPerEU() [2/2]

unsigned llvm::AMDGPU::getMaxWavesPerEU ( Triple::SubArchType SubArch )

Definition at line 594 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getMaxWavesPerEU().

◆ getMCOpcode()

LLVM_READONLY int32_t llvm::AMDGPU::getMCOpcode	(	uint32_t	Opcode,
		unsigned	Gen )

Definition at line 865 of file AMDGPUBaseInfo.cpp.

References Subtarget.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

MCRegister llvm::AMDGPU::getMCReg	(	MCRegister	Reg,
		const MCSubtargetInfo &	STI )

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 2667 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, llvm::Triple::r600, and Reg.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and llvm::AMDGPUMCInstLower::lowerOperand().

◆ getMFMA_F8F6F4_WithFormatArgs()

LLVM_READONLY const MFMA_F8F6F4_Info * llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs	(	unsigned	CBSZ,
		unsigned	BLGP,
		unsigned	F8F8Opcode )

Definition at line 620 of file AMDGPUBaseInfo.cpp.

References mfmaScaleF8F6F4FormatToNumRegs().

Referenced by llvm::AMDGPUDisassembler::convertMAIInst().

◆ getMFMACoExecInfo()

llvm::AMDGPU::CoExecInfo llvm::AMDGPU::getMFMACoExecInfo ( unsigned Opcode )

Get co-execution info for a gfx950 MFMA instruction.

The occupancy (cycles until the next MFMA may issue) is expressed as the first stage carrying the WMMA bit.

Definition at line 65 of file AMDGPUCoExecSchedStrategy.cpp.

References allowCoExec(), llvm::AMDGPU::CoExecInfo::build(), DS, I, llvm::AMDGPU::CoExecSlotInfo::Mask, MaxCoExecStages, None, llvm::AMDGPU::CoExecInfo::Pattern, SALU, llvm::AMDGPU::CoExecInfo::Slots, llvm::AMDGPU::CoExecInfo::TotalWindow, VALU, VMEM, and WMMA.

Referenced by getCoExecInfo().

◆ getMFMAEarlyClobberOp()

LLVM_READONLY int32_t llvm::AMDGPU::getMFMAEarlyClobberOp ( uint32_t Opcode )

Returns: earlyclobber version of a MAC MFMA is exists.

References LLVM_READONLY.

Referenced by getMFMANonMacAGPRFormOp(), and llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMIMGBaseOpcode()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode ( unsigned Opc )

Definition at line 329 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Opc.

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned BaseOpcode )

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), getSimplifiedVMEMEventsFor(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), simplifyAMDGCNImageIntrinsic(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGBiasMappingInfo()

LLVM_READONLY const MIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo ( unsigned Bias )

References LLVM_READONLY.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo ( unsigned DimEnum )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfoByAsmSuffix()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef AsmSuffix )

◆ getMIMGDimInfoByEncoding()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t DimEnc )

References LLVM_READONLY.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGDimInfoStr()

LLVM_READONLY StringRef llvm::AMDGPU::getMIMGDimInfoStr ( StringTable::Offset )

References LLVM_READONLY.

◆ getMIMGG16MappingInfo()

LLVM_READONLY const MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo ( unsigned G )

References G, LLVM_READONLY, and Opc.

◆ getMIMGInfo()

LLVM_READONLY const MIMGInfo * llvm::AMDGPU::getMIMGInfo ( unsigned Opc )

References LLVM_READONLY, and Opc.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), getSimplifiedVMEMEventsFor(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned L )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGMIPMappingInfo()

LLVM_READONLY const MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned MIP )

References LLVM_READONLY.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOffsetMappingInfo()

LLVM_READONLY const MIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo ( unsigned Offset )

References LLVM_READONLY, and llvm::Offset.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode	(	unsigned	BaseOpcode,
		unsigned	MIMGEncoding,
		unsigned	VDataDwords,
		unsigned	VAddrDwords,
		bool	IndexedRsrc,
		bool	IndexedSamp )

Definition at line 320 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

◆ getMinFlatWorkGroupSize()

unsigned llvm::AMDGPU::getMinFlatWorkGroupSize ( )

constexpr

Returns: Minimum flat work group size.

Definition at line 280 of file AMDGPUTargetParser.h.

Referenced by llvm::GCNSubtarget::getMinFlatWorkGroupSize(), and llvm::R600Subtarget::getMinFlatWorkGroupSize().

◆ getMinRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getMinRedzoneSizeForGlobal ( int AsanScale )

static

Definition at line 24 of file AMDGPUAsanInstrumentation.cpp.

References getRedzoneSizeForScale().

Referenced by getRedzoneSizeForGlobal().

◆ getMinWavesPerEU()

unsigned llvm::AMDGPU::getMinWavesPerEU ( )

constexpr

Returns: Minimum number of waves per execution unit.

Definition at line 266 of file AMDGPUTargetParser.h.

Referenced by llvm::GCNSubtarget::getMinWavesPerEU(), and llvm::R600Subtarget::getMinWavesPerEU().

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode ( unsigned Opc )

Definition at line 490 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements ( unsigned Opc )

Definition at line 501 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset ( unsigned Opc )

Definition at line 516 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc ( unsigned Opc )

Definition at line 511 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr ( unsigned Opc )

Definition at line 506 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements )

Definition at line 495 of file AMDGPUBaseInfo.cpp.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned Opc )

Definition at line 521 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements ( unsigned Opc )

Definition at line 532 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned Opc )

Definition at line 547 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned Opc )

Definition at line 542 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned Opc )

Definition at line 537 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv ( unsigned Opc )

Definition at line 552 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getEventsForImpl().

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements )

Definition at line 526 of file AMDGPUBaseInfo.cpp.

◆ getMUBUFTfe()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFTfe ( unsigned Opc )

Definition at line 557 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SITargetLowering::AddMemOpInit().

◆ getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition ( unsigned COV )

Returns: The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line 262 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

◆ getNameFromOperandTable()

template<size_t N>

StringRef llvm::AMDGPU::getNameFromOperandTable	(	const CustomOperand(&)	Table[N],
		unsigned	Encoding,
		const MCSubtargetInfo &	STI )

static

Map from the encoding of a sendmsg/hwreg asm operand to it's name.

Definition at line 25 of file AMDGPUAsmUtils.cpp.

References llvm::First, N, and llvm::Table.

Referenced by llvm::AMDGPU::Hwreg::getHwreg(), llvm::AMDGPU::SendMsg::getMsgName(), llvm::AMDGPU::SendMsg::getMsgOpName(), and llvm::AMDGPU::WaitEvent::getWaitEventMaskName().

◆ getNSAMaxSize()

unsigned llvm::AMDGPU::getNSAMaxSize	(	const MCSubtargetInfo &	STI,
		bool	HasSampler )

Definition at line 2409 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getCPU(), getIsaVersion(), and llvm::Version.

Referenced by llvm::GCNSubtarget::getNSAMaxSize().

◆ getNullPointerValue()

int64_t llvm::AMDGPU::getNullPointerValue ( unsigned AS )

constexpr

Get the null pointer value for the given address space.

Definition at line 198 of file AMDGPUAddrSpace.h.

Referenced by isKnownNonNull(), isKnownNonNull(), isPtrKnownNeverNull(), and llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits ( const MCSubtargetInfo & ST )

For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

Returns: The number of bits available for the signed offset field in flat instructions. Note that some forms of the instruction disallow negative offsets.

Definition at line 3337 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

◆ getNumNamedBarriersDeclared()

unsigned llvm::AMDGPU::getNumNamedBarriersDeclared	(	const DataLayout &	DL,
		const GlobalVariable &	GV )

Returns: how many named barriers are declared by GV.

Definition at line 95 of file AMDGPUMemoryUtils.cpp.

References assert(), DL, llvm::GlobalVariable::getGlobalSize(), isNamedBarrier(), and NamedBarrierTypeSizeInBytes.

Referenced by llvm::AMDGPUMachineFunctionInfo::allocateBarrierGlobal().

◆ getNumWorkGroupSIMDs()

unsigned llvm::AMDGPU::getNumWorkGroupSIMDs ( bool FullSIMDMode )

constexpr

Returns: Number of SIMDs a work-group's waves run on. All four SIMDs of the functional block in full-SIMD mode, half of them otherwise.

Definition at line 261 of file AMDGPUTargetParser.h.

Referenced by llvm::GCNSubtarget::GCNSubtarget(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), and llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize	(	const MCInstrDesc &	Desc,
		unsigned	OpNo )

inline

Definition at line 1660 of file AMDGPUBaseInfo.h.

References getOperandSize().

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo & OpInfo )

inline

Definition at line 1612 of file AMDGPUBaseInfo.h.

Referenced by getOperandSize().

◆ getPKFMACF16InlineEncoding()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getPKFMACF16InlineEncoding	(	uint32_t	Literal,
		bool	IsGFX11Plus )

Definition at line 3103 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), llvm::Hi, llvm::Literal, llvm::Lo, and llvm::Signed.

Referenced by isPKFMACF16InlineConstant().

◆ getReasonName()

StringRef llvm::AMDGPU::getReasonName ( AMDGPUSchedReason R )

inline

Definition at line 39 of file AMDGPUCoExecSchedStrategy.h.

References CritResourceBalance, CritResourceDep, llvm_unreachable, MemoryPipeline, None, NUM_REASONS, and Stall.

Referenced by llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary().

◆ getRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getRedzoneSizeForGlobal	(	int	AsanScale,
		uint64_t	SizeInBytes )

Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.

Definition at line 28 of file AMDGPUAsanInstrumentation.cpp.

References assert(), and getMinRedzoneSizeForGlobal().

◆ getRedzoneSizeForScale()

uint64_t llvm::AMDGPU::getRedzoneSizeForScale ( int AsanScale )

static

Definition at line 18 of file AMDGPUAsanInstrumentation.cpp.

Referenced by getMinRedzoneSizeForGlobal().

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass & RC )

Get the size in bits of a register from the register class RC.

Definition at line 2917 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned RCID )

Get the size in bits of a register from the register class RC.

Definition at line 2759 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), llvm::SIRegisterInfo::getRegSplitParts(), and llvm::SIInstrInfo::isLegalRegOperand().

◆ getSamplecntBitMask()

unsigned llvm::AMDGPU::getSamplecntBitMask ( const IsaVersion & Version )

Returns: Samplecnt bit mask for given isa Version. Returns 0 for versions that do not support SAMPLEcnt

Definition at line 1671 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getSchedStrategy()

StringRef llvm::AMDGPU::getSchedStrategy	(	const AMDGPUOptions &	CLOpts,
		const Function &	F )

Definition at line 444 of file AMDGPUTargetMachine.cpp.

References F, llvm::Attribute::getValueAsString(), and llvm::Attribute::isValid().

Referenced by llvm::GCNTargetMachine::createMachineScheduler(), llvm::GCNSubtarget::overrideSchedPolicy(), and useNoopPostScheduler().

◆ getSDWAOp()

LLVM_READONLY int32_t llvm::AMDGPU::getSDWAOp ( uint32_t Opcode )

References LLVM_READONLY.

◆ getSGPRAllocGranule() [1/2]

unsigned llvm::AMDGPU::getSGPRAllocGranule ( GPUKind AK )

Definition at line 412 of file AMDGPUTargetParser.cpp.

References getAddressableNumSGPRs(), getIsaVersion(), getSubArch(), and llvm::Version.

Referenced by createOccupancy(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(), and llvm::GCNSubtarget::getSGPRAllocGranule().

◆ getSGPRAllocGranule() [2/2]

unsigned llvm::AMDGPU::getSGPRAllocGranule ( Triple::SubArchType SubArch )

Definition at line 421 of file AMDGPUTargetParser.cpp.

References getAddressableNumSGPRs(), getIsaVersion(), and llvm::Version.

◆ getShiftMask()

std::pair< unsigned, unsigned > llvm::AMDGPU::getShiftMask ( unsigned Value )

constexpr

Deduce the least significant bit aligned shift and mask values for a binary Complement Value (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.

That is to say Value == ~(mask << shift)

For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from SIDefines.h, this will return the pair as (31,1).

Definition at line 27 of file SIDefinesUtils.h.

◆ getSimplifiedVMEMEventsFor()

HWEvents llvm::AMDGPU::getSimplifiedVMEMEventsFor	(	const MachineInstr &	Inst,
		const SIInstrInfo &	TII )

Parameters

Inst	A VMEM instruction (as per SIInstrInfo::isVMEM).

Returns: the simplified set of events triggered by the VMEM instruction Inst. The returned mask is not exhaustive, but is guaranteed to be a subset of the mask that'd be returned by getEventsFor.

Useful to quickly categorize VMEM instructions without having to fetch all events.

Definition at line 59 of file AMDGPUHWEvents.cpp.

References assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, getMIMGBaseOpcodeInfo(), getMIMGInfo(), llvm::MachineInstr::getOpcode(), llvm::SIInstrInfo::isAtomicNoRet(), llvm::SIInstrInfo::isFLAT(), llvm::SIInstrInfo::isImage(), llvm::SIInstrInfo::isVMEM(), llvm::SIInstrInfo::isVSAMPLE(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::SIInstrInfo::mayWriteLDSThroughDMA(), llvm::AMDGPU::MIMGBaseOpcodeInfo::MSAA, llvm::AMDGPU::MIMGBaseOpcodeInfo::Sampler, and TII.

Referenced by getEventsForImpl().

◆ getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer ( unsigned Opc )

Definition at line 562 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::isBufferInstruction(), and supportsScaleOffset().

◆ getSMRDEncodedLiteralOffset32()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset )

Returns: The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 3327 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), isDwordAligned(), and llvm::isUInt().

◆ getSMRDEncodedOffset()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset,
		bool	IsBuffer,
		bool	HasSOffset = false )

Returns: The encoding that will be used for ByteOffset in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 3298 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isGFX12Plus(), llvm::isInt(), and isLegalSMRDEncodedUnsignedOffset().

◆ getSOPKOp()

LLVM_READONLY int32_t llvm::AMDGPU::getSOPKOp ( uint32_t Opcode )

References LLVM_READONLY.

◆ getSOPPWithRelaxation()

LLVM_READONLY int32_t llvm::AMDGPU::getSOPPWithRelaxation ( uint32_t Opcode )

◆ getSpecifier()

AMDGPUMCExpr::Specifier llvm::AMDGPU::getSpecifier ( const MCSymbolRefExpr * SRE )

inlinestatic

Definition at line 150 of file AMDGPUMCExpr.h.

References llvm::MCSymbolRefExpr::getKind().

Referenced by needsPCRel().

◆ getStageTypeName()

const char * llvm::AMDGPU::getStageTypeName ( CoExecStageType T )

inline

Definition at line 175 of file AMDGPUCoExecInfo.h.

References E, E0, I, IS, llvm_unreachable, NONE, T, TR, and V.

◆ getStorecntBitMask()

unsigned llvm::AMDGPU::getStorecntBitMask ( const IsaVersion & Version )

Returns: STOREcnt or VScnt bit mask for given isa Version. returns 0 for versions that do not support STOREcnt or VScnt. STOREcnt and VScnt are the same counter, the name used depends on the ISA version.

Definition at line 1703 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getSubArch()

Triple::SubArchType llvm::AMDGPU::getSubArch ( GPUKind AK )

Definition at line 170 of file AMDGPUTargetParser.cpp.

References llvm::Triple::NoSubArch.

Referenced by llvm::AMDGPUTargetMachine::AMDGPUTargetMachine(), llvm::AMDGPUAsmPrinter::doInitialization(), getAddressableNumSGPRs(), getSGPRAllocGranule(), getSubArchFromGPUName(), llvm::GCNTargetMachine::getSubtargetImpl(), getTotalNumSGPRs(), isCPUValidForSubArch(), and llvm::AMDGPU::TargetID::providesFor().

◆ getSubArchFromGPUName()

Triple::SubArchType llvm::AMDGPU::getSubArchFromGPUName ( StringRef CPU )

Returns the preferred subarch for a GPU name CPU, or NoSubArch if unrecognized.

Definition at line 175 of file AMDGPUTargetParser.cpp.

References getSubArch(), and parseArchAMDGCN().

◆ getSubArchName()

StringRef llvm::AMDGPU::getSubArchName ( Triple::SubArchType SubArch )

Returns the triple subarch name for an AMDGPU subarch, e.g.

AMDGPUSubArch900 -> "amdgpu9.00". Returns "amdgpu" for NoSubArch.

Definition at line 289 of file AMDGPUTargetParser.cpp.

References assert(), llvm::Triple::FirstAMDGPUSubArch, llvm::Triple::LastAMDGPUSubArch, and llvm::Triple::NoSubArch.

Referenced by llvm::Triple::getArchName().

◆ getSyntheticApertureNumber()

unsigned llvm::AMDGPU::getSyntheticApertureNumber ( unsigned AS )

Definition at line 34 of file AMDGPUMemoryUtils.cpp.

References llvm::AMDGPU::SyntheticAperture::BARRIER, llvm::AMDGPUAS::BARRIER, and llvm::AMDGPU::SyntheticAperture::None.

Referenced by llvm::AMDGPULegalizerInfo::getSegmentAperture().

◆ getTargetExtType()

TargetExtType * llvm::AMDGPU::getTargetExtType ( const GlobalVariable & GV )

static

Definition at line 68 of file AMDGPUMemoryUtils.cpp.

References llvm::dyn_cast(), and llvm::GlobalValue::getValueType().

Referenced by isNamedBarrier().

◆ getTemporalHintType()

LLVM_READONLY unsigned llvm::AMDGPU::getTemporalHintType ( const MCInstrDesc TID )

Definition at line 820 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), isAsyncStore(), llvm::SIInstrFlags::isAtomic(), isTensorStore(), llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), Opc, llvm::AMDGPU::CPol::TH_TYPE_ATOMIC, llvm::AMDGPU::CPol::TH_TYPE_LOAD, and llvm::AMDGPU::CPol::TH_TYPE_STORE.

◆ getTotalNumSGPRs() [1/2]

unsigned llvm::AMDGPU::getTotalNumSGPRs ( GPUKind AK )

Definition at line 374 of file AMDGPUTargetParser.cpp.

References getIsaVersion(), getSubArch(), and llvm::Version.

Referenced by createOccupancy(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(), and llvm::GCNSubtarget::getTotalNumSGPRs().

◆ getTotalNumSGPRs() [2/2]

unsigned llvm::AMDGPU::getTotalNumSGPRs ( Triple::SubArchType SubArch )

Definition at line 381 of file AMDGPUTargetParser.cpp.

References getIsaVersion(), and llvm::Version.

◆ getTotalNumVGPRs() [1/3]

uint32_t llvm::AMDGPU::getTotalNumVGPRs	(	bool	has90AInsts,
		uint32_t	ArgNumAGPR,
		uint32_t	ArgNumVGPR )

Definition at line 2581 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo().

◆ getTotalNumVGPRs() [2/3]

unsigned llvm::AMDGPU::getTotalNumVGPRs	(	GPUKind	AK,
		bool	IsWave32 )

Returns: Number of physical VGPRs, i.e. the size of the register file a work-group's waves share. IsWave32 selects the wavefront size.

Definition at line 446 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), and llvm::Bitset< NumBits >::test().

Referenced by llvm::SIRegisterInfo::filterAndSortForAntiHintedRegs(), getAddressableNumVGPRs(), llvm::AMDGPU::IsaInfo::getMaxNumVGPRs(), llvm::AMDGPU::IsaInfo::getMinNumVGPRs(), llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs(), getTotalNumVGPRs(), and llvm::GCNSubtarget::getTotalNumVGPRs().

◆ getTotalNumVGPRs() [3/3]

unsigned llvm::AMDGPU::getTotalNumVGPRs	(	Triple::SubArchType	SubArch,
		bool	IsWave32 )

Definition at line 457 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getTotalNumVGPRs().

◆ getTransitiveUsesOfGV()

GVUsesInfoTy llvm::AMDGPU::getTransitiveUsesOfGV	(	const CallGraph &	CG,
		Module &	M,
		function_ref< bool(const GlobalVariable &)>	Filter )

Collects all uses of Global Variables in M using getUsesOfGVByFunction.

Parameters

CG	`M` Call Graph
M	Module
Filter	Filter for getUsesOfGVByFunction - only GVs for which the filter returns true will be considered.

Returns: Uses of GVs that were found within each function, sorted by direct and indirect accesses.

Definition at line 164 of file AMDGPUMemoryUtils.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy >::contains(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, llvm::Filter, getUsesOfGVByFunction(), llvm::detail::DenseSetImpl< ValueT, MapTy >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert(), isKernel(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::set_union().

Referenced by getTransitiveUsesOfLDSForLowering().

◆ getTransitiveUsesOfLDSForLowering()

GVUsesInfoTy llvm::AMDGPU::getTransitiveUsesOfLDSForLowering	(	const CallGraph &	CG,
		Module &	M )

Collects all uses of LDS Global Variables in M using getUsesOfGVByFunction, with isLDSVariableToLower as the filter.

Parameters

CG	`M` Call Graph
M	Module

Returns: Uses of LDS GVs that need lowering that were found within each function, sorted by direct and indirect accesses.

Definition at line 296 of file AMDGPUMemoryUtils.cpp.

References llvm::MapVector< KeyT, ValueT, MapType, VectorType, N >::contains(), llvm::AMDGPU::GVUsesInfoTy::DirectAccess, getTransitiveUsesOfGV(), llvm::AMDGPU::GVUsesInfoTy::IndirectAccess, isDynamicLDS(), isLDSVariableToLower(), and llvm::reportFatalUsageError().

◆ getUsesOfGVByFunction()

void llvm::AMDGPU::getUsesOfGVByFunction	(	const CallGraph &	CG,
		Module &	M,
		function_ref< bool(const GlobalVariable &)>	Filter,
		FunctionVariableMap &	Kernels,
		FunctionVariableMap &	Functions )

Finds uses of Global Variables on a per-function basis.

Parameters

CG	`M` Call Graph
M	Module
Filter	Function that returns true for GVs that need to be considered.
Kernels[out]	Maps kernels to global variables used by that kernel.
Functions[out]	Maps functions to global variables used by that function.

Definition at line 142 of file AMDGPUMemoryUtils.cpp.

References llvm::dyn_cast(), F, llvm::Filter, I, isKernel(), and V.

Referenced by getTransitiveUsesOfGV().

◆ getVCMPXOpFromVCMP()

LLVM_READONLY int32_t llvm::AMDGPU::getVCMPXOpFromVCMP ( uint32_t Opcode )

Returns: v_cmpx version of a v_cmp instruction.

◆ getVGPRAllocGranule() [1/2]

unsigned llvm::AMDGPU::getVGPRAllocGranule	(	GPUKind	AK,
		bool	IsWave32 )

Returns: VGPR allocation granularity for AK, in registers. IsWave32 selects the wavefront size, which is a per-kernel mode rather than a property of the GPU. This does not account for dynamic VGPR mode, where the block size chosen by the caller is the granule.

Definition at line 430 of file AMDGPUTargetParser.cpp.

References getFeatureBitset(), and llvm::Bitset< NumBits >::test().

Referenced by getVGPRAllocGranule(), and isVOPD3F64OPYSrcHazard().

◆ getVGPRAllocGranule() [2/2]

unsigned llvm::AMDGPU::getVGPRAllocGranule	(	Triple::SubArchType	SubArch,
		bool	IsWave32 )

Definition at line 441 of file AMDGPUTargetParser.cpp.

References getGPUKindFromSubArch(), and getVGPRAllocGranule().

◆ getVGPREncodingMSBs()

unsigned llvm::AMDGPU::getVGPREncodingMSBs	(	MCRegister	Reg,
		const MCRegisterInfo &	MRI )

Returns: the MODE bits which have to be set by the S_SET_VGPR_MSB for the physical register Reg.

Definition at line 3458 of file AMDGPUBaseInfo.cpp.

References Idx, MRI, Reg, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by llvm::AMDGPU::VOPD::InstInfo::getInvalidCompOperandIndex().

◆ getVGPRLoweringOperandTables()

std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > llvm::AMDGPU::getVGPRLoweringOperandTables ( const MCInstrDesc & Desc )

Definition at line 3522 of file AMDGPUBaseInfo.cpp.

References assert(), getVOPDComponents(), llvm::SIInstrFlags::isBuffer(), llvm::SIInstrFlags::isDPP(), llvm::SIInstrFlags::isDS(), llvm::SIInstrFlags::isEXP(), llvm::SIInstrFlags::isFLAT(), llvm::SIInstrFlags::isMIMG(), llvm::SIInstrFlags::isVIMAGE(), llvm::SIInstrFlags::isVOP1(), llvm::SIInstrFlags::isVOP2(), llvm::SIInstrFlags::isVOP3Like(), llvm::SIInstrFlags::isVOPC(), isVOPD(), llvm::SIInstrFlags::isVSAMPLE(), and llvm_unreachable.

Referenced by getRegFromMIA().

◆ getVGPRPhysRegClass()

const MCRegisterClass * llvm::AMDGPU::getVGPRPhysRegClass	(	MCRegister	Reg,
		const MCRegisterInfo &	MRI )

Returns: a register class for the physical register Reg if it is a VGPR or nullptr otherwise.

Definition at line 3437 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), MRI, and Reg.

Referenced by getRegForPrinting(), and getVGPRWithMSBs().

◆ getVGPRWithMSBs()

MCRegister llvm::AMDGPU::getVGPRWithMSBs	(	MCRegister	Reg,
		unsigned	MSBs,
		const MCRegisterInfo &	MRI )

If Reg is a low VGPR return a corresponding high VGPR with MSBs set.

Definition at line 3464 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), llvm::MCRegisterClass::getRegister(), getVGPRPhysRegClass(), Idx, llvm::AMDGPU::HWEncoding::IS_HI16, MRI, Reg, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by getRegFromMIA().

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion & Version )

Returns: Vmcnt bit mask for given isa Version.

Definition at line 1661 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle ( unsigned Opc )

Definition at line 566 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle ( unsigned Opc )

Definition at line 570 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle ( unsigned Opc )

Definition at line 574 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOPDComponents()

LLVM_READONLY std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents ( unsigned VOPDOpcode )

Definition at line 894 of file AMDGPUBaseInfo.cpp.

References assert().

Referenced by getVGPRLoweringOperandTables(), and getVOPDInstInfo().

◆ getVOPDEncodingFamily()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDEncodingFamily ( const MCSubtargetInfo & ST )

Returns: SIEncodingFamily used for VOPD encoding on a ST.

Definition at line 682 of file AMDGPUBaseInfo.cpp.

References llvm::SIEncodingFamily::GFX11, llvm::SIEncodingFamily::GFX1170, llvm::SIEncodingFamily::GFX12, llvm::SIEncodingFamily::GFX1250, llvm::SIEncodingFamily::GFX13, and llvm_unreachable.

Referenced by checkVOPDRegConstraints(), shouldScheduleVOPDAdjacent(), and llvm::tryMatchVOPDPair().

◆ getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull	(	unsigned	OpX,
		unsigned	OpY,
		unsigned	EncodingFamily,
		bool	VOPD3 )

Definition at line 884 of file AMDGPUBaseInfo.cpp.

References getBitOp2().

Referenced by checkVOPDRegConstraints().

◆ getVOPDInstInfo() [1/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	const MCInstrDesc &	OpX,
		const MCInstrDesc &	OpY )

Definition at line 1072 of file AMDGPUBaseInfo.cpp.

Referenced by checkVOPDRegConstraints().

◆ getVOPDInstInfo() [2/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	unsigned	VOPDOpcode,
		const MCInstrInfo *	InstrInfo )

Definition at line 1076 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::VOPD::COMPONENT_X, getVOPDComponents(), and llvm::SIInstrFlags::isVOPD3().

◆ getVOPDOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode	(	unsigned	Opc,
		bool	VOPD3 )

Definition at line 712 of file AMDGPUBaseInfo.cpp.

References getBitOp2(), and Opc.

Referenced by checkVOPDRegConstraints().

◆ getVOPe32()

LLVM_READONLY int32_t llvm::AMDGPU::getVOPe32 ( uint32_t Opcode )

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::hasVALU32BitEncoding(), and isVCmp().

◆ getVOPe64()

LLVM_READONLY int32_t llvm::AMDGPU::getVOPe64 ( uint32_t Opcode )

References LLVM_READONLY.

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion & Version )

Returns: Waitcnt bit mask for given isa Version.

Definition at line 1711 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ getWMMA_F8F6F4_WithFormatArgs()

LLVM_READONLY const MFMA_F8F6F4_Info * llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs	(	unsigned	FmtA,
		unsigned	FmtB,
		unsigned	F8F8Opcode )

Definition at line 643 of file AMDGPUBaseInfo.cpp.

References wmmaScaleF8F6F4FormatToNumRegs().

Referenced by llvm::AMDGPUDisassembler::convertWMMAInst().

◆ getWMMAIsXDL()

LLVM_READONLY bool llvm::AMDGPU::getWMMAIsXDL ( unsigned Opc )

Definition at line 594 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isXDLWMMA().

◆ getWMMAMatrixFmts()

template<typename InstT>

std::pair< unsigned, unsigned > llvm::AMDGPU::getWMMAMatrixFmts ( const InstT & MI )

Returns: the matrix_a_fmt and matrix_b_fmt operands of an f8f6f4 WMMA. Works on both MCInst and MachineInstr.

Definition at line 596 of file AMDGPUBaseInfo.h.

References assert(), llvm::getImm(), MI, and Opc.

Referenced by isWMMAAnyF8(), and isWMMABothF4().

◆ getXcntBitMask()

unsigned llvm::AMDGPU::getXcntBitMask ( const IsaVersion & Version )

Returns: Xcnt bit mask for given isa Version. Returns 0 for versions that do not support Xcnt.

Definition at line 1695 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ hasA16()

bool llvm::AMDGPU::hasA16 ( const MCSubtargetInfo & STI )

Definition at line 2392 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasAny64BitVGPROperands()

bool llvm::AMDGPU::hasAny64BitVGPROperands	(	const MCInstrDesc &	OpDesc,
		const MCInstrInfo &	MII,
		const MCSubtargetInfo &	ST )

static

Definition at line 3631 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), llvm::MCInstrInfo::getOpRegClassID(), llvm::MCSubtargetInfo::HwMode_RegInfo, Idx, and llvm::MCInstrDesc::operands().

Referenced by isDPALU_DPP().

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch ( const MCSubtargetInfo & STI )

Definition at line 2561 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ hasDPPSrc1SGPR()

bool llvm::AMDGPU::hasDPPSrc1SGPR ( const MCSubtargetInfo & STI )

Definition at line 2573 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasG16()

bool llvm::AMDGPU::hasG16 ( const MCSubtargetInfo & STI )

Definition at line 2396 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasGDS()

bool llvm::AMDGPU::hasGDS ( const MCSubtargetInfo & STI )

Definition at line 2405 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts ( const MCSubtargetInfo & STI )

Definition at line 2545 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ hasKernargPreload()

unsigned llvm::AMDGPU::hasKernargPreload ( const MCSubtargetInfo & STI )

Definition at line 2577 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUDisassembler::hasKernargPreload().

◆ hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts ( const MCSubtargetInfo & STI )

Definition at line 2565 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo & STI )

Definition at line 2387 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasNamedOperand()

LLVM_READONLY bool llvm::AMDGPU::hasNamedOperand	(	uint32_t	Opcode,
		OpName	NamedIdx )

inline

Definition at line 349 of file AMDGPUBaseInfo.h.

◆ hasNoOpSelHi()

LLVM_READONLY bool llvm::AMDGPU::hasNoOpSelHi ( unsigned Opc )

Returns true if this VOP3P opcode has no op_sel_hi field, in which case those bits are encoded as zero instead of defaulting to one.

Definition at line 837 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo & STI )

Definition at line 2400 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isCI(), and isSI().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasPopsExitingWaveID()

bool llvm::AMDGPU::hasPopsExitingWaveID ( const MCSubtargetInfo & STI )

Definition at line 2464 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeSpecialReg32(), and llvm::AMDGPUDisassembler::decodeSpecialReg64().

◆ hasPrivateApertureRegs()

bool llvm::AMDGPU::hasPrivateApertureRegs ( const MCSubtargetInfo & STI )

Returns: true if the src_private_base and src_private_limit aperture registers are available on STI. Targets with globally addressable scratch have no private aperture and expose src_flat_scratch_base instead.

Definition at line 2468 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeSpecialReg32(), and llvm::AMDGPUDisassembler::decodeSpecialReg64().

◆ hasSMEMByteOffset()

bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo & ST )

static

Definition at line 3261 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), and isGFX10Plus().

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().

◆ hasSMRDSignedImmOffset()

bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo & ST )

Returns: true if the target supports signed immediate offset for SMRD instructions.

Definition at line 210 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

◆ hasValueInRangeLikeMetadata()

bool llvm::AMDGPU::hasValueInRangeLikeMetadata	(	const MDNode &	MD,
		int64_t	Val )

Checks if Val is inside MD, a !range-like metadata.

Definition at line 1638 of file AMDGPUBaseInfo.cpp.

References assert(), E, llvm::mdconst::extract(), llvm::MDNode::getNumOperands(), llvm::MDNode::getOperand(), High, I, and llvm::Low.

Referenced by flatInstrMayAccessPrivate().

◆ hasVOPD()

bool llvm::AMDGPU::hasVOPD ( const MCSubtargetInfo & STI )

Definition at line 2569 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT	(	AMDGPUMCKernelCodeT &	KernelCode,
		const MCSubtargetInfo &	STI )

Definition at line 1465 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::AMDGPUMCKernelCodeT::initDefault().

◆ inst_counter_types()

iota_range< InstCounterType > llvm::AMDGPU::inst_counter_types ( InstCounterType MaxCounter )

Definition at line 24 of file AMDGPUWaitcntUtils.cpp.

References llvm::enum_seq(), and LOAD_CNT.

Referenced by llvm::AMDGPU::Waitcnt::combined(), llvm::AMDGPU::Waitcnt::hasWaitExceptStoreCnt(), and llvm::AMDGPU::Waitcnt::print().

◆ instrumentAddress()

void llvm::AMDGPU::instrumentAddress	(	Module &	M,
		IRBuilder<> &	IRB,
		Instruction *	OrigIns,
		Instruction *	InsertBefore,
		Value *	Addr,
		Align	Alignment,
		TypeSize	TypeStoreSize,
		bool	IsWrite,
		Value *	SizeArgument,
		bool	UseCalls,
		bool	Recover,
		int	Scale,
		int	Offset )

Instrument the memory operand Addr.

Generates report blocks that catch the addressing errors.

Definition at line 183 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateIntToPtr(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreatePtrToInt(), llvm::IRBuilderBase::CreateTypeSize(), llvm::Constant::getAllOnesValue(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::Value::getType(), instrumentAddressImpl(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::IRBuilderBase::SetInsertPoint(), and llvm::Size.

◆ instrumentAddressImpl()

void llvm::AMDGPU::instrumentAddressImpl	(	Module &	M,
		IRBuilder<> &	IRB,
		Instruction *	OrigIns,
		Instruction *	InsertBefore,
		Value *	Addr,
		Align	Alignment,
		uint32_t	TypeStoreSize,
		bool	IsWrite,
		Value *	SizeArgument,
		bool	UseCalls,
		bool	Recover,
		int	AsanScale,
		int	AsanOffset )

static

◆ isAnyPtr()

bool llvm::AMDGPU::isAnyPtr	(	LLT	Ty,
		unsigned	Width )

Returns: true if Ty is a pointer type with size Width.

Definition at line 30 of file AMDGPURegBankLegalizeRules.cpp.

Referenced by LLTToBId(), and matchUniformityAndLLT().

◆ isArgPassedInSGPR() [1/2]

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument * A )

◆ isArgPassedInSGPR() [2/2]

bool llvm::AMDGPU::isArgPassedInSGPR	(	const CallBase *	CB,
		unsigned	ArgNo )

Definition at line 3235 of file AMDGPUBaseInfo.cpp.

◆ isAsyncStore()

LLVM_READONLY bool llvm::AMDGPU::isAsyncStore ( unsigned Opc )

Definition at line 804 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getTemporalHintType().

◆ isBF16SrcOperand()

bool llvm::AMDGPU::isBF16SrcOperand ( const MCOperandInfo & OpInfo )

constexpr

Is this a scalar (i.e. not packed) bf16 source operand?

Definition at line 1594 of file AMDGPUBaseInfo.h.

References OPERAND_REG_IMM_BF16, and OPERAND_REG_INLINE_C_BF16.

◆ isChainCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isChainCC ( CallingConv::ID CC )

constexpr

Definition at line 1437 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, and CC.

Referenced by llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::MCResourceInfo::gatherResourceInfo(), getCallOpcode(), llvm::AMDGPUFunctionArgInfo::getPrivateSegmentBufferReg(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::SITargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerTailCall(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo & STI )

Definition at line 2430 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().

◆ isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction	(	const LoadInst *	Load,
		MemorySSA *	MSSA,
		AAResults *	AA )

Check is a Load is clobbered in its function.

Definition at line 419 of file AMDGPUMemoryUtils.cpp.

References llvm::cast(), llvm::dbgs(), Def, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), LLVM_DEBUG, llvm::Load, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ isCompute()

LLVM_READNONE constexpr bool llvm::AMDGPU::isCompute ( CallingConv::ID CC )

constexpr

Definition at line 1414 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS, CC, and isGraphics().

Referenced by EmitPALMetadataCommon(), llvm::SIProgramInfo::getPGMRSrc1(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::SIFrameLowering::mayReserveScratchForCWSR(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

◆ isConstantAddressSpace()

bool llvm::AMDGPU::isConstantAddressSpace ( unsigned AS )

inline

Definition at line 125 of file AMDGPUAddrSpace.h.

◆ isCPUValidForSubArch() [1/2]

bool llvm::AMDGPU::isCPUValidForSubArch	(	Triple::SubArchType	SubArch,
		GPUKind	AK )

Return true if the GPU AK is usable with the triple subarch SubArch.

A NoSubArch triple (legacy "amdgcn") accepts any GPU. Otherwise the GPU's subarch must equal SubArch, or SubArch must be the major-family subarch of the GPU (e.g. the amdgpu9 triple accepts gfx900).

Definition at line 209 of file AMDGPUTargetParser.cpp.

References getSubArch(), GK_NONE, isSubArchCompatible(), and llvm::Triple::NoSubArch.

Referenced by fillValidArchListAMDGCN(), isCPUValidForSubArch(), and llvm::AMDGPU::TargetID::parse().

◆ isCPUValidForSubArch() [2/2]

bool llvm::AMDGPU::isCPUValidForSubArch	(	Triple::SubArchType	SubArch,
		StringRef	CPU )

Convenience overload of isCPUValidForSubArch taking a GPU name CPU, which is parsed via parseArchAMDGCN.

An unrecognized name is never valid.

Definition at line 225 of file AMDGPUTargetParser.cpp.

References isCPUValidForSubArch(), and parseArchAMDGCN().

◆ isCvt_F32_Fp8_Bf8_e64()

LLVM_READNONE bool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 ( unsigned Opc )

Definition at line 769 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isDPALU_DPP()

bool llvm::AMDGPU::isDPALU_DPP	(	const MCInstrDesc &	OpDesc,
		const MCInstrInfo &	MII,
		const MCSubtargetInfo &	ST )

Returns: true if an instruction is a DP ALU DPP.

Definition at line 3670 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), hasAny64BitVGPROperands(), and isDPALU_DPP32BitOpc().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ isDPALU_DPP32BitOpc()

bool llvm::AMDGPU::isDPALU_DPP32BitOpc ( unsigned Opc )

Returns: true if an instruction is a DP ALU DPP without any 64-bit operands.

Definition at line 3650 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by isDPALU_DPP().

◆ isDPMACCInstruction()

bool llvm::AMDGPU::isDPMACCInstruction ( unsigned Opc )

Definition at line 853 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getExpertSchedulingEventType(), and llvm::SIInstrInfo::isVOPDAntidependencyAllowed().

◆ isDwordAligned()

bool llvm::AMDGPU::isDwordAligned ( uint64_t ByteOffset )

static

Definition at line 3285 of file AMDGPUBaseInfo.cpp.

References uint64_t.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ isDynamicLDS()

bool llvm::AMDGPU::isDynamicLDS ( const GlobalVariable & GV )

Definition at line 103 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::GlobalVariable::getGlobalSize(), llvm::GlobalValue::getParent(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by getTransitiveUsesOfLDSForLowering(), and isLDSVariableToLower().

◆ isEntryFunctionCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID CC )

constexpr

Definition at line 1419 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::MCResourceInfo::gatherResourceInfo(), llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), llvm::GCNSubtarget::getMaxNumVGPRs(), isModuleEntryFunctionCC(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), llvm::SIFrameLowering::mayReserveScratchForCWSR(), mustPreserveGV(), and recursivelyVisitUsers().

◆ isExpertSchedulingMode()

bool llvm::AMDGPU::isExpertSchedulingMode	(	const GCNSubtarget &	ST,
		const Function &	F )

Return whether expert scheduling mode is available and enabled for F.

Definition at line 17 of file AMDGPUWaitcntUtils.cpp.

References F, and llvm::valueOr().

◆ isExtendedGlobalAddrSpace()

bool llvm::AMDGPU::isExtendedGlobalAddrSpace ( unsigned AS )

inline

Definition at line 119 of file AMDGPUAddrSpace.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::GCNTTIImpl::getMemoryOpCost(), llvm::GCNTTIImpl::getScalingFactorCost(), llvm::SITargetLowering::lowerPREFETCH(), llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), and llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned AS )

inline

Definition at line 114 of file AMDGPUAddrSpace.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::SITargetLowering::shouldExpandAtomicRMWInIR(), llvm::GCNTTIImpl::shouldPrefetchAddressSpace(), and llvm::verifyAMDGPUIntrinsicCall().

◆ isFullSIMDMode()

bool llvm::AMDGPU::isFullSIMDMode ( const MCSubtargetInfo & STI )

Returns: true if a work-group's waves run on all four SIMD32s (one contiguous LDS) and not just on two.

Definition at line 2507 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), isGFX1250(), and llvm::FeatureBitset::test().

Referenced by llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), and llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo & STI )

Definition at line 2537 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by hasSMEMByteOffset().

◆ isGenericAtomic()

LLVM_READNONE bool llvm::AMDGPU::isGenericAtomic ( unsigned Opc )

Definition at line 782 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo & STI )

Definition at line 2473 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by getGcnBufferFormatInfo(), getGcnBufferFormatInfo(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10_GFX11(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().

◆ isGFX10_3_GFX11()

bool llvm::AMDGPU::isGFX10_3_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2549 of file AMDGPUBaseInfo.cpp.

References isGFX10_BEncoding(), and isGFX12Plus().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding ( const MCSubtargetInfo & STI )

Definition at line 2541 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_3_GFX11(), and isGFX10Before1030().

◆ isGFX10_GFX11()

bool llvm::AMDGPU::isGFX10_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2477 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11().

◆ isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030 ( const MCSubtargetInfo & STI )

Definition at line 2533 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX10_BEncoding().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus ( const MCSubtargetInfo & STI )

Definition at line 2481 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by createAMDGPUMCSubtargetInfo(), llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), hasSMEMByteOffset(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding(), supportsWGP(), and llvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX11()

bool llvm::AMDGPU::isGFX11 ( const MCSubtargetInfo & STI )

Definition at line 2485 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_GFX11(), isGFX11Plus(), isGFX9_GFX10_GFX11(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

◆ isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus ( const MCSubtargetInfo & STI )

◆ isGFX12()

bool llvm::AMDGPU::isGFX12 ( const MCSubtargetInfo & STI )

Definition at line 2493 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX12Plus(), and isLegalDPALU_DPPControl().

◆ isGFX1250()

bool llvm::AMDGPU::isGFX1250 ( const MCSubtargetInfo & STI )

Definition at line 2503 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and isGFX13().

Referenced by isFullSIMDMode(), llvm::AMDGPUDisassembler::isGFX1250(), llvm::SIInstrInfo::isVAVDSTOrderedXDL(), and supportsWGP().

◆ isGFX1250Plus()

bool llvm::AMDGPU::isGFX1250Plus ( const MCSubtargetInfo & STI )

Definition at line 2511 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), getMaxNumUserSGPRs(), and llvm::AMDGPUDisassembler::isGFX1250Plus().

◆ isGFX12Plus()

bool llvm::AMDGPU::isGFX12Plus ( const MCSubtargetInfo & STI )

Definition at line 2497 of file AMDGPUBaseInfo.cpp.

References isGFX12(), and isGFX13Plus().

Referenced by llvm::SIInstrInfo::allowNegativeFlatOffset(), getInstPrefSizeFieldWidth(), getSMRDEncodedOffset(), isGFX10_3_GFX11(), isGFX11Plus(), llvm::AMDGPUDisassembler::isGFX12Plus(), isLegalSMRDEncodedSignedOffset(), isLegalSMRDEncodedUnsignedOffset(), isNotGFX12Plus(), llvm::SIInstrInfo::isXDL(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

◆ isGFX13()

bool llvm::AMDGPU::isGFX13 ( const MCSubtargetInfo & STI )

Definition at line 2515 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX1250(), llvm::AMDGPUDisassembler::isGFX13(), and isGFX13Plus().

◆ isGFX13Plus()

bool llvm::AMDGPU::isGFX13Plus ( const MCSubtargetInfo & STI )

Definition at line 2519 of file AMDGPUBaseInfo.cpp.

References isGFX13().

Referenced by isGFX12Plus(), llvm::AMDGPUDisassembler::isGFX13Plus(), and llvm::AMDGPU::Exp::isSupportedTgtId().

◆ isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10 ( const MCSubtargetInfo & STI )

Definition at line 2450 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX9(), and isVI().

◆ isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus ( const MCSubtargetInfo & STI )

Definition at line 2454 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and isVI().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo & STI )

Definition at line 2438 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), isGFX9Plus(), and isNotGFX10Plus().

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A ( const MCSubtargetInfo & STI )

Definition at line 2553 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), and isLegalDPALU_DPPControl().

◆ isGFX940()

bool llvm::AMDGPU::isGFX940 ( const MCSubtargetInfo & STI )

Definition at line 2557 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10 ( const MCSubtargetInfo & STI )

Definition at line 2442 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX9().

◆ isGFX9_GFX10_GFX11()

bool llvm::AMDGPU::isGFX9_GFX10_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2446 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX11(), and isGFX9().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus ( const MCSubtargetInfo & STI )

Definition at line 2458 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX9().

Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), llvm::AMDGPUDisassembler::isGFX9Plus(), isNotGFX9Plus(), and llvm::AMDGPUInstPrinter::printSwizzle().

◆ isGraphics()

LLVM_READNONE constexpr bool llvm::AMDGPU::isGraphics ( CallingConv::ID CC )

constexpr

Definition at line 1408 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, CC, and isShader().

Referenced by llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isHi16Reg()

bool llvm::AMDGPU::isHi16Reg	(	MCRegister	Reg,
		const MCRegisterInfo &	MRI )

Returns: if Reg occupies the high 16-bits of a 32-bit register.

Definition at line 2600 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::HWEncoding::IS_HI16, MRI, and Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::getRegAllocationHints(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::AMDGPUMCInstLower::lowerT16FmaMixFP16(), and llvm::SIRegisterInfo::SIRegisterInfo().

◆ isHsaAbi()

bool llvm::AMDGPU::isHsaAbi ( const MCSubtargetInfo & STI )

Returns: True if STI is AMDHSA.

Definition at line 215 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::Triple::getOS(), and llvm::MCSubtargetInfo::getTargetTriple().

◆ isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t Literal )

inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line 1667 of file AMDGPUBaseInfo.h.

References llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isInlinableLiteral32(), isInlinableLiteral64(), isInlinableLiteralBF16(), isInlinableLiteralFP16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32	(	int32_t	Literal,
		bool	HasInv2Pi )

Definition at line 2938 of file AMDGPUBaseInfo.cpp.

References llvm::bit_cast(), isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), isInlinableLiteralI16(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isLegalAV64PseudoImm().

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64	(	int64_t	Literal,
		bool	HasInv2Pi )

Is this literal inlinable.

Definition at line 2921 of file AMDGPUBaseInfo.cpp.

References llvm::bit_cast(), isInlinableIntLiteral(), llvm::Literal, and uint64_t.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteral64Constant(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), llvm::SIInstrInfo::isInlineConstant(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isOperandLegal().

◆ isInlinableLiteralBF16()

bool llvm::AMDGPU::isInlinableLiteralBF16	(	int16_t	Literal,
		bool	HasInv2Pi,
		bool *	IsBF16 )

Definition at line 2964 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralFP16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralFP16	(	int16_t	Literal,
		bool	HasInv2Pi )

Definition at line 2989 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralI16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralI16	(	int32_t	Literal,
		bool	HasInv2Pi )

Definition at line 2985 of file AMDGPUBaseInfo.cpp.

References isInlinableLiteral32(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216	(	uint32_t	Literal,
		uint8_t	OpType )

Definition at line 3128 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), isInlinableLiteralV2BF16(), llvm::Literal, llvm_unreachable, OPERAND_REG_IMM_NOINLINE_V2FP16, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2INT16.

◆ isInlinableLiteralV2BF16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2BF16 ( uint32_t Literal )

Definition at line 3154 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2BF16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2F16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2F16 ( uint32_t Literal )

Definition at line 3159 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2F16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2I16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2I16 ( uint32_t Literal )

Definition at line 3149 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2I16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlineValue()

LLVM_READNONE bool llvm::AMDGPU::isInlineValue ( MCRegister Reg )

Definition at line 2694 of file AMDGPUBaseInfo.cpp.

References Reg.

◆ isIntrinsicAlwaysUniform()

bool llvm::AMDGPU::isIntrinsicAlwaysUniform ( unsigned IntrID )

Returns: true if the intrinsic is uniform

Definition at line 3385 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity(), llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform(), and isTriviallyUniform().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned IntrID )

Returns: true if the intrinsic is divergent

Definition at line 3381 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity(), and llvm::SITargetLowering::isSDNodeSourceOfDivergence().

◆ isKernel() [1/2]

LLVM_READNONE constexpr bool llvm::AMDGPU::isKernel ( CallingConv::ID CC )

inlineconstexpr

Definition at line 1469 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, CC, and llvm::CallingConv::SPIR_KERNEL.

Referenced by getTransitiveUsesOfGV(), getUsesOfGVByFunction(), isKernel(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), and removeFnAttrFromReachable().

◆ isKernel() [2/2]

bool llvm::AMDGPU::isKernel ( const Function & F )

inline

Definition at line 1479 of file AMDGPUBaseInfo.h.

References F, and isKernel().

◆ isKImmOperand()

bool llvm::AMDGPU::isKImmOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo )

Is this a KImm operand?

Definition at line 2725 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_KIMM_FIRST, and OPERAND_KIMM_LAST.

◆ isLDSDMAIntrinsic()

bool llvm::AMDGPU::isLDSDMAIntrinsic ( unsigned IntrID )

Returns: true if the intrinsic executes an LDSDMA operation

Definition at line 3408 of file AMDGPUBaseInfo.cpp.

◆ isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower ( const GlobalVariable & GV )

Definition at line 112 of file AMDGPUMemoryUtils.cpp.

References llvm::GlobalVariable::getInitializer(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalVariable::hasInitializer(), llvm::isa(), llvm::GlobalVariable::isConstant(), isDynamicLDS(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by getTransitiveUsesOfLDSForLowering().

◆ isLegalDPALU_DPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegalDPALU_DPPControl	(	const MCSubtargetInfo &	ST,
		unsigned	DC )

inline

Definition at line 1771 of file AMDGPUBaseInfo.h.

References isGFX12(), isGFX90A(), llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST, llvm::AMDGPU::DPP::ROW_SHARE_FIRST, and llvm::AMDGPU::DPP::ROW_SHARE_LAST.

Referenced by llvm::SIInstrInfo::expandMovDPP64(), llvm::AMDGPULegalizerInfo::legalizeLaneOp(), lowerLaneOp(), and llvm::SIInstrInfo::verifyInstruction().

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset,
		bool	IsBuffer )

Definition at line 3274 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset(), isGFX12Plus(), and llvm::isInt().

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset )

Definition at line 3265 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset(), isGFX12Plus(), and llvm::isUInt().

Referenced by getSMRDEncodedOffset().

◆ isLitExpr()

bool llvm::AMDGPU::isLitExpr ( const MCExpr * Expr )

Definition at line 761 of file AMDGPUMCExpr.cpp.

References llvm::AMDGPUMCExpr::AGVK_Lit, llvm::AMDGPUMCExpr::AGVK_Lit64, llvm::dyn_cast(), and E.

Referenced by getLitValue().

◆ isMAC()

LLVM_READNONE bool llvm::AMDGPU::isMAC ( unsigned Opc )

Definition at line 723 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isModuleEntryFunctionCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isModuleEntryFunctionCC ( CallingConv::ID CC )

constexpr

Definition at line 1458 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_Gfx, CC, and isEntryFunctionCC().

Referenced by llvm::AMDGPUTargetMachine::getAssumedAddrSpace().

◆ isNamedBarrier()

TargetExtType * llvm::AMDGPU::isNamedBarrier ( const GlobalVariable & GV )

Definition at line 87 of file AMDGPUMemoryUtils.cpp.

References llvm::AMDGPUAS::BARRIER, llvm::GlobalValue::getAddressSpace(), llvm::TargetExtType::getName(), and getTargetExtType().

Referenced by llvm::AMDGPUMachineFunctionInfo::allocateBarrierGlobal(), getNumNamedBarriersDeclared(), llvm::SITargetLowering::isOffsetFoldingLegal(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), and llvm::AMDGPUTargetLowering::LowerGlobalAddress().

◆ isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus ( const MCSubtargetInfo & STI )

Definition at line 2529 of file AMDGPUBaseInfo.cpp.

References isCI(), isGFX9(), isSI(), and isVI().

◆ isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus ( const MCSubtargetInfo & STI )

Definition at line 2527 of file AMDGPUBaseInfo.cpp.

References isGFX11Plus().

◆ isNotGFX12Plus()

bool llvm::AMDGPU::isNotGFX12Plus ( const MCSubtargetInfo & STI )

Definition at line 2501 of file AMDGPUBaseInfo.cpp.

References isGFX12Plus().

◆ isNotGFX9Plus()

bool llvm::AMDGPU::isNotGFX9Plus ( const MCSubtargetInfo & STI )

Definition at line 2462 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

◆ isPackedSingleSGPR64BitInst()

LLVM_READONLY bool llvm::AMDGPU::isPackedSingleSGPR64BitInst ( unsigned Opc )

The opcode is a packed 64-bit instruction which only reads low 64 bits of a scalar operand and propagates it to high channel.

Definition at line 3693 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by isSingleSGPRReadInst(), and llvm::SIInstrInfo::legalizeOpWithMove().

◆ isPackedSingleSGPRFP32Inst()

LLVM_READONLY bool llvm::AMDGPU::isPackedSingleSGPRFP32Inst ( unsigned Opc )

The opcode is a packed fp32 instruction which only reads low 32 bits of a scalar operand and propagates it to high channel.

Definition at line 3678 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by isSingleSGPRReadInst().

◆ isPermlane16()

LLVM_READNONE bool llvm::AMDGPU::isPermlane16 ( unsigned Opc )

Definition at line 754 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isPKFMACF16InlineConstant()

LLVM_READNONE bool llvm::AMDGPU::isPKFMACF16InlineConstant	(	uint32_t	Literal,
		bool	IsGFX11Plus )

Definition at line 3164 of file AMDGPUBaseInfo.cpp.

References getPKFMACF16InlineEncoding(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isPseudoTarget() [1/2]

bool llvm::AMDGPU::isPseudoTarget ( GPUKind AK )

Return true if AK is a pseudo target (e.g.

"generic"/"generic-hsa"): a recognized AMDGCN GPU that represents no concrete hardware and has no subarch of its own. Such targets are resolved by the backend as a default device but are not valid as an explicit -mcpu.

Definition at line 229 of file AMDGPUTargetParser.cpp.

References llvm::Triple::NoSubArch.

Referenced by isPseudoTarget().

◆ isPseudoTarget() [2/2]

bool llvm::AMDGPU::isPseudoTarget ( StringRef CPU )

Convenience overload of isPseudoTarget taking a GPU name CPU, which is parsed via parseArchAMDGCN.

Definition at line 234 of file AMDGPUTargetParser.cpp.

References isPseudoTarget(), and parseArchAMDGCN().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue * GV )

Definition at line 1499 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber	(	const Value *	Ptr,
		MemoryDef *	Def,
		AAResults *	AA )

Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line 377 of file AMDGPUMemoryUtils.cpp.

References Def, llvm::dyn_cast(), I, II, and llvm::isa().

Referenced by isClobberedInFunction().

◆ isRsrcIndexReg()

bool llvm::AMDGPU::isRsrcIndexReg	(	MCRegister	Reg,
		const MCRegisterInfo &	MRI )

Returns: true if Reg is an indexed-resource index register, i.e. either a 32-bit SGPR (uniform-indexed form) or a Lo256 VGPR (per-lane indexed form).

Definition at line 2596 of file AMDGPUBaseInfo.cpp.

References MRI, and Reg.

◆ isSGPR()

bool llvm::AMDGPU::isSGPR	(	MCRegister	Reg,
		const MCRegisterInfo *	TRI )

Is Reg - scalar register.

Definition at line 2588 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), Reg, and TRI.

◆ isShader()

LLVM_READNONE constexpr bool llvm::AMDGPU::isShader ( CallingConv::ID CC )

constexpr

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo & STI )

Definition at line 2426 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().

◆ isSingleSGPRReadInst()

LLVM_READONLY bool llvm::AMDGPU::isSingleSGPRReadInst ( unsigned Opc )

Packed instructions that read a single SGPR for SGPR operands, except for 64-bit elements which read two SGPRs.

Definition at line 3709 of file AMDGPUBaseInfo.cpp.

References isPackedSingleSGPR64BitInst(), isPackedSingleSGPRFP32Inst(), and Opc.

Referenced by llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::verifyInstruction().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo )

Is this floating-point operand?

Definition at line 2732 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_NOINLINE_FP16, OPERAND_REG_IMM_NOINLINE_V2FP16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2FP64, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, and OPERAND_REG_INLINE_C_V2FP16.

Referenced by llvm::AMDGPU::VOPD::ComponentProps::ComponentProps().

◆ isSISrcOperand() [1/2]

bool llvm::AMDGPU::isSISrcOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo )

inline

Definition at line 1589 of file AMDGPUBaseInfo.h.

References isSISrcOperand().

◆ isSISrcOperand() [2/2]

bool llvm::AMDGPU::isSISrcOperand ( const MCOperandInfo & OpInfo )

constexpr

Is this an AMDGPU specific source operand?

These include registers, inline constants, literals and mandatory literals (KImm).

Definition at line 1584 of file AMDGPUBaseInfo.h.

References OPERAND_SRC_FIRST, and OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isLiteralOperandLegal(), llvm::SIInstrInfo::isOperandLegal(), and isSISrcOperand().

◆ isSubArchCompatible() [1/2]

bool llvm::AMDGPU::isSubArchCompatible	(	const Triple &	A,
		const Triple &	B )

Return true if subarch A is compatible with subarch B, i.e.

they are equal or one is the major-family subarch of the other (e.g. AMDGPUSubArch9 is compatible with AMDGPUSubArch900). NoSubArch is compatible with anything.

Definition at line 238 of file AMDGPUTargetParser.cpp.

References A(), B(), isSubArchCompatible(), and llvm::Triple::NoSubArch.

Referenced by llvm::Triple::isCompatibleWith(), isCPUValidForSubArch(), and isSubArchCompatible().

◆ isSubArchCompatible() [2/2]

bool llvm::AMDGPU::isSubArchCompatible	(	Triple::SubArchType	A,
		Triple::SubArchType	B )

Definition at line 193 of file AMDGPUTargetParser.cpp.

References A(), B(), getMajorSubArch(), and llvm::Triple::NoSubArch.

◆ isSymbolicCustomOperandEncoding()

bool llvm::AMDGPU::isSymbolicCustomOperandEncoding	(	const CustomOperandVal *	Opr,
		int	Size,
		unsigned	Code,
		bool &	HasNonDefaultVal,
		const MCSubtargetInfo &	STI )

static

Definition at line 1845 of file AMDGPUBaseInfo.cpp.

References Idx, and llvm::Size.

Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().

◆ isTensorStore()

LLVM_READONLY bool llvm::AMDGPU::isTensorStore ( unsigned Opc )

Definition at line 815 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getTemporalHintType().

◆ isTgSplitEnabled()

bool llvm::AMDGPU::isTgSplitEnabled ( const Function & F )

inline

Definition at line 1048 of file AMDGPUBaseInfo.h.

References F.

◆ isTriviallyUniform() [1/2]

bool llvm::AMDGPU::isTriviallyUniform ( const Use & U )

Return true if we can easily prove that use U is uniform.

Definition at line 3404 of file AMDGPUBaseInfo.cpp.

References llvm::cast(), and isTriviallyUniform().

◆ isTriviallyUniform() [2/2]

bool llvm::AMDGPU::isTriviallyUniform	(	const Value *	V,
		const Instruction *	CtxI )

Return true if we can easily prove that V is uniform at CtxI.

Definition at line 3389 of file AMDGPUBaseInfo.cpp.

References A(), llvm::dyn_cast(), llvm::ilist_detail::node_parent_access< NodeTy, ParentTy >::getParent(), II, llvm::isa(), isArgPassedInSGPR(), isIntrinsicAlwaysUniform(), and V.

Referenced by hasUniformPointerOperand(), llvm::GCNTTIImpl::hoistLaneIntrinsicThroughOperand(), llvm::GCNTTIImpl::instCombineIntrinsic(), and isTriviallyUniform().

◆ isTrue16Inst()

LLVM_READONLY bool llvm::AMDGPU::isTrue16Inst ( unsigned Opc )

Definition at line 835 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isUniformMMO()

bool llvm::AMDGPU::isUniformMMO ( const MachineMemOperand * MMO )

Definition at line 29 of file AMDGPUInstrInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::dyn_cast(), llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getPseudoValue(), llvm::MachineMemOperand::getValue(), I, llvm::isa(), and isArgPassedInSGPR().

Referenced by llvm::AMDGPURegisterBankInfo::isScalarLoadLegal(), llvm::SITargetLowering::isUniformLoad(), llvm::AMDGPU::RegBankLegalizeRules::RegBankLegalizeRules(), and llvm::AMDGPUTargetLowering::shouldReduceLoadWidth().

◆ isUnscaledIEEEDivFmas()

bool llvm::AMDGPU::isUnscaledIEEEDivFmas	(	const MachineInstr &	MI,
		const MachineRegisterInfo &	MRI )

Return whether div.fmas can use ordinary FMA without changing denormals.

Definition at line 26 of file AMDGPUGlobalISelUtils.cpp.

References llvm::getDefIgnoringCopies(), llvm::getFltSemanticForLLT(), llvm::getIConstantVRegValWithLookThrough(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::DenormalMode::IEEE, MI, and MRI.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPU::RegBankLegalizeRules::RegBankLegalizeRules().

◆ isValid32BitLiteral()

LLVM_READNONE bool llvm::AMDGPU::isValid32BitLiteral	(	uint64_t	Val,
		bool	IsFP64 )

Definition at line 3168 of file AMDGPUBaseInfo.cpp.

References llvm::isInt(), llvm::isUInt(), llvm::Lo_32(), and uint64_t.

Referenced by llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::isOperandLegal(), llvm::AMDGPUDAGToDAGISel::Select(), and llvm::SIInstrInfo::verifyInstruction().

◆ isValidAsyncStageMask()

bool llvm::AMDGPU::isValidAsyncStageMask ( int64_t Mask )

constexpr

Returns: true if Mask is a legal stage mask operand of the asyncmark / wait_asyncmark intrinsics and pseudos.

Definition at line 88 of file AMDGPUAsyncStages.h.

References ALL, and llvm::to_underlying().

Referenced by asyncStagesFromMaskOperand(), and llvm::SIInstrInfo::verifyInstruction().

◆ isValidRegPrefix()

bool llvm::AMDGPU::isValidRegPrefix ( char C )

static

Definition at line 1509 of file AMDGPUBaseInfo.cpp.

References C().

Referenced by parseAsmPhysRegName().

◆ isValidWMMAScaleFmtCombination()

LLVM_READONLY bool llvm::AMDGPU::isValidWMMAScaleFmtCombination	(	unsigned	AFmt,
		unsigned	AScale,
		unsigned	BFmt,
		unsigned	BScale )

Returns: true if this combination is listed as valid.

Definition at line 651 of file AMDGPUBaseInfo.cpp.

References isValid(), llvm::AMDGPU::WMMA::MATRIX_FMT_BF6, llvm::AMDGPU::WMMA::MATRIX_FMT_BF8, llvm::AMDGPU::WMMA::MATRIX_FMT_FP4, llvm::AMDGPU::WMMA::MATRIX_FMT_FP6, llvm::AMDGPU::WMMA::MATRIX_FMT_FP8, llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E4M3, llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E5M3, and llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E8.

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo & STI )

Definition at line 2434 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().

◆ isVOPC64DPP()

LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP ( unsigned Opc )

Definition at line 578 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isVOPCAsmOnly()

LLVM_READONLY bool llvm::AMDGPU::isVOPCAsmOnly ( unsigned Opc )

Definition at line 582 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isVOPD()

LLVM_READONLY bool llvm::AMDGPU::isVOPD ( unsigned Opc )

Definition at line 719 of file AMDGPUBaseInfo.cpp.

References hasNamedOperand(), and Opc.

Referenced by llvm::AMDGPUDisassembler::decodeNonVGPRSrcOp(), getSrcOperandIndices(), and getVGPRLoweringOperandTables().

◆ isWMMAAnyF8()

template<typename InstT>

bool llvm::AMDGPU::isWMMAAnyF8 ( const InstT & MI )

Returns: true if either matrix input of an f8f6f4 WMMA is f8.

Definition at line 606 of file AMDGPUBaseInfo.h.

References getWMMAMatrixFmts(), llvm::AMDGPU::WMMA::MATRIX_FMT_BF8, and MI.

◆ isWMMABothF4()

template<typename InstT>

bool llvm::AMDGPU::isWMMABothF4 ( const InstT & MI )

Returns: true if both matrix inputs of an f8f6f4 WMMA are f4.

Definition at line 612 of file AMDGPUBaseInfo.h.

References getWMMAMatrixFmts(), llvm::AMDGPU::WMMA::MATRIX_FMT_FP4, and MI.

◆ LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE()

llvm::AMDGPU::LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE ( )

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned Intr )

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::SITargetLowering::getTgtMemIntrinsic(), and simplifyAMDGCNMemoryIntrinsicDemanded().

◆ mapToDWARFAddrSpace()

int llvm::AMDGPU::mapToDWARFAddrSpace ( unsigned LLVMAddrSpace )

constexpr

If LLVMAddressSpace has a corresponding DWARF encoding, return it; otherwise return the sentinel value -1 to indicate no such mapping exists.

This maps private/scratch to the focused lane view.

These mappings must be kept in sync with llvm/docs/AMDGPUUsage.md table "AMDGPU DWARF Address Space Mapping".

Note: This could return std::optional<int> but that would require an extra #include.

Definition at line 188 of file AMDGPUAddrSpace.h.

References llvm::AMDGPU::impl::LLVMToDWARFAddrSpaceMapping.

◆ mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode ( unsigned Opc )

Definition at line 857 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ maskShiftGet()

const MCExpr * llvm::AMDGPU::maskShiftGet	(	const MCExpr *	Val,
		uint32_t	Mask,
		uint32_t	Shift,
		MCContext &	Ctx )

inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr

will be the equivalent of (Val >> 6) & 0xf

Definition at line 63 of file SIDefinesUtils.h.

References llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), and llvm::MCBinaryExpr::createLShr().

◆ maskShiftSet()

const MCExpr * llvm::AMDGPU::maskShiftSet	(	const MCExpr *	Val,
		uint32_t	Mask,
		uint32_t	Shift,
		MCContext &	Ctx )

inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr

will be the equivalent of (Val & 0xf) << 6

Definition at line 44 of file SIDefinesUtils.h.

References llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), and llvm::MCBinaryExpr::createShl().

Referenced by llvm::AMDGPU::AMDGPUMCKernelCodeT::EmitKernelCodeT().

◆ mayTailCallThisCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::mayTailCallThisCC ( CallingConv::ID CC )

constexpr

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 1488 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, llvm::CallingConv::C, canGuaranteeTCO(), and CC.

Referenced by llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), and llvm::SITargetLowering::isEligibleForTailCallOptimization().

◆ mc2PseudoReg()

LLVM_READNONE MCRegister llvm::AMDGPU::mc2PseudoReg ( MCRegister Reg )

Convert hardware register Reg to a pseudo register.

Definition at line 2692 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG, and Reg.

Referenced by checkWriteLane().

◆ memToShadow()

Value * llvm::AMDGPU::memToShadow	(	Module &	M,
		IRBuilder<> &	IRB,
		Type *	IntptrTy,
		Value *	Shadow,
		int	AsanScale,
		uint32_t	AsanOffset )

static

Definition at line 139 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), and llvm::IRBuilderBase::CreateLShr().

Referenced by instrumentAddressImpl().

◆ mergeSubArch()

std::string llvm::AMDGPU::mergeSubArch	(	const Triple &	A,
		const Triple &	B )

Returns the effective triple appropriate to use when linking B into A by merging the subarches in case of inexact match.

In cases where isSubArchCompatible would return / false, returns B. This assumes that the non-arch triple components are the same

Definition at line 252 of file AMDGPUTargetParser.cpp.

References A(), B(), getMajorSubArch(), and llvm::Triple::NoSubArch.

Referenced by llvm::Triple::merge().

◆ mfmaScaleF8F6F4FormatToNumRegs()

LLVM_READNONE uint8_t llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs ( unsigned EncodingVal )

Definition at line 604 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MFMAScaleFormats::FP4_E2M1, llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3, llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2, llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3, llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2, and llvm_unreachable.

Referenced by getMFMA_F8F6F4_WithFormatArgs().

◆ operator<<() [1/2]

raw_ostream & llvm::AMDGPU::operator<<	(	raw_ostream &	OS,
		AsyncStages	Mask )

inline

Print the stages named by Mask as a '|'-separated list, or "all" if it names every stage.

Definition at line 124 of file AMDGPUAsyncStages.h.

References ALL, asyncStages(), getAsyncStageName(), llvm::interleave(), and NONE.

◆ operator<<() [2/2]

raw_ostream & llvm::AMDGPU::operator<<	(	raw_ostream &	OS,
		const TargetID &	TargetID )

inline

Definition at line 423 of file AMDGPUTargetParser.h.

References llvm::AMDGPU::TargetID::print().

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef CPU )

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef CPU )

Definition at line 310 of file AMDGPUTargetParser.cpp.

Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().

◆ parseAsmConstraintPhysReg()

std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmConstraintPhysReg ( StringRef Constraint )

Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.

Followed by the start register number, and the register width. Does not validate the number of registers exists in the class.

Definition at line 1544 of file AMDGPUBaseInfo.cpp.

References parseAsmPhysRegName(), and RegName.

Referenced by llvm::SITargetLowering::getRegForInlineAsmConstraint().

◆ parseAsmPhysRegName()

std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmPhysRegName ( StringRef TupleString )

Returns a valid charcode or 0 in the first entry if this is a valid physical register name.

Followed by the start register number, and the register width. Does not validate the number of registers exists in the class. Unlike parseAsmConstraintPhysReg, this does not expect the name to be wrapped in "{}".

Definition at line 1513 of file AMDGPUBaseInfo.cpp.

References llvm::End, llvm::Failed(), Idx, isValidRegPrefix(), and RegName.

Referenced by parseAsmConstraintPhysReg().

◆ printAMDGPUMCExpr()

void llvm::AMDGPU::printAMDGPUMCExpr	(	const MCExpr *	Expr,
		raw_ostream &	OS,
		const MCAsmInfo *	MAI )

Definition at line 750 of file AMDGPUMCExpr.cpp.

References llvm::MCAsmInfo::printExpr().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ removeFnAttrFromReachable()

void llvm::AMDGPU::removeFnAttrFromReachable	(	CallGraph &	CG,
		Function *	KernelRoot,
		ArrayRef< StringRef >	FnAttrs )

Strip FnAttr attribute from any functions where we may have introduced its use.

Definition at line 333 of file AMDGPUMemoryUtils.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, llvm::CallGraph::getExternalCallingNode(), llvm::Function::getFunction(), llvm::SmallPtrSetImpl< PtrType >::insert(), isKernel(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::Function::removeFnAttr().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple & TT )

Returns: True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 1505 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::r600.

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().

◆ supportsScaleOffset()

bool llvm::AMDGPU::supportsScaleOffset	(	const MCInstrInfo &	MII,
		unsigned	Opcode )

Returns: true if a memory instruction supports scale_offset modifier.

Definition at line 3613 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrInfo::get(), getSMEMIsBuffer(), hasNamedOperand(), llvm::SIInstrFlags::isFLAT(), llvm::SIInstrFlags::isFlatScratch(), and llvm::SIInstrFlags::isSMRD().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ supportsWGP()

bool llvm::AMDGPU::supportsWGP ( const MCSubtargetInfo & STI )

Definition at line 2521 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX1250().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ TypeStoreSizeToSizeIndex()

size_t llvm::AMDGPU::TypeStoreSizeToSizeIndex ( uint32_t TypeSize )

static

Definition at line 52 of file AMDGPUAsanInstrumentation.cpp.

References llvm::countr_zero().

Referenced by instrumentAddressImpl().

◆ wmmaScaleF8F6F4FormatToNumRegs()

LLVM_READNONE uint8_t llvm::AMDGPU::wmmaScaleF8F6F4FormatToNumRegs ( unsigned Fmt )

Definition at line 628 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable, llvm::AMDGPU::WMMA::MATRIX_FMT_BF6, llvm::AMDGPU::WMMA::MATRIX_FMT_BF8, llvm::AMDGPU::WMMA::MATRIX_FMT_FP4, llvm::AMDGPU::WMMA::MATRIX_FMT_FP6, and llvm::AMDGPU::WMMA::MATRIX_FMT_FP8.

Referenced by getWMMA_F8F6F4_WithFormatArgs(), and llvm::GCNTTIImpl::instCombineIntrinsic().

Variable Documentation

◆ AsyncStageNames

StringLiteral llvm::AMDGPU::AsyncStageNames[NumAsyncStages]

inlineconstexpr

Initial value:

= {
    "TENSOR",
    "GLOBAL_LOAD_ASYNC_TO_LDS",
    "GLOBAL_LOAD_ASYNC_TO_LDS_MCAST",
    "GLOBAL_STORE_ASYNC_FROM_LDS",
    "RESERVED_4",
    "BUFFER_GLOBAL_LOAD",
    "RESERVED_6",
    "RESERVED_7",
    "RESERVED_8",
    "RESERVED_9",
    "RESERVED_10",
}

The name of each stage, indexed by the position of its bit.

Definition at line 72 of file AMDGPUAsyncStages.h.

Referenced by getAsyncStageName().

◆ ExtendedFltRoundOffset

uint32_t llvm::AMDGPU::ExtendedFltRoundOffset = 4

staticconstexpr

Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.

Definition at line 140 of file SIModeRegisterDefaults.h.

Referenced by decodeFltRoundToHWConversionTable(), decodeIndexFltRoundConversionTable(), encodeFltRoundsTable(), encodeFltRoundsToHWTable(), and encodeFltRoundsToHWTableSame().

◆ F32FltRoundOffset

uint32_t llvm::AMDGPU::F32FltRoundOffset = 0

staticconstexpr

Offset in mode register of f32 rounding mode.

Definition at line 143 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

◆ F64FltRoundOffset

uint32_t llvm::AMDGPU::F64FltRoundOffset = 2

staticconstexpr

Offset in mode register of f64/f16 rounding mode.

Definition at line 146 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

◆ FltRoundConversionTable

const uint64_t llvm::AMDGPU::FltRoundConversionTable

extern

Definition at line 74 of file SIModeRegisterDefaults.cpp.

Referenced by decodeIndexFltRoundConversionTable(), and llvm::SITargetLowering::lowerGET_ROUNDING().

◆ FltRoundToHWConversionTable

const uint64_t llvm::AMDGPU::FltRoundToHWConversionTable

extern

Definition at line 188 of file SIModeRegisterDefaults.cpp.

Referenced by decodeFltRoundToHW(), decodeFltRoundToHWConversionTable(), decodeFltRoundToHWConversionTable(), and llvm::SITargetLowering::lowerSET_ROUNDING().

◆ LaneMaskConstants32

LaneMaskConstants llvm::AMDGPU::LaneMaskConstants32

staticconstexpr

Initial value:

=

LaneMaskConstants(true)

llvm::AMDGPU::LaneMaskConstants

Definition AMDGPULaneMaskUtils.h:21

Definition at line 81 of file AMDGPULaneMaskUtils.h.

Referenced by llvm::AMDGPU::LaneMaskConstants::get().

◆ LaneMaskConstants64

LaneMaskConstants llvm::AMDGPU::LaneMaskConstants64

staticconstexpr

Initial value:

=

LaneMaskConstants(false)

Definition at line 83 of file AMDGPULaneMaskUtils.h.

Referenced by llvm::AMDGPU::LaneMaskConstants::get().

◆ MaxCoExecStages

unsigned llvm::AMDGPU::MaxCoExecStages = 32

constexpr

Max stages: INT8 16x16x64 = 17 cycles, round up for safety.

Definition at line 221 of file AMDGPUCoExecInfo.h.

Referenced by llvm::AMDGPU::CoExecInfo::build(), llvm::AMDGPU::CoExecInfo::CoExecInfo(), getMFMACoExecInfo(), and llvm::GCNHazardRecognizer::~GCNHazardRecognizer().

◆ NamedBarrierTypeSizeInBytes

unsigned llvm::AMDGPU::NamedBarrierTypeSizeInBytes = 1

staticconstexpr

Definition at line 34 of file AMDGPUMemoryUtils.h.

Referenced by getNumNamedBarriersDeclared().

◆ NumAsyncStages

unsigned llvm::AMDGPU::NumAsyncStages = BitWidth<AsyncStages>

inlineconstexpr

The number of stages, which is also the number of bits in a stage mask.

Definition at line 69 of file AMDGPUAsyncStages.h.

Referenced by asyncStages().

◆ OPR_ID_DUPLICATE

const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3

Definition at line 25 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand().

◆ OPR_ID_UNKNOWN

const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1

Definition at line 23 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getEncodingFromOperandTable().

◆ OPR_ID_UNSUPPORTED

const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2

Definition at line 24 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getEncodingFromOperandTable().

◆ OPR_VAL_INVALID

const int llvm::AMDGPU::OPR_VAL_INVALID = -4

Definition at line 26 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperandVal().

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 2042 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 2043 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 2044 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 2045 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

Namespaces

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ AdvanceForRawWindowFn

◆ AMDGPUFeatureBitset

◆ CoExecMaskT

◆ EncodingBit

◆ FunctionVariableMap

◆ HazardClassMask

◆ InstPredicate

◆ R600FeatureBitset

◆ RulePredicate

◆ TargetID

◆ TargetIDSetting

◆ VariableFunctionMap

Enumeration Type Documentation

◆ anonymous enum

◆ anonymous enum

◆ AMDGPUFeature

◆ AMDGPUFltRounds

◆ AMDGPUSchedReason

◆ AntiHintDirection

◆ AntiHintRule

◆ AsmComments

◆ AsyncStages

◆ CarriedLatency

◆ CoExecMask

◆ CoExecStageType

◆ FastRulesTypes

◆ FeatureError

◆ Fixups

◆ FlatAddrSpace

◆ FPType

◆ FuncInfoFlags

◆ GPUKind

◆ HazardOperand

◆ IGLPStrategyID

◆ InfoKind

◆ InstCounterType

◆ InstructionFlavor

◆ LDSLoweringKind

◆ Lifetime

◆ LoweringMethodID

◆ OperandType

◆ R600Feature

◆ RegBankLLTMappingApplyID

◆ ScanOptions

◆ SchedGroupMask

◆ SchedulingPhase

◆ TargetIDSetting

◆ TargetIndex

◆ UniformityLLTOpPredicateID

◆ WMMAVariant

Function Documentation

◆ addrspacesMayAlias()

◆ applyAntiHintRules()

◆ asyncStages()

◆ asyncStagesFromMaskOperand()

◆ buildReadAnyLane()

◆ buildReadFirstLane()

◆ canGuaranteeTCO()

◆ classifyFlavor()

◆ convertSetRegImmToVgprMSBs() [1/3]

◆ convertSetRegImmToVgprMSBs() [2/3]

◆ convertSetRegImmToVgprMSBs() [3/3]

◆ convertSMRDOffsetUnits()

◆ copyMetadataForWidenedLoad()

◆ counterTypeForInstr()

◆ createAMDGPUTargetID()

◆ createLaneMaskReg()

◆ createSlowPathCmp()

◆ decodeCustomOperand()

◆ decodeDscnt()

◆ decodeExpcnt()

◆ decodeFltRoundToHWConversionTable()

◆ decodeLgkmcnt()