LLVM  16.0.0git
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llvm::AMDGPU Namespace Reference

Namespaces

 CPol
 
 DepCtr
 
 DPP
 
 ElfNote
 
 EncValues
 
 Exp
 
 HSAMD
 
 Hwreg
 
 ImplicitArg
 
 IsaInfo
 
 MTBUFFormat
 
 PALMD
 
 SDWA
 
 SendMsg
 
 Swizzle
 
 UfmtGFX10
 
 UfmtGFX11
 
 VGPRIndexMode
 
 VOP3PEncoding
 

Classes

struct  CanBeVOPD
 
struct  CustomOperand
 
struct  CustomOperandVal
 
struct  D16ImageDimIntrinsic
 
struct  GcnBufferFormatInfo
 
struct  ImageDimIntrinsicInfo
 
struct  IsaVersion
 Instruction set architecture version. More...
 
struct  MAIInstInfo
 
struct  MIMGBaseOpcodeInfo
 
struct  MIMGBiasMappingInfo
 
struct  MIMGDimInfo
 
struct  MIMGG16MappingInfo
 
struct  MIMGInfo
 
struct  MIMGLZMappingInfo
 
struct  MIMGMIPMappingInfo
 
struct  MIMGOffsetMappingInfo
 
struct  MTBUFInfo
 
struct  MUBUFInfo
 
struct  RsrcIntrinsic
 
struct  SIModeRegisterDefaults
 
struct  SMInfo
 
struct  VOPC64DPPInfo
 
struct  VOPDComponentInfo
 
struct  VOPDInfo
 
struct  VOPInfo
 
struct  Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction. More...
 
struct  WMMAOpcodeMappingInfo
 

Enumerations

enum  GPUKind : uint32_t {
  GK_NONE = 0, GK_R600 = 1, GK_R630 = 2, GK_RS880 = 3,
  GK_RV670 = 4, GK_RV710 = 5, GK_RV730 = 6, GK_RV770 = 7,
  GK_CEDAR = 8, GK_CYPRESS = 9, GK_JUNIPER = 10, GK_REDWOOD = 11,
  GK_SUMO = 12, GK_BARTS = 13, GK_CAICOS = 14, GK_CAYMAN = 15,
  GK_TURKS = 16, GK_R600_FIRST = GK_R600, GK_R600_LAST = GK_TURKS, GK_GFX600 = 32,
  GK_GFX601 = 33, GK_GFX602 = 34, GK_GFX700 = 40, GK_GFX701 = 41,
  GK_GFX702 = 42, GK_GFX703 = 43, GK_GFX704 = 44, GK_GFX705 = 45,
  GK_GFX801 = 50, GK_GFX802 = 51, GK_GFX803 = 52, GK_GFX805 = 53,
  GK_GFX810 = 54, GK_GFX900 = 60, GK_GFX902 = 61, GK_GFX904 = 62,
  GK_GFX906 = 63, GK_GFX908 = 64, GK_GFX909 = 65, GK_GFX90A = 66,
  GK_GFX90C = 67, GK_GFX940 = 68, GK_GFX1010 = 71, GK_GFX1011 = 72,
  GK_GFX1012 = 73, GK_GFX1013 = 74, GK_GFX1030 = 75, GK_GFX1031 = 76,
  GK_GFX1032 = 77, GK_GFX1033 = 78, GK_GFX1034 = 79, GK_GFX1035 = 80,
  GK_GFX1036 = 81, GK_GFX1100 = 90, GK_GFX1101 = 91, GK_GFX1102 = 92,
  GK_GFX1103 = 93, GK_AMDGCN_FIRST = GK_GFX600, GK_AMDGCN_LAST = GK_GFX1103
}
 GPU kinds supported by the AMDGPU target. More...
 
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0, FEATURE_FMA = 1 << 1, FEATURE_LDEXP = 1 << 2, FEATURE_FP64 = 1 << 3,
  FEATURE_FAST_FMA_F32 = 1 << 4, FEATURE_FAST_DENORMAL_F32 = 1 << 5, FEATURE_WAVE32 = 1 << 6, FEATURE_XNACK = 1 << 7,
  FEATURE_SRAMECC = 1 << 8
}
 
enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType : unsigned {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32_DEFERRED,
  OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_IMM_V2FP32,
  OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16,
  OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2FP16,
  OPERAND_REG_INLINE_C_V2INT32, OPERAND_REG_INLINE_C_V2FP32, OPERAND_KIMM32, OPERAND_KIMM16,
  OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32,
  OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT32,
  OPERAND_REG_INLINE_AC_V2FP32, OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
  OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
  OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, OPERAND_INPUT_MODS, OPERAND_SDWA_VOPC_DST
}
 

Functions

StringRef getArchNameAMDGCN (GPUKind AK)
 
StringRef getArchNameR600 (GPUKind AK)
 
StringRef getCanonicalArchName (const Triple &T, StringRef Arch)
 
GPUKind parseArchAMDGCN (StringRef CPU)
 
GPUKind parseArchR600 (StringRef CPU)
 
unsigned getArchAttrAMDGCN (GPUKind AK)
 
unsigned getArchAttrR600 (GPUKind AK)
 
void fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
 
void fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
 
IsaVersion getIsaVersion (StringRef GPU)
 
bool isFlatGlobalAddrSpace (unsigned AS)
 
std::pair< Register, unsigned > getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr)
 Returns base register and constant offset. More...
 
bool isLegalVOP3PShuffleMask (ArrayRef< int > Mask)
 
bool hasAtomicFaddRtnForTy (const GCNSubtarget &Subtarget, const LLT &Ty)
 
const RsrcIntrinsiclookupRsrcIntrinsic (unsigned Intr)
 
const D16ImageDimIntrinsiclookupD16ImageDimIntrinsic (unsigned Intr)
 
const ImageDimIntrinsicInfogetImageDimIntrinsicInfo (unsigned Intr)
 
const ImageDimIntrinsicInfogetImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp32 (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp64 (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getIfAddr64Inst (uint16_t Opcode)
 Check if Opcode is an Addr64 opcode. More...
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalSaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalVaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXNoSDstOp (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSTfromSS (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSVfromSVS (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSSfromSV (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSVfromSS (uint16_t Opcode)
 
LLVM_READONLY int getMFMAEarlyClobberOp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXOpFromVCMP (uint16_t Opcode)
 
Optional< uint8_t > getHsaAbiVersion (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion2 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion3 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion4 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion5 (const MCSubtargetInfo *STI)
 
bool isHsaAbiVersion3AndAbove (const MCSubtargetInfo *STI)
 
unsigned getAmdhsaCodeObjectVersion ()
 
unsigned getMultigridSyncArgImplicitArgPosition ()
 
unsigned getHostcallImplicitArgPosition ()
 
int getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
const MIMGBaseOpcodeInfogetMIMGBaseOpcode (unsigned Opc)
 
int getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
unsigned getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
 
int getMTBUFBaseOpcode (unsigned Opc)
 
int getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int getMTBUFElements (unsigned Opc)
 
bool getMTBUFHasVAddr (unsigned Opc)
 
bool getMTBUFHasSrsrc (unsigned Opc)
 
bool getMTBUFHasSoffset (unsigned Opc)
 
int getMUBUFBaseOpcode (unsigned Opc)
 
int getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int getMUBUFElements (unsigned Opc)
 
bool getMUBUFHasVAddr (unsigned Opc)
 
bool getMUBUFHasSrsrc (unsigned Opc)
 
bool getMUBUFHasSoffset (unsigned Opc)
 
bool getMUBUFIsBufferInv (unsigned Opc)
 
bool getSMEMIsBuffer (unsigned Opc)
 
bool getVOP1IsSingle (unsigned Opc)
 
bool getVOP2IsSingle (unsigned Opc)
 
bool getVOP3IsSingle (unsigned Opc)
 
bool isVOPC64DPP (unsigned Opc)
 
bool getMAIIsDGEMM (unsigned Opc)
 Returns true if MAI operation is a double precision GEMM. More...
 
bool getMAIIsGFX940XDL (unsigned Opc)
 
CanBeVOPD getCanBeVOPD (unsigned Opc)
 
unsigned getVOPDOpcode (unsigned Opc)
 
bool isVOPD (unsigned Opc)
 
unsigned mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
 
unsigned mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
 
int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
int getVOPDFull (unsigned OpX, unsigned OpY)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, intgetIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getVmcntBitMask (const IsaVersion &Version)
 
unsigned getExpcntBitMask (const IsaVersion &Version)
 
unsigned getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned getWaitcntBitMask (const IsaVersion &Version)
 
unsigned decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
Waitcnt decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
template<class T >
static bool isValidOpr (int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int getOprIdx (std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int getOprIdx (const StringRef Name, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int getOprIdx (int Id, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context, bool QuickCheck=true)
 
static unsigned getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
 
static bool isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
 
static bool decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
 
static int encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
 
static int encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool getHasColorExport (const Function &F)
 
bool getHasDepthExport (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isGraphics (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::ID CC)
 
bool isModuleEntryFunctionCC (CallingConv::ID CC)
 
bool isKernelCC (const Function *Func)
 
bool hasXNACK (const MCSubtargetInfo &STI)
 
bool hasSRAMECC (const MCSubtargetInfo &STI)
 
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool hasGFX10A16 (const MCSubtargetInfo &STI)
 
bool hasG16 (const MCSubtargetInfo &STI)
 
bool hasPackedD16 (const MCSubtargetInfo &STI)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
bool isGFX9 (const MCSubtargetInfo &STI)
 
bool isGFX9_GFX10 (const MCSubtargetInfo &STI)
 
bool isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
 
bool isGFX8Plus (const MCSubtargetInfo &STI)
 
bool isGFX9Plus (const MCSubtargetInfo &STI)
 
bool isGFX10 (const MCSubtargetInfo &STI)
 
bool isGFX10Plus (const MCSubtargetInfo &STI)
 
bool isGFX11 (const MCSubtargetInfo &STI)
 
bool isGFX11Plus (const MCSubtargetInfo &STI)
 
bool isNotGFX11Plus (const MCSubtargetInfo &STI)
 
bool isNotGFX10Plus (const MCSubtargetInfo &STI)
 
bool isGFX10Before1030 (const MCSubtargetInfo &STI)
 
bool isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool isGFX10_AEncoding (const MCSubtargetInfo &STI)
 
bool isGFX10_BEncoding (const MCSubtargetInfo &STI)
 
bool hasGFX10_3Insts (const MCSubtargetInfo &STI)
 
bool isGFX90A (const MCSubtargetInfo &STI)
 
bool isGFX940 (const MCSubtargetInfo &STI)
 
bool hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
 
bool hasMAIInsts (const MCSubtargetInfo &STI)
 
bool hasVOPD (const MCSubtargetInfo &STI)
 
int32_t getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
 
bool isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this operand support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableIntLiteralV216 (int32_t Literal)
 
bool isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isArgPassedInSGPR (const Argument *A)
 
static bool hasSMEMByteOffset (const MCSubtargetInfo &ST)
 
static bool hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
 
bool isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
 
static bool isDwordAligned (uint64_t ByteOffset)
 
uint64_t convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets. More...
 
Optional< int64_t > getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
 
Optional< int64_t > getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned getNumFlatOffsetBits (const MCSubtargetInfo &ST, bool Signed)
 For FLAT segment the offset must be positive; MSB is ignored and forced to zero. More...
 
bool splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
const GcnBufferFormatInfogetGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
 
const GcnBufferFormatInfogetGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READONLY int getSOPPWithRelaxation (uint16_t Opcode)
 
const LLVM_READONLY MIMGBaseOpcodeInfogetMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
const LLVM_READONLY MIMGDimInfogetMIMGDimInfo (unsigned DimEnum)
 
const LLVM_READONLY MIMGDimInfogetMIMGDimInfoByEncoding (uint8_t DimEnc)
 
const LLVM_READONLY MIMGDimInfogetMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
 
const LLVM_READONLY MIMGLZMappingInfogetMIMGLZMappingInfo (unsigned L)
 
const LLVM_READONLY MIMGMIPMappingInfogetMIMGMIPMappingInfo (unsigned MIP)
 
const LLVM_READONLY MIMGBiasMappingInfogetMIMGBiasMappingInfo (unsigned Bias)
 
const LLVM_READONLY MIMGOffsetMappingInfogetMIMGOffsetMappingInfo (unsigned Offset)
 
const LLVM_READONLY MIMGG16MappingInfogetMIMGG16MappingInfo (unsigned G)
 
const LLVM_READONLY MIMGInfogetMIMGInfo (unsigned Opc)
 
LLVM_READNONE bool isKernel (CallingConv::ID CC)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 
LLVM_READNONE bool isInlinableIntLiteral (int64_t Literal)
 Is this literal inlinable, and not one of the values intended for floating point values. More...
 
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
LLVM_READNONE bool isLegal64BitDPPControl (unsigned DC)
 
Align getAlign (DataLayout const &DL, const GlobalVariable *GV)
 
static bool shouldLowerLDSToStruct (const GlobalVariable &GV, const Function *F)
 
bool isLDSVariableToLower (const GlobalVariable &GV)
 
std::vector< GlobalVariable * > findLDSVariablesToLower (Module &M, const Function *F)
 
bool isReallyAClobber (const Value *Ptr, MemoryDef *Def, AAResults *AA)
 Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints. More...
 
bool isClobberedInFunction (const LoadInst *Load, MemorySSA *MSSA, AAResults *AA)
 Check is a Load is clobbered in its function. More...
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 
const int OPR_ID_UNKNOWN = -1
 
const int OPR_ID_UNSUPPORTED = -2
 
const int OPR_ID_DUPLICATE = -3
 
const int OPR_VAL_INVALID = -4
 

Enumeration Type Documentation

◆ ArchFeatureKind

Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 
FEATURE_WAVE32 
FEATURE_XNACK 
FEATURE_SRAMECC 

Definition at line 121 of file TargetParser.h.

◆ Fixups

Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ GPUKind

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE 
GK_R600 
GK_R630 
GK_RS880 
GK_RV670 
GK_RV710 
GK_RV730 
GK_RV770 
GK_CEDAR 
GK_CYPRESS 
GK_JUNIPER 
GK_REDWOOD 
GK_SUMO 
GK_BARTS 
GK_CAICOS 
GK_CAYMAN 
GK_TURKS 
GK_R600_FIRST 
GK_R600_LAST 
GK_GFX600 
GK_GFX601 
GK_GFX602 
GK_GFX700 
GK_GFX701 
GK_GFX702 
GK_GFX703 
GK_GFX704 
GK_GFX705 
GK_GFX801 
GK_GFX802 
GK_GFX803 
GK_GFX805 
GK_GFX810 
GK_GFX900 
GK_GFX902 
GK_GFX904 
GK_GFX906 
GK_GFX908 
GK_GFX909 
GK_GFX90A 
GK_GFX90C 
GK_GFX940 
GK_GFX1010 
GK_GFX1011 
GK_GFX1012 
GK_GFX1013 
GK_GFX1030 
GK_GFX1031 
GK_GFX1032 
GK_GFX1033 
GK_GFX1034 
GK_GFX1035 
GK_GFX1036 
GK_GFX1100 
GK_GFX1101 
GK_GFX1102 
GK_GFX1103 
GK_AMDGCN_FIRST 
GK_AMDGCN_LAST 

Definition at line 38 of file TargetParser.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned
Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_IMM_FP16_DEFERRED 
OPERAND_REG_IMM_FP32_DEFERRED 
OPERAND_REG_IMM_V2FP16 
OPERAND_REG_IMM_V2INT16 
OPERAND_REG_IMM_V2INT32 
OPERAND_REG_IMM_V2FP32 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT32 
OPERAND_REG_INLINE_C_V2FP32 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 
OPERAND_REG_INLINE_AC_INT16 

Operands with an AccVGPR register or inline constant.

OPERAND_REG_INLINE_AC_INT32 
OPERAND_REG_INLINE_AC_FP16 
OPERAND_REG_INLINE_AC_FP32 
OPERAND_REG_INLINE_AC_FP64 
OPERAND_REG_INLINE_AC_V2INT16 
OPERAND_REG_INLINE_AC_V2FP16 
OPERAND_REG_INLINE_AC_V2INT32 
OPERAND_REG_INLINE_AC_V2FP32 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_REG_INLINE_AC_FIRST 
OPERAND_REG_INLINE_AC_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 

Definition at line 152 of file SIDefines.h.

◆ TargetIndex

Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 347 of file AMDGPU.h.

Function Documentation

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits ( const MCSubtargetInfo ST,
uint64_t  ByteOffset 
)

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 2254 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), isDwordAligned(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ decodeCustomOperand()

static bool llvm::AMDGPU::decodeCustomOperand ( const CustomOperandVal Opr,
int  Size,
unsigned  Code,
int Idx,
StringRef Name,
unsigned &  Val,
bool &  IsDefault,
const MCSubtargetInfo STI 
)
static

Definition at line 1223 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Hwreg::Opr.

Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 1073 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by decodeWaitcnt().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 1078 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by decodeWaitcnt().

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 1065 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by decodeWaitcnt().

◆ decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt ( const IsaVersion Version,
unsigned  Encoded 
)

◆ decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned &  Vmcnt,
unsigned &  Expcnt,
unsigned &  Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9) Vmcnt = Waitcnt[15:14,3:0] (gfx9,10) Vmcnt = Waitcnt[15:10] (gfx11+) Expcnt = Waitcnt[6:4] (pre-gfx11) Expcnt = Waitcnt[2:0] (gfx11+) Lgkmcnt = Waitcnt[11:8] (pre-gfx10) Lgkmcnt = Waitcnt[13:8] (gfx10) Lgkmcnt = Waitcnt[9:4] (gfx11+)

Definition at line 1083 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and llvm::IndexedInstrProf::Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ encodeCustomOperand()

static int llvm::AMDGPU::encodeCustomOperand ( const CustomOperandVal Opr,
int  Size,
const StringRef  Name,
int64_t  InputVal,
unsigned &  UsedOprMask,
const MCSubtargetInfo STI 
)
static

◆ encodeCustomOperandVal()

static int llvm::AMDGPU::encodeCustomOperandVal ( const CustomOperandVal Op,
int64_t  InputVal 
)
static

Definition at line 1240 of file AMDGPUBaseInfo.cpp.

References OPR_VAL_INVALID.

Referenced by encodeCustomOperand().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 1107 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 1113 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by encodeWaitcnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 1098 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion Version,
const Waitcnt Decoded 
)

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[2:0] = Expcnt (gfx11+) Waitcnt[3:0] = Vmcnt (pre-gfx9) Waitcnt[3:0] = Vmcnt[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt (pre-gfx11) Waitcnt[9:4] = Lgkmcnt (gfx11+) Waitcnt[11:8] = Lgkmcnt (pre-gfx10) Waitcnt[13:8] = Lgkmcnt (gfx10) Waitcnt[15:10] = Vmcnt (gfx11+) Waitcnt[15:14] = Vmcnt[5:4] (gfx9,10)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 1119 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and llvm::IndexedInstrProf::Version.

Referenced by encodeWaitcnt().

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > &  Values)

Definition at line 182 of file TargetParser.cpp.

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > &  Values)

Definition at line 188 of file TargetParser.cpp.

◆ findLDSVariablesToLower()

std::vector< GlobalVariable * > llvm::AMDGPU::findLDSVariablesToLower ( Module M,
const Function F 
)

Definition at line 103 of file AMDGPUMemoryUtils.cpp.

References F, isLDSVariableToLower(), M, and shouldLowerLDSToStruct().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)

◆ getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp ( const MIMGBaseOpcodeInfo BaseOpcode,
const MIMGDimInfo Dim,
bool  IsA16,
bool  IsG16Supported 
)

◆ getAlign()

Align llvm::AMDGPU::getAlign ( DataLayout const DL,
const GlobalVariable GV 
)

◆ getAmdhsaCodeObjectVersion()

unsigned llvm::AMDGPU::getAmdhsaCodeObjectVersion ( )

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind  AK)

Definition at line 170 of file TargetParser.cpp.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind  AK)

Definition at line 176 of file TargetParser.cpp.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind  AK)

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind  AK)

◆ getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)

◆ getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset ( MachineRegisterInfo MRI,
Register  Reg,
GISelKnownBits KnownBits = nullptr 
)

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t  Opcode)

◆ getCanBeVOPD()

LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD ( unsigned  Opc)

Definition at line 417 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by shouldScheduleVOPDAdjacent().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName ( const Triple T,
StringRef  Arch 
)

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)

◆ getDefaultAmdhsaKernelDescriptor()

amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor ( const MCSubtargetInfo STI)

◆ getDefaultCustomOperandEncoding()

static unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding ( const CustomOperandVal Opr,
int  Size,
const MCSubtargetInfo STI 
)
static

◆ getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32 ( uint16_t  Opcode)

◆ getDPPOp64()

LLVM_READONLY int llvm::AMDGPU::getDPPOp64 ( uint16_t  Opcode)

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 1045 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV ( uint16_t  Opcode)
Returns
SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS ( uint16_t  Opcode)
Returns
ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS ( uint16_t  Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getFlatScratchInstSVfromSVS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS ( uint16_t  Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SVS (SADDR + VADDR) form.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getGcnBufferFormatInfo() [1/2]

const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t  BitsPerComp,
uint8_t  NumComponents,
uint8_t  NumFormat,
const MCSubtargetInfo STI 
)

Definition at line 2395 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by getBufferFormatWithCompCount().

◆ getGcnBufferFormatInfo() [2/2]

const LLVM_READONLY GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t  Format,
const MCSubtargetInfo STI 
)

Definition at line 2408 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp ( uint16_t  Opcode)
Returns
SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

◆ getGlobalVaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp ( uint16_t  Opcode)
Returns
VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport ( const Function F)

Definition at line 1657 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, F, and getIntegerAttribute().

Referenced by generateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport ( const Function F)

Definition at line 1664 of file AMDGPUBaseInfo.cpp.

References F, and getIntegerAttribute().

Referenced by generateEndPgm().

◆ getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition ( )
Returns
The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line 174 of file AMDGPUBaseInfo.cpp.

References AmdhsaCodeObjectVersion, llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET, and llvm_unreachable.

◆ getHsaAbiVersion()

Optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion ( const MCSubtargetInfo STI)

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst ( uint16_t  Opcode)

Check if Opcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

◆ getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode ( unsigned  BaseOpcode,
unsigned  Dim 
)

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned  Intr)

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function F)

Definition at line 1653 of file AMDGPUBaseInfo.cpp.

References F, and getIntegerAttribute().

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function F,
StringRef  Name,
int  Default 
)
Returns
Integer value requested using F's Name attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

Definition at line 999 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), and F.

Referenced by llvm::GCNSubtarget::getBaseMaxNumSGPRs(), llvm::GCNSubtarget::getBaseMaxNumVGPRs(), getHasColorExport(), getHasDepthExport(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), getInitialPSInputAddr(), and llvm::AMDGPUTTIImpl::getUnrollingPreferences().

◆ getIntegerPairAttribute()

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function F,
StringRef  Name,
std::pair< int, int Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1014 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), and F.

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef  GPU)

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 1049 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getMAIIsDGEMM()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM ( unsigned  Opc)

Returns true if MAI operation is a double precision GEMM.

Definition at line 407 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isDGEMM().

◆ getMAIIsGFX940XDL()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL ( unsigned  Opc)

Definition at line 412 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isXDL().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( unsigned  Opc,
unsigned  NewChannels 
)

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)

Definition at line 447 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 1913 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, and llvm::Triple::r600.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().

◆ getMFMAEarlyClobberOp()

LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp ( uint16_t  Opcode)
Returns
earlyclobber version of a MAC MFMA is exists.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), and llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMIMGBaseOpcode()

const LLVM_READONLY MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode ( unsigned  Opc)

Definition at line 206 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.

◆ getMIMGBaseOpcodeInfo()

const LLVM_READONLY MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned  BaseOpcode)

◆ getMIMGBiasMappingInfo()

const LLVM_READONLY MIMGBiasMappingInfo* llvm::AMDGPU::getMIMGBiasMappingInfo ( unsigned  Bias)

◆ getMIMGDimInfo()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfo ( unsigned  DimEnum)

◆ getMIMGDimInfoByAsmSuffix()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef  AsmSuffix)

◆ getMIMGDimInfoByEncoding()

const LLVM_READONLY MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t  DimEnc)

◆ getMIMGG16MappingInfo()

const LLVM_READONLY MIMGG16MappingInfo* llvm::AMDGPU::getMIMGG16MappingInfo ( unsigned  G)

◆ getMIMGInfo()

const LLVM_READONLY MIMGInfo* llvm::AMDGPU::getMIMGInfo ( unsigned  Opc)

◆ getMIMGLZMappingInfo()

const LLVM_READONLY MIMGLZMappingInfo* llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned  L)

◆ getMIMGMIPMappingInfo()

const LLVM_READONLY MIMGMIPMappingInfo* llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned  MIP)

◆ getMIMGOffsetMappingInfo()

const LLVM_READONLY MIMGOffsetMappingInfo* llvm::AMDGPU::getMIMGOffsetMappingInfo ( unsigned  Offset)

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode ( unsigned  BaseOpcode,
unsigned  MIMGEncoding,
unsigned  VDataDwords,
unsigned  VAddrDwords 
)

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode ( unsigned  Opc)

Definition at line 318 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements ( unsigned  Opc)

Definition at line 328 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset ( unsigned  Opc)

Definition at line 343 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc ( unsigned  Opc)

Definition at line 338 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr ( unsigned  Opc)

Definition at line 333 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode ( unsigned  BaseOpc,
unsigned  Elements 
)

Definition at line 323 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned  Opc)

Definition at line 348 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements ( unsigned  Opc)

Definition at line 358 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned  Opc)

Definition at line 373 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned  Opc)

Definition at line 368 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned  Opc)

Definition at line 363 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv ( unsigned  Opc)

Definition at line 378 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode ( unsigned  BaseOpc,
unsigned  Elements 
)

Definition at line 353 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition ( )
Returns
The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line 157 of file AMDGPUBaseInfo.cpp.

References AmdhsaCodeObjectVersion, llvm_unreachable, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)

Referenced by llvm::SITargetLowering::AddIMGInit(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::SIRegisterInfo::buildSpillLoadStore(), collectVOPModifiers(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), cvtVOP3DstOpSelOnly(), decodeOperand_AVLdSt_Any(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), getFlatScratchSpillOpcode(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::getRegClass(), llvm::SIRegisterInfo::getScratchInstrOffset(), getSrcOperandIndices(), llvm::SIInstrInfo::hasModifiers(), insertNamedMCOperand(), IsAGPROperand(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isOperandLegal(), isSendMsgTraceDataOrGDS(), isValidDPP8(), isVOPD(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), AMDGPUMCInstLower::lower(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), nodesHaveSameOperandValue(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIInstrInfo::removeModOperands(), and llvm::SIInstrInfo::verifyInstruction().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits ( const MCSubtargetInfo ST,
bool  Signed 
)

For FLAT segment the offset must be positive; MSB is ignored and forced to zero.

Returns
The number of bits available for the offset field in flat instructions.

Definition at line 2289 of file AMDGPUBaseInfo.cpp.

References isGFX10(), Signed, and llvm::ARM_MB::ST.

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc Desc,
unsigned  OpNo 
)
inline

Definition at line 933 of file AMDGPUBaseInfo.h.

References getOperandSize(), and llvm::MCInstrDesc::OpInfo.

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo OpInfo)
inline

◆ getOprIdx() [1/3]

template<class T >
static int llvm::AMDGPU::getOprIdx ( const StringRef  Name,
const CustomOperand< T OpInfo[],
int  OpInfoSize,
T  Context 
)
static

Definition at line 1166 of file AMDGPUBaseInfo.cpp.

References Context, and llvm::Test.

◆ getOprIdx() [2/3]

template<class T >
static int llvm::AMDGPU::getOprIdx ( int  Id,
const CustomOperand< T OpInfo[],
int  OpInfoSize,
T  Context,
bool  QuickCheck = true 
)
static

◆ getOprIdx() [3/3]

template<class T >
static int llvm::AMDGPU::getOprIdx ( std::function< bool(const CustomOperand< T > &)>  Test,
const CustomOperand< T OpInfo[],
int  OpInfoSize,
T  Context 
)
static

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass RC)

Get the size in bits of a register from the register class RC.

Definition at line 2089 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

Get the size in bits of a register from the register class RC.

Definition at line 1984 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo MRI,
const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t  Opcode)

◆ getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer ( unsigned  Opc)

Definition at line 383 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getSMRDEncodedLiteralOffset32()

Optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 2280 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), isDwordAligned(), llvm::None, and llvm::ARM_MB::ST.

◆ getSMRDEncodedOffset()

Optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset,
bool  IsBuffer 
)
Returns
The encoding that will be used for ByteOffset in the SMRD offset field, or None if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 2263 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isLegalSMRDEncodedUnsignedOffset(), llvm::None, and llvm::ARM_MB::ST.

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

◆ getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation ( uint16_t  Opcode)

◆ getTotalNumVGPRs()

int llvm::AMDGPU::getTotalNumVGPRs ( bool  has90AInsts,
int32_t  ArgNumAGPR,
int32_t  ArgNumVGPR 
)

◆ getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp ( uint16_t  Opcode)

◆ getVCMPXOpFromVCMP()

LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP ( uint16_t  Opcode)
Returns
v_cmpx version of a v_cmp instruction.

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 1039 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle ( unsigned  Opc)

Definition at line 388 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle ( unsigned  Opc)

Definition at line 393 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle ( unsigned  Opc)

Definition at line 398 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull ( unsigned  OpX,
unsigned  OpY 
)

Definition at line 451 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPDOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode ( unsigned  Opc)

Definition at line 425 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 1053 of file AMDGPUBaseInfo.cpp.

References llvm::IndexedInstrProf::Version.

Referenced by encodeWaitcnt().

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch ( const MCSubtargetInfo STI)

◆ hasAtomicFaddRtnForTy()

bool llvm::AMDGPU::hasAtomicFaddRtnForTy ( const GCNSubtarget Subtarget,
const LLT Ty 
)

◆ hasG16()

bool llvm::AMDGPU::hasG16 ( const MCSubtargetInfo STI)

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts ( const MCSubtargetInfo STI)

◆ hasGFX10A16()

bool llvm::AMDGPU::hasGFX10A16 ( const MCSubtargetInfo STI)

Definition at line 1733 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts ( const MCSubtargetInfo STI)

Definition at line 1834 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo STI)

Definition at line 1729 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo STI)

◆ hasSMEMByteOffset()

static bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo ST)
static

◆ hasSMRDSignedImmOffset()

static bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo ST)
static

Definition at line 2232 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC ( const MCSubtargetInfo STI)

Definition at line 1725 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ hasVOPD()

bool llvm::AMDGPU::hasVOPD ( const MCSubtargetInfo STI)

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo STI)

Definition at line 1721 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t Header,
const MCSubtargetInfo STI 
)

◆ isArgPassedInSGPR()

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument A)

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo STI)

◆ isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction ( const LoadInst Load,
MemorySSA MSSA,
AAResults AA 
)

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)

◆ isDwordAligned()

static bool llvm::AMDGPU::isDwordAligned ( uint64_t  ByteOffset)
static

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID  CC)

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned  AS)
inline

◆ isFoldableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isFoldableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 2188 of file AMDGPUBaseInfo.cpp.

References assert().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo STI)

Definition at line 1806 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by hasSMEMByteOffset().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo STI)

◆ isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding ( const MCSubtargetInfo STI)

Definition at line 1810 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding ( const MCSubtargetInfo STI)

Definition at line 1814 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX10Before1030().

◆ isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030 ( const MCSubtargetInfo STI)

Definition at line 1802 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX10_BEncoding().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus ( const MCSubtargetInfo STI)

◆ isGFX11()

bool llvm::AMDGPU::isGFX11 ( const MCSubtargetInfo STI)

Definition at line 1786 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX11Plus().

◆ isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus ( const MCSubtargetInfo STI)

◆ isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10 ( const MCSubtargetInfo STI)

Definition at line 1766 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX9(), and isVI().

◆ isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus ( const MCSubtargetInfo STI)

Definition at line 1770 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and isVI().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo STI)

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A ( const MCSubtargetInfo STI)

◆ isGFX940()

bool llvm::AMDGPU::isGFX940 ( const MCSubtargetInfo STI)

Definition at line 1826 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10 ( const MCSubtargetInfo STI)

Definition at line 1762 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX9().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus ( const MCSubtargetInfo STI)

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue GV)

◆ isGraphics()

LLVM_READNONE bool llvm::AMDGPU::isGraphics ( CallingConv::ID  cc)

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue GV)

◆ isHsaAbiVersion2()

bool llvm::AMDGPU::isHsaAbiVersion2 ( const MCSubtargetInfo STI)

◆ isHsaAbiVersion3()

bool llvm::AMDGPU::isHsaAbiVersion3 ( const MCSubtargetInfo STI)
Returns
True if HSA OS ABI Version identification is 3, false otherwise.

Definition at line 130 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, and getHsaAbiVersion().

Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), and isHsaAbiVersion3AndAbove().

◆ isHsaAbiVersion3AndAbove()

bool llvm::AMDGPU::isHsaAbiVersion3AndAbove ( const MCSubtargetInfo STI)
Returns
True if HSA OS ABI Version identification is 3 and above, false otherwise.

Definition at line 148 of file AMDGPUBaseInfo.cpp.

References isHsaAbiVersion3(), isHsaAbiVersion4(), and isHsaAbiVersion5().

Referenced by llvm::AMDGPUAsmPrinter::emitFunctionEntryLabel().

◆ isHsaAbiVersion4()

bool llvm::AMDGPU::isHsaAbiVersion4 ( const MCSubtargetInfo STI)
Returns
True if HSA OS ABI Version identification is 4, false otherwise.

Definition at line 136 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, and getHsaAbiVersion().

Referenced by isHsaAbiVersion3AndAbove().

◆ isHsaAbiVersion5()

bool llvm::AMDGPU::isHsaAbiVersion5 ( const MCSubtargetInfo STI)
Returns
True if HSA OS ABI Version identification is 5, false otherwise.

Definition at line 142 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, and getHsaAbiVersion().

Referenced by llvm::AMDGPUAsmPrinter::AMDGPUAsmPrinter(), and isHsaAbiVersion3AndAbove().

◆ isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t  Literal)
inline

◆ isInlinableIntLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteralV216 ( int32_t  Literal)

Definition at line 2177 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral().

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 2162 of file AMDGPUBaseInfo.cpp.

References assert(), and isInlinableLiteral16().

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned  IntrID)
Returns
true if the intrinsic is divergent

Definition at line 2391 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC)
inline

◆ isKernelCC()

bool llvm::AMDGPU::isKernelCC ( const Function Func)

Definition at line 1717 of file AMDGPUBaseInfo.cpp.

References isModuleEntryFunctionCC().

Referenced by shouldLowerLDSToStruct().

◆ isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower ( const GlobalVariable GV)

◆ isLegal64BitDPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegal64BitDPPControl ( unsigned  DC)
inline

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset ( const MCSubtargetInfo ST,
int64_t  EncodedOffset,
bool  IsBuffer 
)

Definition at line 2242 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset(), and llvm::ARM_MB::ST.

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset ( const MCSubtargetInfo ST,
int64_t  EncodedOffset 
)

Definition at line 2236 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset(), and llvm::ARM_MB::ST.

Referenced by getSMRDEncodedOffset().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

◆ isLegalVOP3PShuffleMask()

bool llvm::AMDGPU::isLegalVOP3PShuffleMask ( ArrayRef< int Mask)

◆ isModuleEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC ( CallingConv::ID  CC)

Definition at line 1708 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, CC, and isEntryFunctionCC().

Referenced by isKernelCC().

◆ isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus ( const MCSubtargetInfo STI)

Definition at line 1798 of file AMDGPUBaseInfo.cpp.

References isCI(), isGFX9(), isSI(), and isVI().

◆ isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus ( const MCSubtargetInfo STI)

Definition at line 1794 of file AMDGPUBaseInfo.cpp.

References isGFX11Plus().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue GV)

◆ isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber ( const Value Ptr,
MemoryDef Def,
AAResults AA 
)

Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line 118 of file AMDGPUMemoryUtils.cpp.

References llvm::tgtok::Def, I, and Ptr.

Referenced by isClobberedInFunction().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( unsigned  Reg,
const MCRegisterInfo TRI 
)

Is Reg - scalar register.

Definition at line 1849 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), llvm::AMDGPU::CPol::SCC, and TRI.

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo STI)

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isSymbolicCustomOperandEncoding()

static bool llvm::AMDGPU::isSymbolicCustomOperandEncoding ( const CustomOperandVal Opr,
int  Size,
unsigned  Code,
bool &  HasNonDefaultVal,
const MCSubtargetInfo STI 
)
static

◆ isValidOpr()

template<class T >
static bool llvm::AMDGPU::isValidOpr ( int  Idx,
const CustomOperand< T OpInfo[],
int  OpInfoSize,
T  Context 
)
static

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo STI)

◆ isVOPC64DPP()

LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP ( unsigned  Opc)

◆ isVOPD()

LLVM_READONLY bool llvm::AMDGPU::isVOPD ( unsigned  Opc)

Definition at line 430 of file AMDGPUBaseInfo.cpp.

References getNamedOperandIdx().

Referenced by getSrcOperandIndices().

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned  Intr)

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned  Intr)

◆ mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode ( unsigned  Opc)

Definition at line 434 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

◆ mapWMMA3AddrTo2AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode ( unsigned  Opc)

Definition at line 439 of file AMDGPUBaseInfo.cpp.

References Info.

◆ mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg ( unsigned  Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 1929 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef  CPU)

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef  CPU)

Definition at line 161 of file TargetParser.cpp.

References GK_NONE.

Referenced by getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 995 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::r600.

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().

◆ shouldLowerLDSToStruct()

static bool llvm::AMDGPU::shouldLowerLDSToStruct ( const GlobalVariable GV,
const Function F 
)
static

◆ splitMUBUFOffset()

bool llvm::AMDGPU::splitMUBUFOffset ( uint32_t  Imm,
uint32_t SOffset,
uint32_t ImmOffset,
const GCNSubtarget Subtarget,
Align  Alignment 
)

Variable Documentation

◆ OPR_ID_DUPLICATE

const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3

Definition at line 25 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand().

◆ OPR_ID_UNKNOWN

const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1

Definition at line 23 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getOprIdx().

◆ OPR_ID_UNSUPPORTED

const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2

Definition at line 24 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getOprIdx().

◆ OPR_VAL_INVALID

const int llvm::AMDGPU::OPR_VAL_INVALID = -4

Definition at line 26 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperandVal().

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 1316 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 1317 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 1318 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().