llvm::AMDGPU Namespace Reference

Namespaces
namespace	CPol
namespace	DepCtr
namespace	DPP
namespace	ElfNote
namespace	EncValues
namespace	Exp
namespace	HSAMD
namespace	Hwreg
namespace	ImplicitArg
namespace	IsaInfo
namespace	MTBUFFormat
namespace	PALMD
namespace	SDWA
namespace	SendMsg
namespace	Swizzle
namespace	UfmtGFX10
namespace	UfmtGFX11
namespace	VGPRIndexMode
namespace	VirtRegFlag
namespace	VOP3PEncoding
namespace	VOPD

Classes
struct	CanBeVOPD
struct	CustomOperand
struct	CustomOperandVal
struct	D16ImageDimIntrinsic
struct	GcnBufferFormatInfo
struct	ImageDimIntrinsicInfo
struct	IsaVersion
	Instruction set architecture version. More...
struct	MAIInstInfo
struct	MIMGBaseOpcodeInfo
struct	MIMGBiasMappingInfo
struct	MIMGDimInfo
struct	MIMGG16MappingInfo
struct	MIMGInfo
struct	MIMGLZMappingInfo
struct	MIMGMIPMappingInfo
struct	MIMGOffsetMappingInfo
struct	MTBUFInfo
struct	MUBUFInfo
struct	RsrcIntrinsic
struct	SMInfo
struct	VOPC64DPPInfo
struct	VOPDComponentInfo
struct	VOPDInfo
struct	VOPInfo
struct	VOPTrue16Info
struct	Waitcnt
	Represents the counter values to wait for in an s_waitcnt instruction. More...
struct	WMMAOpcodeMappingInfo

Enumerations
enum	GPUKind : uint32_t {   GK_NONE = 0 , GK_R600 = 1 , GK_R630 = 2 , GK_RS880 = 3 ,   GK_RV670 = 4 , GK_RV710 = 5 , GK_RV730 = 6 , GK_RV770 = 7 ,   GK_CEDAR = 8 , GK_CYPRESS = 9 , GK_JUNIPER = 10 , GK_REDWOOD = 11 ,   GK_SUMO = 12 , GK_BARTS = 13 , GK_CAICOS = 14 , GK_CAYMAN = 15 ,   GK_TURKS = 16 , GK_R600_FIRST = GK_R600 , GK_R600_LAST = GK_TURKS , GK_GFX600 = 32 ,   GK_GFX601 = 33 , GK_GFX602 = 34 , GK_GFX700 = 40 , GK_GFX701 = 41 ,   GK_GFX702 = 42 , GK_GFX703 = 43 , GK_GFX704 = 44 , GK_GFX705 = 45 ,   GK_GFX801 = 50 , GK_GFX802 = 51 , GK_GFX803 = 52 , GK_GFX805 = 53 ,   GK_GFX810 = 54 , GK_GFX900 = 60 , GK_GFX902 = 61 , GK_GFX904 = 62 ,   GK_GFX906 = 63 , GK_GFX908 = 64 , GK_GFX909 = 65 , GK_GFX90A = 66 ,   GK_GFX90C = 67 , GK_GFX940 = 68 , GK_GFX941 = 69 , GK_GFX942 = 70 ,   GK_GFX1010 = 71 , GK_GFX1011 = 72 , GK_GFX1012 = 73 , GK_GFX1013 = 74 ,   GK_GFX1030 = 75 , GK_GFX1031 = 76 , GK_GFX1032 = 77 , GK_GFX1033 = 78 ,   GK_GFX1034 = 79 , GK_GFX1035 = 80 , GK_GFX1036 = 81 , GK_GFX1100 = 90 ,   GK_GFX1101 = 91 , GK_GFX1102 = 92 , GK_GFX1103 = 93 , GK_GFX1150 = 94 ,   GK_GFX1151 = 95 , GK_AMDGCN_FIRST = GK_GFX600 , GK_AMDGCN_LAST = GK_GFX1151 }
	GPU kinds supported by the AMDGPU target. More...
enum	ArchFeatureKind : uint32_t {   FEATURE_NONE = 0 , FEATURE_FMA = 1 << 1 , FEATURE_LDEXP = 1 << 2 , FEATURE_FP64 = 1 << 3 ,   FEATURE_FAST_FMA_F32 = 1 << 4 , FEATURE_FAST_DENORMAL_F32 = 1 << 5 , FEATURE_WAVE32 = 1 << 6 , FEATURE_XNACK = 1 << 7 ,   FEATURE_SRAMECC = 1 << 8 , FEATURE_WGP = 1 << 9 }
enum	TargetIndex {   TI_CONSTDATA_START , TI_SCRATCH_RSRC_DWORD0 , TI_SCRATCH_RSRC_DWORD1 , TI_SCRATCH_RSRC_DWORD2 ,   TI_SCRATCH_RSRC_DWORD3 }
enum	Fixups { fixup_si_sopp_br = FirstTargetFixupKind , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	OperandType : unsigned {   OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET , OPERAND_REG_IMM_INT64 , OPERAND_REG_IMM_INT16 , OPERAND_REG_IMM_FP32 ,   OPERAND_REG_IMM_FP64 , OPERAND_REG_IMM_FP16 , OPERAND_REG_IMM_FP16_DEFERRED , OPERAND_REG_IMM_FP32_DEFERRED ,   OPERAND_REG_IMM_V2FP16 , OPERAND_REG_IMM_V2INT16 , OPERAND_REG_IMM_V2INT32 , OPERAND_REG_IMM_V2FP32 ,   OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_INT32 , OPERAND_REG_INLINE_C_INT64 , OPERAND_REG_INLINE_C_FP16 ,   OPERAND_REG_INLINE_C_FP32 , OPERAND_REG_INLINE_C_FP64 , OPERAND_REG_INLINE_C_V2INT16 , OPERAND_REG_INLINE_C_V2FP16 ,   OPERAND_REG_INLINE_C_V2INT32 , OPERAND_REG_INLINE_C_V2FP32 , OPERAND_KIMM32 , OPERAND_KIMM16 ,   OPERAND_REG_INLINE_AC_INT16 , OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_FP16 , OPERAND_REG_INLINE_AC_FP32 ,   OPERAND_REG_INLINE_AC_FP64 , OPERAND_REG_INLINE_AC_V2INT16 , OPERAND_REG_INLINE_AC_V2FP16 , OPERAND_REG_INLINE_AC_V2INT32 ,   OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_INPUT_MODS , OPERAND_SDWA_VOPC_DST , OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32 ,   OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32 , OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16 ,   OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST , OPERAND_KIMM_FIRST = OPERAND_KIMM32 ,   OPERAND_KIMM_LAST = OPERAND_KIMM16 }
enum	AMDGPUFltRounds : int8_t {   TowardZero = static_cast<int8_t>(RoundingMode::TowardZero) , NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven) , TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive) , TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative) ,   NearestTiesToAwayUnsupported , Dynamic = static_cast<int8_t>(RoundingMode::Dynamic) , NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven , NearestTiesToEvenF32_TowardPositiveF64 = 8 ,   NearestTiesToEvenF32_TowardNegativeF64 = 9 , NearestTiesToEvenF32_TowardZeroF64 = 10 , TowardPositiveF32_NearestTiesToEvenF64 = 11 , TowardPositiveF32_TowardPositiveF64 = TowardPositive ,   TowardPositiveF32_TowardNegativeF64 = 12 , TowardPositiveF32_TowardZeroF64 = 13 , TowardNegativeF32_NearestTiesToEvenF64 = 14 , TowardNegativeF32_TowardPositiveF64 = 15 ,   TowardNegativeF32_TowardNegativeF64 = TowardNegative , TowardNegativeF32_TowardZeroF64 = 16 , TowardZeroF32_NearestTiesToEvenF64 = 17 , TowardZeroF32_TowardPositiveF64 = 18 ,   TowardZeroF32_TowardNegativeF64 = 19 , TowardZeroF32_TowardZeroF64 = TowardZero , Invalid = static_cast<int8_t>(RoundingMode::Invalid) }
	Return values used for llvm.get.rounding. More...
enum	{ AMDHSA_COV3 = 3 , AMDHSA_COV4 = 4 , AMDHSA_COV5 = 5 }

Functions
StringRef	getArchNameAMDGCN (GPUKind AK)
StringRef	getArchNameR600 (GPUKind AK)
StringRef	getCanonicalArchName (const Triple &T, StringRef Arch)
GPUKind	parseArchAMDGCN (StringRef CPU)
GPUKind	parseArchR600 (StringRef CPU)
unsigned	getArchAttrAMDGCN (GPUKind AK)
unsigned	getArchAttrR600 (GPUKind AK)
void	fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
void	fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
IsaVersion	getIsaVersion (StringRef GPU)
void	fillAMDGPUFeatureMap (StringRef GPU, const Triple &T, StringMap< bool > &Features)
	Fills Features map with default values for given target GPU.
bool	insertWaveSizeFeature (StringRef GPU, const Triple &T, StringMap< bool > &Features, std::string &ErrorMsg)
	Inserts wave size feature for given GPU into features map.
bool	isFlatGlobalAddrSpace (unsigned AS)
bool	isExtendedGlobalAddrSpace (unsigned AS)
static bool	addrspacesMayAlias (unsigned AS1, unsigned AS2)
std::pair< Register, unsigned >	getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr)
	Returns base register and constant offset.
bool	hasAtomicFaddRtnForTy (const GCNSubtarget &Subtarget, const LLT &Ty)
unsigned	getIntrinsicID (const MachineInstr &I)
	Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
const RsrcIntrinsic *	lookupRsrcIntrinsic (unsigned Intr)
const D16ImageDimIntrinsic *	lookupD16ImageDimIntrinsic (unsigned Intr)
const ImageDimIntrinsicInfo *	getImageDimIntrinsicInfo (unsigned Intr)
const ImageDimIntrinsicInfo *	getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)
LLVM_READONLY int	getVOPe64 (uint16_t Opcode)
LLVM_READONLY int	getVOPe32 (uint16_t Opcode)
LLVM_READONLY int	getSDWAOp (uint16_t Opcode)
LLVM_READONLY int	getDPPOp32 (uint16_t Opcode)
LLVM_READONLY int	getDPPOp64 (uint16_t Opcode)
LLVM_READONLY int	getBasicFromSDWAOp (uint16_t Opcode)
LLVM_READONLY int	getCommuteRev (uint16_t Opcode)
LLVM_READONLY int	getCommuteOrig (uint16_t Opcode)
LLVM_READONLY int	getAddr64Inst (uint16_t Opcode)
LLVM_READONLY int	getIfAddr64Inst (uint16_t Opcode)
	Check if Opcode is an Addr64 opcode.
LLVM_READONLY int	getAtomicNoRetOp (uint16_t Opcode)
LLVM_READONLY int	getSOPKOp (uint16_t Opcode)
LLVM_READONLY int	getGlobalSaddrOp (uint16_t Opcode)
LLVM_READONLY int	getGlobalVaddrOp (uint16_t Opcode)
LLVM_READONLY int	getVCMPXNoSDstOp (uint16_t Opcode)
LLVM_READONLY int	getFlatScratchInstSTfromSS (uint16_t Opcode)
LLVM_READONLY int	getFlatScratchInstSVfromSVS (uint16_t Opcode)
LLVM_READONLY int	getFlatScratchInstSSfromSV (uint16_t Opcode)
LLVM_READONLY int	getFlatScratchInstSVfromSS (uint16_t Opcode)
LLVM_READONLY int	getMFMAEarlyClobberOp (uint16_t Opcode)
LLVM_READONLY int	getVCMPXOpFromVCMP (uint16_t Opcode)
unsigned	getRegBitWidth (const TargetRegisterClass &RC)
	Get the size in bits of a register from the register class RC.
bool	isHsaAbi (const MCSubtargetInfo &STI)
std::optional< uint8_t >	getHsaAbiVersion (const MCSubtargetInfo *STI)
bool	isHsaAbiVersion3 (const MCSubtargetInfo *STI)
bool	isHsaAbiVersion4 (const MCSubtargetInfo *STI)
bool	isHsaAbiVersion5 (const MCSubtargetInfo *STI)
unsigned	getAmdhsaCodeObjectVersion ()
unsigned	getCodeObjectVersion (const Module &M)
unsigned	getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
unsigned	getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
int	getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
const MIMGBaseOpcodeInfo *	getMIMGBaseOpcode (unsigned Opc)
int	getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
unsigned	getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int	getMTBUFBaseOpcode (unsigned Opc)
int	getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
int	getMTBUFElements (unsigned Opc)
bool	getMTBUFHasVAddr (unsigned Opc)
bool	getMTBUFHasSrsrc (unsigned Opc)
bool	getMTBUFHasSoffset (unsigned Opc)
int	getMUBUFBaseOpcode (unsigned Opc)
int	getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
int	getMUBUFElements (unsigned Opc)
bool	getMUBUFHasVAddr (unsigned Opc)
bool	getMUBUFHasSrsrc (unsigned Opc)
bool	getMUBUFHasSoffset (unsigned Opc)
bool	getMUBUFIsBufferInv (unsigned Opc)
bool	getSMEMIsBuffer (unsigned Opc)
bool	getVOP1IsSingle (unsigned Opc)
bool	getVOP2IsSingle (unsigned Opc)
bool	getVOP3IsSingle (unsigned Opc)
bool	isVOPC64DPP (unsigned Opc)
bool	getMAIIsDGEMM (unsigned Opc)
	Returns true if MAI operation is a double precision GEMM.
bool	getMAIIsGFX940XDL (unsigned Opc)
CanBeVOPD	getCanBeVOPD (unsigned Opc)
unsigned	getVOPDOpcode (unsigned Opc)
bool	isVOPD (unsigned Opc)
bool	isMAC (unsigned Opc)
bool	isPermlane16 (unsigned Opc)
bool	isGenericAtomic (unsigned Opc)
bool	isTrue16Inst (unsigned Opc)
unsigned	mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
unsigned	mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
int	getMCOpcode (uint16_t Opcode, unsigned Gen)
int	getVOPDFull (unsigned OpX, unsigned OpY)
std::pair< unsigned, unsigned >	getVOPDComponents (unsigned VOPDOpcode)
VOPD::InstInfo	getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)
VOPD::InstInfo	getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)
void	initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
amdhsa::kernel_descriptor_t	getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
bool	isGroupSegment (const GlobalValue *GV)
bool	isGlobalSegment (const GlobalValue *GV)
bool	isReadOnlySegment (const GlobalValue *GV)
bool	shouldEmitConstantsToTextSection (const Triple &TT)
std::pair< unsigned, unsigned >	getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned	getVmcntBitMask (const IsaVersion &Version)
unsigned	getExpcntBitMask (const IsaVersion &Version)
unsigned	getLgkmcntBitMask (const IsaVersion &Version)
unsigned	getWaitcntBitMask (const IsaVersion &Version)
unsigned	decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned	decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
void	decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
	Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.
Waitcnt	decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
unsigned	encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned	encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned	encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
unsigned	encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
	Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned	encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
template<class T >
static bool	isValidOpr (int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
template<class T >
static int	getOprIdx (std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
template<class T >
static int	getOprIdx (const StringRef Name, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
template<class T >
static int	getOprIdx (int Id, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context, bool QuickCheck=true)
static unsigned	getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static bool	isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
static bool	decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
static int	encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
static int	encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned	getInitialPSInputAddr (const Function &F)
bool	getHasColorExport (const Function &F)
bool	getHasDepthExport (const Function &F)
bool	isShader (CallingConv::ID cc)
bool	isGraphics (CallingConv::ID cc)
bool	isCompute (CallingConv::ID cc)
bool	isEntryFunctionCC (CallingConv::ID CC)
bool	isModuleEntryFunctionCC (CallingConv::ID CC)
bool	isChainCC (CallingConv::ID CC)
bool	isKernelCC (const Function *Func)
bool	hasXNACK (const MCSubtargetInfo &STI)
bool	hasSRAMECC (const MCSubtargetInfo &STI)
bool	hasMIMG_R128 (const MCSubtargetInfo &STI)
bool	hasA16 (const MCSubtargetInfo &STI)
bool	hasG16 (const MCSubtargetInfo &STI)
bool	hasPackedD16 (const MCSubtargetInfo &STI)
bool	hasGDS (const MCSubtargetInfo &STI)
unsigned	getNSAMaxSize (const MCSubtargetInfo &STI)
unsigned	getMaxNumUserSGPRs (const MCSubtargetInfo &STI)
bool	isSI (const MCSubtargetInfo &STI)
bool	isCI (const MCSubtargetInfo &STI)
bool	isVI (const MCSubtargetInfo &STI)
bool	isGFX9 (const MCSubtargetInfo &STI)
bool	isGFX9_GFX10 (const MCSubtargetInfo &STI)
bool	isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
bool	isGFX8Plus (const MCSubtargetInfo &STI)
bool	isGFX9Plus (const MCSubtargetInfo &STI)
bool	isGFX10 (const MCSubtargetInfo &STI)
bool	isGFX10Plus (const MCSubtargetInfo &STI)
bool	isGFX11 (const MCSubtargetInfo &STI)
bool	isGFX11Plus (const MCSubtargetInfo &STI)
bool	isNotGFX11Plus (const MCSubtargetInfo &STI)
bool	isNotGFX10Plus (const MCSubtargetInfo &STI)
bool	isGFX10Before1030 (const MCSubtargetInfo &STI)
bool	isGCN3Encoding (const MCSubtargetInfo &STI)
bool	isGFX10_AEncoding (const MCSubtargetInfo &STI)
bool	isGFX10_BEncoding (const MCSubtargetInfo &STI)
bool	hasGFX10_3Insts (const MCSubtargetInfo &STI)
bool	isGFX90A (const MCSubtargetInfo &STI)
bool	isGFX940 (const MCSubtargetInfo &STI)
bool	hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
bool	hasMAIInsts (const MCSubtargetInfo &STI)
bool	hasVOPD (const MCSubtargetInfo &STI)
unsigned	hasKernargPreload (const MCSubtargetInfo &STI)
int32_t	getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool	isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
	Is Reg - scalar register.
bool	isHi (unsigned Reg, const MCRegisterInfo &MRI)
unsigned	getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
	If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
unsigned	mc2PseudoReg (unsigned Reg)
	Convert hardware register Reg to a pseudo register.
bool	isInlineValue (unsigned Reg)
bool	isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).
bool	isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this a KImm operand?
bool	isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this floating-point operand?
bool	isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Does this operand support only inlinable literals?
unsigned	getRegBitWidth (unsigned RCID)
	Get the size in bits of a register from the register class RC.
unsigned	getRegBitWidth (const MCRegisterClass &RC)
	Get the size in bits of a register from the register class RC.
unsigned	getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
	Get size of register operand.
bool	isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
	Is this literal inlinable.
bool	isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
bool	isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
bool	isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
bool	isInlinableIntLiteralV216 (int32_t Literal)
bool	isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
bool	isArgPassedInSGPR (const Argument *A)
bool	isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)
static bool	hasSMEMByteOffset (const MCSubtargetInfo &ST)
static bool	hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
bool	isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool	isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
static bool	isDwordAligned (uint64_t ByteOffset)
uint64_t	convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
	Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
std::optional< int64_t >	getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
std::optional< int64_t >	getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned	getNumFlatOffsetBits (const MCSubtargetInfo &ST)
	For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
bool	isIntrinsicSourceOfDivergence (unsigned IntrID)
bool	isIntrinsicAlwaysUniform (unsigned IntrID)
const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
bool	hasAny64BitVGPROperands (const MCInstrDesc &OpDesc)
bool	isDPALU_DPP (const MCInstrDesc &OpDesc)
LLVM_READONLY int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY bool	hasNamedOperand (uint64_t Opcode, uint64_t NamedIdx)
LLVM_READONLY int	getSOPPWithRelaxation (uint16_t Opcode)
LLVM_READONLY const MIMGBaseOpcodeInfo *	getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfo (unsigned DimEnum)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByEncoding (uint8_t DimEnc)
LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
LLVM_READONLY const MIMGLZMappingInfo *	getMIMGLZMappingInfo (unsigned L)
LLVM_READONLY const MIMGMIPMappingInfo *	getMIMGMIPMappingInfo (unsigned MIP)
LLVM_READONLY const MIMGBiasMappingInfo *	getMIMGBiasMappingInfo (unsigned Bias)
LLVM_READONLY const MIMGOffsetMappingInfo *	getMIMGOffsetMappingInfo (unsigned Offset)
LLVM_READONLY const MIMGG16MappingInfo *	getMIMGG16MappingInfo (unsigned G)
LLVM_READONLY const MIMGInfo *	getMIMGInfo (unsigned Opc)
int	getIntegerAttribute (const Function &F, StringRef Name, int Default)
LLVM_READNONE bool	isKernel (CallingConv::ID CC)
LLVM_READNONE unsigned	getOperandSize (const MCOperandInfo &OpInfo)
LLVM_READNONE unsigned	getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
LLVM_READNONE bool	isInlinableIntLiteral (int64_t Literal)
	Is this literal inlinable, and not one of the values intended for floating point values.
bool	isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
LLVM_READNONE bool	isLegalDPALU_DPPControl (unsigned DC)
Align	getAlign (DataLayout const &DL, const GlobalVariable *GV)
bool	isDynamicLDS (const GlobalVariable &GV)
bool	isLDSVariableToLower (const GlobalVariable &GV)
bool	isReallyAClobber (const Value *Ptr, MemoryDef *Def, AAResults *AA)
	Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
bool	isClobberedInFunction (const LoadInst *Load, MemorySSA *MSSA, AAResults *AA)
	Check is a Load is clobbered in its function.

Variables
const uint64_t	RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t	RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
const uint64_t	RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
const uint64_t	RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
static constexpr uint32_t	ExtendedFltRoundOffset = 4
	Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
static constexpr uint32_t	F32FltRoundOffset = 0
	Offset in mode register of f32 rounding mode.
static constexpr uint32_t	F64FltRoundOffset = 2
	Offset in mode register of f64/f16 rounding mode.
const uint64_t	FltRoundConversionTable
const int	OPR_ID_UNKNOWN = -1
const int	OPR_ID_UNSUPPORTED = -2
const int	OPR_ID_DUPLICATE = -3
const int	OPR_VAL_INVALID = -4

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
AMDHSA_COV3
AMDHSA_COV4
AMDHSA_COV5

Definition at line 45 of file AMDGPUBaseInfo.h.

AMDGPUFltRounds

enum llvm::AMDGPU::AMDGPUFltRounds : int8_t

Return values used for llvm.get.rounding.

When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.

Enumerator
TowardZero
NearestTiesToEven
TowardPositive
TowardNegative
NearestTiesToAwayUnsupported
Dynamic
NearestTiesToEvenF32_NearestTiesToEvenF64
NearestTiesToEvenF32_TowardPositiveF64
NearestTiesToEvenF32_TowardNegativeF64
NearestTiesToEvenF32_TowardZeroF64
TowardPositiveF32_NearestTiesToEvenF64
TowardPositiveF32_TowardPositiveF64
TowardPositiveF32_TowardNegativeF64
TowardPositiveF32_TowardZeroF64
TowardNegativeF32_NearestTiesToEvenF64
TowardNegativeF32_TowardPositiveF64
TowardNegativeF32_TowardNegativeF64
TowardNegativeF32_TowardZeroF64
TowardZeroF32_NearestTiesToEvenF64
TowardZeroF32_TowardPositiveF64
TowardZeroF32_TowardNegativeF64
TowardZeroF32_TowardZeroF64
Invalid

Definition at line 94 of file SIModeRegisterDefaults.h.

ArchFeatureKind

enum llvm::AMDGPU::ArchFeatureKind : uint32_t

Enumerator
FEATURE_NONE
FEATURE_FMA
FEATURE_LDEXP
FEATURE_FP64
FEATURE_FAST_FMA_F32
FEATURE_FAST_DENORMAL_F32
FEATURE_WAVE32
FEATURE_XNACK
FEATURE_SRAMECC
FEATURE_WGP

Definition at line 122 of file TargetParser.h.

Fixups

enum llvm::AMDGPU::Fixups

Enumerator
fixup_si_sopp_br	16-bit PC relative fixup for SOPP branch instructions.
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file AMDGPUFixupKinds.h.

GPUKind

enum llvm::AMDGPU::GPUKind : uint32_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE
GK_R600
GK_R630
GK_RS880
GK_RV670
GK_RV710
GK_RV730
GK_RV770
GK_CEDAR
GK_CYPRESS
GK_JUNIPER
GK_REDWOOD
GK_SUMO
GK_BARTS
GK_CAICOS
GK_CAYMAN
GK_TURKS
GK_R600_FIRST
GK_R600_LAST
GK_GFX600
GK_GFX601
GK_GFX602
GK_GFX700
GK_GFX701
GK_GFX702
GK_GFX703
GK_GFX704
GK_GFX705
GK_GFX801
GK_GFX802
GK_GFX803
GK_GFX805
GK_GFX810
GK_GFX900
GK_GFX902
GK_GFX904
GK_GFX906
GK_GFX908
GK_GFX909
GK_GFX90A
GK_GFX90C
GK_GFX940
GK_GFX941
GK_GFX942
GK_GFX1010
GK_GFX1011
GK_GFX1012
GK_GFX1013
GK_GFX1030
GK_GFX1031
GK_GFX1032
GK_GFX1033
GK_GFX1034
GK_GFX1035
GK_GFX1036
GK_GFX1100
GK_GFX1101
GK_GFX1102
GK_GFX1103
GK_GFX1150
GK_GFX1151
GK_AMDGCN_FIRST
GK_AMDGCN_LAST

Definition at line 35 of file TargetParser.h.

OperandType

enum llvm::AMDGPU::OperandType : unsigned

Enumerator
OPERAND_REG_IMM_INT32	Operands with register or 32-bit immediate.
OPERAND_REG_IMM_INT64
OPERAND_REG_IMM_INT16
OPERAND_REG_IMM_FP32
OPERAND_REG_IMM_FP64
OPERAND_REG_IMM_FP16
OPERAND_REG_IMM_FP16_DEFERRED
OPERAND_REG_IMM_FP32_DEFERRED
OPERAND_REG_IMM_V2FP16
OPERAND_REG_IMM_V2INT16
OPERAND_REG_IMM_V2INT32
OPERAND_REG_IMM_V2FP32
OPERAND_REG_INLINE_C_INT16	Operands with register or inline constant.
OPERAND_REG_INLINE_C_INT32
OPERAND_REG_INLINE_C_INT64
OPERAND_REG_INLINE_C_FP16
OPERAND_REG_INLINE_C_FP32
OPERAND_REG_INLINE_C_FP64
OPERAND_REG_INLINE_C_V2INT16
OPERAND_REG_INLINE_C_V2FP16
OPERAND_REG_INLINE_C_V2INT32
OPERAND_REG_INLINE_C_V2FP32
OPERAND_KIMM32	Operand with 32-bit immediate that uses the constant bus.
OPERAND_KIMM16
OPERAND_REG_INLINE_AC_INT16	Operands with an AccVGPR register or inline constant.
OPERAND_REG_INLINE_AC_INT32
OPERAND_REG_INLINE_AC_FP16
OPERAND_REG_INLINE_AC_FP32
OPERAND_REG_INLINE_AC_FP64
OPERAND_REG_INLINE_AC_V2INT16
OPERAND_REG_INLINE_AC_V2FP16
OPERAND_REG_INLINE_AC_V2INT32
OPERAND_REG_INLINE_AC_V2FP32
OPERAND_INPUT_MODS
OPERAND_SDWA_VOPC_DST
OPERAND_REG_IMM_FIRST
OPERAND_REG_IMM_LAST
OPERAND_REG_INLINE_C_FIRST
OPERAND_REG_INLINE_C_LAST
OPERAND_REG_INLINE_AC_FIRST
OPERAND_REG_INLINE_AC_LAST
OPERAND_SRC_FIRST
OPERAND_SRC_LAST
OPERAND_KIMM_FIRST
OPERAND_KIMM_LAST

Definition at line 186 of file SIDefines.h.

TargetIndex

enum llvm::AMDGPU::TargetIndex

Enumerator
TI_CONSTDATA_START
TI_SCRATCH_RSRC_DWORD0
TI_SCRATCH_RSRC_DWORD1
TI_SCRATCH_RSRC_DWORD2
TI_SCRATCH_RSRC_DWORD3

Definition at line 370 of file AMDGPU.h.

Function Documentation

addrspacesMayAlias()

static bool llvm::AMDGPU::addrspacesMayAlias ( unsigned  AS1, unsigned  AS2  )

inlinestatic

Definition at line 458 of file AMDGPU.h.

References llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::GCNTTIImpl::addrspacesMayAlias(), and llvm::AMDGPUAAResult::alias().

convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits	(	const MCSubtargetInfo &	ST,
		uint64_t	ByteOffset
	)

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 2600 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), and isDwordAligned().

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

decodeCustomOperand()

static bool llvm::AMDGPU::decodeCustomOperand ( const CustomOperandVal *  Opr, int  Size, unsigned  Code, int &  Idx, StringRef &  Name, unsigned &  Val, bool &  IsDefault, const MCSubtargetInfo &  STI  )

static

Definition at line 1406 of file AMDGPUBaseInfo.cpp.

References Idx, Name, and Size.

Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().

decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns

Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 1256 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns

Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 1261 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns

Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 1248 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Encoded
	)

Definition at line 1273 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, and llvm::AMDGPU::Waitcnt::VmCnt.

decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned &	Vmcnt,
		unsigned &	Expcnt,
		unsigned &	Lgkmcnt
	)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9) Vmcnt = Waitcnt[15:14,3:0] (gfx9,10) Vmcnt = Waitcnt[15:10] (gfx11+) Expcnt = Waitcnt[6:4] (pre-gfx11) Expcnt = Waitcnt[2:0] (gfx11+) Lgkmcnt = Waitcnt[11:8] (pre-gfx10) Lgkmcnt = Waitcnt[13:8] (gfx10) Lgkmcnt = Waitcnt[9:4] (gfx11+)

Definition at line 1266 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

encodeCustomOperand()

static int llvm::AMDGPU::encodeCustomOperand ( const CustomOperandVal *  Opr, int  Size, const StringRef  Name, int64_t  InputVal, unsigned &  UsedOprMask, const MCSubtargetInfo &  STI  )

static

Definition at line 1430 of file AMDGPUBaseInfo.cpp.

References encodeCustomOperandVal(), Idx, Name, OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and Size.

Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().

encodeCustomOperandVal()

static int llvm::AMDGPU::encodeCustomOperandVal ( const CustomOperandVal &  Op, int64_t  InputVal  )

static

Definition at line 1423 of file AMDGPUBaseInfo.cpp.

References OPR_VAL_INVALID.

Referenced by encodeCustomOperand().

encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Expcnt
	)

Returns

Waitcnt with encoded Expcnt for given isa Version.

Definition at line 1290 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Lgkmcnt
	)

Returns

Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 1296 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Vmcnt
	)

Returns

Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 1281 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded
	)

Definition at line 1311 of file AMDGPUBaseInfo.cpp.

References encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, and llvm::AMDGPU::Waitcnt::VmCnt.

encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Vmcnt,
		unsigned	Expcnt,
		unsigned	Lgkmcnt
	)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[2:0] = Expcnt (gfx11+) Waitcnt[3:0] = Vmcnt (pre-gfx9) Waitcnt[3:0] = Vmcnt[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt (pre-gfx11) Waitcnt[9:4] = Lgkmcnt (gfx11+) Waitcnt[11:8] = Lgkmcnt (pre-gfx10) Waitcnt[13:8] = Lgkmcnt (gfx10) Waitcnt[15:10] = Vmcnt (gfx11+) Waitcnt[15:14] = Vmcnt[5:4] (gfx9,10)

Returns

Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 1302 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().

Referenced by encodeWaitcnt().

fillAMDGPUFeatureMap()

void llvm::AMDGPU::fillAMDGPUFeatureMap	(	StringRef	GPU,
		const Triple &	T,
		StringMap< bool > &	Features
	)

Fills Features map with default values for given target GPU.

Definition at line 262 of file TargetParser.cpp.

References llvm::StringRef::empty(), GK_BARTS, GK_CAICOS, GK_CAYMAN, GK_CEDAR, GK_CYPRESS, GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, GK_JUNIPER, GK_NONE, GK_R600, GK_R630, GK_REDWOOD, GK_RS880, GK_RV670, GK_RV710, GK_RV730, GK_RV770, GK_SUMO, GK_TURKS, llvm_unreachable, parseArchAMDGCN(), and parseArchR600().

fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN

(

SmallVectorImpl< StringRef > &

Values

)

Definition at line 185 of file TargetParser.cpp.

References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600

(

SmallVectorImpl< StringRef > &

Values

)

Definition at line 191 of file TargetParser.cpp.

References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::legalizeOperands().

getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp	(	const MIMGBaseOpcodeInfo *	BaseOpcode,
		const MIMGDimInfo *	Dim,
		bool	IsA16,
		bool	IsG16Supported
	)

Definition at line 253 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

getAlign()

Align llvm::AMDGPU::getAlign	(	DataLayout const &	DL,
		const GlobalVariable *	GV
	)

Definition at line 29 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().

getAmdhsaCodeObjectVersion()

unsigned llvm::AMDGPU::getAmdhsaCodeObjectVersion

(

)

Returns

Code object version.

Definition at line 161 of file AMDGPUBaseInfo.cpp.

References AmdhsaCodeObjectVersion.

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN

(

GPUKind

AK

)

Definition at line 173 of file TargetParser.cpp.

References FEATURE_NONE.

getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600

(

GPUKind

AK

)

Definition at line 179 of file TargetParser.cpp.

References FEATURE_NONE.

getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN

(

GPUKind

AK

)

Definition at line 143 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600

(

GPUKind

AK

)

Definition at line 149 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp

(

uint16_t

Opcode

)

getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset	(	MachineRegisterInfo &	MRI,
		Register	Reg,
		GISelKnownBits *	KnownBits = nullptr
	)

Returns base register and constant offset.

Definition at line 20 of file AMDGPUGlobalISelUtils.cpp.

References llvm::sampleprof::Base, llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GOr(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, and llvm::Offset.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().

getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::verifyInstruction().

getCanBeVOPD()

LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD

(

unsigned

Opc

)

Definition at line 458 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by shouldScheduleVOPDAdjacent().

getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName	(	const Triple &	T,
		StringRef	Arch
	)

Definition at line 253 of file TargetParser.cpp.

References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), and parseArchR600().

getCodeObjectVersion()

unsigned llvm::AMDGPU::getCodeObjectVersion

(

const Module &

M

)

Returns

Code object version.

Definition at line 165 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4.

Referenced by llvm::SITargetLowering::allocateHSAUserSGPRs(), allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateSpecialInputSGPRs(), llvm::AMDGPUAsmPrinter::doInitialization(), llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV3::emitKernel(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic(), llvm::AMDGPULowerKernelAttributesPass::run(), and llvm::AMDGPUResourceUsageAnalysis::runOnModule().

getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::commuteOpcode().

getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::commuteOpcode().

getCompletionActionImplicitArgPosition()

unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition

(

unsigned

CodeObjectVersion

)

Definition at line 211 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV3, AMDHSA_COV4, AMDHSA_COV5, and llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.

getDefaultAmdhsaKernelDescriptor()

amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor

(

const MCSubtargetInfo *

STI

)

Definition at line 1145 of file AMDGPUBaseInfo.cpp.

References AMDHSA_BITS_SET, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), isGFX90A(), llvm::amdhsa::kernel_descriptor_t::kernel_code_properties, and llvm::FeatureBitset::test().

getDefaultCustomOperandEncoding()

static unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding ( const CustomOperandVal *  Opr, int  Size, const MCSubtargetInfo &  STI  )

static

Definition at line 1375 of file AMDGPUBaseInfo.cpp.

References Idx, and Size.

Referenced by llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().

getDefaultQueueImplicitArgPosition()

unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition

(

unsigned

CodeObjectVersion

)

Definition at line 200 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV3, AMDHSA_COV4, AMDHSA_COV5, and llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.

getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32

(

uint16_t

Opcode

)

getDPPOp64()

LLVM_READONLY int llvm::AMDGPU::getDPPOp64

(

uint16_t

Opcode

)

getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask

(

const IsaVersion &

Version

)

Returns

Expcnt bit mask for given isa Version.

Definition at line 1228 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

getFlatScratchInstSSfromSV()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV

(

uint16_t

Opcode

)

Returns

SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

getFlatScratchInstSTfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS

(

uint16_t

Opcode

)

Returns

ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

getFlatScratchInstSVfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS

(

uint16_t

Opcode

)

Returns

SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().

getFlatScratchInstSVfromSVS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS

(

uint16_t

Opcode

)

Returns

SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SVS (SADDR + VADDR) form.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

getGcnBufferFormatInfo() [1/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	BitsPerComp,
		uint8_t	NumComponents,
		uint8_t	NumFormat,
		const MCSubtargetInfo &	STI
	)

Definition at line 2674 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by getBufferFormatWithCompCount().

getGcnBufferFormatInfo() [2/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	Format,
		const MCSubtargetInfo &	STI
	)

Definition at line 2687 of file AMDGPUBaseInfo.cpp.

References llvm::Format, isGFX10(), and isGFX11Plus().

getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp

(

uint16_t

Opcode

)

Returns

SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

getGlobalVaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp

(

uint16_t

Opcode

)

Returns

VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

getHasColorExport()

bool llvm::AMDGPU::getHasColorExport

(

const Function &

F

)

Definition at line 1876 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, and F.

Referenced by generateEndPgm().

getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport

(

const Function &

F

)

Definition at line 1883 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by generateEndPgm().

getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition

(

unsigned

COV

)

Returns

The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line 189 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV3, AMDHSA_COV4, AMDHSA_COV5, and llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.

getHsaAbiVersion()

std::optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion

(

const MCSubtargetInfo *

STI

)

Returns

HSA OS ABI Version identification.

Definition at line 126 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, AmdhsaCodeObjectVersion, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::Triple::getOS(), llvm::MCSubtargetInfo::getTargetTriple(), and llvm::report_fatal_error().

Referenced by llvm::createAMDGPUAsmBackend(), isHsaAbiVersion3(), isHsaAbiVersion4(), and isHsaAbiVersion5().

getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst

(

uint16_t

Opcode

)

Check if Opcode is an Addr64 opcode.

Returns

Opcode if it is an Addr64 opcode, otherwise -1.

Referenced by llvm::SIInstrInfo::legalizeOperands().

getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode	(	unsigned	BaseOpcode,
		unsigned	Dim
	)

Referenced by simplifyAMDGCNImageIntrinsic().

getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo

(

unsigned

Intr

)

Referenced by collectMergeableInsts(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::GCNTTIImpl::instCombineIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), optimizeSection(), and llvm::AMDGPUInstructionSelector::select().

getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr

(

const Function &

F

)

Definition at line 1872 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute	(	const Function &	F,
		StringRef	Name,
		int	Default
	)

Returns

Integer value requested using F's Name attribute.

Default if attribute is not present.

Default and emits error if requested value cannot be converted to integer.

getIntegerPairAttribute()

std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute	(	const Function &	F,
		StringRef	Name,
		std::pair< unsigned, unsigned >	Default,
		bool	OnlyFirstRequired = false
	)

Returns

A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).

Default if attribute is not present.

Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1198 of file AMDGPUBaseInfo.cpp.

References A, llvm::Default, llvm::LLVMContext::emitError(), F, and Name.

Referenced by llvm::AMDGPUMachineFunction::AMDGPUMachineFunction(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

getIntrinsicID()

Intrinsic::ID llvm::AMDGPU::getIntrinsicID

(

const MachineInstr &

I

)

Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But they are not actual instances of GIntrinsics, so we cannot use GIntrinsic::getIntrinsicID() on them.

Definition at line 30 of file AMDGPUInstrInfo.cpp.

References I.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPUInstructionSelector::select().

getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion

(

StringRef

GPU

)

Definition at line 196 of file TargetParser.cpp.

References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, and parseArchAMDGCN().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPUInstPrinter::printSWaitCnt(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().

getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask

(

const IsaVersion &

Version

)

Returns

Lgkmcnt bit mask for given isa Version.

Definition at line 1232 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

getMAIIsDGEMM()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM

(

unsigned

Opc

)

Returns true if MAI operation is a double precision GEMM.

Definition at line 448 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isDGEMM().

getMAIIsGFX940XDL()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL

(

unsigned

Opc

)

Definition at line 453 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isXDL().

getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp	(	unsigned	Opc,
		unsigned	NewChannels
	)

Definition at line 245 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

getMaxNumUserSGPRs()

unsigned llvm::AMDGPU::getMaxNumUserSGPRs

(

const MCSubtargetInfo &

STI

)

Definition at line 1990 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(), llvm::GCNSubtarget::getMaxNumUserSGPRs(), and llvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().

getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode	(	uint16_t	Opcode,
		unsigned	Gen
	)

Definition at line 543 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

getMCReg()

unsigned llvm::AMDGPU::getMCReg	(	unsigned	Reg,
		const MCSubtargetInfo &	STI
	)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 2167 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, llvm::Triple::r600, and Reg.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().

getMFMAEarlyClobberOp()

LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp

(

uint16_t

Opcode

)

Returns

earlyclobber version of a MAC MFMA is exists.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), and llvm::SIInstrInfo::pseudoToMCOpcode().

getMIMGBaseOpcode()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode

(

unsigned

Opc

)

Definition at line 240 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.

getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo

(

unsigned

BaseOpcode

)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), simplifyAMDGCNImageIntrinsic(), and llvm::SIInstrInfo::verifyInstruction().

getMIMGBiasMappingInfo()

LLVM_READONLY const MIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo

(

unsigned

Bias

)

Referenced by simplifyAMDGCNImageIntrinsic().

getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo

(

unsigned

DimEnum

)

getMIMGDimInfoByAsmSuffix()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix

(

StringRef

AsmSuffix

)

getMIMGDimInfoByEncoding()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding

(

uint8_t

DimEnc

)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

getMIMGG16MappingInfo()

LLVM_READONLY const MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo

(

unsigned

G

)

getMIMGInfo()

LLVM_READONLY const MIMGInfo * llvm::AMDGPU::getMIMGInfo

(

unsigned

Opc

)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), and llvm::SIInstrInfo::verifyInstruction().

getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo

(

unsigned

L

)

Referenced by simplifyAMDGCNImageIntrinsic().

getMIMGMIPMappingInfo()

LLVM_READONLY const MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo

(

unsigned

MIP

)

Referenced by simplifyAMDGCNImageIntrinsic().

getMIMGOffsetMappingInfo()

LLVM_READONLY const MIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo

(

unsigned

Offset

)

Referenced by simplifyAMDGCNImageIntrinsic().

getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode	(	unsigned	BaseOpcode,
		unsigned	MIMGEncoding,
		unsigned	VDataDwords,
		unsigned	VAddrDwords
	)

Definition at line 233 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode

(

unsigned

Opc

)

Definition at line 359 of file AMDGPUBaseInfo.cpp.

References Info.

getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements

(

unsigned

Opc

)

Definition at line 369 of file AMDGPUBaseInfo.cpp.

References Info.

getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset

(

unsigned

Opc

)

Definition at line 384 of file AMDGPUBaseInfo.cpp.

References Info.

getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc

(

unsigned

Opc

)

Definition at line 379 of file AMDGPUBaseInfo.cpp.

References Info.

getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr

(

unsigned

Opc

)

Definition at line 374 of file AMDGPUBaseInfo.cpp.

References Info.

getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements
	)

Definition at line 364 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode

(

unsigned

Opc

)

Definition at line 389 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements

(

unsigned

Opc

)

Definition at line 399 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset

(

unsigned

Opc

)

Definition at line 414 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc

(

unsigned

Opc

)

Definition at line 409 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr

(

unsigned

Opc

)

Definition at line 404 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv

(

unsigned

Opc

)

Definition at line 419 of file AMDGPUBaseInfo.cpp.

References Info.

getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements
	)

Definition at line 394 of file AMDGPUBaseInfo.cpp.

References Info.

getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition

(

unsigned

COV

)

Returns

The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line 175 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV3, AMDHSA_COV4, AMDHSA_COV5, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIdx
	)

Referenced by llvm::SITargetLowering::AddIMGInit(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::SIRegisterInfo::buildSpillLoadStore(), collectVOPModifiers(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), cvtVOP3DstOpSelOnly(), decodeOperand_AVLdSt_Any(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::SIInstrInfo::getRegClass(), llvm::SIRegisterInfo::getScratchInstrOffset(), getSrcOperandIndices(), hasAny64BitVGPROperands(), hasNamedOperand(), llvm::SIInstrWorklist::insert(), insertNamedMCOperand(), IsAGPROperand(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::AMDGPUDisassembler::isMacDPP(), llvm::SIInstrInfo::isOperandLegal(), isSendMsgTraceDataOrGDS(), isValidDPP8(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), AMDGPUMCInstLower::lower(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), nodesHaveSameOperandValue(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIInstrInfo::removeModOperands(), updateOperandIfDifferent(), and llvm::SIInstrInfo::verifyInstruction().

getNSAMaxSize()

unsigned llvm::AMDGPU::getNSAMaxSize

(

const MCSubtargetInfo &

STI

)

Definition at line 1981 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getCPU(), and getIsaVersion().

Referenced by llvm::GCNSubtarget::getNSAMaxSize().

getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits

(

const MCSubtargetInfo &

ST

)

For FLAT segment the offset must be positive; MSB is ignored and forced to zero.

Returns

The number of bits available for the signed offset field in flat instructions. Note that some forms of the instruction disallow negative offsets.

Definition at line 2637 of file AMDGPUBaseInfo.cpp.

References isGFX10().

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc &  Desc, unsigned  OpNo  )

inline

Definition at line 1262 of file AMDGPUBaseInfo.h.

References getOperandSize().

getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo &  OpInfo )

inline

Definition at line 1217 of file AMDGPUBaseInfo.h.

References llvm_unreachable, OPERAND_KIMM16, OPERAND_KIMM32, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2INT32, and llvm::MCOperandInfo::OperandType.

Referenced by getOperandSize().

getOprIdx() [1/3]

template<class T >

static int llvm::AMDGPU::getOprIdx ( const StringRef  Name, const CustomOperand< T >  OpInfo[], int  OpInfoSize, T  Context  )

static

Definition at line 1349 of file AMDGPUBaseInfo.cpp.

References Context, Name, and llvm::Test.

getOprIdx() [2/3]

template<class T >

static int llvm::AMDGPU::getOprIdx ( int  Id, const CustomOperand< T >  OpInfo[], int  OpInfoSize, T  Context, bool  QuickCheck = true  )

static

Definition at line 1356 of file AMDGPUBaseInfo.cpp.

References Context, llvm::AMDGPU::CustomOperand< T >::Encoding, and llvm::Test.

getOprIdx() [3/3]

template<class T >

static int llvm::AMDGPU::getOprIdx ( std::function< bool(const CustomOperand< T > &)>  Test, const CustomOperand< T >  OpInfo[], int  OpInfoSize, T  Context  )

static

Definition at line 1334 of file AMDGPUBaseInfo.cpp.

References Cond, Context, Idx, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and llvm::Test.

getRegBitWidth() [1/3]

unsigned llvm::AMDGPU::getRegBitWidth

(

const MCRegisterClass &

RC

)

Get the size in bits of a register from the register class RC.

Definition at line 2406 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

getRegBitWidth() [2/3]

unsigned llvm::AMDGPU::getRegBitWidth

(

const TargetRegisterClass &

RC

)

Get the size in bits of a register from the register class RC.

Definition at line 2578 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID(), and getRegBitWidth().

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().

getRegBitWidth() [3/3]

unsigned llvm::AMDGPU::getRegBitWidth

(

unsigned

RCID

)

Get the size in bits of a register from the register class RC.

Definition at line 2265 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize	(	const MCRegisterInfo *	MRI,
		const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Get size of register operand.

Definition at line 2410 of file AMDGPUBaseInfo.cpp.

References assert(), and getRegBitWidth().

getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp

(

uint16_t

Opcode

)

getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer

(

unsigned

Opc

)

Definition at line 424 of file AMDGPUBaseInfo.cpp.

References Info.

getSMRDEncodedLiteralOffset32()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset
	)

Returns

The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 2627 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), and isDwordAligned().

getSMRDEncodedOffset()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset,
		bool	IsBuffer
	)

Returns

The encoding that will be used for ByteOffset in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 2609 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), and isLegalSMRDEncodedUnsignedOffset().

getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp

(

uint16_t

Opcode

)

getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation

(

uint16_t

Opcode

)

getTotalNumVGPRs()

int llvm::AMDGPU::getTotalNumVGPRs	(	bool	has90AInsts,
		int32_t	ArgNumAGPR,
		int32_t	ArgNumVGPR
	)

Definition at line 2092 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo().

Referenced by llvm::AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs().

getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp

(

uint16_t

Opcode

)

getVCMPXOpFromVCMP()

LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP

(

uint16_t

Opcode

)

Returns

v_cmpx version of a v_cmp instruction.

getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask

(

const IsaVersion &

Version

)

Returns

Vmcnt bit mask for given isa Version.

Definition at line 1222 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle

(

unsigned

Opc

)

Definition at line 429 of file AMDGPUBaseInfo.cpp.

References Info.

getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle

(

unsigned

Opc

)

Definition at line 434 of file AMDGPUBaseInfo.cpp.

References Info.

getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle

(

unsigned

Opc

)

Definition at line 439 of file AMDGPUBaseInfo.cpp.

References Info.

getVOPDComponents()

LLVM_READONLY std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents

(

unsigned

VOPDOpcode

)

Definition at line 552 of file AMDGPUBaseInfo.cpp.

References assert(), and Info.

Referenced by getVOPDInstInfo().

getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull	(	unsigned	OpX,
		unsigned	OpY
	)

Definition at line 547 of file AMDGPUBaseInfo.cpp.

References Info.

getVOPDInstInfo() [1/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	const MCInstrDesc &	OpX,
		const MCInstrDesc &	OpY
	)

Definition at line 646 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::checkVOPDRegConstraints().

getVOPDInstInfo() [2/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	unsigned	VOPDOpcode,
		const MCInstrInfo *	InstrInfo
	)

Definition at line 650 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::VOPD::COMPONENT_X, getVOPDComponents(), and InstrInfo.

getVOPDOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode

(

unsigned

Opc

)

Definition at line 466 of file AMDGPUBaseInfo.cpp.

References Info.

getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().

getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64

(

uint16_t

Opcode

)

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask

(

const IsaVersion &

Version

)

Returns

Waitcnt bit mask for given isa Version.

Definition at line 1236 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

hasA16()

bool llvm::AMDGPU::hasA16

(

const MCSubtargetInfo &

STI

)

Definition at line 1964 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

hasAny64BitVGPROperands()

bool llvm::AMDGPU::hasAny64BitVGPROperands

(

const MCInstrDesc &

OpDesc

)

Returns

true if an instruction may have a 64-bit VGPR operand.

Definition at line 2694 of file AMDGPUBaseInfo.cpp.

References getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), Idx, and llvm::MCInstrDesc::operands().

Referenced by isDPALU_DPP().

hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch

(

const MCSubtargetInfo &

STI

)

Definition at line 2076 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

hasAtomicFaddRtnForTy()

bool llvm::AMDGPU::hasAtomicFaddRtnForTy	(	const GCNSubtarget &	Subtarget,
		const LLT &	Ty
	)

Definition at line 67 of file AMDGPUGlobalISelUtils.cpp.

References llvm::LLT::fixed_vector(), llvm::GCNSubtarget::hasAtomicFaddRtnInsts(), llvm::GCNSubtarget::hasGFX90AInsts(), and llvm::LLT::scalar().

hasG16()

bool llvm::AMDGPU::hasG16

(

const MCSubtargetInfo &

STI

)

Definition at line 1968 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

hasGDS()

bool llvm::AMDGPU::hasGDS

(

const MCSubtargetInfo &

STI

)

Definition at line 1977 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts

(

const MCSubtargetInfo &

STI

)

Definition at line 2064 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

hasKernargPreload()

unsigned llvm::AMDGPU::hasKernargPreload

(

const MCSubtargetInfo &

STI

)

Definition at line 2088 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::emitFunctionBodyStart(), and llvm::AMDGPUDisassembler::hasKernargPreload().

hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts

(

const MCSubtargetInfo &

STI

)

Definition at line 2080 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128

(

const MCSubtargetInfo &

STI

)

Definition at line 1960 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

hasNamedOperand()

LLVM_READONLY bool llvm::AMDGPU::hasNamedOperand ( uint64_t  Opcode, uint64_t  NamedIdx  )

inline

Definition at line 329 of file AMDGPUBaseInfo.h.

References getNamedOperandIdx().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::eliminateFrameIndex(), getFlatScratchSpillOpcode(), llvm::SIInstrInfo::getRegClass(), llvm::SIInstrInfo::hasModifiers(), llvm::AMDGPUDisassembler::isMacDPP(), isVOPD(), and llvm::SITargetLowering::PostISelFolding().

hasPackedD16()

bool llvm::AMDGPU::hasPackedD16

(

const MCSubtargetInfo &

STI

)

Definition at line 1972 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isCI(), and isSI().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

hasSMEMByteOffset()

static bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo &  ST )

static

Definition at line 2574 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), and isGFX10Plus().

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().

hasSMRDSignedImmOffset()

static bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo &  ST )

static

Definition at line 2578 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC

(

const MCSubtargetInfo &

STI

)

Definition at line 1956 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

hasVOPD()

bool llvm::AMDGPU::hasVOPD

(

const MCSubtargetInfo &

STI

)

Definition at line 2084 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().

hasXNACK()

bool llvm::AMDGPU::hasXNACK

(

const MCSubtargetInfo &

STI

)

Definition at line 1952 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT	(	amd_kernel_code_t &	Header,
		const MCSubtargetInfo *	STI
	)

Definition at line 1109 of file AMDGPUBaseInfo.cpp.

References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, and llvm::FeatureBitset::test().

insertWaveSizeFeature()

bool llvm::AMDGPU::insertWaveSizeFeature	(	StringRef	GPU,
		const Triple &	T,
		StringMap< bool > &	Features,
		std::string &	ErrorMsg
	)

Inserts wave size feature for given GPU into features map.

Definition at line 487 of file TargetParser.cpp.

References llvm::StringMap< ValueTy, AllocatorTy >::count(), llvm::StringRef::empty(), llvm::StringMap< ValueTy, AllocatorTy >::insert(), and isWave32Capable().

isArgPassedInSGPR() [1/2]

bool llvm::AMDGPU::isArgPassedInSGPR

(

const Argument *

A

)

Definition at line 2518 of file AMDGPUBaseInfo.cpp.

References A, llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, F, and llvm::CallingConv::SPIR_KERNEL.

Referenced by adjustInliningThresholdUsingCallee(), llvm::GCNTTIImpl::isSourceOfDivergence(), and llvm::AMDGPUInstrInfo::isUniformMMO().

isArgPassedInSGPR() [2/2]

bool llvm::AMDGPU::isArgPassedInSGPR	(	const CallBase *	CB,
		unsigned	ArgNo
	)

Definition at line 2547 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, llvm::CallBase::getCallingConv(), llvm::CallBase::paramHasAttr(), and llvm::CallingConv::SPIR_KERNEL.

isChainCC()

LLVM_READNONE bool llvm::AMDGPU::isChainCC

(

CallingConv::ID

CC

)

Definition at line 1938 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, and CC.

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

isCI()

bool llvm::AMDGPU::isCI

(

const MCSubtargetInfo &

STI

)

Definition at line 1996 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().

isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction	(	const LoadInst *	Load,
		MemorySSA *	MSSA,
		AAResults *	AA
	)

Check is a Load is clobbered in its function.

Definition at line 99 of file AMDGPUMemoryUtils.cpp.

References llvm::dbgs(), llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::SmallSet< T, N, C >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), and LLVM_DEBUG.

isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute

(

CallingConv::ID

cc

)

Definition at line 1908 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, and isGraphics().

Referenced by llvm::SIProgramInfo::getPGMRSrc1(), llvm::SIProgramInfo::getPGMRSrc2(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

isDPALU_DPP()

bool llvm::AMDGPU::isDPALU_DPP

(

const MCInstrDesc &

OpDesc

)

Returns

true if an instruction is a DP ALU DPP.

Definition at line 2709 of file AMDGPUBaseInfo.cpp.

References hasAny64BitVGPROperands().

Referenced by llvm::SIInstrInfo::verifyInstruction().

isDwordAligned()

static bool llvm::AMDGPU::isDwordAligned ( uint64_t  ByteOffset )

static

Definition at line 2596 of file AMDGPUBaseInfo.cpp.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

isDynamicLDS()

bool llvm::AMDGPU::isDynamicLDS

(

const GlobalVariable &

GV

)

Definition at line 34 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::GlobalValue::getParent(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalValue::getValueType(), llvm::GlobalValue::hasExternalLinkage(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by isLDSVariableToLower().

isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC

(

CallingConv::ID

CC

)

Definition at line 1912 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), INITIALIZE_PASS(), isModuleEntryFunctionCC(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), mustPreserveGV(), recursivelyVisitUsers(), and llvm::SIMachineFunctionInfo::usesAGPRs().

isExtendedGlobalAddrSpace()

bool llvm::AMDGPU::isExtendedGlobalAddrSpace ( unsigned  AS )

inline

Definition at line 452 of file AMDGPU.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), and llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace().

isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned  AS )

inline

Definition at line 445 of file AMDGPU.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), and llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

isFoldableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isFoldableLiteralV216	(	int32_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2505 of file AMDGPUBaseInfo.cpp.

References assert(), and llvm::Literal.

isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding

(

const MCSubtargetInfo &

STI

)

Definition at line 2052 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by hasSMEMByteOffset().

isGenericAtomic()

LLVM_READNONE bool llvm::AMDGPU::isGenericAtomic

(

unsigned

Opc

)

Definition at line 503 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity().

isGFX10()

bool llvm::AMDGPU::isGFX10

(

const MCSubtargetInfo &

STI

)

Definition at line 2024 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by getGcnBufferFormatInfo(), getNumFlatOffsetBits(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().

isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding

(

const MCSubtargetInfo &

STI

)

Definition at line 2056 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding

(

const MCSubtargetInfo &

STI

)

Definition at line 2060 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10Before1030().

isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030

(

const MCSubtargetInfo &

STI

)

Definition at line 2048 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX10_BEncoding().

isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2028 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::GCNSubtarget::initializeSubtargetDependencies(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), and llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding().

isGFX11()

bool llvm::AMDGPU::isGFX11

(

const MCSubtargetInfo &

STI

)

Definition at line 2032 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX11Plus().

isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2036 of file AMDGPUBaseInfo.cpp.

References isGFX11().

Referenced by llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt(), llvm::AMDGPU::SendMsg::decodeMsg(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getGcnBufferFormatInfo(), llvm::AMDGPU::SendMsg::getMsgIdMask(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormat(), imageIntrinsicOptimizerImpl(), isGFX10Plus(), llvm::AMDGPUDisassembler::isGFX11Plus(), isNotGFX11Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::SendMsg::isValidMsgOp(), llvm::AMDGPU::SendMsg::isValidMsgStream(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPU::SendMsg::msgRequiresOp(), and llvm::AMDGPU::SendMsg::msgSupportsStream().

isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10

(

const MCSubtargetInfo &

STI

)

Definition at line 2012 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX9(), and isVI().

isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2016 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and isVI().

isGFX9()

bool llvm::AMDGPU::isGFX9

(

const MCSubtargetInfo &

STI

)

Definition at line 2004 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9Plus(), and isNotGFX10Plus().

isGFX90A()

bool llvm::AMDGPU::isGFX90A

(

const MCSubtargetInfo &

STI

)

Definition at line 2068 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getDefaultAmdhsaKernelDescriptor(), and llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().

isGFX940()

bool llvm::AMDGPU::isGFX940

(

const MCSubtargetInfo &

STI

)

Definition at line 2072 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10

(

const MCSubtargetInfo &

STI

)

Definition at line 2008 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX9().

isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2020 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX9().

Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), and llvm::AMDGPUDisassembler::isGFX9Plus().

isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment

(

const GlobalValue *

GV

)

Definition at line 1183 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.

isGraphics()

LLVM_READNONE bool llvm::AMDGPU::isGraphics

(

CallingConv::ID

cc

)

Definition at line 1904 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, and isShader().

Referenced by llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

isGroupSegment()

bool llvm::AMDGPU::isGroupSegment

(

const GlobalValue *

GV

)

Definition at line 1179 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

isHi()

bool llvm::AMDGPU::isHi	(	unsigned	Reg,
		const MCRegisterInfo &	MRI
	)

Returns

if Reg occupies the high 16-bits of a 32-bit register. The bit indicating isHi is the LSB of the encoding.

Definition at line 2106 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::EncValues::IS_HI, MRI, and Reg.

isHsaAbi()

bool llvm::AMDGPU::isHsaAbi

(

const MCSubtargetInfo &

STI

)

Returns

True if STI is AMDHSA.

Definition at line 122 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::Triple::getOS(), and llvm::MCSubtargetInfo::getTargetTriple().

isHsaAbiVersion3()

bool llvm::AMDGPU::isHsaAbiVersion3

(

const MCSubtargetInfo *

STI

)

Returns

True if HSA OS ABI Version identification is 3, false otherwise.

Definition at line 143 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3, and getHsaAbiVersion().

isHsaAbiVersion4()

bool llvm::AMDGPU::isHsaAbiVersion4

(

const MCSubtargetInfo *

STI

)

Returns

True if HSA OS ABI Version identification is 4, false otherwise.

Definition at line 149 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, and getHsaAbiVersion().

isHsaAbiVersion5()

bool llvm::AMDGPU::isHsaAbiVersion5

(

const MCSubtargetInfo *

STI

)

Returns

True if HSA OS ABI Version identification is 5, false otherwise.

Definition at line 155 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, and getHsaAbiVersion().

isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t  Literal )

inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line 1269 of file AMDGPUBaseInfo.h.

References llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), isInlinableIntLiteralV216(), isInlinableLiteral16(), isInlinableLiteral32(), isInlinableLiteral64(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().

isInlinableIntLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteralV216

(

int32_t

Literal

)

Definition at line 2494 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16	(	int16_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2460 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlinableLiteralV216(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().

isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32	(	int32_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2434 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIRegisterInfo::eliminateFrameIndex(), and llvm::SIInstrInfo::isInlineConstant().

isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64	(	int64_t	Literal,
		bool	HasInv2Pi
	)

Is this literal inlinable.

Definition at line 2417 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and llvm::SIInstrInfo::isInlineConstant().

isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216	(	int32_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2479 of file AMDGPUBaseInfo.cpp.

References assert(), isInlinableLiteral16(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

isInlineValue()

LLVM_READNONE bool llvm::AMDGPU::isInlineValue

(

unsigned

Reg

)

Definition at line 2187 of file AMDGPUBaseInfo.cpp.

References Reg.

isIntrinsicAlwaysUniform()

bool llvm::AMDGPU::isIntrinsicAlwaysUniform

(

unsigned

IntrID

)

Returns

true if the intrinsic is uniform

Definition at line 2670 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), and llvm::GCNTTIImpl::isAlwaysUniform().

isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence

(

unsigned

IntrID

)

Returns

true if the intrinsic is divergent

Definition at line 2666 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC )

inline

Definition at line 1128 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, CC, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::SITargetLowering::LowerReturn().

isKernelCC()

bool llvm::AMDGPU::isKernelCC

(

const Function *

Func

)

Definition at line 1948 of file AMDGPUBaseInfo.cpp.

References isModuleEntryFunctionCC().

isKImmOperand()

bool llvm::AMDGPU::isKImmOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this a KImm operand?

Definition at line 2223 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_KIMM_FIRST, and OPERAND_KIMM_LAST.

isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower

(

const GlobalVariable &

GV

)

Definition at line 47 of file AMDGPUMemoryUtils.cpp.

References llvm::GlobalVariable::getInitializer(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalVariable::hasInitializer(), llvm::GlobalVariable::isConstant(), isDynamicLDS(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

isLegalDPALU_DPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegalDPALU_DPPControl ( unsigned  DC )

inline

Definition at line 1335 of file AMDGPUBaseInfo.h.

References llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, and llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.

Referenced by llvm::SIInstrInfo::expandMovDPP64(), and llvm::SIInstrInfo::verifyInstruction().

isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset,
		bool	IsBuffer
	)

Definition at line 2588 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset().

isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset
	)

Definition at line 2582 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset().

Referenced by getSMRDEncodedOffset().

isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset
	)

Returns

true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

isMAC()

LLVM_READNONE bool llvm::AMDGPU::isMAC

(

unsigned

Opc

)

Definition at line 475 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

isModuleEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC

(

CallingConv::ID

CC

)

Definition at line 1929 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, CC, and isEntryFunctionCC().

Referenced by isKernelCC().

isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2044 of file AMDGPUBaseInfo.cpp.

References isCI(), isGFX9(), isSI(), and isVI().

isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus

(

const MCSubtargetInfo &

STI

)

Definition at line 2040 of file AMDGPUBaseInfo.cpp.

References isGFX11Plus().

isPermlane16()

LLVM_READNONE bool llvm::AMDGPU::isPermlane16

(

unsigned

Opc

)

Definition at line 496 of file AMDGPUBaseInfo.cpp.

isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment

(

const GlobalValue *

GV

)

Definition at line 1187 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber	(	const Value *	Ptr,
		MemoryDef *	Def,
		AAResults *	AA
	)

Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line 68 of file AMDGPUMemoryUtils.cpp.

References I, llvm::AAResults::isNoAlias(), and Ptr.

Referenced by isClobberedInFunction().

isSGPR()

bool llvm::AMDGPU::isSGPR	(	unsigned	Reg,
		const MCRegisterInfo *	TRI
	)

Is Reg - scalar register.

Definition at line 2099 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), Reg, and TRI.

isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader

(

CallingConv::ID

cc

)

Definition at line 1887 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.

Referenced by llvm::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().

isSI()

bool llvm::AMDGPU::isSI

(

const MCSubtargetInfo &

STI

)

Definition at line 1992 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().

isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this floating-point operand?

Definition at line 2230 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2FP32.

isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Does this operand support only inlinable literals?

Definition at line 2256 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_INLINE_C_FIRST, and OPERAND_REG_INLINE_C_LAST.

isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

Definition at line 2216 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_SRC_FIRST, and OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIInstrInfo::isOperandLegal().

isSymbolicCustomOperandEncoding()

static bool llvm::AMDGPU::isSymbolicCustomOperandEncoding ( const CustomOperandVal *  Opr, int  Size, unsigned  Code, bool &  HasNonDefaultVal, const MCSubtargetInfo &  STI  )

static

Definition at line 1387 of file AMDGPUBaseInfo.cpp.

References Idx, and Size.

Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().

isTrue16Inst()

LLVM_READONLY bool llvm::AMDGPU::isTrue16Inst

(

unsigned

Opc

)

Definition at line 525 of file AMDGPUBaseInfo.cpp.

References Info.

isValidOpr()

template<class T >

static bool llvm::AMDGPU::isValidOpr ( int  Idx, const CustomOperand< T >  OpInfo[], int  OpInfoSize, T  Context  )

static

Definition at line 1327 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::CustomOperand< T >::Cond, Context, llvm::StringRef::empty(), Idx, and llvm::AMDGPU::CustomOperand< T >::Name.

isVI()

bool llvm::AMDGPU::isVI

(

const MCSubtargetInfo &

STI

)

Definition at line 2000 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().

isVOPC64DPP()

LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP

(

unsigned

Opc

)

Definition at line 444 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), and llvm::AMDGPUDisassembler::getInstruction().

isVOPD()

LLVM_READONLY bool llvm::AMDGPU::isVOPD

(

unsigned

Opc

)

Definition at line 471 of file AMDGPUBaseInfo.cpp.

References hasNamedOperand().

Referenced by getSrcOperandIndices().

lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic * llvm::AMDGPU::lookupD16ImageDimIntrinsic

(

unsigned

Intr

)

lookupRsrcIntrinsic()

const RsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic

(

unsigned

Intr

)

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::SITargetLowering::getTgtMemIntrinsic().

mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode

(

unsigned

Opc

)

Definition at line 530 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

mapWMMA3AddrTo2AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode

(

unsigned

Opc

)

Definition at line 535 of file AMDGPUBaseInfo.cpp.

References Info.

mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg

(

unsigned

Reg

)

Convert hardware register Reg to a pseudo register.

Definition at line 2183 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN

(

StringRef

CPU

)

Definition at line 155 of file TargetParser.cpp.

References llvm::CallingConv::C.

Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), llvm::AMDGPUTargetStreamer::getElfMach(), getIsaVersion(), and isWave32Capable().

parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600

(

StringRef

CPU

)

Definition at line 164 of file TargetParser.cpp.

References llvm::CallingConv::C.

Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().

shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection

(

const Triple &

TT

)

Returns

True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 1193 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::r600.

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().

Variable Documentation

ExtendedFltRoundOffset

constexpr uint32_t llvm::AMDGPU::ExtendedFltRoundOffset = 4

staticconstexpr

Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.

Definition at line 133 of file SIModeRegisterDefaults.h.

Referenced by decodeIndexFltRoundConversionTable(), and encodeFltRoundsTable().

F32FltRoundOffset

constexpr uint32_t llvm::AMDGPU::F32FltRoundOffset = 0

staticconstexpr

Offset in mode register of f32 rounding mode.

Definition at line 136 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

F64FltRoundOffset

constexpr uint32_t llvm::AMDGPU::F64FltRoundOffset = 2

staticconstexpr

Offset in mode register of f64/f16 rounding mode.

Definition at line 139 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

FltRoundConversionTable

const uint64_t llvm::AMDGPU::FltRoundConversionTable

extern

Definition at line 80 of file SIModeRegisterDefaults.cpp.

Referenced by decodeIndexFltRoundConversionTable(), and llvm::SITargetLowering::lowerGET_ROUNDING().

OPR_ID_DUPLICATE

const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3

Definition at line 25 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand().

OPR_ID_UNKNOWN

const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1

Definition at line 23 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getOprIdx().

OPR_ID_UNSUPPORTED

const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2

Definition at line 24 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getOprIdx().

OPR_VAL_INVALID

const int llvm::AMDGPU::OPR_VAL_INVALID = -4

Definition at line 26 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperandVal().

RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 1393 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().

RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 1394 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 1395 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 1396 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().