LLVM 23.0.0git
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llvm::AMDGPU Namespace Reference

Namespaces

namespace  Barrier
namespace  CPol
namespace  DepCtr
namespace  DPP
namespace  DWARFAS
namespace  ElfNote
namespace  EncValues
namespace  Exp
namespace  FlavorGroups
namespace  GenericVersion
 Generic target versions emitted by this version of LLVM.
namespace  HSAMD
namespace  HWEncoding
namespace  Hwreg
namespace  impl
namespace  ImplicitArg
namespace  IsaInfo
namespace  MFMAScaleFormats
namespace  MTBUFFormat
namespace  PALMD
namespace  SDWA
namespace  SendMsg
namespace  Swizzle
namespace  UCVersion
namespace  UfmtGFX10
namespace  UfmtGFX11
namespace  VGPRIndexMode
namespace  VirtRegFlag
namespace  VOP3PEncoding
namespace  VOPD
namespace  WaitEvent
namespace  WMMA
namespace  WMMAMods

Classes

class  AMDGPUMCInstrAnalysis
struct  AMDGPUMCKernelCodeT
struct  CanBeVOPD
class  ClusterDimsAttr
struct  CustomOperand
struct  CustomOperandVal
struct  CvtScaleF32_F32F16ToF8F4_Info
struct  D16ImageDimIntrinsic
struct  DPMACCInstructionInfo
struct  EncodingField
struct  EncodingFields
struct  FP4FP8DstByteSelInfo
struct  FuncInfo
struct  GcnBufferFormatInfo
struct  HardwareLimits
 Represents the hardware counter limits for different wait count types. More...
struct  ImageDimIntrinsicInfo
struct  Incoming
 Incoming for lane mask phi as machine instruction, incoming register Reg and incoming block Block are taken from machine instruction. More...
struct  InfoSectionData
class  IntrinsicLaneMaskAnalyzer
struct  IsaVersion
 Instruction set architecture version. More...
class  LaneMaskConstants
struct  LDSUsesInfoTy
struct  MAIInstInfo
struct  MCKernelDescriptor
struct  MFMA_F8F6F4_Info
struct  MIMGBaseOpcodeInfo
struct  MIMGBiasMappingInfo
struct  MIMGDimInfo
struct  MIMGG16MappingInfo
struct  MIMGInfo
struct  MIMGLZMappingInfo
struct  MIMGMIPMappingInfo
struct  MIMGOffsetMappingInfo
struct  MTBUFInfo
struct  MUBUFInfo
class  PhiLoweringHelper
struct  PredicateMapping
class  RegBankLegalizeHelper
struct  RegBankLegalizeRule
class  RegBankLegalizeRules
struct  RegBankLLTMapping
struct  RsrcIntrinsic
class  SetOfRulesForOpcode
struct  SMInfo
struct  True16D16Info
struct  VOP3CDPPAsmOnlyInfo
struct  VOPC64DPPInfo
struct  VOPCDPPAsmOnlyInfo
struct  VOPDComponentInfo
struct  VOPDInfo
struct  VOPDXYInfo
struct  VOPInfo
struct  VOPTrue16Info
class  Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction. More...
struct  WaterfallInfo
 Holds waterfall loop information: the set of SGPR operand registers that need waterfalling, and an instruction range [Start, End) to wrap in the loop. More...
struct  WMMAInstInfo
struct  WMMAOpcodeMappingInfo

Typedefs

using FlavorGroup = SmallVector<InstructionFlavor, 4>
using FunctionVariableMap = DenseMap<Function *, DenseSet<GlobalVariable *>>
using VariableFunctionMap = DenseMap<GlobalVariable *, DenseSet<Function *>>
template<unsigned Bit, unsigned D = 0>
using EncodingBit = EncodingField<Bit, Bit, D>

Enumerations

enum class  InfoKind : uint8_t {
  INFO_FUNC = 1 , INFO_FLAGS = 2 , INFO_NUM_SGPR = 3 , INFO_NUM_VGPR = 4 ,
  INFO_NUM_AGPR = 5 , INFO_PRIVATE_SEGMENT_SIZE = 6 , INFO_USE = 7 , INFO_CALL = 8 ,
  INFO_INDIRECT_CALL = 9 , INFO_TYPEID = 10
}
 Entry kind values for the .amdgpu.info section. More...
enum class  FuncInfoFlags : uint32_t { FUNC_USES_VCC = 1U << 0 , FUNC_USES_FLAT_SCRATCH = 1U << 1 , FUNC_HAS_DYN_STACK = 1U << 2 , LLVM_MARK_AS_BITMASK_ENUM =(FUNC_HAS_DYN_STACK) }
 Per-function flags packed into INFO_FLAGS entries. More...
enum  GPUKind : uint32_t { GK_NONE = 0 , GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC , GK_AMDGCN_GENERIC_LAST = GK_GFX12_5_GENERIC }
 GPU kinds supported by the AMDGPU target. More...
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0 , FEATURE_FMA = 1 << 1 , FEATURE_LDEXP = 1 << 2 , FEATURE_FP64 = 1 << 3 ,
  FEATURE_FAST_FMA_F32 = 1 << 4 , FEATURE_FAST_DENORMAL_F32 = 1 << 5 , FEATURE_WAVE32 = 1 << 6 , FEATURE_XNACK = 1 << 7 ,
  FEATURE_SRAMECC = 1 << 8 , FEATURE_WGP = 1 << 9 , FEATURE_XNACK_ALWAYS = 1 << 10
}
enum  FeatureError : uint32_t { NO_ERROR = 0 , INVALID_FEATURE_COMBINATION , UNSUPPORTED_TARGET_FEATURE }
enum  TargetIndex {
  TI_CONSTDATA_START , TI_SCRATCH_RSRC_DWORD0 , TI_SCRATCH_RSRC_DWORD1 , TI_SCRATCH_RSRC_DWORD2 ,
  TI_SCRATCH_RSRC_DWORD3
}
enum class  InstructionFlavor : uint8_t {
  WMMA , SingleCycleVALU , TRANS , MultiCycleVALU ,
  VMEM , DS , SALU , DMA ,
  Fence , Other , NUM_FLAVORS
}
enum class  AMDGPUSchedReason : uint8_t { None , CritResourceBalance , CritResourceDep , NUM_REASONS }
 AMDGPU-specific scheduling decision reasons. More...
enum class  SchedulingPhase { Initial , PreRAReentry , PostRA }
enum  IGLPStrategyID : int { MFMASmallGemmOptID = 0 , MFMASmallGemmSingleWaveOptID = 1 , MFMAExpInterleaveID = 2 , MFMAExpSimpleInterleaveID = 3 }
 Operand 0 immediate for IGLP_OPT pseudo instructions. More...
enum  UniformityLLTOpPredicateID {
  _ , S1 , S16 , S32 ,
  S64 , S128 , UniS1 , UniS16 ,
  UniS32 , UniS64 , UniS128 , DivS1 ,
  DivS16 , DivS32 , DivS64 , DivS128 ,
  DivAnyTy , P0 , P1 , P2 ,
  P3 , P4 , P5 , P8 ,
  Ptr32 , Ptr64 , Ptr128 , UniP0 ,
  UniP1 , UniP2 , UniP3 , UniP4 ,
  UniP5 , UniP8 , UniPtr32 , UniPtr64 ,
  UniPtr128 , DivP0 , DivP1 , DivP2 ,
  DivP3 , DivP4 , DivP5 , DivPtr32 ,
  DivPtr64 , DivPtr128 , V2S16 , V2S32 ,
  V2S64 , V3S32 , V4S32 , UniV2S16 ,
  UniV2S32 , UniV2S64 , DivV2S16 , DivV2S32 ,
  DivV2S64 , DivV3S32 , DivV4S16 , DivV6S32 ,
  B32 , B64 , B96 , B128 ,
  B160 , B256 , B512 , BRC ,
  UniB32 , UniB64 , UniB96 , UniB128 ,
  UniB160 , UniB256 , UniB512 , UniBRC ,
  DivB32 , DivB64 , DivB96 , DivB128 ,
  DivB160 , DivB256 , DivB512 , DivBRC
}
enum  RegBankLLTMappingApplyID {
  InvalidMapping , None , IntrId , Imm ,
  Vcc , VgprAnyTy , AgprAnyTy , Sgpr16 ,
  Sgpr32 , Sgpr64 , Sgpr128 , SgprP0 ,
  SgprP1 , SgprP2 , SgprP3 , SgprP4 ,
  SgprP5 , SgprP8 , SgprPtr32 , SgprPtr64 ,
  SgprPtr128 , SgprV2S16 , SgprV4S32 , SgprV2S32 ,
  SgprB32 , SgprB64 , SgprB96 , SgprB128 ,
  SgprB256 , SgprB512 , SgprBRC , Vgpr16 ,
  Vgpr32 , Vgpr64 , Vgpr128 , VgprP0 ,
  VgprP1 , VgprP2 , VgprP3 , VgprP4 ,
  VgprP5 , VgprPtr32 , VgprPtr64 , VgprPtr128 ,
  VgprV2S16 , VgprV2S32 , VgprV3S32 , VgprB32 ,
  VgprB64 , VgprB96 , VgprB128 , VgprB160 ,
  VgprB256 , VgprB512 , VgprBRC , VgprV4S16 ,
  VgprV4S32 , VgprV8S32 , VgprV2S64 , UniInVcc ,
  UniInVgprS16 , UniInVgprS32 , UniInVgprS64 , UniInVgprV2S16 ,
  UniInVgprV2S32 , UniInVgprV4S32 , UniInVgprV2S64 , UniInVgprB32 ,
  UniInVgprB64 , UniInVgprB96 , UniInVgprB128 , UniInVgprB160 ,
  UniInVgprB256 , UniInVgprB512 , Sgpr32Trunc , Sgpr32ToVgprDst ,
  Sgpr64ToVgprDst , Sgpr32_WF , SgprV4S32_WF , SgprP0Call_WF ,
  SgprP4Call_WF , SgprB32_M0 , SgprB32_ReadFirstLane , SgprB64_ReadFirstLane ,
  SgprV4S32_ReadFirstLane , Sgpr32AExt , Sgpr32AExtBoolInReg , Sgpr32SExt ,
  Sgpr32ZExt , Vgpr32AExt , Vgpr32SExt , Vgpr32ZExt ,
  VgprV6S32 , VgprV32S16 , VgprV32S32
}
enum  LoweringMethodID {
  DoNotLower , VccExtToSel , UniExtToSel , UnpackBitShift ,
  UnpackMinMax , S_BFE , V_BFE , VgprToVccCopy ,
  UniMAD64 , UniMul64 , DivSMulToMAD , SplitTo32 ,
  SplitTo32Mul , ScalarizeToS16 , SplitTo32Select , SplitTo32SExtInReg ,
  Ext32To64 , UniCstExt , CtPop64To32 , SplitLoad ,
  WidenLoad , WidenMMOToS32 , UnpackAExt , VerifyAllSgpr ,
  ApplyAllVgpr , UnmergeToShiftTrunc , AextToS32InIncomingBlockGPHI , VerifyAllSgprGPHI ,
  VerifyAllSgprOrVgprGPHI , ApplyINTRIN_IMAGE , ApplyBVH_INTERSECT_RAY , SplitBitCount64To32 ,
  ExtrVecEltToSel , ExtrVecEltTo32 , InsVecEltToSel , InsVecEltTo32 ,
  AbsToNegMax , AbsToS32
}
enum  FastRulesTypes { NoFastRules , Standard , StandardB , Vector }
enum  InstCounterType {
  LOAD_CNT = 0 , DS_CNT , EXP_CNT , STORE_CNT ,
  NUM_NORMAL_INST_CNTS , SAMPLE_CNT = NUM_NORMAL_INST_CNTS , BVH_CNT , KM_CNT ,
  X_CNT , ASYNC_CNT , NUM_EXTENDED_INST_CNTS , VA_VDST = NUM_EXTENDED_INST_CNTS ,
  VM_VSRC , NUM_EXPERT_INST_CNTS , NUM_INST_CNTS = NUM_EXPERT_INST_CNTS
}
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum  OperandType : unsigned {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET , OPERAND_REG_IMM_INT64 , OPERAND_REG_IMM_INT16 , OPERAND_REG_IMM_FP32 ,
  OPERAND_REG_IMM_FP64 , OPERAND_REG_IMM_BF16 , OPERAND_REG_IMM_FP16 , OPERAND_REG_IMM_V2BF16 ,
  OPERAND_REG_IMM_V2FP16 , OPERAND_REG_IMM_V2FP16_SPLAT , OPERAND_REG_IMM_V2INT16 , OPERAND_REG_IMM_NOINLINE_V2FP16 ,
  OPERAND_REG_IMM_V2INT32 , OPERAND_REG_IMM_V2FP32 , OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_INT32 ,
  OPERAND_REG_INLINE_C_INT64 , OPERAND_REG_INLINE_C_BF16 , OPERAND_REG_INLINE_C_FP16 , OPERAND_REG_INLINE_C_FP32 ,
  OPERAND_REG_INLINE_C_FP64 , OPERAND_REG_INLINE_C_V2INT16 , OPERAND_REG_INLINE_C_V2BF16 , OPERAND_REG_INLINE_C_V2FP16 ,
  OPERAND_INLINE_SPLIT_BARRIER_INT32 , OPERAND_KIMM32 , OPERAND_KIMM16 , OPERAND_KIMM64 ,
  OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_FP32 , OPERAND_REG_INLINE_AC_FP64 , OPERAND_INLINE_C_AV64_PSEUDO ,
  OPERAND_INPUT_MODS , OPERAND_SDWA_VOPC_DST , OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32 ,
  OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64 , OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO ,
  OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST , OPERAND_KIMM_FIRST = OPERAND_KIMM32 , OPERAND_KIMM_LAST = OPERAND_KIMM64
}
enum  AsmComments : MachineInstr::AsmPrinterFlagTy { SGPR_SPILL = MachineInstr::TAsmComments }
enum  AMDGPUFltRounds : int8_t {
  TowardZero = static_cast<int8_t>(RoundingMode::TowardZero) , NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven) , TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive) , TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative) ,
  NearestTiesToAwayUnsupported , Dynamic = static_cast<int8_t>(RoundingMode::Dynamic) , NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven , NearestTiesToEvenF32_TowardPositiveF64 = 8 ,
  NearestTiesToEvenF32_TowardNegativeF64 = 9 , NearestTiesToEvenF32_TowardZeroF64 = 10 , TowardPositiveF32_NearestTiesToEvenF64 = 11 , TowardPositiveF32_TowardPositiveF64 = TowardPositive ,
  TowardPositiveF32_TowardNegativeF64 = 12 , TowardPositiveF32_TowardZeroF64 = 13 , TowardNegativeF32_NearestTiesToEvenF64 = 14 , TowardNegativeF32_TowardPositiveF64 = 15 ,
  TowardNegativeF32_TowardNegativeF64 = TowardNegative , TowardNegativeF32_TowardZeroF64 = 16 , TowardZeroF32_NearestTiesToEvenF64 = 17 , TowardZeroF32_TowardPositiveF64 = 18 ,
  TowardZeroF32_TowardNegativeF64 = 19 , TowardZeroF32_TowardZeroF64 = TowardZero , Invalid = static_cast<int8_t>(RoundingMode::Invalid)
}
 Return values used for llvm.get.rounding. More...
enum  { AMDHSA_COV4 = 4 , AMDHSA_COV5 = 5 , AMDHSA_COV6 = 6 }
enum class  FPType { None , FP4 , FP8 }

Functions

bool isFlatGlobalAddrSpace (unsigned AS)
bool isExtendedGlobalAddrSpace (unsigned AS)
bool isConstantAddressSpace (unsigned AS)
constexpr int mapToDWARFAddrSpace (unsigned LLVMAddrSpace)
 If LLVMAddressSpace has a corresponding DWARF encoding, return it; otherwise return the sentinel value -1 to indicate no such mapping exists.
constexpr int64_t getNullPointerValue (unsigned AS)
 Get the null pointer value for the given address space.
LLVM_ABI StringRef getArchFamilyNameAMDGCN (GPUKind AK)
LLVM_ABI StringRef getArchNameAMDGCN (GPUKind AK)
LLVM_ABI StringRef getArchNameR600 (GPUKind AK)
LLVM_ABI StringRef getCanonicalArchName (const Triple &T, StringRef Arch)
LLVM_ABI GPUKind parseArchAMDGCN (StringRef CPU)
LLVM_ABI GPUKind parseArchR600 (StringRef CPU)
LLVM_ABI unsigned getArchAttrAMDGCN (GPUKind AK)
LLVM_ABI unsigned getArchAttrR600 (GPUKind AK)
LLVM_ABI void fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
LLVM_ABI void fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
LLVM_ABI IsaVersion getIsaVersion (StringRef GPU)
LLVM_ABI std::pair< FeatureError, StringRef > fillAMDGPUFeatureMap (StringRef GPU, const Triple &T, StringMap< bool > &Features)
 Fills Features map with default values for given target GPU.
static bool addrspacesMayAlias (unsigned AS1, unsigned AS2)
static uint64_t getRedzoneSizeForScale (int AsanScale)
static uint64_t getMinRedzoneSizeForGlobal (int AsanScale)
uint64_t getRedzoneSizeForGlobal (int Scale, uint64_t SizeInBytes)
 Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.
static size_t TypeStoreSizeToSizeIndex (uint32_t TypeSize)
static Instruction * genAMDGPUReportBlock (Module &M, IRBuilder<> &IRB, Value *Cond, bool Recover)
static Value * createSlowPathCmp (Module &M, IRBuilder<> &IRB, Type *IntptrTy, Value *AddrLong, Value *ShadowValue, uint32_t TypeStoreSize, int AsanScale)
static Instruction * generateCrashCode (Module &M, IRBuilder<> &IRB, Type *IntptrTy, Instruction *InsertBefore, Value *Addr, bool IsWrite, size_t AccessSizeIndex, Value *SizeArgument, bool Recover)
static Value * memToShadow (Module &M, IRBuilder<> &IRB, Type *IntptrTy, Value *Shadow, int AsanScale, uint32_t AsanOffset)
static void instrumentAddressImpl (Module &M, IRBuilder<> &IRB, Instruction *OrigIns, Instruction *InsertBefore, Value *Addr, Align Alignment, uint32_t TypeStoreSize, bool IsWrite, Value *SizeArgument, bool UseCalls, bool Recover, int AsanScale, int AsanOffset)
void instrumentAddress (Module &M, IRBuilder<> &IRB, Instruction *OrigIns, Instruction *InsertBefore, Value *Addr, Align Alignment, TypeSize TypeStoreSize, bool IsWrite, Value *SizeArgument, bool UseCalls, bool Recover, int Scale, int Offset)
 Instrument the memory operand Addr.
void getInterestingMemoryOperands (Module &M, Instruction *I, SmallVectorImpl< InterestingMemoryOperand > &Interesting)
 Get all the memory operands from the instruction that needs to be instrumented.
constexpr StringRef getFlavorName (InstructionFlavor F)
constexpr StringRef getFlavorShortName (InstructionFlavor F)
InstructionFlavor classifyFlavor (const MachineInstr &MI, const SIInstrInfo &SII)
constexpr StringRef getReasonName (AMDGPUSchedReason R)
std::pair< Register, unsigned > getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg, GISelValueTracking *ValueTracking=nullptr, bool CheckNUW=false)
 Returns base register and constant offset.
void buildReadAnyLane (MachineIRBuilder &B, Register SgprDst, Register VgprSrc, const RegisterBankInfo &RBI)
void buildReadFirstLane (MachineIRBuilder &B, Register SgprDst, Register VgprSrc, const RegisterBankInfo &RBI)
bool isUniformMMO (const MachineMemOperand *MMO)
Intrinsic::ID getIntrinsicID (const MachineInstr &I)
 Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
const RsrcIntrinsic * lookupRsrcIntrinsic (unsigned Intr)
const D16ImageDimIntrinsic * lookupD16ImageDimIntrinsic (unsigned Intr)
const ImageDimIntrinsicInfo * getImageDimIntrinsicInfo (unsigned Intr)
const ImageDimIntrinsicInfo * getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)
Align getAlign (const DataLayout &DL, const GlobalVariable *GV)
static TargetExtType * getTargetExtType (const GlobalVariable &GV)
TargetExtType * isNamedBarrier (const GlobalVariable &GV)
bool isDynamicLDS (const GlobalVariable &GV)
bool isLDSVariableToLower (const GlobalVariable &GV)
bool eliminateConstantExprUsesOfLDSFromAllInstructions (Module &M)
void getUsesOfLDSByFunction (const CallGraph &CG, Module &M, FunctionVariableMap &kernels, FunctionVariableMap &Functions)
LDSUsesInfoTy getTransitiveUsesOfLDS (const CallGraph &CG, Module &M)
void removeFnAttrFromReachable (CallGraph &CG, Function *KernelRoot, ArrayRef< StringRef > FnAttrs)
 Strip FnAttr attribute from any functions where we may have introduced its use.
bool isReallyAClobber (const Value *Ptr, MemoryDef *Def, AAResults *AA)
 Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
bool isClobberedInFunction (const LoadInst *Load, MemorySSA *MSSA, AAResults *AA)
 Check is a Load is clobbered in its function.
bool isAnyPtr (LLT Ty, unsigned Width)
StringRef getSchedStrategy (const Function &F)
iota_range< InstCounterType > inst_counter_types (InstCounterType MaxCounter)
StringLiteral getInstCounterName (InstCounterType T)
Waitcnt decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
unsigned encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
Waitcnt decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)
Waitcnt decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)
unsigned encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
unsigned encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
void printAMDGPUMCExpr (const MCExpr *Expr, raw_ostream &OS, const MCAsmInfo *MAI)
const MCExpr * foldAMDGPUMCExpr (const MCExpr *Expr, MCContext &Ctx)
static AMDGPUMCExpr::Specifier getSpecifier (const MCSymbolRefExpr *SRE)
LLVM_READONLY bool isLitExpr (const MCExpr *Expr)
LLVM_READONLY int64_t getLitValue (const MCExpr *Expr)
LLVM_READONLY AMDGPUMCExpr::VariantKind getExprKind (const MCExpr *Expr)
LLVM_READONLY int32_t getVOPe64 (uint32_t Opcode)
LLVM_READONLY int32_t getVOPe32 (uint32_t Opcode)
LLVM_READONLY int32_t getSDWAOp (uint32_t Opcode)
LLVM_READONLY int32_t getDPPOp32 (uint32_t Opcode)
LLVM_READONLY int32_t getDPPOp64 (uint32_t Opcode)
LLVM_READONLY int32_t getBasicFromSDWAOp (uint32_t Opcode)
LLVM_READONLY int32_t getCommuteRev (uint32_t Opcode)
LLVM_READONLY int32_t getCommuteOrig (uint32_t Opcode)
LLVM_READONLY int32_t getAddr64Inst (uint32_t Opcode)
LLVM_READONLY int32_t getIfAddr64Inst (uint32_t Opcode)
 Check if Opcode is an Addr64 opcode.
LLVM_READONLY int32_t getSOPKOp (uint32_t Opcode)
LLVM_READONLY int32_t getGlobalSaddrOp (uint32_t Opcode)
LLVM_READONLY int32_t getGlobalVaddrOp (uint32_t Opcode)
LLVM_READONLY int32_t getVCMPXNoSDstOp (uint32_t Opcode)
LLVM_READONLY int32_t getFlatScratchInstSTfromSS (uint32_t Opcode)
LLVM_READONLY int32_t getFlatScratchInstSVfromSVS (uint32_t Opcode)
LLVM_READONLY int32_t getFlatScratchInstSSfromSV (uint32_t Opcode)
LLVM_READONLY int32_t getFlatScratchInstSVfromSS (uint32_t Opcode)
LLVM_READONLY int32_t getMFMAEarlyClobberOp (uint32_t Opcode)
LLVM_READONLY int32_t getMFMASrcCVDstAGPROp (uint32_t Opcode)
LLVM_READONLY int32_t getVCMPXOpFromVCMP (uint32_t Opcode)
Register createLaneMaskReg (MachineRegisterInfo *MRI, MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs)
uint32_t decodeFltRoundToHWConversionTable (uint32_t FltRounds)
 Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
unsigned getRegBitWidth (const TargetRegisterClass &RC)
 Get the size in bits of a register from the register class RC.
template<size_t N>
static StringRef getNameFromOperandTable (const CustomOperand(&Table)[N], unsigned Encoding, const MCSubtargetInfo &STI)
 Map from the encoding of a sendmsg/hwreg asm operand to it's name.
template<size_t N>
static int64_t getEncodingFromOperandTable (const CustomOperand(&Table)[N], StringRef Name, const MCSubtargetInfo &STI)
 Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.
bool hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
bool isHsaAbi (const MCSubtargetInfo &STI)
unsigned getAMDHSACodeObjectVersion (const Module &M)
unsigned getDefaultAMDHSACodeObjectVersion ()
unsigned getAMDHSACodeObjectVersion (unsigned ABIVersion)
uint8_t getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)
unsigned getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
unsigned getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
unsigned getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
unsigned getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
int getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode (unsigned Opc)
int getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
unsigned getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFBaseOpcode (unsigned Opc)
int getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
int getMTBUFElements (unsigned Opc)
bool getMTBUFHasVAddr (unsigned Opc)
bool getMTBUFHasSrsrc (unsigned Opc)
bool getMTBUFHasSoffset (unsigned Opc)
int getMUBUFBaseOpcode (unsigned Opc)
int getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
int getMUBUFElements (unsigned Opc)
bool getMUBUFHasVAddr (unsigned Opc)
bool getMUBUFHasSrsrc (unsigned Opc)
bool getMUBUFHasSoffset (unsigned Opc)
bool getMUBUFIsBufferInv (unsigned Opc)
bool getMUBUFTfe (unsigned Opc)
bool getSMEMIsBuffer (unsigned Opc)
bool getVOP1IsSingle (unsigned Opc)
bool getVOP2IsSingle (unsigned Opc)
bool getVOP3IsSingle (unsigned Opc)
bool isVOPC64DPP (unsigned Opc)
bool isVOPCAsmOnly (unsigned Opc)
bool getMAIIsDGEMM (unsigned Opc)
 Returns true if MAI operation is a double precision GEMM.
bool getMAIIsGFX940XDL (unsigned Opc)
bool getWMMAIsXDL (unsigned Opc)
bool getHasMatrixScale (unsigned Opc)
uint8_t mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)
const MFMA_F8F6F4_Info * getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
uint8_t wmmaScaleF8F6F4FormatToNumRegs (unsigned Fmt)
const MFMA_F8F6F4_Info * getWMMA_F8F6F4_WithFormatArgs (unsigned FmtA, unsigned FmtB, unsigned F8F8Opcode)
unsigned getVOPDEncodingFamily (const MCSubtargetInfo &ST)
static constexpr unsigned getVOPDXYKey (unsigned VOPDOp, unsigned Subtarget, bool VOPD3)
static constexpr std::array< CanBeVOPD, 1<< VOPDXYKeyBits > buildVOPDXYLookup ()
CanBeVOPD getCanBeVOPD (unsigned Opc, unsigned EncodingFamily, bool VOPD3)
unsigned getVOPDOpcode (unsigned Opc, bool VOPD3)
bool isVOPD (unsigned Opc)
bool isMAC (unsigned Opc)
bool isPermlane16 (unsigned Opc)
bool isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)
bool isGenericAtomic (unsigned Opc)
bool isAsyncStore (unsigned Opc)
bool isTensorStore (unsigned Opc)
unsigned getTemporalHintType (const MCInstrDesc TID)
bool isTrue16Inst (unsigned Opc)
FPType getFPDstSelType (unsigned Opc)
bool isDPMACCInstruction (unsigned Opc)
unsigned mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
unsigned mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
int32_t getMCOpcode (uint32_t Opcode, unsigned Gen)
unsigned getBitOp2 (unsigned Opc)
int getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily, bool VOPD3)
std::pair< unsigned, unsigned > getVOPDComponents (unsigned VOPDOpcode)
VOPD::InstInfo getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)
VOPD::InstInfo getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)
void initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo &STI)
bool isGroupSegment (const GlobalValue *GV)
bool isGlobalSegment (const GlobalValue *GV)
bool isReadOnlySegment (const GlobalValue *GV)
bool shouldEmitConstantsToTextSection (const Triple &TT)
static bool isValidRegPrefix (char C)
std::tuple< char, unsigned, unsigned > parseAsmPhysRegName (StringRef TupleString)
 Returns a valid charcode or 0 in the first entry if this is a valid physical register name.
std::tuple< char, unsigned, unsigned > parseAsmConstraintPhysReg (StringRef Constraint)
 Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.
std::pair< unsigned, unsigned > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
std::optional< std::pair< unsigned, std::optional< unsigned > > > getIntegerPairAttribute (const Function &F, StringRef Name, bool OnlyFirstRequired)
SmallVector< unsigned > getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)
std::optional< SmallVector< unsigned > > getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size)
 Similar to the function above, but returns std::nullopt if any error occurs.
bool hasValueInRangeLikeMetadata (const MDNode &MD, int64_t Val)
 Checks if Val is inside MD, a !range-like metadata.
unsigned getVmcntBitMask (const IsaVersion &Version)
unsigned getLoadcntBitMask (const IsaVersion &Version)
unsigned getSamplecntBitMask (const IsaVersion &Version)
unsigned getBvhcntBitMask (const IsaVersion &Version)
unsigned getExpcntBitMask (const IsaVersion &Version)
unsigned getLgkmcntBitMask (const IsaVersion &Version)
unsigned getDscntBitMask (const IsaVersion &Version)
unsigned getKmcntBitMask (const IsaVersion &Version)
unsigned getXcntBitMask (const IsaVersion &Version)
unsigned getAsynccntBitMask (const IsaVersion &Version)
unsigned getStorecntBitMask (const IsaVersion &Version)
unsigned getWaitcntBitMask (const IsaVersion &Version)
unsigned decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned decodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned decodeStorecnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned decodeDscnt (const IsaVersion &Version, unsigned Waitcnt)
void decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.
unsigned encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
unsigned encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
static unsigned getCombinedCountBitMask (const IsaVersion &Version, bool IsStore)
static unsigned encodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
static unsigned encodeStorecnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static unsigned encodeDscnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
unsigned encodeLoadcntDscnt (const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
unsigned encodeStorecntDscnt (const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
static unsigned getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static bool isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
static bool decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
static int encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
static int encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr (const Function &F)
bool getHasColorExport (const Function &F)
bool getHasDepthExport (const Function &F)
unsigned getDynamicVGPRBlockSize (const Function &F)
bool hasXNACK (const MCSubtargetInfo &STI)
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
bool hasA16 (const MCSubtargetInfo &STI)
bool hasG16 (const MCSubtargetInfo &STI)
bool hasPackedD16 (const MCSubtargetInfo &STI)
bool hasGDS (const MCSubtargetInfo &STI)
unsigned getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)
unsigned getMaxNumUserSGPRs (const MCSubtargetInfo &STI)
bool isSI (const MCSubtargetInfo &STI)
bool isCI (const MCSubtargetInfo &STI)
bool isVI (const MCSubtargetInfo &STI)
bool isGFX9 (const MCSubtargetInfo &STI)
bool isGFX9_GFX10 (const MCSubtargetInfo &STI)
bool isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)
bool isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
bool isGFX8Plus (const MCSubtargetInfo &STI)
bool isGFX9Plus (const MCSubtargetInfo &STI)
bool isNotGFX9Plus (const MCSubtargetInfo &STI)
bool isGFX10 (const MCSubtargetInfo &STI)
bool isGFX10_GFX11 (const MCSubtargetInfo &STI)
bool isGFX10Plus (const MCSubtargetInfo &STI)
bool isGFX11 (const MCSubtargetInfo &STI)
bool isGFX11Plus (const MCSubtargetInfo &STI)
bool isGFX12 (const MCSubtargetInfo &STI)
bool isGFX12Plus (const MCSubtargetInfo &STI)
bool isNotGFX12Plus (const MCSubtargetInfo &STI)
bool isGFX1250 (const MCSubtargetInfo &STI)
bool isGFX1250Plus (const MCSubtargetInfo &STI)
bool isGFX13 (const MCSubtargetInfo &STI)
bool isGFX13Plus (const MCSubtargetInfo &STI)
bool supportsWGP (const MCSubtargetInfo &STI)
bool isNotGFX11Plus (const MCSubtargetInfo &STI)
bool isNotGFX10Plus (const MCSubtargetInfo &STI)
bool isGFX10Before1030 (const MCSubtargetInfo &STI)
bool isGCN3Encoding (const MCSubtargetInfo &STI)
bool isGFX10_AEncoding (const MCSubtargetInfo &STI)
bool isGFX10_BEncoding (const MCSubtargetInfo &STI)
bool hasGFX10_3Insts (const MCSubtargetInfo &STI)
bool isGFX10_3_GFX11 (const MCSubtargetInfo &STI)
bool isGFX90A (const MCSubtargetInfo &STI)
bool isGFX940 (const MCSubtargetInfo &STI)
bool hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
bool hasMAIInsts (const MCSubtargetInfo &STI)
bool hasVOPD (const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR (const MCSubtargetInfo &STI)
unsigned hasKernargPreload (const MCSubtargetInfo &STI)
int32_t getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isSGPR (MCRegister Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register.
bool isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister getMCReg (MCRegister Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
MCRegister mc2PseudoReg (MCRegister Reg)
 Convert hardware register Reg to a pseudo register.
bool isInlineValue (MCRegister Reg)
bool isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this a KImm operand?
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand?
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this operand support only inlinable literals?
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC.
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC.
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable.
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi)
bool isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)
std::optional< unsigned > getInlineEncodingV216 (bool IsFloat, uint32_t Literal)
std::optional< unsigned > getInlineEncodingV2I16 (uint32_t Literal)
std::optional< unsigned > getInlineEncodingV2BF16 (uint32_t Literal)
std::optional< unsigned > getInlineEncodingV2F16 (uint32_t Literal)
std::optional< unsigned > getPKFMACF16InlineEncoding (uint32_t Literal, bool IsGFX11Plus)
bool isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)
bool isInlinableLiteralV2I16 (uint32_t Literal)
bool isInlinableLiteralV2BF16 (uint32_t Literal)
bool isInlinableLiteralV2F16 (uint32_t Literal)
bool isPKFMACF16InlineConstant (uint32_t Literal, bool IsGFX11Plus)
bool isValid32BitLiteral (uint64_t Val, bool IsFP64)
int64_t encode32BitLiteral (int64_t Imm, OperandType Type, bool IsLit)
bool isArgPassedInSGPR (const Argument *A)
bool isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)
static bool hasSMEMByteOffset (const MCSubtargetInfo &ST)
bool isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
static bool isDwordAligned (uint64_t ByteOffset)
uint64_t convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
std::optional< int64_t > getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
std::optional< int64_t > getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getNumFlatOffsetBits (const MCSubtargetInfo &ST)
 For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
bool isIntrinsicAlwaysUniform (unsigned IntrID)
const GcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
const GcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
const MCRegisterClass * getVGPRPhysRegClass (MCRegister Reg, const MCRegisterInfo &MRI)
unsigned getVGPREncodingMSBs (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister getVGPRWithMSBs (MCRegister Reg, unsigned MSBs, const MCRegisterInfo &MRI)
 If Reg is a low VGPR return a corresponding high VGPR with MSBs set.
static std::optional< unsigned > convertSetRegImmToVgprMSBs (unsigned Imm, unsigned Simm16, bool HasSetregVGPRMSBFixup)
std::optional< unsigned > convertSetRegImmToVgprMSBs (const MachineInstr &MI, bool HasSetregVGPRMSBFixup)
std::optional< unsigned > convertSetRegImmToVgprMSBs (const MCInst &MI, bool HasSetregVGPRMSBFixup)
std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > getVGPRLoweringOperandTables (const MCInstrDesc &Desc)
bool supportsScaleOffset (const MCInstrInfo &MII, unsigned Opcode)
bool hasAny64BitVGPROperands (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool isDPALU_DPP32BitOpc (unsigned Opc)
bool isDPALU_DPP (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
unsigned getLdsDwGranularity (const MCSubtargetInfo &ST)
bool isPackedFP32Inst (unsigned Opc)
LLVM_READONLY bool hasNamedOperand (uint64_t Opcode, OpName NamedIdx)
LLVM_READONLY int32_t getSOPPWithRelaxation (uint32_t Opcode)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo (unsigned DimEnum)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding (uint8_t DimEnc)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo (unsigned L)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo (unsigned MIP)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo (unsigned Bias)
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo (unsigned Offset)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo (unsigned G)
LLVM_READONLY const MIMGInfo * getMIMGInfo (unsigned Opc)
LLVM_READONLY bool isInvalidSingleUseConsumerInst (unsigned Opc)
LLVM_READONLY bool isInvalidSingleUseProducerInst (unsigned Opc)
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
bool hasDynamicVGPR (const Function &F)
LLVM_READNONE constexpr bool isShader (CallingConv::ID CC)
LLVM_READNONE constexpr bool isGraphics (CallingConv::ID CC)
LLVM_READNONE constexpr bool isCompute (CallingConv::ID CC)
LLVM_READNONE constexpr bool isEntryFunctionCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool isChainCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool isModuleEntryFunctionCC (CallingConv::ID CC)
LLVM_READNONE constexpr bool isKernel (CallingConv::ID CC)
bool isKernel (const Function &F)
LLVM_READNONE constexpr bool canGuaranteeTCO (CallingConv::ID CC)
LLVM_READNONE constexpr bool mayTailCallThisCC (CallingConv::ID CC)
 Return true if we might ever do TCO for calls with this calling convention.
bool supportsWave32 (const MCSubtargetInfo &STI)
constexpr bool isSISrcOperand (const MCOperandInfo &OpInfo)
 Is this an AMDGPU specific source operand?
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
LLVM_READNONE bool isInlinableIntLiteral (int64_t Literal)
 Is this literal inlinable, and not one of the values intended for floating point values.
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
LLVM_READNONE bool isLegalDPALU_DPPControl (const MCSubtargetInfo &ST, unsigned DC)
bool hasAny64BitVGPROperands (const MCInstrDesc &OpDesc, const MCSubtargetInfo &ST)
constexpr std::pair< unsigned, unsigned > getShiftMask (unsigned Value)
 Deduce the least significant bit aligned shift and mask values for a binary Complement Value (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.
const MCExpr * maskShiftSet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
 Provided with the MCExpr * Val, uint32 Mask and Shift, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext Ctx.
const MCExpr * maskShiftGet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
 Provided with the MCExpr * Val, uint32 Mask and Shift, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext Ctx.

Variables

static constexpr LaneMaskConstants LaneMaskConstants32
static constexpr LaneMaskConstants LaneMaskConstants64
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
static constexpr uint32_t ExtendedFltRoundOffset = 4
 Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
static constexpr uint32_t F32FltRoundOffset = 0
 Offset in mode register of f32 rounding mode.
static constexpr uint32_t F64FltRoundOffset = 2
 Offset in mode register of f64/f16 rounding mode.
const uint64_t FltRoundConversionTable
const uint64_t FltRoundToHWConversionTable
const int OPR_ID_UNKNOWN = -1
const int OPR_ID_UNSUPPORTED = -2
const int OPR_ID_DUPLICATE = -3
const int OPR_VAL_INVALID = -4
constexpr unsigned VOPDXYKeyBits = 11
constexpr auto VOPDXYLookup = buildVOPDXYLookup()

Typedef Documentation

◆ EncodingBit

template<unsigned Bit, unsigned D = 0>
using llvm::AMDGPU::EncodingBit = EncodingField<Bit, Bit, D>

Definition at line 421 of file AMDGPUBaseInfo.h.

◆ FlavorGroup

using llvm::AMDGPU::FlavorGroup = SmallVector<InstructionFlavor, 4>

Definition at line 101 of file AMDGPUCoExecSchedStrategy.h.

◆ FunctionVariableMap

using llvm::AMDGPU::FunctionVariableMap = DenseMap<Function *, DenseSet<GlobalVariable *>>

Definition at line 33 of file AMDGPUMemoryUtils.h.

◆ VariableFunctionMap

using llvm::AMDGPU::VariableFunctionMap = DenseMap<GlobalVariable *, DenseSet<Function *>>

Definition at line 34 of file AMDGPUMemoryUtils.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
AMDHSA_COV4 
AMDHSA_COV5 
AMDHSA_COV6 

Definition at line 64 of file AMDGPUBaseInfo.h.

◆ AMDGPUFltRounds

enum llvm::AMDGPU::AMDGPUFltRounds : int8_t

Return values used for llvm.get.rounding.

When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.

Enumerator
TowardZero 
NearestTiesToEven 
TowardPositive 
TowardNegative 
NearestTiesToAwayUnsupported 
Dynamic 
NearestTiesToEvenF32_NearestTiesToEvenF64 
NearestTiesToEvenF32_TowardPositiveF64 
NearestTiesToEvenF32_TowardNegativeF64 
NearestTiesToEvenF32_TowardZeroF64 
TowardPositiveF32_NearestTiesToEvenF64 
TowardPositiveF32_TowardPositiveF64 
TowardPositiveF32_TowardNegativeF64 
TowardPositiveF32_TowardZeroF64 
TowardNegativeF32_NearestTiesToEvenF64 
TowardNegativeF32_TowardPositiveF64 
TowardNegativeF32_TowardNegativeF64 
TowardNegativeF32_TowardZeroF64 
TowardZeroF32_NearestTiesToEvenF64 
TowardZeroF32_TowardPositiveF64 
TowardZeroF32_TowardNegativeF64 
TowardZeroF32_TowardZeroF64 
Invalid 

Definition at line 96 of file SIModeRegisterDefaults.h.

◆ AMDGPUSchedReason

enum class llvm::AMDGPU::AMDGPUSchedReason : uint8_t
strong

AMDGPU-specific scheduling decision reasons.

These provide more granularity than the generic CandReason enum for debugging purposes.

Enumerator
None 
CritResourceBalance 
CritResourceDep 
NUM_REASONS 

Definition at line 124 of file AMDGPUCoExecSchedStrategy.h.

◆ ArchFeatureKind

enum llvm::AMDGPU::ArchFeatureKind : uint32_t
Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 
FEATURE_WAVE32 
FEATURE_XNACK 
FEATURE_SRAMECC 
FEATURE_WGP 
FEATURE_XNACK_ALWAYS 

Definition at line 51 of file AMDGPUTargetParser.h.

◆ AsmComments

enum llvm::AMDGPU::AsmComments : MachineInstr::AsmPrinterFlagTy
Enumerator
SGPR_SPILL 

Definition at line 1912 of file SIInstrInfo.h.

◆ FastRulesTypes

enum llvm::AMDGPU::FastRulesTypes
Enumerator
NoFastRules 
Standard 
StandardB 
Vector 

Definition at line 318 of file AMDGPURegBankLegalizeRules.h.

◆ FeatureError

enum llvm::AMDGPU::FeatureError : uint32_t
Enumerator
NO_ERROR 
INVALID_FEATURE_COMBINATION 
UNSUPPORTED_TARGET_FEATURE 

Definition at line 79 of file AMDGPUTargetParser.h.

◆ Fixups

enum llvm::AMDGPU::Fixups
Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ FPType

enum class llvm::AMDGPU::FPType
strong
Enumerator
None 
FP4 
FP8 

Definition at line 66 of file AMDGPUBaseInfo.h.

◆ FuncInfoFlags

enum class llvm::AMDGPU::FuncInfoFlags : uint32_t
strong

Per-function flags packed into INFO_FLAGS entries.

Enumerator
FUNC_USES_VCC 
FUNC_USES_FLAT_SCRATCH 
FUNC_HAS_DYN_STACK 
LLVM_MARK_AS_BITMASK_ENUM 

Definition at line 64 of file AMDGPUObjLinkingInfo.h.

◆ GPUKind

enum llvm::AMDGPU::GPUKind : uint32_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE 
GK_AMDGCN_GENERIC_FIRST 
GK_AMDGCN_GENERIC_LAST 

Definition at line 30 of file AMDGPUTargetParser.h.

◆ IGLPStrategyID

enum llvm::AMDGPU::IGLPStrategyID : int

Operand 0 immediate for IGLP_OPT pseudo instructions.

Enumerator
MFMASmallGemmOptID 
MFMASmallGemmSingleWaveOptID 
MFMAExpInterleaveID 
MFMAExpSimpleInterleaveID 

Definition at line 22 of file AMDGPUIGroupLP.h.

◆ InfoKind

enum class llvm::AMDGPU::InfoKind : uint8_t
strong

Entry kind values for the .amdgpu.info section.

Entries that appear between an INFO_FUNC and the next INFO_FUNC (or end of section) belong to the function scope opened by that INFO_FUNC.

Enumerator
INFO_FUNC 

Opens a new function scope.

Payload is an 8-byte symbol reference (relocated) identifying the function. All subsequent entries until the next INFO_FUNC belong to this function.

INFO_FLAGS 

Bitfield of FuncInfoFlags properties for the function. [u32].

INFO_NUM_SGPR 

Number of SGPRs explicitly used by the function. [u32].

INFO_NUM_VGPR 

Number of architectural VGPRs used by the function. [u32].

INFO_NUM_AGPR 

Number of accumulator VGPRs (AGPRs) used by the function. [u32].

INFO_PRIVATE_SEGMENT_SIZE 

Private (scratch) memory size in bytes required by the function. [u32].

INFO_USE 

Dependency edge: the function uses the resource identified by the 8-byte relocated symbol (e.g.

an LDS variable or named barrier).

INFO_CALL 

Direct call edge: the function calls the callee identified by the 8-byte relocated symbol.

INFO_INDIRECT_CALL 

Indirect call edge: the function contains an indirect call whose callee is expected to match the type-ID string at the given .amdgpu.strtab offset.

[u32]

INFO_TYPEID 

Function type ID: tags an address-taken function with a type-ID string (at the given .amdgpu.strtab offset) so the linker can match it against INFO_INDIRECT_CALL entries.

[u32]

Definition at line 32 of file AMDGPUObjLinkingInfo.h.

◆ InstCounterType

enum llvm::AMDGPU::InstCounterType
Enumerator
LOAD_CNT 
DS_CNT 
EXP_CNT 
STORE_CNT 
NUM_NORMAL_INST_CNTS 
SAMPLE_CNT 
BVH_CNT 
KM_CNT 
X_CNT 
ASYNC_CNT 
NUM_EXTENDED_INST_CNTS 
VA_VDST 
VM_VSRC 
NUM_EXPERT_INST_CNTS 
NUM_INST_CNTS 

Definition at line 22 of file AMDGPUWaitcntUtils.h.

◆ InstructionFlavor

enum class llvm::AMDGPU::InstructionFlavor : uint8_t
strong
Enumerator
WMMA 
SingleCycleVALU 
TRANS 
MultiCycleVALU 
VMEM 
DS 
SALU 
DMA 
Fence 
Other 
NUM_FLAVORS 

Definition at line 28 of file AMDGPUCoExecSchedStrategy.h.

◆ LoweringMethodID

enum llvm::AMDGPU::LoweringMethodID
Enumerator
DoNotLower 
VccExtToSel 
UniExtToSel 
UnpackBitShift 
UnpackMinMax 
S_BFE 
V_BFE 
VgprToVccCopy 
UniMAD64 
UniMul64 
DivSMulToMAD 
SplitTo32 
SplitTo32Mul 
ScalarizeToS16 
SplitTo32Select 
SplitTo32SExtInReg 
Ext32To64 
UniCstExt 
CtPop64To32 
SplitLoad 
WidenLoad 
WidenMMOToS32 
UnpackAExt 
VerifyAllSgpr 
ApplyAllVgpr 
UnmergeToShiftTrunc 
AextToS32InIncomingBlockGPHI 
VerifyAllSgprGPHI 
VerifyAllSgprOrVgprGPHI 
ApplyINTRIN_IMAGE 
ApplyBVH_INTERSECT_RAY 
SplitBitCount64To32 
ExtrVecEltToSel 
ExtrVecEltTo32 
InsVecEltToSel 
InsVecEltTo32 
AbsToNegMax 
AbsToS32 

Definition at line 277 of file AMDGPURegBankLegalizeRules.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned
Enumerator
OPERAND_REG_IMM_INT32 

Operands with register, 32-bit, or 64-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_BF16 
OPERAND_REG_IMM_FP16 
OPERAND_REG_IMM_V2BF16 
OPERAND_REG_IMM_V2FP16 
OPERAND_REG_IMM_V2FP16_SPLAT 
OPERAND_REG_IMM_V2INT16 
OPERAND_REG_IMM_NOINLINE_V2FP16 
OPERAND_REG_IMM_V2INT32 
OPERAND_REG_IMM_V2FP32 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_BF16 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_INLINE_C_V2BF16 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_INLINE_SPLIT_BARRIER_INT32 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 
OPERAND_KIMM64 
OPERAND_REG_INLINE_AC_INT32 

Operands with an AccVGPR register or inline constant.

OPERAND_REG_INLINE_AC_FP32 
OPERAND_REG_INLINE_AC_FP64 
OPERAND_INLINE_C_AV64_PSEUDO 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_REG_INLINE_AC_FIRST 
OPERAND_REG_INLINE_AC_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_KIMM_FIRST 
OPERAND_KIMM_LAST 

Definition at line 201 of file SIDefines.h.

◆ RegBankLLTMappingApplyID

enum llvm::AMDGPU::RegBankLLTMappingApplyID
Enumerator
InvalidMapping 
None 
IntrId 
Imm 
Vcc 
VgprAnyTy 
AgprAnyTy 
Sgpr16 
Sgpr32 
Sgpr64 
Sgpr128 
SgprP0 
SgprP1 
SgprP2 
SgprP3 
SgprP4 
SgprP5 
SgprP8 
SgprPtr32 
SgprPtr64 
SgprPtr128 
SgprV2S16 
SgprV4S32 
SgprV2S32 
SgprB32 
SgprB64 
SgprB96 
SgprB128 
SgprB256 
SgprB512 
SgprBRC 
Vgpr16 
Vgpr32 
Vgpr64 
Vgpr128 
VgprP0 
VgprP1 
VgprP2 
VgprP3 
VgprP4 
VgprP5 
VgprPtr32 
VgprPtr64 
VgprPtr128 
VgprV2S16 
VgprV2S32 
VgprV3S32 
VgprB32 
VgprB64 
VgprB96 
VgprB128 
VgprB160 
VgprB256 
VgprB512 
VgprBRC 
VgprV4S16 
VgprV4S32 
VgprV8S32 
VgprV2S64 
UniInVcc 
UniInVgprS16 
UniInVgprS32 
UniInVgprS64 
UniInVgprV2S16 
UniInVgprV2S32 
UniInVgprV4S32 
UniInVgprV2S64 
UniInVgprB32 
UniInVgprB64 
UniInVgprB96 
UniInVgprB128 
UniInVgprB160 
UniInVgprB256 
UniInVgprB512 
Sgpr32Trunc 
Sgpr32ToVgprDst 
Sgpr64ToVgprDst 
Sgpr32_WF 
SgprV4S32_WF 
SgprP0Call_WF 
SgprP4Call_WF 
SgprB32_M0 
SgprB32_ReadFirstLane 
SgprB64_ReadFirstLane 
SgprV4S32_ReadFirstLane 
Sgpr32AExt 
Sgpr32AExtBoolInReg 
Sgpr32SExt 
Sgpr32ZExt 
Vgpr32AExt 
Vgpr32SExt 
Vgpr32ZExt 
VgprV6S32 
VgprV32S16 
VgprV32S32 

Definition at line 148 of file AMDGPURegBankLegalizeRules.h.

◆ SchedulingPhase

enum class llvm::AMDGPU::SchedulingPhase
strong
Enumerator
Initial 
PreRAReentry 
PostRA 

Definition at line 19 of file AMDGPUIGroupLP.h.

◆ TargetIndex

enum llvm::AMDGPU::TargetIndex
Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 611 of file AMDGPU.h.

◆ UniformityLLTOpPredicateID

enum llvm::AMDGPU::UniformityLLTOpPredicateID
Enumerator
_ 
S1 
S16 
S32 
S64 
S128 
UniS1 
UniS16 
UniS32 
UniS64 
UniS128 
DivS1 
DivS16 
DivS32 
DivS64 
DivS128 
DivAnyTy 
P0 
P1 
P2 
P3 
P4 
P5 
P8 
Ptr32 
Ptr64 
Ptr128 
UniP0 
UniP1 
UniP2 
UniP3 
UniP4 
UniP5 
UniP8 
UniPtr32 
UniPtr64 
UniPtr128 
DivP0 
DivP1 
DivP2 
DivP3 
DivP4 
DivP5 
DivPtr32 
DivPtr64 
DivPtr128 
V2S16 
V2S32 
V2S64 
V3S32 
V4S32 
UniV2S16 
UniV2S32 
UniV2S64 
DivV2S16 
DivV2S32 
DivV2S64 
DivV3S32 
DivV4S16 
DivV6S32 
B32 
B64 
B96 
B128 
B160 
B256 
B512 
BRC 
UniB32 
UniB64 
UniB96 
UniB128 
UniB160 
UniB256 
UniB512 
UniBRC 
DivB32 
DivB64 
DivB96 
DivB128 
DivB160 
DivB256 
DivB512 
DivBRC 

Definition at line 39 of file AMDGPURegBankLegalizeRules.h.

Function Documentation

◆ addrspacesMayAlias()

bool llvm::AMDGPU::addrspacesMayAlias ( unsigned AS1,
unsigned AS2 )
inlinestatic

Definition at line 619 of file AMDGPU.h.

References llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::GCNTTIImpl::addrspacesMayAlias(), llvm::AMDGPUAAResult::alias(), and llvm::GCNTTIImpl::isValidAddrSpaceCast().

◆ buildReadAnyLane()

void llvm::AMDGPU::buildReadAnyLane ( MachineIRBuilder & B,
Register SgprDst,
Register VgprSrc,
const RegisterBankInfo & RBI )

Definition at line 171 of file AMDGPUGlobalISelUtils.cpp.

References B(), and buildReadLane().

◆ buildReadFirstLane()

void llvm::AMDGPU::buildReadFirstLane ( MachineIRBuilder & B,
Register SgprDst,
Register VgprSrc,
const RegisterBankInfo & RBI )

Definition at line 180 of file AMDGPUGlobalISelUtils.cpp.

References B(), and buildReadLane().

◆ buildVOPDXYLookup()

constexpr std::array< CanBeVOPD, 1<< VOPDXYKeyBits > llvm::AMDGPU::buildVOPDXYLookup ( )
staticconstexpr

Definition at line 674 of file AMDGPUBaseInfo.cpp.

References E(), and getVOPDXYKey().

◆ canGuaranteeTCO()

LLVM_READNONE constexpr bool llvm::AMDGPU::canGuaranteeTCO ( CallingConv::ID CC)
constexpr

Definition at line 1548 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::Fast.

Referenced by llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), and mayTailCallThisCC().

◆ classifyFlavor()

InstructionFlavor llvm::AMDGPU::classifyFlavor ( const MachineInstr & MI,
const SIInstrInfo & SII )

Definition at line 45 of file AMDGPUCoExecSchedStrategy.cpp.

References DMA, DS, Fence, llvm::SIInstrInfo::isDS(), llvm::SIInstrInfo::isFLAT(), llvm::SIInstrInfo::isFLATGlobal(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLDSDMA(), llvm::SIInstrInfo::isMFMAorWMMA(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isTRANS(), llvm::SIInstrInfo::isVALU(), MI, Opc, Other, SALU, SingleCycleVALU, TRANS, VMEM, and WMMA.

Referenced by llvm::CandidateHeuristics::collectHWUIPressure(), llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary(), llvm::CandidateHeuristics::tryCriticalResourceDependency(), and llvm::CandidateHeuristics::updateForScheduling().

◆ convertSetRegImmToVgprMSBs() [1/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs ( const MachineInstr & MI,
bool HasSetregVGPRMSBFixup )
Returns
VGPR MSBs encoded in a S_SETREG_IMM32_B32 MI if it sets it. If HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is ignored.

Definition at line 3607 of file AMDGPUBaseInfo.cpp.

References assert(), convertSetRegImmToVgprMSBs(), and MI.

◆ convertSetRegImmToVgprMSBs() [2/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs ( const MCInst & MI,
bool HasSetregVGPRMSBFixup )
Returns
VGPR MSBs encoded in a S_SETREG_IMM32_B32 MI if it sets it. If HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is ignored.

Definition at line 3615 of file AMDGPUBaseInfo.cpp.

References assert(), convertSetRegImmToVgprMSBs(), and MI.

◆ convertSetRegImmToVgprMSBs() [3/3]

std::optional< unsigned > llvm::AMDGPU::convertSetRegImmToVgprMSBs ( unsigned Imm,
unsigned Simm16,
bool HasSetregVGPRMSBFixup )
static

Definition at line 3589 of file AMDGPUBaseInfo.cpp.

References llvm::countr_zero_constexpr(), llvm::AMDGPU::EncodingFields< HwregId, HwregOffset, HwregSize >::decode(), llvm::AMDGPU::Hwreg::DST_VGPR_MSB, llvm::AMDGPU::Hwreg::ID_MODE, Imm, llvm::maskTrailingOnes(), llvm::Offset, llvm::rotr(), Size, and llvm::AMDGPU::Hwreg::VGPR_MSB_MASK.

Referenced by convertSetRegImmToVgprMSBs(), convertSetRegImmToVgprMSBs(), llvm::AMDGPUAsmPrinter::emitInstruction(), and llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState().

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits ( const MCSubtargetInfo & ST,
uint64_t ByteOffset )

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 3435 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), and isDwordAligned().

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ createLaneMaskReg()

Register llvm::AMDGPU::createLaneMaskReg ( MachineRegisterInfo * MRI,
MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs )

Definition at line 373 of file SILowerI1Copies.cpp.

References llvm::MachineRegisterInfo::createVirtualRegister().

Referenced by insertUndefLaneMask(), and llvm::AMDGPU::PhiLoweringHelper::lowerPhis().

◆ createSlowPathCmp()

Value * llvm::AMDGPU::createSlowPathCmp ( Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Value * AddrLong,
Value * ShadowValue,
uint32_t TypeStoreSize,
int AsanScale )
static

Definition at line 79 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateAnd(), llvm::IRBuilderBase::CreateICmpSGE(), llvm::IRBuilderBase::CreateIntCast(), and llvm::Value::getType().

Referenced by instrumentAddressImpl().

◆ decodeCustomOperand()

bool llvm::AMDGPU::decodeCustomOperand ( const CustomOperandVal * Opr,
int Size,
unsigned Code,
int & Idx,
StringRef & Name,
unsigned & Val,
bool & IsDefault,
const MCSubtargetInfo & STI )
static

Definition at line 2023 of file AMDGPUBaseInfo.cpp.

References Size.

Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().

◆ decodeDscnt()

unsigned llvm::AMDGPU::decodeDscnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Dscnt from given Waitcnt for given isa Version.

Definition at line 1898 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeLoadcntDscnt(), and decodeStorecntDscnt().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 1878 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeFltRoundToHWConversionTable()

uint32_t llvm::AMDGPU::decodeFltRoundToHWConversionTable ( uint32_t FltRounds)

Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.

Definition at line 235 of file SIModeRegisterDefaults.cpp.

References FltRoundToHWConversionTable.

Referenced by llvm::SITargetLowering::lowerSET_ROUNDING().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 1883 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeLoadcnt()

unsigned llvm::AMDGPU::decodeLoadcnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Loadcnt from given Waitcnt for given isa Version.

Definition at line 1888 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeLoadcntDscnt().

◆ decodeLoadcntDscnt()

Waitcnt llvm::AMDGPU::decodeLoadcntDscnt ( const IsaVersion & Version,
unsigned LoadcntDscnt )
Returns
Decoded Waitcnt structure from given LoadcntDscnt for given isa Version.

Definition at line 65 of file AMDGPUWaitcntUtils.cpp.

References decodeDscnt(), decodeLoadcnt(), DS_CNT, LOAD_CNT, llvm::AMDGPU::Waitcnt::set(), and llvm::Version.

◆ decodeStorecnt()

unsigned llvm::AMDGPU::decodeStorecnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Storecnt from given Waitcnt for given isa Version.

Definition at line 1893 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeStorecntDscnt().

◆ decodeStorecntDscnt()

Waitcnt llvm::AMDGPU::decodeStorecntDscnt ( const IsaVersion & Version,
unsigned StorecntDscnt )
Returns
Decoded Waitcnt structure from given StorecntDscnt for given isa Version.

Definition at line 72 of file AMDGPUWaitcntUtils.cpp.

References decodeDscnt(), decodeStorecnt(), DS_CNT, llvm::AMDGPU::Waitcnt::set(), STORE_CNT, and llvm::Version.

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaVersion & Version,
unsigned Waitcnt )
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 1870 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt(), and decodeWaitcnt().

◆ decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt ( const IsaVersion & Version,
unsigned Encoded )

Definition at line 52 of file AMDGPUWaitcntUtils.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), DS_CNT, EXP_CNT, LOAD_CNT, llvm::AMDGPU::Waitcnt::set(), and llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned & Vmcnt,
unsigned & Expcnt,
unsigned & Lgkmcnt )

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9) Vmcnt = Waitcnt[15:14,3:0] (gfx9,10) Vmcnt = Waitcnt[15:10] (gfx11) Expcnt = Waitcnt[6:4] (pre-gfx11) Expcnt = Waitcnt[2:0] (gfx11) Lgkmcnt = Waitcnt[11:8] (pre-gfx10) Lgkmcnt = Waitcnt[13:8] (gfx10) Lgkmcnt = Waitcnt[9:4] (gfx11)

Definition at line 1903 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and llvm::Version.

◆ eliminateConstantExprUsesOfLDSFromAllInstructions()

bool llvm::AMDGPU::eliminateConstantExprUsesOfLDSFromAllInstructions ( Module & M)

Definition at line 97 of file AMDGPUMemoryUtils.cpp.

References llvm::convertUsersOfConstantsToInstructions(), isLDSVariableToLower(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ encode32BitLiteral()

LLVM_READNONE int64_t llvm::AMDGPU::encode32BitLiteral ( int64_t Imm,
OperandType Type,
bool IsLit )

Definition at line 3323 of file AMDGPUBaseInfo.cpp.

References llvm::Hi_32(), Imm, llvm::Lo_32(), OPERAND_INLINE_SPLIT_BARRIER_INT32, OPERAND_REG_IMM_BF16, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_C_BF16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, and OPERAND_REG_INLINE_C_INT32.

◆ encodeCustomOperand()

int llvm::AMDGPU::encodeCustomOperand ( const CustomOperandVal * Opr,
int Size,
const StringRef Name,
int64_t InputVal,
unsigned & UsedOprMask,
const MCSubtargetInfo & STI )
static

Definition at line 2047 of file AMDGPUBaseInfo.cpp.

References encodeCustomOperandVal(), OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and Size.

Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().

◆ encodeCustomOperandVal()

int llvm::AMDGPU::encodeCustomOperandVal ( const CustomOperandVal & Op,
int64_t InputVal )
static

Definition at line 2040 of file AMDGPUBaseInfo.cpp.

References OPR_VAL_INVALID.

Referenced by encodeCustomOperand().

◆ encodeDscnt()

unsigned llvm::AMDGPU::encodeDscnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Dscnt )
static

Definition at line 1966 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Expcnt )
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 1919 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Lgkmcnt )
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 1925 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLoadcnt()

unsigned llvm::AMDGPU::encodeLoadcnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Loadcnt )
static

Definition at line 1954 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeLoadcntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt ( const IsaVersion & Version,
const Waitcnt & Decoded )
Returns
Loadcnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa Version.

Definition at line 79 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeLoadcntDscnt(), llvm::AMDGPU::Waitcnt::get(), LOAD_CNT, and llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeLoadcntDscnt() [2/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt ( const IsaVersion & Version,
unsigned Loadcnt,
unsigned Dscnt )
Returns
Waitcnt with encoded Loadcnt and Dscnt for given isa Version.

Definition at line 1972 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeLoadcnt(), getCombinedCountBitMask(), and llvm::Version.

◆ encodeStorecnt()

unsigned llvm::AMDGPU::encodeStorecnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Storecnt )
static

Definition at line 1960 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeStorecntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt ( const IsaVersion & Version,
const Waitcnt & Decoded )
Returns
Storecnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa Version.

Definition at line 84 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeStorecntDscnt(), llvm::AMDGPU::Waitcnt::get(), STORE_CNT, and llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeStorecntDscnt() [2/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt ( const IsaVersion & Version,
unsigned Storecnt,
unsigned Dscnt )
Returns
Waitcnt with encoded Storecnt and Dscnt for given isa Version.

Definition at line 1980 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeStorecnt(), getCombinedCountBitMask(), and llvm::Version.

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaVersion & Version,
unsigned Waitcnt,
unsigned Vmcnt )
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 1910 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion & Version,
const Waitcnt & Decoded )

Definition at line 60 of file AMDGPUWaitcntUtils.cpp.

References DS_CNT, encodeWaitcnt(), EXP_CNT, llvm::AMDGPU::Waitcnt::get(), LOAD_CNT, and llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion & Version,
unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt )

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[2:0] = Expcnt (gfx11+) Waitcnt[3:0] = Vmcnt (pre-gfx9) Waitcnt[3:0] = Vmcnt[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt (pre-gfx11) Waitcnt[9:4] = Lgkmcnt (gfx11) Waitcnt[11:8] = Lgkmcnt (pre-gfx10) Waitcnt[13:8] = Lgkmcnt (gfx10) Waitcnt[15:10] = Vmcnt (gfx11) Waitcnt[15:14] = Vmcnt[5:4] (gfx9,10)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 1931 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and llvm::Version.

◆ fillAMDGPUFeatureMap()

std::pair< FeatureError, StringRef > llvm::AMDGPU::fillAMDGPUFeatureMap ( StringRef GPU,
const Triple & T,
StringMap< bool > & Features )

Fills Features map with default values for given target GPU.

Features contains overriding target features and this function returns default target features with entries overridden by Features.

Definition at line 609 of file AMDGPUTargetParser.cpp.

References llvm::Triple::AMDHSA, B(), llvm::StringRef::empty(), F, fillAMDGCNFeatureMap(), fillValidArchListAMDGCN(), insertWaveSizeFeature(), llvm_unreachable, NO_ERROR, parseArchR600(), and T.

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > & Values)

Definition at line 94 of file AMDGPUTargetParser.cpp.

References llvm::SmallVectorImpl< T >::append().

Referenced by fillAMDGPUFeatureMap().

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > & Values)

Definition at line 103 of file AMDGPUTargetParser.cpp.

References llvm::SmallVectorImpl< T >::append().

◆ foldAMDGPUMCExpr()

const MCExpr * llvm::AMDGPU::foldAMDGPUMCExpr ( const MCExpr * Expr,
MCContext & Ctx )

Definition at line 695 of file AMDGPUMCExpr.cpp.

References knownBitsMapHelper(), and tryFoldHelper().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ genAMDGPUReportBlock()

Instruction * llvm::AMDGPU::genAMDGPUReportBlock ( Module & M,
IRBuilder<> & IRB,
Value * Cond,
bool Recover )
static

Definition at line 57 of file AMDGPUAsanInstrumentation.cpp.

References Cond, llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateIsNotNull(), llvm::MDBuilder::createUnlikelyBranchWeights(), llvm::IRBuilderBase::GetInsertPoint(), llvm::IRBuilderBase::getInt64Ty(), llvm::IRBuilderBase::SetInsertPoint(), and llvm::SplitBlockAndInsertIfThen().

Referenced by instrumentAddressImpl().

◆ generateCrashCode()

Instruction * llvm::AMDGPU::generateCrashCode ( Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Instruction * InsertBefore,
Value * Addr,
bool IsWrite,
size_t AccessSizeIndex,
Value * SizeArgument,
bool Recover )
static

Definition at line 97 of file AMDGPUAsanInstrumentation.cpp.

References Call, llvm::IRBuilderBase::CreateCall(), llvm::FunctionType::get(), llvm::IRBuilderBase::getVoidTy(), kAsanReportErrorTemplate, llvm::IRBuilderBase::SetInsertPoint(), and llvm::raw_svector_ostream::str().

Referenced by instrumentAddressImpl().

◆ getAddr64Inst()

LLVM_READONLY int32_t llvm::AMDGPU::getAddr64Inst ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp ( const MIMGBaseOpcodeInfo * BaseOpcode,
const MIMGDimInfo * Dim,
bool IsA16,
bool IsG16Supported )

Definition at line 334 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getAlign()

Align llvm::AMDGPU::getAlign ( const DataLayout & DL,
const GlobalVariable * GV )

Definition at line 28 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().

◆ getAMDHSACodeObjectVersion() [1/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( const Module & M)
Returns
Code object version from the IR module flag.

Definition at line 213 of file AMDGPUBaseInfo.cpp.

References llvm::mdconst::extract_or_null(), and getDefaultAMDHSACodeObjectVersion().

Referenced by llvm::AMDGPUAsmPrinter::doInitialization(), llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV4::emitKernel(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULowerKernelAttributesPass::run(), llvm::AMDGPUResourceUsageAnalysis::run(), llvm::AMDGPUResourceUsageAnalysisWrapperPass::runOnMachineFunction(), and llvm::AMDGPUDisassembler::setABIVersion().

◆ getAMDHSACodeObjectVersion() [2/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( unsigned ABIVersion)
Returns
Code object version from ELF's e_ident[EI_ABIVERSION].

Definition at line 226 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and getDefaultAMDHSACodeObjectVersion().

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind AK)

Definition at line 72 of file AMDGPUTargetParser.cpp.

References FEATURE_NONE.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind AK)

Definition at line 83 of file AMDGPUTargetParser.cpp.

References FEATURE_NONE.

◆ getArchFamilyNameAMDGCN()

StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN ( GPUKind AK)

Definition at line 22 of file AMDGPUTargetParser.cpp.

References assert(), llvm::StringRef::drop_back(), llvm::StringRef::empty(), llvm::StringRef::ends_with(), llvm::StringRef::find(), getArchNameAMDGCN(), GK_AMDGCN_GENERIC_FIRST, GK_AMDGCN_GENERIC_LAST, and llvm::StringRef::take_front().

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind AK)

Definition at line 34 of file AMDGPUTargetParser.cpp.

Referenced by getArchFamilyNameAMDGCN(), llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind AK)

Definition at line 45 of file AMDGPUTargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getAsynccntBitMask()

unsigned llvm::AMDGPU::getAsynccntBitMask ( const IsaVersion & Version)
Returns
Asynccnt bit mask for given isa Version. Returns 0 for versions that do not support Asynccnt

Definition at line 1830 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset ( MachineRegisterInfo & MRI,
Register Reg,
GISelValueTracking * ValueTracking = nullptr,
bool CheckNUW = false )

Returns base register and constant offset.

Definition at line 26 of file AMDGPUGlobalISelUtils.cpp.

References assert(), llvm::sampleprof::Base, llvm::getDefIgnoringCopies(), llvm::LLT::getScalarSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GOr(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::m_Reg(), llvm::GISelValueTracking::maskedValueIsZero(), llvm::MIPatternMatch::mi_match(), llvm::MachineInstr::NoUWrap, llvm::Offset, and Register.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().

◆ getBasicFromSDWAOp()

LLVM_READONLY int32_t llvm::AMDGPU::getBasicFromSDWAOp ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getBitOp2()

unsigned llvm::AMDGPU::getBitOp2 ( unsigned Opc)

Definition at line 860 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getCanBeVOPD(), getVOPDFull(), and getVOPDOpcode().

◆ getBvhcntBitMask()

unsigned llvm::AMDGPU::getBvhcntBitMask ( const IsaVersion & Version)
Returns
Bvhcnt bit mask for given isa Version. Returns 0 for versions that do not support BVHcnt

Definition at line 1806 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getCanBeVOPD()

LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD ( unsigned Opc,
unsigned EncodingFamily,
bool VOPD3 )

Definition at line 687 of file AMDGPUBaseInfo.cpp.

References getBitOp2(), getVOPDXYKey(), Opc, and VOPDXYLookup.

Referenced by shouldScheduleVOPDAdjacent(), and tryMatchVOPDPairVariant().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName ( const Triple & T,
StringRef Arch )

Definition at line 133 of file AMDGPUTargetParser.cpp.

References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), parseArchR600(), and T.

◆ getCombinedCountBitMask()

unsigned llvm::AMDGPU::getCombinedCountBitMask ( const IsaVersion & Version,
bool IsStore )
static

Definition at line 1940 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ getCommuteOrig()

LLVM_READONLY int32_t llvm::AMDGPU::getCommuteOrig ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCommuteRev()

LLVM_READONLY int32_t llvm::AMDGPU::getCommuteRev ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCompletionActionImplicitArgPosition()

unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition ( unsigned CodeObjectVersion)

Definition at line 291 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.

◆ getDefaultAMDHSACodeObjectVersion()

unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ( )
Returns
The default HSA code object version. This should only be used when we lack a more accurate CodeObjectVersion value (e.g. from the IR module flag or a .amdhsa_code_object_version directive)

Definition at line 222 of file AMDGPUBaseInfo.cpp.

References DefaultAMDHSACodeObjectVersion.

Referenced by getAMDHSACodeObjectVersion(), and getAMDHSACodeObjectVersion().

◆ getDefaultCustomOperandEncoding()

unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding ( const CustomOperandVal * Opr,
int Size,
const MCSubtargetInfo & STI )
static

Definition at line 1992 of file AMDGPUBaseInfo.cpp.

References Size.

Referenced by llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().

◆ getDefaultQueueImplicitArgPosition()

unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition ( unsigned CodeObjectVersion)

Definition at line 280 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.

◆ getDPPOp32()

LLVM_READONLY int32_t llvm::AMDGPU::getDPPOp32 ( uint32_t Opcode)

References LLVM_READONLY.

◆ getDPPOp64()

LLVM_READONLY int32_t llvm::AMDGPU::getDPPOp64 ( uint32_t Opcode)

References LLVM_READONLY.

◆ getDscntBitMask()

unsigned llvm::AMDGPU::getDscntBitMask ( const IsaVersion & Version)
Returns
Dscnt bit mask for given isa Version. Returns 0 for versions that do not support DScnt

Definition at line 1818 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getDynamicVGPRBlockSize()

unsigned llvm::AMDGPU::getDynamicVGPRBlockSize ( const Function & F)

Definition at line 2532 of file AMDGPUBaseInfo.cpp.

References BlockSize, and F.

Referenced by llvm::GCNSubtarget::computeOccupancy(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getELFABIVersion()

uint8_t llvm::AMDGPU::getELFABIVersion ( const Triple & OS,
unsigned CodeObjectVersion )
Returns
ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION].
Parameters
CodeObjectVersionis a value returned by getAMDHSACodeObjectVersion().

Definition at line 239 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, llvm::report_fatal_error(), and T.

Referenced by llvm::AMDGPUTargetELFStreamer::finish().

◆ getEncodingFromOperandTable()

template<size_t N>
int64_t llvm::AMDGPU::getEncodingFromOperandTable ( const CustomOperand(&) Table[N],
StringRef Name,
const MCSubtargetInfo & STI )
static

Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.

Definition at line 46 of file AMDGPUAsmUtils.cpp.

References N, OPR_ID_UNKNOWN, and OPR_ID_UNSUPPORTED.

Referenced by llvm::AMDGPU::Hwreg::getHwregId(), llvm::AMDGPU::SendMsg::getMsgId(), llvm::AMDGPU::SendMsg::getMsgOpId(), and llvm::AMDGPU::WaitEvent::getWaitEventMask().

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion & Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 1810 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getExprKind()

AMDGPUMCExpr::VariantKind llvm::AMDGPU::getExprKind ( const MCExpr * Expr)

Definition at line 727 of file AMDGPUMCExpr.cpp.

References llvm::AMDGPUMCExpr::AGVK_None, and llvm::dyn_cast().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSSfromSV ( uint32_t Opcode)
Returns
SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

References LLVM_READONLY.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSTfromSS ( uint32_t Opcode)
Returns
ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSVfromSS ( uint32_t Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getFlatScratchInstSVfromSVS()

LLVM_READONLY int32_t llvm::AMDGPU::getFlatScratchInstSVfromSVS ( uint32_t Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SVS (SADDR + VADDR) form.

References LLVM_READONLY.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getFlavorName()

StringRef llvm::AMDGPU::getFlavorName ( InstructionFlavor F)
constexpr

Definition at line 42 of file AMDGPUCoExecSchedStrategy.h.

References DMA, DS, F, Fence, llvm_unreachable, MultiCycleVALU, NUM_FLAVORS, Other, SALU, SingleCycleVALU, TRANS, VMEM, and WMMA.

Referenced by llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary(), and llvm::CandidateHeuristics::dumpRegionSummary().

◆ getFlavorShortName()

StringRef llvm::AMDGPU::getFlavorShortName ( InstructionFlavor F)
constexpr

Definition at line 70 of file AMDGPUCoExecSchedStrategy.h.

References DMA, DS, F, Fence, llvm_unreachable, MultiCycleVALU, NUM_FLAVORS, Other, SALU, SingleCycleVALU, TRANS, VMEM, and WMMA.

◆ getFPDstSelType()

LLVM_READONLY FPType llvm::AMDGPU::getFPDstSelType ( unsigned Opc)

Definition at line 826 of file AMDGPUBaseInfo.cpp.

References FP4, FP8, None, and Opc.

Referenced by getDstSelForwardingOperand().

◆ getGcnBufferFormatInfo() [1/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t BitsPerComp,
uint8_t NumComponents,
uint8_t NumFormat,
const MCSubtargetInfo & STI )

Definition at line 3521 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by getBufferFormatWithCompCount().

◆ getGcnBufferFormatInfo() [2/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo ( uint8_t Format,
const MCSubtargetInfo & STI )

Definition at line 3532 of file AMDGPUBaseInfo.cpp.

References llvm::Format, isGFX10(), and isGFX11Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int32_t llvm::AMDGPU::getGlobalSaddrOp ( uint32_t Opcode)
Returns
SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

References LLVM_READONLY.

◆ getGlobalVaddrOp()

LLVM_READONLY int32_t llvm::AMDGPU::getGlobalVaddrOp ( uint32_t Opcode)
Returns
VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport ( const Function & F)

Definition at line 2521 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, and F.

Referenced by generateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport ( const Function & F)

Definition at line 2528 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by generateEndPgm().

◆ getHasMatrixScale()

LLVM_READONLY bool llvm::AMDGPU::getHasMatrixScale ( unsigned Opc)

Definition at line 599 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition ( unsigned COV)
Returns
The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line 269 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.

◆ getIfAddr64Inst()

LLVM_READONLY int32_t llvm::AMDGPU::getIfAddr64Inst ( uint32_t Opcode)

Check if Opcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode ( unsigned BaseOpcode,
unsigned Dim )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned Intr)

Referenced by collectMergeableInsts(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::GCNTTIImpl::instCombineIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), optimizeSection(), and llvm::AMDGPUInstructionSelector::select().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function & F)

Definition at line 2517 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getInlineEncodingV216()

std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV216 ( bool IsFloat,
uint32_t Literal )

Definition at line 3154 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and llvm::Signed.

Referenced by getInlineEncodingV2F16(), getInlineEncodingV2I16(), getPKFMACF16InlineEncoding(), and isInlinableLiteralV216().

◆ getInlineEncodingV2BF16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2BF16 ( uint32_t Literal)

Definition at line 3215 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and llvm::Signed.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2BF16().

◆ getInlineEncodingV2F16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2F16 ( uint32_t Literal)

Definition at line 3243 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2F16().

◆ getInlineEncodingV2I16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2I16 ( uint32_t Literal)

Definition at line 3209 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2I16().

◆ getInstCounterName()

StringLiteral llvm::AMDGPU::getInstCounterName ( InstCounterType T)

Definition at line 18 of file AMDGPUWaitcntUtils.cpp.

References ASYNC_CNT, BVH_CNT, DS_CNT, EXP_CNT, KM_CNT, llvm_unreachable, LOAD_CNT, NUM_INST_CNTS, SAMPLE_CNT, STORE_CNT, T, VA_VDST, VM_VSRC, and X_CNT.

Referenced by llvm::AMDGPU::Waitcnt::print().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function & F,
StringRef Name,
int Default )
Returns
Integer value requested using F's Name attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

References llvm::Default, F, and Size.

◆ getIntegerPairAttribute() [1/2]

std::optional< std::pair< unsigned, std::optional< unsigned > > > llvm::AMDGPU::getIntegerPairAttribute ( const Function & F,
StringRef Name,
bool OnlyFirstRequired = false )
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
std::nullopt if attribute is not present.
std::nullopt and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1697 of file AMDGPUBaseInfo.cpp.

References A(), and F.

◆ getIntegerPairAttribute() [2/2]

std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute ( const Function & F,
StringRef Name,
std::pair< unsigned, unsigned > Default,
bool OnlyFirstRequired = false )
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1688 of file AMDGPUBaseInfo.cpp.

References llvm::Default, F, and getIntegerPairAttribute().

Referenced by llvm::AMDGPUMachineFunctionInfo::AMDGPUMachineFunctionInfo(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), getIntegerPairAttribute(), llvm::GCNSubtarget::getMaxNumVectorRegs(), llvm::AMDGPUSubtarget::getWavesPerEU(), llvm::AMDGPUSubtarget::getWavesPerEU(), llvm::SIMachineFunctionInfo::mayUseAGPRs(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getIntegerVecAttribute() [1/2]

std::optional< SmallVector< unsigned > > llvm::AMDGPU::getIntegerVecAttribute ( const Function & F,
StringRef Name,
unsigned Size )

Similar to the function above, but returns std::nullopt if any error occurs.

Definition at line 1732 of file AMDGPUBaseInfo.cpp.

References A(), assert(), llvm::StringRef::empty(), F, Size, llvm::StringRef::split(), and llvm::utostr().

◆ getIntegerVecAttribute() [2/2]

SmallVector< unsigned > llvm::AMDGPU::getIntegerVecAttribute ( const Function & F,
StringRef Name,
unsigned Size,
unsigned DefaultVal )
Returns
Generate a vector of integer values requested using F's Name attribute.
A vector of size Size, with all elements set to DefaultVal, if any error occurs. The corresponding error will also be emitted.

Definition at line 1723 of file AMDGPUBaseInfo.cpp.

References F, getIntegerVecAttribute(), and Size.

Referenced by llvm::AMDGPU::ClusterDimsAttr::get(), getIntegerVecAttribute(), llvm::AMDGPUSubtarget::getMaxNumWorkGroups(), and processUse().

◆ getInterestingMemoryOperands()

void llvm::AMDGPU::getInterestingMemoryOperands ( Module & M,
Instruction * I,
SmallVectorImpl< InterestingMemoryOperand > & Interesting )

Get all the memory operands from the instruction that needs to be instrumented.

Definition at line 221 of file AMDGPUAsanInstrumentation.cpp.

References llvm::cast(), DL, llvm::dyn_cast(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::VectorType::get(), llvm::Value::getPointerAlignment(), llvm::Value::getType(), I, llvm::isa(), llvm::Align::value(), and llvm::MaybeAlign::valueOrOne().

◆ getIntrinsicID()

Intrinsic::ID llvm::AMDGPU::getIntrinsicID ( const MachineInstr & I)

Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But they are not actual instances of GIntrinsics, so we cannot use GIntrinsic::getIntrinsicID() on them.

Definition at line 25 of file AMDGPUInstrInfo.cpp.

References I.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPUInstructionSelector::select().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef GPU)

Definition at line 111 of file AMDGPUTargetParser.cpp.

References GK_NONE, and parseArchAMDGCN().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPU::DepCtr::encodeFieldHoldCnt(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPU::IsaInfo::AMDGPUTargetID::print(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getKmcntBitMask()

unsigned llvm::AMDGPU::getKmcntBitMask ( const IsaVersion & Version)
Returns
Dscnt bit mask for given isa Version. Returns 0 for versions that do not support KMcnt

Definition at line 1822 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getLdsDwGranularity()

unsigned llvm::AMDGPU::getLdsDwGranularity ( const MCSubtargetInfo & ST)
Returns
lds block size in terms of dwords. This is used to calculate the lds size encoded for PAL metadata 3.0+ which must be defined in terms of bytes.

Definition at line 3785 of file AMDGPUBaseInfo.cpp.

Referenced by EmitPALMetadataCommon().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion & Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 1814 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getLitValue()

int64_t llvm::AMDGPU::getLitValue ( const MCExpr * Expr)

Definition at line 721 of file AMDGPUMCExpr.cpp.

References assert(), llvm::cast(), and isLitExpr().

◆ getLoadcntBitMask()

unsigned llvm::AMDGPU::getLoadcntBitMask ( const IsaVersion & Version)
Returns
Loadcnt bit mask for given isa Version. Returns 0 for versions that do not support LOADcnt

Definition at line 1798 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getMAIIsDGEMM()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM ( unsigned Opc)

Returns true if MAI operation is a double precision GEMM.

Definition at line 584 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isDGEMM().

◆ getMAIIsGFX940XDL()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL ( unsigned Opc)

Definition at line 589 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isXDL().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( unsigned Opc,
unsigned NewChannels )

Definition at line 326 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, Opc, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMaxNumUserSGPRs()

unsigned llvm::AMDGPU::getMaxNumUserSGPRs ( const MCSubtargetInfo & STI)

Definition at line 2579 of file AMDGPUBaseInfo.cpp.

References isGFX1250Plus().

Referenced by llvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(), getComputePGMRSrc2Reg(), llvm::GCNSubtarget::getMaxNumUserSGPRs(), and llvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().

◆ getMCOpcode()

LLVM_READONLY int32_t llvm::AMDGPU::getMCOpcode ( uint32_t Opcode,
unsigned Gen )

Definition at line 856 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

MCRegister llvm::AMDGPU::getMCReg ( MCRegister Reg,
const MCSubtargetInfo & STI )

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 2812 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, llvm::Triple::r600, and Reg.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and llvm::AMDGPUMCInstLower::lowerOperand().

◆ getMFMA_F8F6F4_WithFormatArgs()

LLVM_READONLY const MFMA_F8F6F4_Info * llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs ( unsigned CBSZ,
unsigned BLGP,
unsigned F8F8Opcode )

Definition at line 620 of file AMDGPUBaseInfo.cpp.

References mfmaScaleF8F6F4FormatToNumRegs().

Referenced by llvm::AMDGPUDisassembler::convertMAIInst().

◆ getMFMAEarlyClobberOp()

LLVM_READONLY int32_t llvm::AMDGPU::getMFMAEarlyClobberOp ( uint32_t Opcode)
Returns
earlyclobber version of a MAC MFMA is exists.

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMFMASrcCVDstAGPROp()

LLVM_READONLY int32_t llvm::AMDGPU::getMFMASrcCVDstAGPROp ( uint32_t Opcode)
Returns
Version of an MFMA instruction which uses AGPRs for srcC and vdst, given an Opcode of an MFMA which uses VGPRs for srcC/vdst.

References LLVM_READONLY.

◆ getMIMGBaseOpcode()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode ( unsigned Opc)

Definition at line 321 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Opc.

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned BaseOpcode)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), simplifyAMDGCNImageIntrinsic(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGBiasMappingInfo()

LLVM_READONLY const MIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo ( unsigned Bias)

References LLVM_READONLY.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo ( unsigned DimEnum)

References LLVM_READONLY.

◆ getMIMGDimInfoByAsmSuffix()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef AsmSuffix)

◆ getMIMGDimInfoByEncoding()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t DimEnc)

References LLVM_READONLY.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGG16MappingInfo()

LLVM_READONLY const MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo ( unsigned G)

References G, LLVM_READONLY, and Opc.

◆ getMIMGInfo()

LLVM_READONLY const MIMGInfo * llvm::AMDGPU::getMIMGInfo ( unsigned Opc)

References LLVM_READONLY, and Opc.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned L)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGMIPMappingInfo()

LLVM_READONLY const MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned MIP)

References LLVM_READONLY.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOffsetMappingInfo()

LLVM_READONLY const MIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo ( unsigned Offset)

References LLVM_READONLY, and llvm::Offset.

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode ( unsigned BaseOpcode,
unsigned MIMGEncoding,
unsigned VDataDwords,
unsigned VAddrDwords )

Definition at line 314 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

◆ getMinRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getMinRedzoneSizeForGlobal ( int AsanScale)
static

Definition at line 24 of file AMDGPUAsanInstrumentation.cpp.

References getRedzoneSizeForScale().

Referenced by getRedzoneSizeForGlobal().

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode ( unsigned Opc)

Definition at line 486 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements ( unsigned Opc)

Definition at line 497 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset ( unsigned Opc)

Definition at line 512 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc ( unsigned Opc)

Definition at line 507 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr ( unsigned Opc)

Definition at line 502 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode ( unsigned BaseOpc,
unsigned Elements )

Definition at line 491 of file AMDGPUBaseInfo.cpp.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned Opc)

Definition at line 517 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements ( unsigned Opc)

Definition at line 528 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned Opc)

Definition at line 543 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned Opc)

Definition at line 538 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned Opc)

Definition at line 533 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv ( unsigned Opc)

Definition at line 548 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode ( unsigned BaseOpc,
unsigned Elements )

Definition at line 522 of file AMDGPUBaseInfo.cpp.

◆ getMUBUFTfe()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFTfe ( unsigned Opc)

Definition at line 553 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SITargetLowering::AddMemOpInit().

◆ getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition ( unsigned COV)
Returns
The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line 256 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

◆ getNameFromOperandTable()

template<size_t N>
StringRef llvm::AMDGPU::getNameFromOperandTable ( const CustomOperand(&) Table[N],
unsigned Encoding,
const MCSubtargetInfo & STI )
static

Map from the encoding of a sendmsg/hwreg asm operand to it's name.

Definition at line 25 of file AMDGPUAsmUtils.cpp.

References llvm::First, and N.

Referenced by llvm::AMDGPU::Hwreg::getHwreg(), llvm::AMDGPU::SendMsg::getMsgName(), llvm::AMDGPU::SendMsg::getMsgOpName(), and llvm::AMDGPU::WaitEvent::getWaitEventMaskName().

◆ getNSAMaxSize()

unsigned llvm::AMDGPU::getNSAMaxSize ( const MCSubtargetInfo & STI,
bool HasSampler )

Definition at line 2568 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getCPU(), getIsaVersion(), and llvm::Version.

Referenced by llvm::GCNSubtarget::getNSAMaxSize().

◆ getNullPointerValue()

int64_t llvm::AMDGPU::getNullPointerValue ( unsigned AS)
constexpr

Get the null pointer value for the given address space.

Definition at line 174 of file AMDGPUAddrSpace.h.

Referenced by isKnownNonNull(), isKnownNonNull(), isPtrKnownNeverNull(), and llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits ( const MCSubtargetInfo & ST)

For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

Returns
The number of bits available for the signed offset field in flat instructions. Note that some forms of the instruction disallow negative offsets.

Definition at line 3483 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc & Desc,
unsigned OpNo )
inline

Definition at line 1709 of file AMDGPUBaseInfo.h.

References getOperandSize().

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo & OpInfo)
inline

Definition at line 1664 of file AMDGPUBaseInfo.h.

References llvm_unreachable, OPERAND_INLINE_SPLIT_BARRIER_INT32, OPERAND_KIMM16, OPERAND_KIMM32, OPERAND_KIMM64, OPERAND_REG_IMM_BF16, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_NOINLINE_V2FP16, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_C_BF16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2INT16.

Referenced by getOperandSize().

◆ getPKFMACF16InlineEncoding()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getPKFMACF16InlineEncoding ( uint32_t Literal,
bool IsGFX11Plus )

Definition at line 3251 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), llvm::Hi, llvm::Literal, llvm::Lo, and llvm::Signed.

Referenced by isPKFMACF16InlineConstant().

◆ getReasonName()

StringRef llvm::AMDGPU::getReasonName ( AMDGPUSchedReason R)
constexpr

Definition at line 131 of file AMDGPUCoExecSchedStrategy.h.

References CritResourceBalance, CritResourceDep, llvm_unreachable, None, and NUM_REASONS.

Referenced by llvm::AMDGPUCoExecSchedStrategy::dumpPickSummary().

◆ getRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getRedzoneSizeForGlobal ( int AsanScale,
uint64_t SizeInBytes )

Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.

Definition at line 28 of file AMDGPUAsanInstrumentation.cpp.

References assert(), and getMinRedzoneSizeForGlobal().

◆ getRedzoneSizeForScale()

uint64_t llvm::AMDGPU::getRedzoneSizeForScale ( int AsanScale)
static

Definition at line 18 of file AMDGPUAsanInstrumentation.cpp.

Referenced by getMinRedzoneSizeForGlobal().

◆ getRegBitWidth() [1/3]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass & RC)

Get the size in bits of a register from the register class RC.

Definition at line 3069 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegBitWidth() [2/3]

unsigned llvm::AMDGPU::getRegBitWidth ( const TargetRegisterClass & RC)

Get the size in bits of a register from the register class RC.

Definition at line 3576 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID(), and getRegBitWidth().

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegBitWidth(), llvm::SIRegisterInfo::getRegSplitParts(), and llvm::SIInstrInfo::isLegalRegOperand().

◆ getRegBitWidth() [3/3]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned RCID)

Get the size in bits of a register from the register class RC.

Definition at line 2911 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

◆ getSamplecntBitMask()

unsigned llvm::AMDGPU::getSamplecntBitMask ( const IsaVersion & Version)
Returns
Samplecnt bit mask for given isa Version. Returns 0 for versions that do not support SAMPLEcnt

Definition at line 1802 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getSchedStrategy()

StringRef llvm::AMDGPU::getSchedStrategy ( const Function & F)

Definition at line 590 of file AMDGPUTargetMachine.cpp.

References AMDGPUSchedStrategy, F, llvm::Attribute::getValueAsString(), and llvm::Attribute::isValid().

Referenced by llvm::GCNTargetMachine::createMachineScheduler(), and llvm::GCNSubtarget::overrideSchedPolicy().

◆ getSDWAOp()

LLVM_READONLY int32_t llvm::AMDGPU::getSDWAOp ( uint32_t Opcode)

References LLVM_READONLY.

◆ getShiftMask()

std::pair< unsigned, unsigned > llvm::AMDGPU::getShiftMask ( unsigned Value)
constexpr

Deduce the least significant bit aligned shift and mask values for a binary Complement Value (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.

That is to say Value == ~(mask << shift)

For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from SIDefines.h, this will return the pair as (31,1).

Definition at line 27 of file SIDefinesUtils.h.

◆ getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer ( unsigned Opc)

Definition at line 558 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::isBufferInstruction(), and supportsScaleOffset().

◆ getSMRDEncodedLiteralOffset32()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 ( const MCSubtargetInfo & ST,
int64_t ByteOffset )
Returns
The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 3473 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), isDwordAligned(), and llvm::isUInt().

◆ getSMRDEncodedOffset()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo & ST,
int64_t ByteOffset,
bool IsBuffer,
bool HasSOffset = false )
Returns
The encoding that will be used for ByteOffset in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 3444 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isGFX12Plus(), llvm::isInt(), and isLegalSMRDEncodedUnsignedOffset().

◆ getSOPKOp()

LLVM_READONLY int32_t llvm::AMDGPU::getSOPKOp ( uint32_t Opcode)

References LLVM_READONLY.

◆ getSOPPWithRelaxation()

LLVM_READONLY int32_t llvm::AMDGPU::getSOPPWithRelaxation ( uint32_t Opcode)

◆ getSpecifier()

AMDGPUMCExpr::Specifier llvm::AMDGPU::getSpecifier ( const MCSymbolRefExpr * SRE)
inlinestatic

Definition at line 139 of file AMDGPUMCExpr.h.

References llvm::MCSymbolRefExpr::getKind().

Referenced by needsPCRel().

◆ getStorecntBitMask()

unsigned llvm::AMDGPU::getStorecntBitMask ( const IsaVersion & Version)
Returns
STOREcnt or VScnt bit mask for given isa Version. returns 0 for versions that do not support STOREcnt or VScnt. STOREcnt and VScnt are the same counter, the name used depends on the ISA version.

Definition at line 1834 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ getTargetExtType()

TargetExtType * llvm::AMDGPU::getTargetExtType ( const GlobalVariable & GV)
static

Definition at line 42 of file AMDGPUMemoryUtils.cpp.

References llvm::dyn_cast(), and llvm::GlobalValue::getValueType().

Referenced by isNamedBarrier().

◆ getTemporalHintType()

LLVM_READONLY unsigned llvm::AMDGPU::getTemporalHintType ( const MCInstrDesc TID)

Definition at line 806 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), isAsyncStore(), llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, isTensorStore(), llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), Opc, llvm::AMDGPU::CPol::TH_TYPE_ATOMIC, llvm::AMDGPU::CPol::TH_TYPE_LOAD, llvm::AMDGPU::CPol::TH_TYPE_STORE, and llvm::MCInstrDesc::TSFlags.

◆ getTotalNumVGPRs()

int llvm::AMDGPU::getTotalNumVGPRs ( bool has90AInsts,
int32_t ArgNumAGPR,
int32_t ArgNumVGPR )

Definition at line 2731 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo().

◆ getTransitiveUsesOfLDS()

LDSUsesInfoTy llvm::AMDGPU::getTransitiveUsesOfLDS ( const CallGraph & CG,
Module & M )

Definition at line 138 of file AMDGPUMemoryUtils.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, getUsesOfLDSByFunction(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert(), isDynamicLDS(), isKernel(), isNamedBarrier(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reportFatalUsageError(), and llvm::set_union().

◆ getUsesOfLDSByFunction()

void llvm::AMDGPU::getUsesOfLDSByFunction ( const CallGraph & CG,
Module & M,
FunctionVariableMap & kernels,
FunctionVariableMap & Functions )

Definition at line 118 of file AMDGPUMemoryUtils.cpp.

References llvm::dyn_cast(), F, I, isKernel(), isLDSVariableToLower(), and llvm::Value::users().

Referenced by getTransitiveUsesOfLDS().

◆ getVCMPXNoSDstOp()

LLVM_READONLY int32_t llvm::AMDGPU::getVCMPXNoSDstOp ( uint32_t Opcode)

References LLVM_READONLY.

◆ getVCMPXOpFromVCMP()

LLVM_READONLY int32_t llvm::AMDGPU::getVCMPXOpFromVCMP ( uint32_t Opcode)
Returns
v_cmpx version of a v_cmp instruction.

◆ getVGPREncodingMSBs()

unsigned llvm::AMDGPU::getVGPREncodingMSBs ( MCRegister Reg,
const MCRegisterInfo & MRI )
Returns
the MODE bits which have to be set by the S_SET_VGPR_MSB for the physical register Reg.

Definition at line 3560 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterInfo::getEncodingValue(), Reg, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by llvm::AMDGPU::VOPD::InstInfo::getInvalidCompOperandIndex().

◆ getVGPRLoweringOperandTables()

std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > llvm::AMDGPU::getVGPRLoweringOperandTables ( const MCInstrDesc & Desc)

Definition at line 3624 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, llvm::SIInstrFlags::EXP, llvm::SIInstrFlags::FLAT, getVOPDComponents(), isVOPD(), llvm_unreachable, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.

Referenced by getRegFromMIA().

◆ getVGPRPhysRegClass()

const MCRegisterClass * llvm::AMDGPU::getVGPRPhysRegClass ( MCRegister Reg,
const MCRegisterInfo & MRI )
Returns
a register class for the physical register Reg if it is a VGPR or nullptr otherwise.

Definition at line 3539 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), llvm::MCRegisterInfo::getRegClass(), and Reg.

Referenced by getRegForPrinting(), and getVGPRWithMSBs().

◆ getVGPRWithMSBs()

MCRegister llvm::AMDGPU::getVGPRWithMSBs ( MCRegister Reg,
unsigned MSBs,
const MCRegisterInfo & MRI )

If Reg is a low VGPR return a corresponding high VGPR with MSBs set.

Definition at line 3566 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterInfo::getEncodingValue(), llvm::MCRegisterClass::getID(), llvm::MCRegisterClass::getRegister(), getVGPRPhysRegClass(), llvm::AMDGPU::HWEncoding::IS_HI16, Reg, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by getRegFromMIA().

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion & Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 1792 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle ( unsigned Opc)

Definition at line 563 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle ( unsigned Opc)

Definition at line 568 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle ( unsigned Opc)

Definition at line 573 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ getVOPDComponents()

LLVM_READONLY std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents ( unsigned VOPDOpcode)

Definition at line 884 of file AMDGPUBaseInfo.cpp.

References assert().

Referenced by getVGPRLoweringOperandTables(), and getVOPDInstInfo().

◆ getVOPDEncodingFamily()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDEncodingFamily ( const MCSubtargetInfo & ST)
Returns
SIEncodingFamily used for VOPD encoding on a ST.

Definition at line 651 of file AMDGPUBaseInfo.cpp.

References llvm::SIEncodingFamily::GFX11, llvm::SIEncodingFamily::GFX1170, llvm::SIEncodingFamily::GFX12, llvm::SIEncodingFamily::GFX1250, llvm::SIEncodingFamily::GFX13, and llvm_unreachable.

Referenced by shouldScheduleVOPDAdjacent(), and llvm::tryMatchVOPDPair().

◆ getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull ( unsigned OpX,
unsigned OpY,
unsigned EncodingFamily,
bool VOPD3 )

Definition at line 875 of file AMDGPUBaseInfo.cpp.

References getBitOp2().

◆ getVOPDInstInfo() [1/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo ( const MCInstrDesc & OpX,
const MCInstrDesc & OpY )

Definition at line 1054 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::checkVOPDRegConstraints().

◆ getVOPDInstInfo() [2/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo ( unsigned VOPDOpcode,
const MCInstrInfo * InstrInfo )

Definition at line 1058 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::VOPD::COMPONENT_X, getVOPDComponents(), and llvm::SIInstrFlags::VOPD3.

◆ getVOPDOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode ( unsigned Opc,
bool VOPD3 )

Definition at line 698 of file AMDGPUBaseInfo.cpp.

References getBitOp2(), and Opc.

◆ getVOPDXYKey()

constexpr unsigned llvm::AMDGPU::getVOPDXYKey ( unsigned VOPDOp,
unsigned Subtarget,
bool VOPD3 )
staticconstexpr

Definition at line 665 of file AMDGPUBaseInfo.cpp.

Referenced by buildVOPDXYLookup(), and getCanBeVOPD().

◆ getVOPe32()

LLVM_READONLY int32_t llvm::AMDGPU::getVOPe32 ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().

◆ getVOPe64()

LLVM_READONLY int32_t llvm::AMDGPU::getVOPe64 ( uint32_t Opcode)

References LLVM_READONLY.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion & Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 1858 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ getWMMA_F8F6F4_WithFormatArgs()

LLVM_READONLY const MFMA_F8F6F4_Info * llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs ( unsigned FmtA,
unsigned FmtB,
unsigned F8F8Opcode )

Definition at line 643 of file AMDGPUBaseInfo.cpp.

References wmmaScaleF8F6F4FormatToNumRegs().

Referenced by llvm::AMDGPUDisassembler::convertWMMAInst().

◆ getWMMAIsXDL()

LLVM_READONLY bool llvm::AMDGPU::getWMMAIsXDL ( unsigned Opc)

Definition at line 594 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isXDLWMMA().

◆ getXcntBitMask()

unsigned llvm::AMDGPU::getXcntBitMask ( const IsaVersion & Version)
Returns
Xcnt bit mask for given isa Version. Returns 0 for versions that do not support Xcnt.

Definition at line 1826 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPU::HardwareLimits::HardwareLimits().

◆ hasA16()

bool llvm::AMDGPU::hasA16 ( const MCSubtargetInfo & STI)

Definition at line 2551 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasAny64BitVGPROperands() [1/2]

bool llvm::AMDGPU::hasAny64BitVGPROperands ( const MCInstrDesc & OpDesc,
const MCInstrInfo & MII,
const MCSubtargetInfo & ST )

Definition at line 3736 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), llvm::MCInstrInfo::getOpRegClassID(), llvm::MCSubtargetInfo::HwMode_RegInfo, and llvm::MCInstrDesc::operands().

Referenced by isDPALU_DPP().

◆ hasAny64BitVGPROperands() [2/2]

bool llvm::AMDGPU::hasAny64BitVGPROperands ( const MCInstrDesc & OpDesc,
const MCSubtargetInfo & ST )
Returns
true if an instruction may have a 64-bit VGPR operand.

References MI, Opc, and Reg.

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch ( const MCSubtargetInfo & STI)

Definition at line 2711 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ hasDPPSrc1SGPR()

bool llvm::AMDGPU::hasDPPSrc1SGPR ( const MCSubtargetInfo & STI)

Definition at line 2723 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasDynamicVGPR()

bool llvm::AMDGPU::hasDynamicVGPR ( const Function & F)

References F, and LLVM_READNONE.

◆ hasG16()

bool llvm::AMDGPU::hasG16 ( const MCSubtargetInfo & STI)

Definition at line 2555 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasGDS()

bool llvm::AMDGPU::hasGDS ( const MCSubtargetInfo & STI)

Definition at line 2564 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts ( const MCSubtargetInfo & STI)

Definition at line 2695 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ hasKernargPreload()

unsigned llvm::AMDGPU::hasKernargPreload ( const MCSubtargetInfo & STI)

Definition at line 2727 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUDisassembler::hasKernargPreload().

◆ hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts ( const MCSubtargetInfo & STI)

Definition at line 2715 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo & STI)

Definition at line 2546 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasNamedOperand()

LLVM_READONLY bool llvm::AMDGPU::hasNamedOperand ( uint64_t Opcode,
OpName NamedIdx )
inline

Definition at line 436 of file AMDGPUBaseInfo.h.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::checkVOPDRegConstraints(), llvm::AMDGPU::VOPD::ComponentProps::ComponentProps(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPC64DPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::eliminateFrameIndex(), getDstSelForwardingOperand(), getFlatScratchSpillOpcode(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::hasModifiers(), llvm::AMDGPUDisassembler::isMacDPP(), isVOPD(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::SITargetLowering::PostISelFolding(), and supportsScaleOffset().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo & STI)

Definition at line 2559 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isCI(), and isSI().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasSMEMByteOffset()

bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo & ST)
static

Definition at line 3407 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), and isGFX10Plus().

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().

◆ hasSMRDSignedImmOffset()

bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo & ST)
Returns
true if the target supports signed immediate offset for SMRD instructions.

Definition at line 204 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

◆ hasValueInRangeLikeMetadata()

bool llvm::AMDGPU::hasValueInRangeLikeMetadata ( const MDNode & MD,
int64_t Val )

Checks if Val is inside MD, a !range-like metadata.

Definition at line 1769 of file AMDGPUBaseInfo.cpp.

References assert(), E(), llvm::mdconst::extract(), llvm::MDNode::getNumOperands(), llvm::MDNode::getOperand(), High, I, and llvm::Low.

Referenced by flatInstrMayAccessPrivate().

◆ hasVOPD()

bool llvm::AMDGPU::hasVOPD ( const MCSubtargetInfo & STI)

Definition at line 2719 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo & STI)

Definition at line 2542 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( AMDGPUMCKernelCodeT & KernelCode,
const MCSubtargetInfo & STI )

Definition at line 1596 of file AMDGPUBaseInfo.cpp.

References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_kernel_code_version_major, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_kernel_code_version_minor, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_kind, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_major, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_minor, llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_stepping, llvm::AMDGPU::AMDGPUMCKernelCodeT::call_convention, llvm::AMDGPU::AMDGPUMCKernelCodeT::code_properties, llvm::AMDGPU::AMDGPUMCKernelCodeT::compute_pgm_resource_registers, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), llvm::AMDGPU::AMDGPUMCKernelCodeT::group_segment_alignment, llvm::AMDGPU::AMDGPUMCKernelCodeT::kernarg_segment_alignment, llvm::AMDGPU::AMDGPUMCKernelCodeT::kernel_code_entry_byte_offset, llvm::AMDGPU::AMDGPUMCKernelCodeT::private_segment_alignment, S_00B848_FWD_PROGRESS, S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, llvm::FeatureBitset::test(), llvm::Version, and llvm::AMDGPU::AMDGPUMCKernelCodeT::wavefront_size.

Referenced by llvm::AMDGPU::AMDGPUMCKernelCodeT::initDefault().

◆ inst_counter_types()

iota_range< InstCounterType > llvm::AMDGPU::inst_counter_types ( InstCounterType MaxCounter)

Definition at line 14 of file AMDGPUWaitcntUtils.cpp.

References llvm::enum_seq(), and LOAD_CNT.

Referenced by llvm::AMDGPU::Waitcnt::combined(), llvm::AMDGPU::Waitcnt::hasWaitExceptStoreCnt(), and llvm::AMDGPU::Waitcnt::print().

◆ instrumentAddress()

void llvm::AMDGPU::instrumentAddress ( Module & M,
IRBuilder<> & IRB,
Instruction * OrigIns,
Instruction * InsertBefore,
Value * Addr,
Align Alignment,
TypeSize TypeStoreSize,
bool IsWrite,
Value * SizeArgument,
bool UseCalls,
bool Recover,
int Scale,
int Offset )

Instrument the memory operand Addr.

Generates report blocks that catch the addressing errors.

Definition at line 183 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateIntToPtr(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreatePtrToInt(), llvm::IRBuilderBase::CreateTypeSize(), llvm::Constant::getAllOnesValue(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::Value::getType(), instrumentAddressImpl(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::IRBuilderBase::SetInsertPoint(), Size, and llvm::Align::value().

◆ instrumentAddressImpl()

void llvm::AMDGPU::instrumentAddressImpl ( Module & M,
IRBuilder<> & IRB,
Instruction * OrigIns,
Instruction * InsertBefore,
Value * Addr,
Align Alignment,
uint32_t TypeStoreSize,
bool IsWrite,
Value * SizeArgument,
bool UseCalls,
bool Recover,
int AsanScale,
int AsanOffset )
static

Definition at line 150 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAlignedLoad(), llvm::IRBuilderBase::CreateAnd(), llvm::IRBuilderBase::CreateIntToPtr(), llvm::IRBuilderBase::CreateIsNotNull(), llvm::IRBuilderBase::CreatePtrToInt(), createSlowPathCmp(), genAMDGPUReportBlock(), generateCrashCode(), llvm::IntegerType::get(), llvm::PointerType::get(), llvm::Instruction::getDebugLoc(), llvm::Type::getPointerAddressSpace(), llvm::Value::getType(), memToShadow(), llvm::Instruction::setDebugLoc(), llvm::IRBuilderBase::SetInsertPoint(), TypeStoreSizeToSizeIndex(), and llvm::Align::value().

Referenced by instrumentAddress().

◆ isAnyPtr()

bool llvm::AMDGPU::isAnyPtr ( LLT Ty,
unsigned Width )
Returns
true if Ty is a pointer type with size Width.

Definition at line 29 of file AMDGPURegBankLegalizeRules.cpp.

Referenced by LLTToBId(), and matchUniformityAndLLT().

◆ isArgPassedInSGPR() [1/2]

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument * A)

Definition at line 3352 of file AMDGPUBaseInfo.cpp.

References A(), llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, F, and llvm::CallingConv::SPIR_KERNEL.

Referenced by adjustInliningThresholdUsingCallee(), isTriviallyUniform(), and isUniformMMO().

◆ isArgPassedInSGPR() [2/2]

bool llvm::AMDGPU::isArgPassedInSGPR ( const CallBase * CB,
unsigned ArgNo )

Definition at line 3381 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallBase::getCallingConv(), llvm::CallBase::paramHasAttr(), and llvm::CallingConv::SPIR_KERNEL.

◆ isAsyncStore()

LLVM_READONLY bool llvm::AMDGPU::isAsyncStore ( unsigned Opc)

Definition at line 790 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getTemporalHintType().

◆ isChainCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isChainCC ( CallingConv::ID CC)
constexpr

Definition at line 1503 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS_Chain, and llvm::CallingConv::AMDGPU_CS_ChainPreserve.

Referenced by llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::MCResourceInfo::gatherResourceInfo(), getCallOpcode(), llvm::AMDGPUCallLowering::handleImplicitCallArguments(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerTailCall(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo & STI)

Definition at line 2589 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().

◆ isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction ( const LoadInst * Load,
MemorySSA * MSSA,
AAResults * AA )

Check is a Load is clobbered in its function.

Definition at line 398 of file AMDGPUMemoryUtils.cpp.

References llvm::cast(), llvm::dbgs(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), LLVM_DEBUG, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ isCompute()

LLVM_READNONE constexpr bool llvm::AMDGPU::isCompute ( CallingConv::ID CC)
constexpr

Definition at line 1480 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS, and isGraphics().

Referenced by EmitPALMetadataCommon(), llvm::SIProgramInfo::getPGMRSrc1(), llvm::SIProgramInfo::getPGMRSrc2(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::SIFrameLowering::mayReserveScratchForCWSR(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

◆ isConstantAddressSpace()

bool llvm::AMDGPU::isConstantAddressSpace ( unsigned AS)
inline

Definition at line 101 of file AMDGPUAddrSpace.h.

◆ isCvt_F32_Fp8_Bf8_e64()

LLVM_READNONE bool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 ( unsigned Opc)

Definition at line 755 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isDPALU_DPP()

bool llvm::AMDGPU::isDPALU_DPP ( const MCInstrDesc & OpDesc,
const MCInstrInfo & MII,
const MCSubtargetInfo & ST )
Returns
true if an instruction is a DP ALU DPP.

Definition at line 3774 of file AMDGPUBaseInfo.cpp.

References llvm::MCInstrDesc::getOpcode(), hasAny64BitVGPROperands(), and isDPALU_DPP32BitOpc().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ isDPALU_DPP32BitOpc()

bool llvm::AMDGPU::isDPALU_DPP32BitOpc ( unsigned Opc)
Returns
true if an instruction is a DP ALU DPP without any 64-bit operands.

Definition at line 3754 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by isDPALU_DPP().

◆ isDPMACCInstruction()

bool llvm::AMDGPU::isDPMACCInstruction ( unsigned Opc)

Definition at line 838 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isVOPDAntidependencyAllowed().

◆ isDwordAligned()

bool llvm::AMDGPU::isDwordAligned ( uint64_t ByteOffset)
static

Definition at line 3431 of file AMDGPUBaseInfo.cpp.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ isDynamicLDS()

bool llvm::AMDGPU::isDynamicLDS ( const GlobalVariable & GV)

Definition at line 67 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::GlobalVariable::getGlobalSize(), llvm::GlobalValue::getParent(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by getTransitiveUsesOfLDS(), and isLDSVariableToLower().

◆ isEntryFunctionCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID CC)
constexpr

Definition at line 1485 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::MCResourceInfo::gatherResourceInfo(), llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isModuleEntryFunctionCC(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), llvm::SIFrameLowering::mayReserveScratchForCWSR(), mustPreserveGV(), and recursivelyVisitUsers().

◆ isExtendedGlobalAddrSpace()

bool llvm::AMDGPU::isExtendedGlobalAddrSpace ( unsigned AS)
inline

Definition at line 95 of file AMDGPUAddrSpace.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::GCNTTIImpl::getScalingFactorCost(), llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), and llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned AS)
inline

Definition at line 90 of file AMDGPUAddrSpace.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::SITargetLowering::shouldExpandAtomicRMWInIR(), and llvm::GCNTTIImpl::shouldPrefetchAddressSpace().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo & STI)

Definition at line 2683 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by hasSMEMByteOffset().

◆ isGenericAtomic()

LLVM_READNONE bool llvm::AMDGPU::isGenericAtomic ( unsigned Opc)

Definition at line 768 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo & STI)

Definition at line 2623 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by getGcnBufferFormatInfo(), getGcnBufferFormatInfo(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10_GFX11(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().

◆ isGFX10_3_GFX11()

bool llvm::AMDGPU::isGFX10_3_GFX11 ( const MCSubtargetInfo & STI)

Definition at line 2699 of file AMDGPUBaseInfo.cpp.

References isGFX10_BEncoding(), and isGFX12Plus().

◆ isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding ( const MCSubtargetInfo & STI)

Definition at line 2687 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding ( const MCSubtargetInfo & STI)

Definition at line 2691 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_3_GFX11(), and isGFX10Before1030().

◆ isGFX10_GFX11()

bool llvm::AMDGPU::isGFX10_GFX11 ( const MCSubtargetInfo & STI)

Definition at line 2627 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11().

◆ isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030 ( const MCSubtargetInfo & STI)

Definition at line 2679 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX10_BEncoding().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus ( const MCSubtargetInfo & STI)

Definition at line 2631 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by createAMDGPUMCSubtargetInfo(), llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding(), supportsWave32(), supportsWGP(), and llvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX11()

bool llvm::AMDGPU::isGFX11 ( const MCSubtargetInfo & STI)

Definition at line 2635 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_GFX11(), isGFX11Plus(), isGFX9_GFX10_GFX11(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

◆ isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus ( const MCSubtargetInfo & STI)

Definition at line 2639 of file AMDGPUBaseInfo.cpp.

References isGFX11(), and isGFX12Plus().

Referenced by llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt(), llvm::AMDGPU::SendMsg::decodeMsg(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getGcnBufferFormatInfo(), getGcnBufferFormatInfo(), llvm::AMDGPU::SendMsg::getMsgIdMask(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormat(), imageIntrinsicOptimizerImpl(), isGFX10Plus(), llvm::AMDGPUDisassembler::isGFX11Plus(), isNotGFX11Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::SendMsg::isValidMsgStream(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::AMDGPU::SendMsg::msgDoesNotUseM0(), llvm::AMDGPU::SendMsg::msgRequiresOp(), and llvm::AMDGPU::SendMsg::msgSupportsStream().

◆ isGFX12()

bool llvm::AMDGPU::isGFX12 ( const MCSubtargetInfo & STI)

Definition at line 2643 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX12Plus(), and isLegalDPALU_DPPControl().

◆ isGFX1250()

bool llvm::AMDGPU::isGFX1250 ( const MCSubtargetInfo & STI)

Definition at line 2653 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and isGFX13().

Referenced by llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPUDisassembler::isGFX1250(), supportsWave32(), and supportsWGP().

◆ isGFX1250Plus()

bool llvm::AMDGPU::isGFX1250Plus ( const MCSubtargetInfo & STI)

Definition at line 2657 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), getMaxNumUserSGPRs(), and llvm::AMDGPUDisassembler::isGFX1250Plus().

◆ isGFX12Plus()

bool llvm::AMDGPU::isGFX12Plus ( const MCSubtargetInfo & STI)

Definition at line 2647 of file AMDGPUBaseInfo.cpp.

References isGFX12(), and isGFX13Plus().

Referenced by llvm::SIInstrInfo::allowNegativeFlatOffset(), getInstPrefSizeFieldWidth(), getSMRDEncodedOffset(), isGFX10_3_GFX11(), isGFX11Plus(), llvm::AMDGPUDisassembler::isGFX12Plus(), llvm::SIInstrInfo::isLegalRegOperand(), isLegalSMRDEncodedSignedOffset(), isLegalSMRDEncodedUnsignedOffset(), isNotGFX12Plus(), llvm::SIInstrInfo::isXDL(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::verifyInstruction().

◆ isGFX13()

bool llvm::AMDGPU::isGFX13 ( const MCSubtargetInfo & STI)

Definition at line 2661 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isGFX1250(), llvm::AMDGPUDisassembler::isGFX13(), and isGFX13Plus().

◆ isGFX13Plus()

bool llvm::AMDGPU::isGFX13Plus ( const MCSubtargetInfo & STI)

Definition at line 2665 of file AMDGPUBaseInfo.cpp.

References isGFX13().

Referenced by isGFX12Plus(), llvm::AMDGPUDisassembler::isGFX13Plus(), and llvm::AMDGPU::Exp::isSupportedTgtId().

◆ isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10 ( const MCSubtargetInfo & STI)

Definition at line 2609 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX9(), and isVI().

◆ isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus ( const MCSubtargetInfo & STI)

Definition at line 2613 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and isVI().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo & STI)

Definition at line 2597 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), isGFX9Plus(), and isNotGFX10Plus().

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A ( const MCSubtargetInfo & STI)

Definition at line 2703 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and isLegalDPALU_DPPControl().

◆ isGFX940()

bool llvm::AMDGPU::isGFX940 ( const MCSubtargetInfo & STI)

Definition at line 2707 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10 ( const MCSubtargetInfo & STI)

Definition at line 2601 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX9().

◆ isGFX9_GFX10_GFX11()

bool llvm::AMDGPU::isGFX9_GFX10_GFX11 ( const MCSubtargetInfo & STI)

Definition at line 2605 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX11(), and isGFX9().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus ( const MCSubtargetInfo & STI)

Definition at line 2617 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX9().

Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), llvm::AMDGPUDisassembler::isGFX9Plus(), isNotGFX9Plus(), and llvm::AMDGPUInstPrinter::printSwizzle().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue * GV)

Definition at line 1634 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.

◆ isGraphics()

LLVM_READNONE constexpr bool llvm::AMDGPU::isGraphics ( CallingConv::ID CC)
constexpr

Definition at line 1474 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, and isShader().

Referenced by llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue * GV)

Definition at line 1630 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

◆ isHi16Reg()

bool llvm::AMDGPU::isHi16Reg ( MCRegister Reg,
const MCRegisterInfo & MRI )
Returns
if Reg occupies the high 16-bits of a 32-bit register.

Definition at line 2745 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterInfo::getEncodingValue(), llvm::AMDGPU::HWEncoding::IS_HI16, and Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::getRegAllocationHints(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::AMDGPUMCInstLower::lowerT16FmaMixFP16(), and llvm::SIRegisterInfo::SIRegisterInfo().

◆ isHsaAbi()

bool llvm::AMDGPU::isHsaAbi ( const MCSubtargetInfo & STI)
Returns
True if STI is AMDHSA.

Definition at line 209 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::Triple::getOS(), and llvm::MCSubtargetInfo::getTargetTriple().

◆ isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t Literal)
inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line 1716 of file AMDGPUBaseInfo.h.

References llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isInlinableLiteral32(), isInlinableLiteral64(), isInlinableLiteralBF16(), isInlinableLiteralFP16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t Literal,
bool HasInv2Pi )

Definition at line 3090 of file AMDGPUBaseInfo.cpp.

References llvm::bit_cast(), isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), isInlinableLiteralI16(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isLegalAV64PseudoImm().

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t Literal,
bool HasInv2Pi )

Is this literal inlinable.

Definition at line 3073 of file AMDGPUBaseInfo.cpp.

References llvm::bit_cast(), isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteral64Constant(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), llvm::SIInstrInfo::isInlineConstant(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isOperandLegal().

◆ isInlinableLiteralBF16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralBF16 ( int16_t Literal,
bool HasInv2Pi )

Definition at line 3116 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralFP16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralFP16 ( int16_t Literal,
bool HasInv2Pi )

Definition at line 3137 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlineableLiteralOp16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralI16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralI16 ( int32_t Literal,
bool HasInv2Pi )

Definition at line 3133 of file AMDGPUBaseInfo.cpp.

References isInlinableLiteral32(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( uint32_t Literal,
uint8_t OpType )

Definition at line 3276 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), isInlinableLiteralV2BF16(), llvm::Literal, llvm_unreachable, OPERAND_REG_IMM_NOINLINE_V2FP16, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2INT16.

◆ isInlinableLiteralV2BF16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2BF16 ( uint32_t Literal)

Definition at line 3302 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2BF16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2F16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2F16 ( uint32_t Literal)

Definition at line 3307 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2F16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2I16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2I16 ( uint32_t Literal)

Definition at line 3297 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2I16(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlineValue()

LLVM_READNONE bool llvm::AMDGPU::isInlineValue ( MCRegister Reg)

Definition at line 2839 of file AMDGPUBaseInfo.cpp.

References Reg.

◆ isIntrinsicAlwaysUniform()

bool llvm::AMDGPU::isIntrinsicAlwaysUniform ( unsigned IntrID)
Returns
true if the intrinsic is uniform

Definition at line 3517 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity(), llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform(), and isTriviallyUniform().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned IntrID)
Returns
true if the intrinsic is divergent

Definition at line 3513 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericValueUniformity(), and llvm::SITargetLowering::isSDNodeSourceOfDivergence().

◆ isInvalidSingleUseConsumerInst()

LLVM_READONLY bool llvm::AMDGPU::isInvalidSingleUseConsumerInst ( unsigned Opc)

References LLVM_READONLY, and Opc.

◆ isInvalidSingleUseProducerInst()

LLVM_READONLY bool llvm::AMDGPU::isInvalidSingleUseProducerInst ( unsigned Opc)

References LLVM_READONLY, and Opc.

◆ isKernel() [1/2]

LLVM_READNONE constexpr bool llvm::AMDGPU::isKernel ( CallingConv::ID CC)
inlineconstexpr

Definition at line 1535 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, and llvm::CallingConv::SPIR_KERNEL.

Referenced by getTransitiveUsesOfLDS(), getUsesOfLDSByFunction(), isKernel(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), and removeFnAttrFromReachable().

◆ isKernel() [2/2]

bool llvm::AMDGPU::isKernel ( const Function & F)
inline

Definition at line 1545 of file AMDGPUBaseInfo.h.

References F, and isKernel().

◆ isKImmOperand()

bool llvm::AMDGPU::isKImmOperand ( const MCInstrDesc & Desc,
unsigned OpNo )

Is this a KImm operand?

Definition at line 2870 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_KIMM_FIRST, and OPERAND_KIMM_LAST.

◆ isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower ( const GlobalVariable & GV)

Definition at line 76 of file AMDGPUMemoryUtils.cpp.

References llvm::GlobalVariable::getInitializer(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalVariable::hasInitializer(), llvm::isa(), llvm::GlobalVariable::isConstant(), isDynamicLDS(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by eliminateConstantExprUsesOfLDSFromAllInstructions(), and getUsesOfLDSByFunction().

◆ isLegalDPALU_DPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegalDPALU_DPPControl ( const MCSubtargetInfo & ST,
unsigned DC )
inline

Definition at line 1815 of file AMDGPUBaseInfo.h.

References isGFX12(), isGFX90A(), llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST, llvm::AMDGPU::DPP::ROW_SHARE_FIRST, and llvm::AMDGPU::DPP::ROW_SHARE_LAST.

Referenced by llvm::SIInstrInfo::expandMovDPP64(), llvm::AMDGPULegalizerInfo::legalizeLaneOp(), lowerLaneOp(), and llvm::SIInstrInfo::verifyInstruction().

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset ( const MCSubtargetInfo & ST,
int64_t EncodedOffset,
bool IsBuffer )

Definition at line 3420 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset(), isGFX12Plus(), and llvm::isInt().

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset ( const MCSubtargetInfo & ST,
int64_t EncodedOffset )

Definition at line 3411 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset(), isGFX12Plus(), and llvm::isUInt().

Referenced by getSMRDEncodedOffset().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo & ST,
int64_t ByteOffset )
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

References LLVM_READNONE.

◆ isLitExpr()

bool llvm::AMDGPU::isLitExpr ( const MCExpr * Expr)

Definition at line 715 of file AMDGPUMCExpr.cpp.

References llvm::AMDGPUMCExpr::AGVK_Lit, llvm::AMDGPUMCExpr::AGVK_Lit64, and llvm::dyn_cast().

Referenced by getLitValue().

◆ isMAC()

LLVM_READNONE bool llvm::AMDGPU::isMAC ( unsigned Opc)

Definition at line 709 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isModuleEntryFunctionCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::isModuleEntryFunctionCC ( CallingConv::ID CC)
constexpr

Definition at line 1524 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_Gfx, and isEntryFunctionCC().

Referenced by llvm::AMDGPUTargetMachine::getAssumedAddrSpace().

◆ isNamedBarrier()

TargetExtType * llvm::AMDGPU::isNamedBarrier ( const GlobalVariable & GV)

Definition at line 61 of file AMDGPUMemoryUtils.cpp.

References llvm::TargetExtType::getName(), and getTargetExtType().

Referenced by llvm::AMDGPUMachineFunctionInfo::allocateLDSGlobal(), getTransitiveUsesOfLDS(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), and llvm::AMDGPUTargetLowering::LowerGlobalAddress().

◆ isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus ( const MCSubtargetInfo & STI)

Definition at line 2675 of file AMDGPUBaseInfo.cpp.

References isCI(), isGFX9(), isSI(), and isVI().

◆ isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus ( const MCSubtargetInfo & STI)

Definition at line 2673 of file AMDGPUBaseInfo.cpp.

References isGFX11Plus().

◆ isNotGFX12Plus()

bool llvm::AMDGPU::isNotGFX12Plus ( const MCSubtargetInfo & STI)

Definition at line 2651 of file AMDGPUBaseInfo.cpp.

References isGFX12Plus().

◆ isNotGFX9Plus()

bool llvm::AMDGPU::isNotGFX9Plus ( const MCSubtargetInfo & STI)

Definition at line 2621 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

◆ isPackedFP32Inst()

LLVM_READONLY bool llvm::AMDGPU::isPackedFP32Inst ( unsigned Opc)

Definition at line 3797 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::verifyInstruction().

◆ isPermlane16()

LLVM_READNONE bool llvm::AMDGPU::isPermlane16 ( unsigned Opc)

Definition at line 740 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isPKFMACF16InlineConstant()

LLVM_READNONE bool llvm::AMDGPU::isPKFMACF16InlineConstant ( uint32_t Literal,
bool IsGFX11Plus )

Definition at line 3312 of file AMDGPUBaseInfo.cpp.

References getPKFMACF16InlineEncoding(), and llvm::Literal.

Referenced by llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::SIInstrInfo::isInlineConstant().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue * GV)

Definition at line 1638 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber ( const Value * Ptr,
MemoryDef * Def,
AAResults * AA )

Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line 356 of file AMDGPUMemoryUtils.cpp.

References llvm::dyn_cast(), I, II, and llvm::isa().

Referenced by isClobberedInFunction().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( MCRegister Reg,
const MCRegisterInfo * TRI )

Is Reg - scalar register.

Definition at line 2738 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), Reg, and TRI.

◆ isShader()

LLVM_READNONE constexpr bool llvm::AMDGPU::isShader ( CallingConv::ID CC)
constexpr

Definition at line 1456 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.

Referenced by llvm::GCNTTIImpl::fpenvIEEEMode(), llvm::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), and reservePrivateMemoryRegs().

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo & STI)

Definition at line 2585 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc & Desc,
unsigned OpNo )

Is this floating-point operand?

Definition at line 2877 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_NOINLINE_V2FP16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP16_SPLAT, OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, and OPERAND_REG_INLINE_C_V2FP16.

Referenced by llvm::AMDGPU::VOPD::ComponentProps::ComponentProps().

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc & Desc,
unsigned OpNo )

Does this operand support only inlinable literals?

Definition at line 2900 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_INLINE_AC_FIRST, OPERAND_REG_INLINE_AC_LAST, OPERAND_REG_INLINE_C_FIRST, and OPERAND_REG_INLINE_C_LAST.

◆ isSISrcOperand() [1/2]

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc & Desc,
unsigned OpNo )
inline

Definition at line 1644 of file AMDGPUBaseInfo.h.

References isSISrcOperand().

◆ isSISrcOperand() [2/2]

bool llvm::AMDGPU::isSISrcOperand ( const MCOperandInfo & OpInfo)
constexpr

Is this an AMDGPU specific source operand?

These include registers, inline constants, literals and mandatory literals (KImm).

Definition at line 1639 of file AMDGPUBaseInfo.h.

References OPERAND_SRC_FIRST, and OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isLiteralOperandLegal(), llvm::SIInstrInfo::isOperandLegal(), and isSISrcOperand().

◆ isSymbolicCustomOperandEncoding()

bool llvm::AMDGPU::isSymbolicCustomOperandEncoding ( const CustomOperandVal * Opr,
int Size,
unsigned Code,
bool & HasNonDefaultVal,
const MCSubtargetInfo & STI )
static

Definition at line 2004 of file AMDGPUBaseInfo.cpp.

References Size.

Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().

◆ isTensorStore()

LLVM_READONLY bool llvm::AMDGPU::isTensorStore ( unsigned Opc)

Definition at line 801 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by getTemporalHintType().

◆ isTrue16Inst()

LLVM_READONLY bool llvm::AMDGPU::isTrue16Inst ( unsigned Opc)

Definition at line 821 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isUniformMMO()

bool llvm::AMDGPU::isUniformMMO ( const MachineMemOperand * MMO)

Definition at line 30 of file AMDGPUInstrInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::dyn_cast(), llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getPseudoValue(), llvm::MachineMemOperand::getValue(), I, llvm::isa(), and isArgPassedInSGPR().

Referenced by llvm::AMDGPURegisterBankInfo::isScalarLoadLegal(), llvm::AMDGPU::RegBankLegalizeRules::RegBankLegalizeRules(), and llvm::AMDGPUTargetLowering::shouldReduceLoadWidth().

◆ isValid32BitLiteral()

LLVM_READNONE bool llvm::AMDGPU::isValid32BitLiteral ( uint64_t Val,
bool IsFP64 )

Definition at line 3316 of file AMDGPUBaseInfo.cpp.

References llvm::isInt(), llvm::isUInt(), and llvm::Lo_32().

Referenced by llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::isOperandLegal(), llvm::AMDGPUDAGToDAGISel::Select(), and llvm::SIInstrInfo::verifyInstruction().

◆ isValidRegPrefix()

bool llvm::AMDGPU::isValidRegPrefix ( char C)
static

Definition at line 1648 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::C.

Referenced by parseAsmPhysRegName().

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo & STI)

Definition at line 2593 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().

◆ isVOPC64DPP()

LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP ( unsigned Opc)

Definition at line 578 of file AMDGPUBaseInfo.cpp.

References Opc.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isVOPCAsmOnly()

LLVM_READONLY bool llvm::AMDGPU::isVOPCAsmOnly ( unsigned Opc)

Definition at line 582 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ isVOPD()

LLVM_READONLY bool llvm::AMDGPU::isVOPD ( unsigned Opc)

Definition at line 705 of file AMDGPUBaseInfo.cpp.

References hasNamedOperand(), and Opc.

Referenced by getSrcOperandIndices(), and getVGPRLoweringOperandTables().

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic * llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned Intr)

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned Intr)

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::SITargetLowering::getTgtMemIntrinsic().

◆ mapToDWARFAddrSpace()

int llvm::AMDGPU::mapToDWARFAddrSpace ( unsigned LLVMAddrSpace)
constexpr

If LLVMAddressSpace has a corresponding DWARF encoding, return it; otherwise return the sentinel value -1 to indicate no such mapping exists.

This maps private/scratch to the focused lane view.

These mappings must be kept in sync with llvm/docs/AMDGPUUsage.rst table "AMDGPU DWARF Address Space Mapping".

Note: This could return std::optional<int> but that would require an extra #include.

Definition at line 164 of file AMDGPUAddrSpace.h.

References llvm::AMDGPU::impl::LLVMToDWARFAddrSpaceMapping.

◆ mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode ( unsigned Opc)

Definition at line 843 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ mapWMMA3AddrTo2AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode ( unsigned Opc)

Definition at line 848 of file AMDGPUBaseInfo.cpp.

References Opc.

◆ maskShiftGet()

const MCExpr * llvm::AMDGPU::maskShiftGet ( const MCExpr * Val,
uint32_t Mask,
uint32_t Shift,
MCContext & Ctx )
inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr

  • will be the equivalent of (Val >> 6) & 0xf

Definition at line 63 of file SIDefinesUtils.h.

References llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), and llvm::MCBinaryExpr::createLShr().

◆ maskShiftSet()

const MCExpr * llvm::AMDGPU::maskShiftSet ( const MCExpr * Val,
uint32_t Mask,
uint32_t Shift,
MCContext & Ctx )
inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr

  • will be the equivalent of (Val & 0xf) << 6

Definition at line 44 of file SIDefinesUtils.h.

References llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), and llvm::MCBinaryExpr::createShl().

Referenced by llvm::AMDGPU::AMDGPUMCKernelCodeT::EmitKernelCodeT().

◆ mayTailCallThisCC()

LLVM_READNONE constexpr bool llvm::AMDGPU::mayTailCallThisCC ( CallingConv::ID CC)
constexpr

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 1554 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, llvm::CallingConv::C, and canGuaranteeTCO().

Referenced by llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), and llvm::SITargetLowering::isEligibleForTailCallOptimization().

◆ mc2PseudoReg()

LLVM_READNONE MCRegister llvm::AMDGPU::mc2PseudoReg ( MCRegister Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 2837 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG, and Reg.

Referenced by checkWriteLane().

◆ memToShadow()

Value * llvm::AMDGPU::memToShadow ( Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Value * Shadow,
int AsanScale,
uint32_t AsanOffset )
static

Definition at line 139 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), and llvm::IRBuilderBase::CreateLShr().

Referenced by instrumentAddressImpl().

◆ mfmaScaleF8F6F4FormatToNumRegs()

LLVM_READNONE uint8_t llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs ( unsigned EncodingVal)

Definition at line 604 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MFMAScaleFormats::FP4_E2M1, llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3, llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2, llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3, llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2, and llvm_unreachable.

Referenced by getMFMA_F8F6F4_WithFormatArgs().

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef CPU)

Definition at line 56 of file AMDGPUTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default(), and GK_NONE.

Referenced by fillAMDGCNFeatureMap(), getCanonicalArchName(), llvm::AMDGPUTargetStreamer::getElfMach(), and getIsaVersion().

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef CPU)

Definition at line 64 of file AMDGPUTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default(), and GK_NONE.

Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().

◆ parseAsmConstraintPhysReg()

std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmConstraintPhysReg ( StringRef Constraint)

Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.

Followed by the start register number, and the register width. Does not validate the number of registers exists in the class.

Definition at line 1680 of file AMDGPUBaseInfo.cpp.

References parseAsmPhysRegName(), and RegName.

Referenced by llvm::SITargetLowering::getRegForInlineAsmConstraint().

◆ parseAsmPhysRegName()

std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmPhysRegName ( StringRef TupleString)

Returns a valid charcode or 0 in the first entry if this is a valid physical register name.

Followed by the start register number, and the register width. Does not validate the number of registers exists in the class. Unlike parseAsmConstraintPhysReg, this does not expect the name to be wrapped in "{}".

Definition at line 1652 of file AMDGPUBaseInfo.cpp.

References llvm::Failed(), isValidRegPrefix(), and RegName.

Referenced by parseAsmConstraintPhysReg().

◆ printAMDGPUMCExpr()

void llvm::AMDGPU::printAMDGPUMCExpr ( const MCExpr * Expr,
raw_ostream & OS,
const MCAsmInfo * MAI )

Definition at line 704 of file AMDGPUMCExpr.cpp.

References llvm::MCAsmInfo::printExpr().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ removeFnAttrFromReachable()

void llvm::AMDGPU::removeFnAttrFromReachable ( CallGraph & CG,
Function * KernelRoot,
ArrayRef< StringRef > FnAttrs )

Strip FnAttr attribute from any functions where we may have introduced its use.

Definition at line 312 of file AMDGPUMemoryUtils.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, llvm::CallGraph::getExternalCallingNode(), llvm::Function::getFunction(), llvm::SmallPtrSetImpl< PtrType >::insert(), isKernel(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::Function::removeFnAttr().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple & TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 1644 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::r600.

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().

◆ supportsScaleOffset()

bool llvm::AMDGPU::supportsScaleOffset ( const MCInstrInfo & MII,
unsigned Opcode )
Returns
true if a memory instruction supports scale_offset modifier.

Definition at line 3717 of file AMDGPUBaseInfo.cpp.

References llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::FlatScratch, llvm::MCInstrInfo::get(), getSMEMIsBuffer(), hasNamedOperand(), llvm::SIInstrFlags::SMRD, and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ supportsWave32()

bool llvm::AMDGPU::supportsWave32 ( const MCSubtargetInfo & STI)
inline

Definition at line 1612 of file AMDGPUBaseInfo.h.

References isGFX10Plus(), and isGFX1250().

Referenced by createAMDGPUMCSubtargetInfo().

◆ supportsWGP()

bool llvm::AMDGPU::supportsWGP ( const MCSubtargetInfo & STI)

Definition at line 2667 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX1250().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ TypeStoreSizeToSizeIndex()

size_t llvm::AMDGPU::TypeStoreSizeToSizeIndex ( uint32_t TypeSize)
static

Definition at line 52 of file AMDGPUAsanInstrumentation.cpp.

References llvm::countr_zero().

Referenced by instrumentAddressImpl().

◆ wmmaScaleF8F6F4FormatToNumRegs()

LLVM_READNONE uint8_t llvm::AMDGPU::wmmaScaleF8F6F4FormatToNumRegs ( unsigned Fmt)

Definition at line 628 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable, llvm::AMDGPU::WMMA::MATRIX_FMT_BF6, llvm::AMDGPU::WMMA::MATRIX_FMT_BF8, llvm::AMDGPU::WMMA::MATRIX_FMT_FP4, llvm::AMDGPU::WMMA::MATRIX_FMT_FP6, and llvm::AMDGPU::WMMA::MATRIX_FMT_FP8.

Referenced by getWMMA_F8F6F4_WithFormatArgs(), and llvm::GCNTTIImpl::instCombineIntrinsic().

Variable Documentation

◆ ExtendedFltRoundOffset

uint32_t llvm::AMDGPU::ExtendedFltRoundOffset = 4
staticconstexpr

Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.

Definition at line 135 of file SIModeRegisterDefaults.h.

Referenced by decodeFltRoundToHWConversionTable(), decodeIndexFltRoundConversionTable(), encodeFltRoundsTable(), encodeFltRoundsToHWTable(), and encodeFltRoundsToHWTableSame().

◆ F32FltRoundOffset

uint32_t llvm::AMDGPU::F32FltRoundOffset = 0
staticconstexpr

Offset in mode register of f32 rounding mode.

Definition at line 138 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

◆ F64FltRoundOffset

uint32_t llvm::AMDGPU::F64FltRoundOffset = 2
staticconstexpr

Offset in mode register of f64/f16 rounding mode.

Definition at line 141 of file SIModeRegisterDefaults.h.

Referenced by getModeRegisterRoundMode().

◆ FltRoundConversionTable

const uint64_t llvm::AMDGPU::FltRoundConversionTable
extern

Definition at line 74 of file SIModeRegisterDefaults.cpp.

Referenced by decodeIndexFltRoundConversionTable(), and llvm::SITargetLowering::lowerGET_ROUNDING().

◆ FltRoundToHWConversionTable

const uint64_t llvm::AMDGPU::FltRoundToHWConversionTable
extern

Definition at line 188 of file SIModeRegisterDefaults.cpp.

Referenced by decodeFltRoundToHW(), decodeFltRoundToHWConversionTable(), decodeFltRoundToHWConversionTable(), and llvm::SITargetLowering::lowerSET_ROUNDING().

◆ LaneMaskConstants32

LaneMaskConstants llvm::AMDGPU::LaneMaskConstants32
staticconstexpr
Initial value:
=
LaneMaskConstants(true)

Definition at line 76 of file AMDGPULaneMaskUtils.h.

Referenced by llvm::AMDGPU::LaneMaskConstants::get().

◆ LaneMaskConstants64

LaneMaskConstants llvm::AMDGPU::LaneMaskConstants64
staticconstexpr
Initial value:
=
LaneMaskConstants(false)

Definition at line 78 of file AMDGPULaneMaskUtils.h.

Referenced by llvm::AMDGPU::LaneMaskConstants::get().

◆ OPR_ID_DUPLICATE

const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3

Definition at line 25 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand().

◆ OPR_ID_UNKNOWN

const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1

Definition at line 23 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getEncodingFromOperandTable().

◆ OPR_ID_UNSUPPORTED

const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2

Definition at line 24 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperand(), and getEncodingFromOperandTable().

◆ OPR_VAL_INVALID

const int llvm::AMDGPU::OPR_VAL_INVALID = -4

Definition at line 26 of file AMDGPUAsmUtils.h.

Referenced by encodeCustomOperandVal().

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 1904 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 1905 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 1906 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 1907 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ VOPDXYKeyBits

unsigned llvm::AMDGPU::VOPDXYKeyBits = 11
constexpr

Definition at line 673 of file AMDGPUBaseInfo.cpp.

◆ VOPDXYLookup

auto llvm::AMDGPU::VOPDXYLookup = buildVOPDXYLookup()
constexpr

Definition at line 685 of file AMDGPUBaseInfo.cpp.

Referenced by getCanBeVOPD().

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