LLVM  14.0.0git
HWEventListener.h
Go to the documentation of this file.
1 //===----------------------- HWEventListener.h ------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines the main interface for hardware event listeners.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MCA_HWEVENTLISTENER_H
15 #define LLVM_MCA_HWEVENTLISTENER_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/MCA/Instruction.h"
19 #include "llvm/MCA/Support.h"
20 
21 namespace llvm {
22 namespace mca {
23 
24 // An HWInstructionEvent represents state changes of instructions that
25 // listeners might be interested in. Listeners can choose to ignore any event
26 // they are not interested in.
28 public:
29  // This is the list of event types that are shared by all targets, that
30  // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
31  // ...) and generic Views can manipulate.
32  // Subtargets are free to define additional event types, that are goin to be
33  // handled by generic components as opaque values, but can still be
34  // emitted by subtarget-specific pipeline stages (e.g., ExecuteStage,
35  // DispatchStage, ...) and interpreted by subtarget-specific EventListener
36  // implementations.
38  Invalid = 0,
39  // Events generated by the Retire Control Unit.
41  // Events generated by the Scheduler.
46  // Events generated by the Dispatch logic.
48 
50  };
51 
52  HWInstructionEvent(unsigned type, const InstRef &Inst)
53  : Type(type), IR(Inst) {}
54 
55  // The event type. The exact meaning depends on the subtarget.
56  const unsigned Type;
57 
58  // The instruction this event was generated for.
59  const InstRef &IR;
60 };
61 
62 using ResourceRef = std::pair<uint64_t, uint64_t>;
63 using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
64 
66 public:
69 
71 };
72 
74 public:
76  unsigned UOps)
78  UsedPhysRegs(Regs), MicroOpcodes(UOps) {}
79  // Number of physical register allocated for this instruction. There is one
80  // entry per register file.
82  // Number of micro opcodes dispatched.
83  // This field is often set to the total number of micro-opcodes specified by
84  // the instruction descriptor of IR.
85  // The only exception is when IR declares a number of micro opcodes
86  // which exceeds the processor DispatchWidth, and - by construction - it
87  // requires multiple cycles to be fully dispatched. In that particular case,
88  // the dispatch logic would generate more than one dispatch event (one per
89  // cycle), and each event would declare how many micro opcodes are effectively
90  // been dispatched to the schedulers.
91  unsigned MicroOpcodes;
92 };
93 
95 public:
98  FreedPhysRegs(Regs) {}
99  // Number of register writes that have been architecturally committed. There
100  // is one entry per register file.
102 };
103 
104 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
105 // resources.
107 public:
109  Invalid = 0,
110  // Generic stall events generated by the DispatchStage.
113  // Generic stall events generated by the Scheduler.
120  };
121 
122  HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {}
123 
124  // The exact meaning of the stall event type depends on the subtarget.
125  const unsigned Type;
126 
127  // The instruction this event was generated for.
128  const InstRef &IR;
129 };
130 
131 // A HWPressureEvent describes an increase in backend pressure caused by
132 // the presence of data dependencies or unavailability of pipeline resources.
134 public:
136  INVALID = 0,
137  // Scheduler was unable to issue all the ready instructions because some
138  // pipeline resources were unavailable.
140  // Instructions could not be issued because of register data dependencies.
142  // Instructions could not be issued because of memory dependencies.
144  };
145 
147  uint64_t Mask = 0)
148  : Reason(reason), AffectedInstructions(Insts), ResourceMask(Mask) {}
149 
150  // Reason for this increase in backend pressure.
152 
153  // Instructions affected (i.e. delayed) by this increase in backend pressure.
155 
156  // A mask of unavailable processor resources.
158 };
159 
161 public:
162  // Generic events generated by the pipeline.
163  virtual void onCycleBegin() {}
164  virtual void onCycleEnd() {}
165 
166  virtual void onEvent(const HWInstructionEvent &Event) {}
167  virtual void onEvent(const HWStallEvent &Event) {}
168  virtual void onEvent(const HWPressureEvent &Event) {}
169 
170  virtual void onResourceAvailable(const ResourceRef &RRef) {}
171 
172  // Events generated by the Scheduler when buffered resources are
173  // consumed/freed for an instruction.
174  virtual void onReservedBuffers(const InstRef &Inst,
175  ArrayRef<unsigned> Buffers) {}
176  virtual void onReleasedBuffers(const InstRef &Inst,
177  ArrayRef<unsigned> Buffers) {}
178 
179  virtual ~HWEventListener() {}
180 
181 private:
182  virtual void anchor();
183 };
184 } // namespace mca
185 } // namespace llvm
186 
187 #endif // LLVM_MCA_HWEVENTLISTENER_H
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::mca::HWStallEvent::CustomBehaviourStall
@ CustomBehaviourStall
Definition: HWEventListener.h:118
llvm::mca::HWPressureEvent::GenericReason
GenericReason
Definition: HWEventListener.h:135
llvm::mca::HWEventListener::onReservedBuffers
virtual void onReservedBuffers(const InstRef &Inst, ArrayRef< unsigned > Buffers)
Definition: HWEventListener.h:174
llvm::mca::HWInstructionIssuedEvent
Definition: HWEventListener.h:65
llvm::mca::HWEventListener::onCycleBegin
virtual void onCycleBegin()
Definition: HWEventListener.h:163
llvm::mca::HWEventListener::onResourceAvailable
virtual void onResourceAvailable(const ResourceRef &RRef)
Definition: HWEventListener.h:170
llvm::mca::HWStallEvent::HWStallEvent
HWStallEvent(unsigned type, const InstRef &Inst)
Definition: HWEventListener.h:122
llvm::mca::HWInstructionDispatchedEvent::HWInstructionDispatchedEvent
HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef< unsigned > Regs, unsigned UOps)
Definition: HWEventListener.h:75
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::mca::HWStallEvent::RegisterFileStall
@ RegisterFileStall
Definition: HWEventListener.h:111
llvm::mca::HWEventListener::onReleasedBuffers
virtual void onReleasedBuffers(const InstRef &Inst, ArrayRef< unsigned > Buffers)
Definition: HWEventListener.h:176
llvm::mca::HWInstructionEvent::Dispatched
@ Dispatched
Definition: HWEventListener.h:47
llvm::mca::HWStallEvent::StoreQueueFull
@ StoreQueueFull
Definition: HWEventListener.h:117
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::mca::ResourceRef
std::pair< uint64_t, uint64_t > ResourceRef
A resource unit identifier.
Definition: ResourceManager.h:297
Instruction.h
llvm::mca::HWInstructionEvent::Type
const unsigned Type
Definition: HWEventListener.h:56
llvm::mca::HWEventListener::onCycleEnd
virtual void onCycleEnd()
Definition: HWEventListener.h:164
llvm::mca::HWInstructionEvent::IR
const InstRef & IR
Definition: HWEventListener.h:59
llvm::mca::HWInstructionEvent::Issued
@ Issued
Definition: HWEventListener.h:44
llvm::mca::HWStallEvent::DispatchGroupStall
@ DispatchGroupStall
Definition: HWEventListener.h:114
llvm::mca::HWStallEvent::LastGenericEvent
@ LastGenericEvent
Definition: HWEventListener.h:119
llvm::mca::HWInstructionIssuedEvent::HWInstructionIssuedEvent
HWInstructionIssuedEvent(const InstRef &IR, ArrayRef< ResourceUse > UR)
Definition: HWEventListener.h:67
llvm::mca::HWInstructionIssuedEvent::UsedResources
ArrayRef< ResourceUse > UsedResources
Definition: HWEventListener.h:70
llvm::mca::HWPressureEvent
Definition: HWEventListener.h:133
llvm::mca::HWInstructionRetiredEvent::HWInstructionRetiredEvent
HWInstructionRetiredEvent(const InstRef &IR, ArrayRef< unsigned > Regs)
Definition: HWEventListener.h:96
llvm::mca::HWInstructionEvent::HWInstructionEvent
HWInstructionEvent(unsigned type, const InstRef &Inst)
Definition: HWEventListener.h:52
llvm::mca::HWStallEvent::GenericEventType
GenericEventType
Definition: HWEventListener.h:108
llvm::mca::HWInstructionDispatchedEvent::UsedPhysRegs
ArrayRef< unsigned > UsedPhysRegs
Definition: HWEventListener.h:81
llvm::mca::HWPressureEvent::AffectedInstructions
ArrayRef< InstRef > AffectedInstructions
Definition: HWEventListener.h:154
llvm::mca::HWStallEvent::SchedulerQueueFull
@ SchedulerQueueFull
Definition: HWEventListener.h:115
llvm::mca::HWPressureEvent::RESOURCES
@ RESOURCES
Definition: HWEventListener.h:139
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::mca::HWInstructionDispatchedEvent::MicroOpcodes
unsigned MicroOpcodes
Definition: HWEventListener.h:91
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWInstructionEvent &Event)
Definition: HWEventListener.h:166
llvm::mca::HWStallEvent::RetireControlUnitStall
@ RetireControlUnitStall
Definition: HWEventListener.h:112
uint64_t
llvm::mca::HWInstructionEvent::Ready
@ Ready
Definition: HWEventListener.h:43
llvm::mca::HWInstructionEvent::Invalid
@ Invalid
Definition: HWEventListener.h:38
llvm::mca::HWEventListener::~HWEventListener
virtual ~HWEventListener()
Definition: HWEventListener.h:179
ArrayRef.h
llvm::mca::HWStallEvent::IR
const InstRef & IR
Definition: HWEventListener.h:128
llvm::mca::HWInstructionEvent::Pending
@ Pending
Definition: HWEventListener.h:42
llvm::mca::HWInstructionEvent
Definition: HWEventListener.h:27
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:686
llvm::mca::HWInstructionEvent::GenericEventType
GenericEventType
Definition: HWEventListener.h:37
llvm::ArrayRef< ResourceUse >
llvm::mca::HWStallEvent::LoadQueueFull
@ LoadQueueFull
Definition: HWEventListener.h:116
llvm::mca::HWPressureEvent::HWPressureEvent
HWPressureEvent(GenericReason reason, ArrayRef< InstRef > Insts, uint64_t Mask=0)
Definition: HWEventListener.h:146
llvm::mca::HWStallEvent::Type
const unsigned Type
Definition: HWEventListener.h:125
llvm::mca::HWInstructionRetiredEvent
Definition: HWEventListener.h:94
llvm::mca::ResourceUse
std::pair< ResourceRef, ResourceCycles > ResourceUse
Definition: HWEventListener.h:63
llvm::mca::HWPressureEvent::INVALID
@ INVALID
Definition: HWEventListener.h:136
llvm::mca::HWStallEvent
Definition: HWEventListener.h:106
llvm::mca::HWPressureEvent::ResourceMask
const uint64_t ResourceMask
Definition: HWEventListener.h:157
llvm::mca::HWPressureEvent::MEMORY_DEPS
@ MEMORY_DEPS
Definition: HWEventListener.h:143
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWPressureEvent &Event)
Definition: HWEventListener.h:168
llvm::mca::HWStallEvent::Invalid
@ Invalid
Definition: HWEventListener.h:109
llvm::mca::HWInstructionEvent::LastGenericEventType
@ LastGenericEventType
Definition: HWEventListener.h:49
llvm::mca::HWEventListener
Definition: HWEventListener.h:160
llvm::mca::HWPressureEvent::REGISTER_DEPS
@ REGISTER_DEPS
Definition: HWEventListener.h:141
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWStallEvent &Event)
Definition: HWEventListener.h:167
llvm::mca::HWInstructionRetiredEvent::FreedPhysRegs
ArrayRef< unsigned > FreedPhysRegs
Definition: HWEventListener.h:101
Support.h
llvm::mca::HWInstructionEvent::Executed
@ Executed
Definition: HWEventListener.h:45
llvm::mca::HWPressureEvent::Reason
GenericReason Reason
Definition: HWEventListener.h:151
llvm::mca::HWInstructionDispatchedEvent
Definition: HWEventListener.h:73
llvm::mca::HWInstructionEvent::Retired
@ Retired
Definition: HWEventListener.h:40