LLVM 19.0.0git
Classes | Namespaces | Macros | Enumerations | Functions
RISCVISelLowering.h File Reference
#include "RISCV.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
#include <optional>
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Classes

class  llvm::RISCVTargetLowering
 
class  llvm::RVVArgDispatcher
 As per the spec, the rules for passing vector arguments are as follows: More...
 
struct  llvm::RVVArgDispatcher::RVVArgInfo
 
struct  llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCVISD
 
namespace  llvm::RISCV
 
namespace  llvm::RISCVVIntrinsicsTable
 

Macros

#define GET_RISCVVIntrinsicsTable_DECL
 

Enumerations

enum  llvm::RISCVISD::NodeType : unsigned {
  llvm::RISCVISD::FIRST_NUMBER = ISD::BUILTIN_OP_END , llvm::RISCVISD::RET_GLUE , llvm::RISCVISD::SRET_GLUE , llvm::RISCVISD::MRET_GLUE ,
  llvm::RISCVISD::CALL , llvm::RISCVISD::SELECT_CC , llvm::RISCVISD::BR_CC , llvm::RISCVISD::BuildPairF64 ,
  llvm::RISCVISD::SplitF64 , llvm::RISCVISD::TAIL , llvm::RISCVISD::ADD_LO , llvm::RISCVISD::HI ,
  llvm::RISCVISD::LLA , llvm::RISCVISD::ADD_TPREL , llvm::RISCVISD::MULHSU , llvm::RISCVISD::SLLW ,
  llvm::RISCVISD::SRAW , llvm::RISCVISD::SRLW , llvm::RISCVISD::DIVW , llvm::RISCVISD::DIVUW ,
  llvm::RISCVISD::REMUW , llvm::RISCVISD::ROLW , llvm::RISCVISD::RORW , llvm::RISCVISD::CLZW ,
  llvm::RISCVISD::CTZW , llvm::RISCVISD::ABSW , llvm::RISCVISD::FMV_H_X , llvm::RISCVISD::FMV_X_ANYEXTH ,
  llvm::RISCVISD::FMV_X_SIGNEXTH , llvm::RISCVISD::FMV_W_X_RV64 , llvm::RISCVISD::FMV_X_ANYEXTW_RV64 , llvm::RISCVISD::FCVT_X ,
  llvm::RISCVISD::FCVT_XU , llvm::RISCVISD::FCVT_W_RV64 , llvm::RISCVISD::FCVT_WU_RV64 , llvm::RISCVISD::FP_ROUND_BF16 ,
  llvm::RISCVISD::FP_EXTEND_BF16 , llvm::RISCVISD::FROUND , llvm::RISCVISD::FCLASS , llvm::RISCVISD::FMAX ,
  llvm::RISCVISD::FMIN , llvm::RISCVISD::READ_COUNTER_WIDE , llvm::RISCVISD::BREV8 , llvm::RISCVISD::ORC_B ,
  llvm::RISCVISD::ZIP , llvm::RISCVISD::UNZIP , llvm::RISCVISD::CLMUL , llvm::RISCVISD::CLMULH ,
  llvm::RISCVISD::CLMULR , llvm::RISCVISD::SHA256SIG0 , llvm::RISCVISD::SHA256SIG1 , llvm::RISCVISD::SHA256SUM0 ,
  llvm::RISCVISD::SHA256SUM1 , llvm::RISCVISD::SM4KS , llvm::RISCVISD::SM4ED , llvm::RISCVISD::SM3P0 ,
  llvm::RISCVISD::SM3P1 , llvm::RISCVISD::MOPR , llvm::RISCVISD::MOPRR , llvm::RISCVISD::FIRST_VL_VECTOR_OP ,
  llvm::RISCVISD::VMV_V_V_VL = FIRST_VL_VECTOR_OP , llvm::RISCVISD::VMV_V_X_VL , llvm::RISCVISD::VFMV_V_F_VL , llvm::RISCVISD::VMV_X_S ,
  llvm::RISCVISD::VMV_S_X_VL , llvm::RISCVISD::VFMV_S_F_VL , llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL , llvm::RISCVISD::TRUNCATE_VECTOR_VL ,
  llvm::RISCVISD::VSLIDEUP_VL , llvm::RISCVISD::VSLIDEDOWN_VL , llvm::RISCVISD::VSLIDE1UP_VL , llvm::RISCVISD::VSLIDE1DOWN_VL ,
  llvm::RISCVISD::VFSLIDE1UP_VL , llvm::RISCVISD::VFSLIDE1DOWN_VL , llvm::RISCVISD::VID_VL , llvm::RISCVISD::VFNCVT_ROD_VL ,
  llvm::RISCVISD::VECREDUCE_ADD_VL , llvm::RISCVISD::VECREDUCE_UMAX_VL , llvm::RISCVISD::VECREDUCE_SMAX_VL , llvm::RISCVISD::VECREDUCE_UMIN_VL ,
  llvm::RISCVISD::VECREDUCE_SMIN_VL , llvm::RISCVISD::VECREDUCE_AND_VL , llvm::RISCVISD::VECREDUCE_OR_VL , llvm::RISCVISD::VECREDUCE_XOR_VL ,
  llvm::RISCVISD::VECREDUCE_FADD_VL , llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL , llvm::RISCVISD::VECREDUCE_FMIN_VL , llvm::RISCVISD::VECREDUCE_FMAX_VL ,
  llvm::RISCVISD::ADD_VL , llvm::RISCVISD::AND_VL , llvm::RISCVISD::MUL_VL , llvm::RISCVISD::OR_VL ,
  llvm::RISCVISD::SDIV_VL , llvm::RISCVISD::SHL_VL , llvm::RISCVISD::SREM_VL , llvm::RISCVISD::SRA_VL ,
  llvm::RISCVISD::SRL_VL , llvm::RISCVISD::ROTL_VL , llvm::RISCVISD::ROTR_VL , llvm::RISCVISD::SUB_VL ,
  llvm::RISCVISD::UDIV_VL , llvm::RISCVISD::UREM_VL , llvm::RISCVISD::XOR_VL , llvm::RISCVISD::SMIN_VL ,
  llvm::RISCVISD::SMAX_VL , llvm::RISCVISD::UMIN_VL , llvm::RISCVISD::UMAX_VL , llvm::RISCVISD::BITREVERSE_VL ,
  llvm::RISCVISD::BSWAP_VL , llvm::RISCVISD::CTLZ_VL , llvm::RISCVISD::CTTZ_VL , llvm::RISCVISD::CTPOP_VL ,
  llvm::RISCVISD::SADDSAT_VL , llvm::RISCVISD::UADDSAT_VL , llvm::RISCVISD::SSUBSAT_VL , llvm::RISCVISD::USUBSAT_VL ,
  llvm::RISCVISD::AVGFLOORU_VL , llvm::RISCVISD::AVGCEILU_VL , llvm::RISCVISD::MULHS_VL , llvm::RISCVISD::MULHU_VL ,
  llvm::RISCVISD::FADD_VL , llvm::RISCVISD::FSUB_VL , llvm::RISCVISD::FMUL_VL , llvm::RISCVISD::FDIV_VL ,
  llvm::RISCVISD::VFMIN_VL , llvm::RISCVISD::VFMAX_VL , llvm::RISCVISD::FNEG_VL , llvm::RISCVISD::FABS_VL ,
  llvm::RISCVISD::FSQRT_VL , llvm::RISCVISD::FCLASS_VL , llvm::RISCVISD::FCOPYSIGN_VL , llvm::RISCVISD::VFCVT_RTZ_X_F_VL ,
  llvm::RISCVISD::VFCVT_RTZ_XU_F_VL , llvm::RISCVISD::VFCVT_X_F_VL , llvm::RISCVISD::VFCVT_XU_F_VL , llvm::RISCVISD::VFROUND_NOEXCEPT_VL ,
  llvm::RISCVISD::VFCVT_RM_X_F_VL , llvm::RISCVISD::VFCVT_RM_XU_F_VL , llvm::RISCVISD::SINT_TO_FP_VL , llvm::RISCVISD::UINT_TO_FP_VL ,
  llvm::RISCVISD::VFCVT_RM_F_X_VL , llvm::RISCVISD::VFCVT_RM_F_XU_VL , llvm::RISCVISD::FP_ROUND_VL , llvm::RISCVISD::FP_EXTEND_VL ,
  llvm::RISCVISD::VFMADD_VL , llvm::RISCVISD::VFNMADD_VL , llvm::RISCVISD::VFMSUB_VL , llvm::RISCVISD::VFNMSUB_VL ,
  llvm::RISCVISD::VFWMADD_VL , llvm::RISCVISD::VFWNMADD_VL , llvm::RISCVISD::VFWMSUB_VL , llvm::RISCVISD::VFWNMSUB_VL ,
  llvm::RISCVISD::VWMUL_VL , llvm::RISCVISD::VWMULU_VL , llvm::RISCVISD::VWMULSU_VL , llvm::RISCVISD::VWADD_VL ,
  llvm::RISCVISD::VWADDU_VL , llvm::RISCVISD::VWSUB_VL , llvm::RISCVISD::VWSUBU_VL , llvm::RISCVISD::VWADD_W_VL ,
  llvm::RISCVISD::VWADDU_W_VL , llvm::RISCVISD::VWSUB_W_VL , llvm::RISCVISD::VWSUBU_W_VL , llvm::RISCVISD::VWSLL_VL ,
  llvm::RISCVISD::VFWMUL_VL , llvm::RISCVISD::VFWADD_VL , llvm::RISCVISD::VFWSUB_VL , llvm::RISCVISD::VFWADD_W_VL ,
  llvm::RISCVISD::VFWSUB_W_VL , llvm::RISCVISD::VWMACC_VL , llvm::RISCVISD::VWMACCU_VL , llvm::RISCVISD::VWMACCSU_VL ,
  llvm::RISCVISD::VNSRL_VL , llvm::RISCVISD::SETCC_VL , llvm::RISCVISD::VMERGE_VL , llvm::RISCVISD::VMAND_VL ,
  llvm::RISCVISD::VMOR_VL , llvm::RISCVISD::VMXOR_VL , llvm::RISCVISD::VMCLR_VL , llvm::RISCVISD::VMSET_VL ,
  llvm::RISCVISD::VRGATHER_VX_VL , llvm::RISCVISD::VRGATHER_VV_VL , llvm::RISCVISD::VRGATHEREI16_VV_VL , llvm::RISCVISD::VSEXT_VL ,
  llvm::RISCVISD::VZEXT_VL , llvm::RISCVISD::VCPOP_VL , llvm::RISCVISD::VFIRST_VL , llvm::RISCVISD::LAST_VL_VECTOR_OP = VFIRST_VL ,
  llvm::RISCVISD::READ_VLENB , llvm::RISCVISD::READ_CSR , llvm::RISCVISD::WRITE_CSR , llvm::RISCVISD::SWAP_CSR ,
  llvm::RISCVISD::CZERO_EQZ , llvm::RISCVISD::CZERO_NEZ , llvm::RISCVISD::STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE , llvm::RISCVISD::STRICT_FCVT_WU_RV64 ,
  llvm::RISCVISD::STRICT_FADD_VL , llvm::RISCVISD::STRICT_FSUB_VL , llvm::RISCVISD::STRICT_FMUL_VL , llvm::RISCVISD::STRICT_FDIV_VL ,
  llvm::RISCVISD::STRICT_FSQRT_VL , llvm::RISCVISD::STRICT_VFMADD_VL , llvm::RISCVISD::STRICT_VFNMADD_VL , llvm::RISCVISD::STRICT_VFMSUB_VL ,
  llvm::RISCVISD::STRICT_VFNMSUB_VL , llvm::RISCVISD::STRICT_FP_ROUND_VL , llvm::RISCVISD::STRICT_FP_EXTEND_VL , llvm::RISCVISD::STRICT_VFNCVT_ROD_VL ,
  llvm::RISCVISD::STRICT_SINT_TO_FP_VL , llvm::RISCVISD::STRICT_UINT_TO_FP_VL , llvm::RISCVISD::STRICT_VFCVT_RM_X_F_VL , llvm::RISCVISD::STRICT_VFCVT_RTZ_X_F_VL ,
  llvm::RISCVISD::STRICT_VFCVT_RTZ_XU_F_VL , llvm::RISCVISD::STRICT_FSETCC_VL , llvm::RISCVISD::STRICT_FSETCCS_VL , llvm::RISCVISD::STRICT_VFROUND_NOEXCEPT_VL ,
  llvm::RISCVISD::LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL , llvm::RISCVISD::SF_VC_XV_SE , llvm::RISCVISD::SF_VC_IV_SE , llvm::RISCVISD::SF_VC_VV_SE ,
  llvm::RISCVISD::SF_VC_FV_SE , llvm::RISCVISD::SF_VC_XVV_SE , llvm::RISCVISD::SF_VC_IVV_SE , llvm::RISCVISD::SF_VC_VVV_SE ,
  llvm::RISCVISD::SF_VC_FVV_SE , llvm::RISCVISD::SF_VC_XVW_SE , llvm::RISCVISD::SF_VC_IVW_SE , llvm::RISCVISD::SF_VC_VVW_SE ,
  llvm::RISCVISD::SF_VC_FVW_SE , llvm::RISCVISD::SF_VC_V_X_SE , llvm::RISCVISD::SF_VC_V_I_SE , llvm::RISCVISD::SF_VC_V_XV_SE ,
  llvm::RISCVISD::SF_VC_V_IV_SE , llvm::RISCVISD::SF_VC_V_VV_SE , llvm::RISCVISD::SF_VC_V_FV_SE , llvm::RISCVISD::SF_VC_V_XVV_SE ,
  llvm::RISCVISD::SF_VC_V_IVV_SE , llvm::RISCVISD::SF_VC_V_VVV_SE , llvm::RISCVISD::SF_VC_V_FVV_SE , llvm::RISCVISD::SF_VC_V_XVW_SE ,
  llvm::RISCVISD::SF_VC_V_IVW_SE , llvm::RISCVISD::SF_VC_V_VVW_SE , llvm::RISCVISD::SF_VC_V_FVW_SE , llvm::RISCVISD::TH_LWD = ISD::FIRST_TARGET_MEMORY_OPCODE ,
  llvm::RISCVISD::TH_LWUD , llvm::RISCVISD::TH_LDD , llvm::RISCVISD::TH_SWD , llvm::RISCVISD::TH_SDD
}
 

Functions

bool llvm::RISCV::CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
 
bool llvm::RISCV::CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
 
bool llvm::RISCV::CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
ArrayRef< MCPhysReg > llvm::RISCV::getArgGPRs (const RISCVABI::ABI ABI)
 

Macro Definition Documentation

◆ GET_RISCVVIntrinsicsTable_DECL

#define GET_RISCVVIntrinsicsTable_DECL

Definition at line 1113 of file RISCVISelLowering.h.

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