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RISCVISelLowering.h
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1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
21#include <optional>
22
23namespace llvm {
24class InstructionCost;
25class RISCVSubtarget;
26struct RISCVRegisterInfo;
27class RVVArgDispatcher;
28
29namespace RISCVISD {
30// clang-format off
31enum NodeType : unsigned {
37 /// Select with condition operator - This selects between a true value and
38 /// a false value (ops #3 and #4) based on the boolean result of comparing
39 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
40 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
41 /// The lhs and rhs are XLenVT integers. The true and false values can be
42 /// integer or floating point.
48
49 // Add the Lo 12 bits from an address. Selected to ADDI.
51 // Get the Hi 20 bits from an address. Selected to LUI.
53
54 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
56
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
59
60 // Multiply high for signedxunsigned.
62
63 // Represents (ADD (SHL a, b), c) with the arguments appearing in the order
64 // a, b, c. 'b' must be a constant. Maps to sh1add/sh2add/sh3add with zba
65 // or addsl with XTheadBa.
67
68 // RV64I shifts, directly matching the semantics of the named RISC-V
69 // instructions.
73 // 32-bit operations from RV64M that can't be simply matched with a pattern
74 // at instruction selection time. These have undefined behavior for division
75 // by 0 or overflow (divw) like their target independent counterparts.
79 // RV64IB rotates, directly matching the semantics of the named RISC-V
80 // instructions.
83 // RV64IZbb bit counting instructions directly matching the semantics of the
84 // named RISC-V instructions.
87
88 // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
90
91 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
92 // XLEN is the only legal integer width.
93 //
94 // FMV_H_X matches the semantics of the FMV.H.X.
95 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
96 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
97 // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
98 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
99 //
100 // This is a more convenient semantic for producing dagcombines that remove
101 // unnecessary GPR->FPR->GPR moves.
107 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
108 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
109 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
110 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
113 // FP to 32 bit int conversions for RV64. These are used to keep track of the
114 // result being sign extended to 64 bit. These saturate out of range inputs.
115 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
116 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
119
122
123 // Rounds an FP value to its corresponding integer in the same FP format.
124 // First operand is the value to round, the second operand is the largest
125 // integer that can be represented exactly in the FP format. This will be
126 // expanded into multiple instructions and basic blocks with a custom
127 // inserter.
129
131
132 // Floating point fmax and fmin matching the RISC-V instruction semantics.
134
135 // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
136 // It takes a chain operand and another two target constant operands (the
137 // CSR numbers of the low and high parts of the counter).
139
140 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
141 // XLenVT.
146
147 // Scalar cryptography
152
153 // May-Be-Operations
155
156 // Vector Extension
158 // VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
159 // for the VL value to be used for the operation. The first operand is
160 // passthru operand.
162 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
163 // for the VL value to be used for the operation. The first operand is
164 // passthru operand.
166 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
167 // for the VL value to be used for the operation. The first operand is
168 // passthru operand.
170 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
171 // extended from the vector element size.
173 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
175 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
177 // Splats an 64-bit value that has been split into two i32 parts. This is
178 // expanded late to two scalar stores and a stride 0 vector load.
179 // The first operand is passthru operand.
181 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
182 // mask and VL operand.
184 // Matches the semantics of vslideup/vslidedown. The first operand is the
185 // pass-thru operand, the second is the source vector, the third is the XLenVT
186 // index (either constant or non-constant), the fourth is the mask, the fifth
187 // is the VL and the sixth is the policy.
190 // Matches the semantics of vslide1up/slide1down. The first operand is
191 // passthru operand, the second is source vector, third is the XLenVT scalar
192 // value. The fourth and fifth operands are the mask and VL operands.
195 // Matches the semantics of vfslide1up/vfslide1down. The first operand is
196 // passthru operand, the second is source vector, third is a scalar value
197 // whose type matches the element type of the vectors. The fourth and fifth
198 // operands are the mask and VL operands.
201 // Matches the semantics of the vid.v instruction, with a mask and VL
202 // operand.
204 // Matches the semantics of the vfcnvt.rod function (Convert double-width
205 // float to single-width float, rounding towards odd). Takes a double-width
206 // float vector and produces a single-width float vector. Also has a mask and
207 // VL operand.
209 // These nodes match the semantics of the corresponding RVV vector reduction
210 // instructions. They produce a vector result which is the reduction
211 // performed over the second vector operand plus the first element of the
212 // third vector operand. The first operand is the pass-thru operand. The
213 // second operand is an unconstrained vector type, and the result, first, and
214 // third operand's types are expected to be the corresponding full-width
215 // LMUL=1 type for the second operand:
216 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
217 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
218 // The different in types does introduce extra vsetvli instructions but
219 // similarly it reduces the number of registers consumed per reduction.
220 // Also has a mask and VL operand.
233
234 // Vector binary ops with a merge as a third operand, a mask as a fourth
235 // operand, and VL as a fifth operand.
255
261
266
267 // Averaging adds of signed integers.
269 // Averaging adds of unsigned integers.
271 // Rounding averaging adds of signed integers.
273 // Rounding averaging adds of unsigned integers.
275
276 // Operands are (source, shift, merge, mask, roundmode, vl)
279
288
289 // Vector unary ops with a mask as a second operand and VL as a third operand.
294 FCOPYSIGN_VL, // Has a merge operand
300 VFCVT_RM_X_F_VL, // Has a rounding mode operand.
301 VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
304 VFCVT_RM_F_X_VL, // Has a rounding mode operand.
305 VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
308
309 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
314
315 // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth
316 // operand.
321
322 // Widening instructions with a merge value a third operand, a mask as a
323 // fourth operand, and VL as a fifth operand.
336
342
343 // Widening ternary operations with a mask as the fourth operand and VL as the
344 // fifth operand.
348
349 // Narrowing logical shift right.
350 // Operands are (source, shift, passthru, mask, vl)
352
353 // Vector compare producing a mask. Fourth operand is input mask. Fifth
354 // operand is VL.
356
357 // General vmerge node with mask, true, false, passthru, and vl operands.
358 // Tail agnostic vselect can be implemented by setting passthru to undef.
360
361 // Mask binary operators.
365
366 // Set mask vector to all zeros or ones.
369
370 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
371 // for passthru and VL. Operands are (src, index, mask, passthru, vl).
375
376 // Vector sign/zero extend with additional mask & VL operands.
379
380 // vcpop.m with additional mask and VL operands.
382
383 // vfirst.m with additional mask and VL operands.
385
387
388 // Read VLENB CSR
390 // Reads value of CSR.
391 // The first operand is a chain pointer. The second specifies address of the
392 // required CSR. Two results are produced, the read value and the new chain
393 // pointer.
395 // Write value to CSR.
396 // The first operand is a chain pointer, the second specifies address of the
397 // required CSR and the third is the value to write. The result is the new
398 // chain pointer.
400 // Read and write value of CSR.
401 // The first operand is a chain pointer, the second specifies address of the
402 // required CSR and the third is the value to write. Two results are produced,
403 // the value read before the modification and the new chain pointer.
405
406 // Branchless select operations, matching the semantics of the instructions
407 // defined in Zicond or XVentanaCondOps.
408 CZERO_EQZ, // vt.maskc for XVentanaCondOps.
409 CZERO_NEZ, // vt.maskcn for XVentanaCondOps.
410
411 /// Software guarded BRIND node. Operand 0 is the chain operand and
412 /// operand 1 is the target address.
414
415 // FP to 32 bit int conversions for RV64. These are used to keep track of the
416 // result being sign extended to 64 bit. These saturate out of range inputs.
440
467
468 // WARNING: Do not add anything in the end unless you want the node to
469 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
470 // opcodes will be thought as target memory ops!
471
477};
478// clang-format on
479} // namespace RISCVISD
480
482 const RISCVSubtarget &Subtarget;
483
484public:
485 explicit RISCVTargetLowering(const TargetMachine &TM,
486 const RISCVSubtarget &STI);
487
488 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
489
490 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
491 MachineFunction &MF,
492 unsigned Intrinsic) const override;
493 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
494 unsigned AS,
495 Instruction *I = nullptr) const override;
496 bool isLegalICmpImmediate(int64_t Imm) const override;
497 bool isLegalAddImmediate(int64_t Imm) const override;
498 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
499 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
500 bool isZExtFree(SDValue Val, EVT VT2) const override;
501 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
502 bool signExtendConstant(const ConstantInt *CI) const override;
503 bool isCheapToSpeculateCttz(Type *Ty) const override;
504 bool isCheapToSpeculateCtlz(Type *Ty) const override;
505 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
506 bool hasAndNotCompare(SDValue Y) const override;
507 bool hasBitTest(SDValue X, SDValue Y) const override;
510 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
511 SelectionDAG &DAG) const override;
512 /// Return true if the (vector) instruction I will be lowered to an instruction
513 /// with a scalar splat operand for the given Operand number.
514 bool canSplatOperand(Instruction *I, int Operand) const;
515 /// Return true if a vector instruction will lower to a target instruction
516 /// able to splat the given operand.
517 bool canSplatOperand(unsigned Opcode, int Operand) const;
519 SmallVectorImpl<Use *> &Ops) const override;
520 bool shouldScalarizeBinop(SDValue VecOp) const override;
521 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
522 std::pair<int, bool> getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
523 bool isFPImmLegal(const APFloat &Imm, EVT VT,
524 bool ForCodeSize) const override;
525 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
526 unsigned Index) const override;
527
528 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
529
530 bool preferScalarizeSplat(SDNode *N) const override;
531
532 bool softPromoteHalfType() const override { return true; }
533
534 /// Return the register type for a given MVT, ensuring vectors are treated
535 /// as a series of gpr sized integers.
537 EVT VT) const override;
538
539 /// Return the number of registers for a given MVT, ensuring vectors are
540 /// treated as a series of gpr sized integers.
543 EVT VT) const override;
544
547 EVT &IntermediateVT,
548 unsigned &NumIntermediates,
549 MVT &RegisterVT) const override;
550
551 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
552 EVT VT) const override;
553
554 /// Return true if the given shuffle mask can be codegen'd directly, or if it
555 /// should be stack expanded.
556 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
557
558 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
559 // If the pair to store is a mixture of float and int values, we will
560 // save two bitwise instructions and one float-to-int instruction and
561 // increase one store instruction. There is potentially a more
562 // significant benefit because it avoids the float->int domain switch
563 // for input value. So It is more likely a win.
564 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
565 (LTy.isInteger() && HTy.isFloatingPoint()))
566 return true;
567 // If the pair only contains int values, we will save two bitwise
568 // instructions and increase one store instruction (costing one more
569 // store buffer). Since the benefit is more blurred we leave such a pair
570 // out until we get testcase to prove it is a win.
571 return false;
572 }
573
574 bool
576 unsigned DefinedValues) const override;
577
578 bool shouldExpandCttzElements(EVT VT) const override;
579
580 /// Return the cost of LMUL for linear operations.
582
587
588 // Provide custom lowering hooks for some operations.
589 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
591 SelectionDAG &DAG) const override;
592
593 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
594
596 const APInt &DemandedElts,
597 TargetLoweringOpt &TLO) const override;
598
600 KnownBits &Known,
601 const APInt &DemandedElts,
602 const SelectionDAG &DAG,
603 unsigned Depth) const override;
605 const APInt &DemandedElts,
606 const SelectionDAG &DAG,
607 unsigned Depth) const override;
608
610 const APInt &DemandedElts,
611 const SelectionDAG &DAG,
612 bool PoisonOnly, bool ConsiderFlags,
613 unsigned Depth) const override;
614
615 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
616
617 // This method returns the name of a target specific DAG node.
618 const char *getTargetNodeName(unsigned Opcode) const override;
619
621 getTargetMMOFlags(const Instruction &I) const override;
622
624 getTargetMMOFlags(const MemSDNode &Node) const override;
625
626 bool
628 const MemSDNode &NodeY) const override;
629
630 ConstraintType getConstraintType(StringRef Constraint) const override;
631
633 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
634
635 std::pair<unsigned, const TargetRegisterClass *>
637 StringRef Constraint, MVT VT) const override;
638
640 std::vector<SDValue> &Ops,
641 SelectionDAG &DAG) const override;
642
645 MachineBasicBlock *BB) const override;
646
648 SDNode *Node) const override;
649
651 EVT VT) const override;
652
653 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
654 bool MathUsed) const override {
655 if (VT == MVT::i8 || VT == MVT::i16)
656 return false;
657
658 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
659 }
660
661 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
662 unsigned AddrSpace) const override {
663 // If we can replace 4 or more scalar stores, there will be a reduction
664 // in instructions even after we add a vector constant load.
665 return NumElem >= 4;
666 }
667
668 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
669 return VT.isScalarInteger();
670 }
671 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
672
673 bool isCtpopFast(EVT VT) const override;
674
675 unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
676
677 bool preferZeroCompareBranch() const override { return true; }
678
679 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
680 return isa<LoadInst>(I) || isa<StoreInst>(I);
681 }
683 AtomicOrdering Ord) const override;
685 AtomicOrdering Ord) const override;
686
688 EVT VT) const override;
689
691 return ISD::SIGN_EXTEND;
692 }
693
695
697 unsigned KeptBits) const override;
698
701 unsigned ExpansionFactor) const override {
705 ExpansionFactor);
706 }
707
709 CombineLevel Level) const override;
710
711 /// If a physical register, this returns the register that receives the
712 /// exception address on entry to an EH pad.
714 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
715
716 /// If a physical register, this returns the register that receives the
717 /// exception typeid on entry to a landing pad.
719 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
720
721 bool shouldExtendTypeInLibCall(EVT Type) const override;
722 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
723
724 /// Returns the register with the specified architectural or ABI name. This
725 /// method is necessary to lower the llvm.read_register.* and
726 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
727 /// with the clang -ffixed-xX flag for access to be allowed.
728 Register getRegisterByName(const char *RegName, LLT VT,
729 const MachineFunction &MF) const override;
730
731 // Lower incoming arguments, copy physregs into vregs
733 bool IsVarArg,
735 const SDLoc &DL, SelectionDAG &DAG,
736 SmallVectorImpl<SDValue> &InVals) const override;
738 bool IsVarArg,
740 LLVMContext &Context) const override;
741 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
743 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
744 SelectionDAG &DAG) const override;
746 SmallVectorImpl<SDValue> &InVals) const override;
747
749 Type *Ty) const override;
750 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
751 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
752 bool shouldConsiderGEPOffsetSplit() const override { return true; }
753
754 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
755 SDValue C) const override;
756
758 SDValue ConstNode) const override;
759
761 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
763 Value *AlignedAddr, Value *Incr,
764 Value *Mask, Value *ShiftAmt,
765 AtomicOrdering Ord) const override;
770 Value *AlignedAddr, Value *CmpVal,
771 Value *NewVal, Value *Mask,
772 AtomicOrdering Ord) const override;
773
774 /// Returns true if the target allows unaligned memory accesses of the
775 /// specified type.
777 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
779 unsigned *Fast = nullptr) const override;
780
782 const AttributeList &FuncAttributes) const override;
783
785 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
786 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
787 const override;
788
790 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
791 unsigned NumParts, MVT PartVT, EVT ValueVT,
792 std::optional<CallingConv::ID> CC) const override;
793
794 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
795 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
796
797 static RISCVII::VLMUL getLMUL(MVT VT);
798 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
799 unsigned MinSize) {
800 // Original equation:
801 // VLMAX = (VectorBits / EltSize) * LMUL
802 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
803 // The following equations have been reordered to prevent loss of precision
804 // when calculating fractional LMUL.
805 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
806 }
807
808 // Return inclusive (low, high) bounds on the value of VLMAX for the
809 // given scalable container type given known bounds on VLEN.
810 static std::pair<unsigned, unsigned>
811 computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget);
812
813 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
814 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
815 static unsigned getRegClassIDForVecVT(MVT VT);
816 static std::pair<unsigned, unsigned>
818 unsigned InsertExtractIdx,
819 const RISCVRegisterInfo *TRI);
821
822 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
823
824 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
825
826 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
827
828 unsigned getJumpTableEncoding() const override;
829
831 const MachineBasicBlock *MBB,
832 unsigned uid,
833 MCContext &Ctx) const override;
834
835 bool isVScaleKnownToBeAPowerOfTwo() const override;
836
838 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
841 SelectionDAG &DAG) const override;
844 SelectionDAG &DAG) const override;
845
847 uint64_t ElemSize) const override {
848 // Scaled addressing not supported on indexed load/stores
849 return Scale == 1;
850 }
851
852 /// If the target has a standard location for the stack protector cookie,
853 /// returns the address of that location. Otherwise, returns nullptr.
854 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
855
856 /// Returns whether or not generating a interleaved load/store intrinsic for
857 /// this type will be legal.
858 bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
859 Align Alignment, unsigned AddrSpace,
860 const DataLayout &) const;
861
862 /// Return true if a stride load store of the given result type and
863 /// alignment is legal.
864 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
865
866 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
867
868 bool fallBackToDAGISel(const Instruction &Inst) const override;
869
872 ArrayRef<unsigned> Indices,
873 unsigned Factor) const override;
874
876 unsigned Factor) const override;
877
879 LoadInst *LI) const override;
880
882 StoreInst *SI) const override;
883
884 bool supportKCFIBundles() const override { return true; }
885
887 int JTI, SelectionDAG &DAG) const override;
888
891 const TargetInstrInfo *TII) const override;
892
893 /// RISCVCCAssignFn - This target-specific function extends the default
894 /// CCValAssign with additional information used to lower RISC-V calling
895 /// conventions.
897 unsigned ValNo, MVT ValVT, MVT LocVT,
898 CCValAssign::LocInfo LocInfo,
899 ISD::ArgFlagsTy ArgFlags, CCState &State,
900 bool IsFixed, bool IsRet, Type *OrigTy,
901 const RISCVTargetLowering &TLI,
902 RVVArgDispatcher &RVVDispatcher);
903
904private:
905 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
906 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
907 RISCVCCAssignFn Fn) const;
908 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
910 bool IsRet, CallLoweringInfo *CLI,
911 RISCVCCAssignFn Fn) const;
912
913 template <class NodeTy>
914 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
915 bool IsExternWeak = false) const;
916 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
917 bool UseGOT) const;
918 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
919 SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
920
921 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
922 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
923 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
924 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
925 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
926 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
927 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
928 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
929 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
930 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
931 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
932 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
933 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
934 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
935 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
936 int64_t ExtTrueVal) const;
937 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
938 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
939 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
940 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
941 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
942 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
943 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
944 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
945 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
946 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
947 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
948 bool IsVP) const;
949 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
950 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
951 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
952 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
953 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
954 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
955 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
956 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
957 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
958 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
959 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
960 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
961 SelectionDAG &DAG) const;
962 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
963 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
964 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
965 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
966 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
967 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
968 SelectionDAG &DAG) const;
969 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
971 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
972 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
973 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
974 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
975 SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
976 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
977 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
978 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
979 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
980 SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
981 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
982 unsigned ExtendOpc) const;
983 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
984 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
985
986 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
987 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
988
989 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
990
991 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
992
993 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
994 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
995
996 bool isEligibleForTailCallOptimization(
997 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
998 const SmallVector<CCValAssign, 16> &ArgLocs) const;
999
1000 /// Generate error diagnostics if any register used by CC has been marked
1001 /// reserved.
1002 void validateCCReservedRegs(
1003 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
1004 MachineFunction &MF) const;
1005
1006 bool useRVVForFixedLengthVectorVT(MVT VT) const;
1007
1008 MVT getVPExplicitVectorLengthTy() const override;
1009
1010 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
1011 bool IsScalable) const override;
1012
1013 /// RVV code generation for fixed length vectors does not lower all
1014 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
1015 /// merge. However, merging them creates a BUILD_VECTOR that is just as
1016 /// illegal as the original, thus leading to an infinite legalisation loop.
1017 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
1018 /// this override can be removed.
1019 bool mergeStoresAfterLegalization(EVT VT) const override;
1020
1021 /// Disable normalizing
1022 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1023 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
1024 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
1025 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
1026 return false;
1027 }
1028
1029 /// For available scheduling models FDIV + two independent FMULs are much
1030 /// faster than two FDIVs.
1031 unsigned combineRepeatedFPDivisors() const override;
1032
1033 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1034 SmallVectorImpl<SDNode *> &Created) const override;
1035
1036 bool shouldFoldSelectWithSingleBitTest(EVT VT,
1037 const APInt &AndMask) const override;
1038
1039 unsigned getMinimumJumpTableEntries() const override;
1040
1041 SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
1042 SDValue End, SDValue Flags, SDLoc DL) const;
1043};
1044
1045/// As per the spec, the rules for passing vector arguments are as follows:
1046///
1047/// 1. For the first vector mask argument, use v0 to pass it.
1048/// 2. For vector data arguments or rest vector mask arguments, starting from
1049/// the v8 register, if a vector register group between v8-v23 that has not been
1050/// allocated can be found and the first register number is a multiple of LMUL,
1051/// then allocate this vector register group to the argument and mark these
1052/// registers as allocated. Otherwise, pass it by reference and are replaced in
1053/// the argument list with the address.
1054/// 3. For tuple vector data arguments, starting from the v8 register, if
1055/// NFIELDS consecutive vector register groups between v8-v23 that have not been
1056/// allocated can be found and the first register number is a multiple of LMUL,
1057/// then allocate these vector register groups to the argument and mark these
1058/// registers as allocated. Otherwise, pass it by reference and are replaced in
1059/// the argument list with the address.
1061public:
1062 static constexpr unsigned NumArgVRs = 16;
1063
1064 struct RVVArgInfo {
1065 unsigned NF;
1067 bool FirstVMask = false;
1068 };
1069
1070 template <typename Arg>
1072 ArrayRef<Arg> ArgList)
1073 : MF(MF), TLI(TLI) {
1074 constructArgInfos(ArgList);
1075 compute();
1076 }
1077
1078 RVVArgDispatcher() = default;
1079
1081
1082private:
1083 SmallVector<RVVArgInfo, 4> RVVArgInfos;
1084 SmallVector<MCPhysReg, 4> AllocatedPhysRegs;
1085
1086 const MachineFunction *MF = nullptr;
1087 const RISCVTargetLowering *TLI = nullptr;
1088
1089 unsigned CurIdx = 0;
1090
1091 template <typename Arg> void constructArgInfos(ArrayRef<Arg> Ret);
1092 void compute();
1093 void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,
1094 unsigned StartReg = 0);
1095};
1096
1097namespace RISCV {
1098
1099bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1100 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1101 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1102 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1103 RVVArgDispatcher &RVVDispatcher);
1104
1105bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1106 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1107 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1108 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1109 RVVArgDispatcher &RVVDispatcher);
1110
1111bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
1112 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
1113 CCState &State);
1114
1116
1117} // end namespace RISCV
1118
1119namespace RISCVVIntrinsicsTable {
1120
1122 unsigned IntrinsicID;
1124 uint8_t VLOperand;
1125 bool hasScalarOperand() const {
1126 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
1127 return ScalarOperand != 0xF;
1128 }
1129 bool hasVLOperand() const {
1130 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
1131 return VLOperand != 0x1F;
1132 }
1133};
1134
1135using namespace RISCV;
1136
1137#define GET_RISCVVIntrinsicsTable_DECL
1138#include "RISCVGenSearchableTables.inc"
1139#undef GET_RISCVVIntrinsicsTable_DECL
1140
1141} // end namespace RISCVVIntrinsicsTable
1142
1143} // end namespace llvm
1144
1145#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Addr
bool End
Definition: ELF_riscv.cpp:480
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:494
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:695
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:685
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:92
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:173
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition: MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
This is an abstract virtual class for memory operations.
static std::pair< unsigned, unsigned > computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget)
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
InstructionCost getVRGatherVVCost(MVT VT) const
Return the cost of a vrgather.vv instruction for the type VT.
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
std::pair< int, bool > getLegalZfaFPImm(const APFloat &Imm, EVT VT) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
const RISCVSubtarget & getSubtarget() const
TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI) const override
Lower an interleave intrinsic to a target specific store intrinsic.
bool preferScalarizeSplat(SDNode *N) const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
InstructionCost getVRGatherVICost(MVT VT) const
Return the cost of a vrgather.vi (or vx) instruction for the type VT.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const override
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
bool shouldExpandCttzElements(EVT VT) const override
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
InstructionCost getLMULCost(MVT VT) const
Return the cost of LMUL for linear operations.
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
InstructionCost getVSlideVICost(MVT VT) const
Return the cost of a vslidedown.vi or vslideup.vi instruction for the type VT.
bool fallBackToDAGISel(const Instruction &Inst) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vlsegN intrinsic.
bool isCtpopFast(EVT VT) const override
Return true if ctpop instruction is fast.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getContainerForFixedLengthVector(MVT VT) const
static unsigned getRegClassIDForVecVT(MVT VT)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
InstructionCost getVSlideVXCost(MVT VT) const
Return the cost of a vslidedown.vx or vslideup.vx instruction for the type VT.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool softPromoteHalfType() const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vssegN intrinsic.
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isLegalElementTypeForRVV(EVT ScalarTy) const
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II, LoadInst *LI) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
static RISCVII::VLMUL getLMUL(MVT VT)
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool shouldConsiderGEPOffsetSplit() const override
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const
Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.
bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override
Return true if Op can create undef or poison from non-undef & non-poison operands.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expansion.
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const
Return true if a stride load store of the given result type and alignment is legal.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
As per the spec, the rules for passing vector arguments are as follows:
static constexpr unsigned NumArgVRs
RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI, ArrayRef< Arg > ArgList)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:481
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:289
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1425
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:782
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1437
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1497
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1431
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1548
@ SW_GUARDED_BRIND
Software guarded BRIND node.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
ArrayRef< MCPhysReg > getArgGPRs(const RISCVABI::ABI ABI)
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static constexpr unsigned RVVBitsPerBlock
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
AtomicOrdering
Atomic ordering for LLVM's memory model.
CombineLevel
Definition: DAGCombine.h:15
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:146
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:156
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:151
This structure contains all information that is necessary for lowering calls.