LLVM  15.0.0git
RISCVISelLowering.h
Go to the documentation of this file.
1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
21 
22 namespace llvm {
23 class RISCVSubtarget;
24 struct RISCVRegisterInfo;
25 namespace RISCVISD {
26 enum NodeType : unsigned {
33  /// Select with condition operator - This selects between a true value and
34  /// a false value (ops #3 and #4) based on the boolean result of comparing
35  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
36  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
37  /// The lhs and rhs are XLenVT integers. The true and false values can be
38  /// integer or floating point.
44  // Multiply high for signedxunsigned.
46  // RV64I shifts, directly matching the semantics of the named RISC-V
47  // instructions.
51  // 32-bit operations from RV64M that can't be simply matched with a pattern
52  // at instruction selection time. These have undefined behavior for division
53  // by 0 or overflow (divw) like their target independent counterparts.
57  // RV64IB rotates, directly matching the semantics of the named RISC-V
58  // instructions.
61  // RV64IZbb bit counting instructions directly matching the semantics of the
62  // named RISC-V instructions.
65  // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
66  // instructions. Operand order is rs1, rs3, rs2/shamt.
67  FSR,
68  FSL,
69  // RV64IB funnel shifts, with the semantics of the named RISC-V instructions.
70  // Operand order is rs1, rs3, rs2/shamt.
73  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
74  // XLEN is the only legal integer width.
75  //
76  // FMV_H_X matches the semantics of the FMV.H.X.
77  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
78  // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
79  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
80  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
81  //
82  // This is a more convenient semantic for producing dagcombines that remove
83  // unnecessary GPR->FPR->GPR moves.
89  // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
90  // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
91  // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
92  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
95  // FP to 32 bit int conversions for RV64. These are used to keep track of the
96  // result being sign extended to 64 bit. These saturate out of range inputs.
97  // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
98  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
101  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
102  // (returns (Lo, Hi)). It takes a chain operand.
104  // Generalized Reverse and Generalized Or-Combine - directly matching the
105  // semantics of the named RISC-V instructions. Lowered as custom nodes as
106  // TableGen chokes when faced with commutative permutations in deeply-nested
107  // DAGs. Each node takes an input operand and a control operand and outputs a
108  // bit-manipulated version of input. All operands are i32 or XLenVT.
117  // Bit Compress/Decompress implement the generic bit extract and bit deposit
118  // functions. This operation is also referred to as bit gather/scatter, bit
119  // pack/unpack, parallel extract/deposit, compress/expand, or right
120  // compress/right expand.
125  // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2
126  // into the value in rs1. The upper bits of rs2 control the length of the bit
127  // field and target position. The layout of rs2 is chosen in a way that makes
128  // it possible to construct rs2 easily using pack[h] instructions and/or
129  // andi/lui.
132  // Vector Extension
133  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
134  // for the VL value to be used for the operation. The first operand is
135  // passthru operand.
137  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
138  // for the VL value to be used for the operation. The first operand is
139  // passthru operand.
141  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
142  // extended from the vector element size.
144  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
146  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
148  // Splats an 64-bit value that has been split into two i32 parts. This is
149  // expanded late to two scalar stores and a stride 0 vector load.
150  // The first operand is passthru operand.
152  // Read VLENB CSR
154  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
155  // mask and VL operand.
157  // Matches the semantics of vslideup/vslidedown. The first operand is the
158  // pass-thru operand, the second is the source vector, the third is the
159  // XLenVT index (either constant or non-constant), the fourth is the mask
160  // and the fifth the VL.
163  // Matches the semantics of vslide1up/slide1down. The first operand is
164  // passthru operand, the second is source vector, third is the XLenVT scalar
165  // value. The fourth and fifth operands are the mask and VL operands.
168  // Matches the semantics of the vid.v instruction, with a mask and VL
169  // operand.
171  // Matches the semantics of the vfcnvt.rod function (Convert double-width
172  // float to single-width float, rounding towards odd). Takes a double-width
173  // float vector and produces a single-width float vector. Also has a mask and
174  // VL operand.
176  // These nodes match the semantics of the corresponding RVV vector reduction
177  // instructions. They produce a vector result which is the reduction
178  // performed over the second vector operand plus the first element of the
179  // third vector operand. The first operand is the pass-thru operand. The
180  // second operand is an unconstrained vector type, and the result, first, and
181  // third operand's types are expected to be the corresponding full-width
182  // LMUL=1 type for the second operand:
183  // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
184  // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
185  // The different in types does introduce extra vsetvli instructions but
186  // similarly it reduces the number of registers consumed per reduction.
187  // Also has a mask and VL operand.
200 
201  // Vector binary and unary ops with a mask as a third operand, and VL as a
202  // fourth operand.
203  // FIXME: Can we replace these with ISD::VP_*?
217 
222 
246 
247  // Widening instructions
259 
260  // Vector compare producing a mask. Fourth operand is input mask. Fifth
261  // operand is VL.
263 
264  // Vector select with an additional VL operand. This operation is unmasked.
266  // Vector select with operand #2 (the value when the condition is false) tied
267  // to the destination and an additional VL operand. This operation is
268  // unmasked.
270 
271  // Mask binary operators.
275 
276  // Set mask vector to all zeros or ones.
279 
280  // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand
281  // for VL.
285 
286  // Vector sign/zero extend with additional mask & VL operands.
289 
290  // vcpop.m with additional mask and VL operands.
292 
293  // Reads value of CSR.
294  // The first operand is a chain pointer. The second specifies address of the
295  // required CSR. Two results are produced, the read value and the new chain
296  // pointer.
298  // Write value to CSR.
299  // The first operand is a chain pointer, the second specifies address of the
300  // required CSR and the third is the value to write. The result is the new
301  // chain pointer.
303  // Read and write value of CSR.
304  // The first operand is a chain pointer, the second specifies address of the
305  // required CSR and the third is the value to write. Two results are produced,
306  // the value read before the modification and the new chain pointer.
308 
309  // FP to 32 bit int conversions for RV64. These are used to keep track of the
310  // result being sign extended to 64 bit. These saturate out of range inputs.
313 
314  // WARNING: Do not add anything in the end unless you want the node to
315  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
316  // opcodes will be thought as target memory ops!
317 };
318 } // namespace RISCVISD
319 
320 namespace RISCV {
321 // We use 64 bits as the known part in the scalable vector types.
322 static constexpr unsigned RVVBitsPerBlock = 64;
323 } // namespace RISCV
324 
326  const RISCVSubtarget &Subtarget;
327 
328 public:
329  explicit RISCVTargetLowering(const TargetMachine &TM,
330  const RISCVSubtarget &STI);
331 
332  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
333 
334  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
335  MachineFunction &MF,
336  unsigned Intrinsic) const override;
337  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
338  unsigned AS,
339  Instruction *I = nullptr) const override;
340  bool isLegalICmpImmediate(int64_t Imm) const override;
341  bool isLegalAddImmediate(int64_t Imm) const override;
342  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
343  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
344  bool isZExtFree(SDValue Val, EVT VT2) const override;
345  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
346  bool signExtendConstant(const ConstantInt *CI) const override;
347  bool isCheapToSpeculateCttz() const override;
348  bool isCheapToSpeculateCtlz() const override;
349  bool hasAndNotCompare(SDValue Y) const override;
350  bool hasBitTest(SDValue X, SDValue Y) const override;
353  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
354  SelectionDAG &DAG) const override;
356  SmallVectorImpl<Use *> &Ops) const override;
357  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
358  bool isFPImmLegal(const APFloat &Imm, EVT VT,
359  bool ForCodeSize) const override;
360 
361  bool softPromoteHalfType() const override { return true; }
362 
363  /// Return the register type for a given MVT, ensuring vectors are treated
364  /// as a series of gpr sized integers.
366  EVT VT) const override;
367 
368  /// Return the number of registers for a given MVT, ensuring vectors are
369  /// treated as a series of gpr sized integers.
371  CallingConv::ID CC,
372  EVT VT) const override;
373 
374  /// Return true if the given shuffle mask can be codegen'd directly, or if it
375  /// should be stack expanded.
376  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
377 
378  bool hasBitPreservingFPLogic(EVT VT) const override;
379  bool
381  unsigned DefinedValues) const override;
382 
383  // Provide custom lowering hooks for some operations.
384  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
386  SelectionDAG &DAG) const override;
387 
388  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
389 
391  const APInt &DemandedElts,
392  TargetLoweringOpt &TLO) const override;
393 
395  KnownBits &Known,
396  const APInt &DemandedElts,
397  const SelectionDAG &DAG,
398  unsigned Depth) const override;
400  const APInt &DemandedElts,
401  const SelectionDAG &DAG,
402  unsigned Depth) const override;
403 
404  // This method returns the name of a target specific DAG node.
405  const char *getTargetNodeName(unsigned Opcode) const override;
406 
407  ConstraintType getConstraintType(StringRef Constraint) const override;
408 
409  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
410 
411  std::pair<unsigned, const TargetRegisterClass *>
413  StringRef Constraint, MVT VT) const override;
414 
415  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
416  std::vector<SDValue> &Ops,
417  SelectionDAG &DAG) const override;
418 
421  MachineBasicBlock *BB) const override;
422 
424  SDNode *Node) const override;
425 
427  EVT VT) const override;
428 
429  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
430  return VT.isScalarInteger();
431  }
432  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
433 
434  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
435  return isa<LoadInst>(I) || isa<StoreInst>(I);
436  }
438  AtomicOrdering Ord) const override;
440  AtomicOrdering Ord) const override;
441 
443  EVT VT) const override;
444 
446  return ISD::SIGN_EXTEND;
447  }
448 
450  return ISD::SIGN_EXTEND;
451  }
452 
453  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
455  return false;
456  return true;
457  }
459  CombineLevel Level) const override;
460 
461  /// If a physical register, this returns the register that receives the
462  /// exception address on entry to an EH pad.
463  Register
464  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
465 
466  /// If a physical register, this returns the register that receives the
467  /// exception typeid on entry to a landing pad.
468  Register
469  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
470 
471  bool shouldExtendTypeInLibCall(EVT Type) const override;
472  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
473 
474  /// Returns the register with the specified architectural or ABI name. This
475  /// method is necessary to lower the llvm.read_register.* and
476  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
477  /// with the clang -ffixed-xX flag for access to be allowed.
478  Register getRegisterByName(const char *RegName, LLT VT,
479  const MachineFunction &MF) const override;
480 
481  // Lower incoming arguments, copy physregs into vregs
483  bool IsVarArg,
485  const SDLoc &DL, SelectionDAG &DAG,
486  SmallVectorImpl<SDValue> &InVals) const override;
488  bool IsVarArg,
490  LLVMContext &Context) const override;
491  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
493  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
494  SelectionDAG &DAG) const override;
496  SmallVectorImpl<SDValue> &InVals) const override;
497  template <class NodeTy>
498  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
499 
501  Type *Ty) const override {
502  return true;
503  }
504  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
505  bool shouldConsiderGEPOffsetSplit() const override { return true; }
506 
508  SDValue C) const override;
509 
511  SDValue ConstNode) const override;
512 
514  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
516  Value *AlignedAddr, Value *Incr,
517  Value *Mask, Value *ShiftAmt,
518  AtomicOrdering Ord) const override;
522  AtomicCmpXchgInst *CI,
523  Value *AlignedAddr, Value *CmpVal,
524  Value *NewVal, Value *Mask,
525  AtomicOrdering Ord) const override;
526 
527  /// Returns true if the target allows unaligned memory accesses of the
528  /// specified type.
530  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
532  bool *Fast = nullptr) const override;
533 
535  SDValue Val, SDValue *Parts,
536  unsigned NumParts, MVT PartVT,
537  Optional<CallingConv::ID> CC) const override;
538 
539  SDValue
541  const SDValue *Parts, unsigned NumParts,
542  MVT PartVT, EVT ValueVT,
543  Optional<CallingConv::ID> CC) const override;
544 
545  static RISCVII::VLMUL getLMUL(MVT VT);
546  inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
547  unsigned MinSize) {
548  // Original equation:
549  // VLMAX = (VectorBits / EltSize) * LMUL
550  // where LMUL = MinSize / RISCV::RVVBitsPerBlock
551  // The following equations have been reordered to prevent loss of precision
552  // when calculating fractional LMUL.
553  return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
554  };
555  static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
556  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
557  static unsigned getRegClassIDForVecVT(MVT VT);
558  static std::pair<unsigned, unsigned>
560  unsigned InsertExtractIdx,
561  const RISCVRegisterInfo *TRI);
563 
564  bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
565 
566  bool isLegalElementTypeForRVV(Type *ScalarTy) const;
567 
568  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
569 
570  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
571  SmallVectorImpl<SDNode *> &Created) const override;
572 
573  unsigned getJumpTableEncoding() const override;
574 
576  const MachineBasicBlock *MBB,
577  unsigned uid,
578  MCContext &Ctx) const override;
579 
580 private:
581  /// RISCVCCAssignFn - This target-specific function extends the default
582  /// CCValAssign with additional information used to lower RISC-V calling
583  /// conventions.
584  typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
585  unsigned ValNo, MVT ValVT, MVT LocVT,
586  CCValAssign::LocInfo LocInfo,
587  ISD::ArgFlagsTy ArgFlags, CCState &State,
588  bool IsFixed, bool IsRet, Type *OrigTy,
589  const RISCVTargetLowering &TLI,
590  Optional<unsigned> FirstMaskArgument);
591 
592  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
593  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
594  RISCVCCAssignFn Fn) const;
595  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
597  bool IsRet, CallLoweringInfo *CLI,
598  RISCVCCAssignFn Fn) const;
599 
600  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
601  bool UseGOT) const;
602  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
603 
604  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
605  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
606  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
607  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
608  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
609  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
610  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
611  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
612  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
613  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
614  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
615  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
616  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
617  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
618  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
619  int64_t ExtTrueVal) const;
620  SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
621  SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
622  SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
623  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
624  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
625  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
626  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
627  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
628  SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
629  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
630  SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
631  bool IsVP) const;
632  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
634  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
637  SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
638  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
641  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
642  SelectionDAG &DAG) const;
643  SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
644  SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
645  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
646  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
647  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
649  unsigned MaskOpc,
650  unsigned VecOpc) const;
651  SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
653  SelectionDAG &DAG) const;
654  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
655  bool HasMask = true) const;
656  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
657  SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
658  unsigned VecOpc) const;
659  SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
660  SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
661  SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
662  unsigned RISCVISDOpc) const;
663  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
664  unsigned ExtendOpc) const;
665  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
666  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
667 
668  SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
669  SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
670 
671  bool isEligibleForTailCallOptimization(
672  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
673  const SmallVector<CCValAssign, 16> &ArgLocs) const;
674 
675  /// Generate error diagnostics if any register used by CC has been marked
676  /// reserved.
677  void validateCCReservedRegs(
678  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
679  MachineFunction &MF) const;
680 
681  bool useRVVForFixedLengthVectorVT(MVT VT) const;
682 
683  MVT getVPExplicitVectorLengthTy() const override;
684 
685  /// RVV code generation for fixed length vectors does not lower all
686  /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
687  /// merge. However, merging them creates a BUILD_VECTOR that is just as
688  /// illegal as the original, thus leading to an infinite legalisation loop.
689  /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
690  /// this override can be removed.
691  bool mergeStoresAfterLegalization(EVT VT) const override;
692 
693  /// Disable normalizing
694  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
695  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
696  /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
697  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
698  return false;
699  };
700 };
701 namespace RISCVVIntrinsicsTable {
702 
704  unsigned IntrinsicID;
705  uint8_t ScalarOperand;
706  uint8_t VLOperand;
707  bool hasScalarOperand() const {
708  // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
709  return ScalarOperand != 0xF;
710  }
711  bool hasVLOperand() const {
712  // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
713  return VLOperand != 0x1F;
714  }
715 };
716 
717 using namespace RISCV;
718 
719 #define GET_RISCVVIntrinsicsTable_DECL
720 #include "RISCVGenSearchableTables.inc"
721 
722 } // end namespace RISCVVIntrinsicsTable
723 
724 } // end namespace llvm
725 
726 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:11689
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:213
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:103
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:205
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:147
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:27
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:199
llvm::RISCVISD::VWSUBU_W_VL
@ VWSUBU_W_VL
Definition: RISCVISelLowering.h:258
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:233
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:242
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:48
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:9613
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:1075
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:307
llvm::RISCVISD::UNSHFL
@ UNSHFL
Definition: RISCVISelLowering.h:115
llvm::RISCVISD::VWADD_W_VL
@ VWADD_W_VL
Definition: RISCVISelLowering.h:255
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:237
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::RISCVTargetLowering::signExtendConstant
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
Definition: RISCVISelLowering.cpp:1079
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4395
llvm::RISCVTargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: RISCVISelLowering.cpp:1103
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.h:500
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::RISCVISD::VWSUB_VL
@ VWSUB_VL
Definition: RISCVISelLowering.h:253
llvm::RISCVISD::BFP
@ BFP
Definition: RISCVISelLowering.h:130
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:236
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:48
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:84
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVTargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: RISCVISelLowering.cpp:1110
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:55
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:282
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:191
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:11211
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:272
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:208
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:9132
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:239
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:288
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:937
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:11776
llvm::RISCVISD::STRICT_FCVT_W_RV64
@ STRICT_FCVT_W_RV64
Definition: RISCVISelLowering.h:311
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:11554
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:206
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RISCVISD::SHFLW
@ SHFLW
Definition: RISCVISelLowering.h:114
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:449
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:209
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:204
llvm::Optional< CallingConv::ID >
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:274
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:11471
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:11481
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:11490
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:194
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1385
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:11796
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:10351
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:1087
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:11025
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:170
llvm::RISCVTargetLowering::computeVLMAX
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
Definition: RISCVISelLowering.h:546
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:9031
llvm::RISCVISD::VWMUL_VL
@ VWMUL_VL
Definition: RISCVISelLowering.h:248
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:287
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:85
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:8401
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1434
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:232
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:11709
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:1255
llvm::RISCVISD::VCPOP_VL
@ VCPOP_VL
Definition: RISCVISelLowering.h:291
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:704
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:1083
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:32
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3395
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:277
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1362
llvm::RISCVISD::VWSUBU_VL
@ VWSUBU_VL
Definition: RISCVISelLowering.h:254
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:223
llvm::RISCVISD::FSL
@ FSL
Definition: RISCVISelLowering.h:68
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:238
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:11850
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:10586
llvm::Instruction
Definition: Instruction.h:42
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:11694
llvm::RISCVTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: RISCVISelLowering.cpp:1234
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:432
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:87
llvm::RISCVISD::FSLW
@ FSLW
Definition: RISCVISelLowering.h:72
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:265
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:234
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::GREVW
@ GREVW
Definition: RISCVISelLowering.h:110
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:1036
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:212
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:11716
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:54
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasVLOperand
bool hasVLOperand() const
Definition: RISCVISelLowering.h:711
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:453
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override
Definition: RISCVISelLowering.cpp:11628
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:63
llvm::RISCVTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: RISCVISelLowering.cpp:11753
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:175
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:228
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:227
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:42
llvm::RISCVISD::FP_TO_UINT_VL
@ FP_TO_UINT_VL
Definition: RISCVISelLowering.h:241
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:210
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:322
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:243
llvm::RISCVISD::GREV
@ GREV
Definition: RISCVISelLowering.h:109
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:39
llvm::RISCVISD::GORC
@ GORC
Definition: RISCVISelLowering.h:111
llvm::APFloat
Definition: APFloat.h:701
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:429
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:145
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:88
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:1032
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:195
llvm::RISCVISD::VWSUB_W_VL
@ VWSUB_W_VL
Definition: RISCVISelLowering.h:257
llvm::RISCVISD::BCOMPRESS
@ BCOMPRESS
Definition: RISCVISelLowering.h:121
llvm::RISCVTargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: RISCVISelLowering.cpp:1091
llvm::RISCVISD::GORCW
@ GORCW
Definition: RISCVISelLowering.h:112
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:262
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1293
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:45
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:162
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:216
llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: RISCVISelLowering.cpp:9646
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::RISCVISD::BDECOMPRESSW
@ BDECOMPRESSW
Definition: RISCVISelLowering.h:124
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:59
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:1043
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:505
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:190
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:11410
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:9241
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVISD::UNSHFLW
@ UNSHFLW
Definition: RISCVISelLowering.h:116
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:302
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3985
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:1002
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:1060
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:207
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVISD::SADDSAT_VL
@ SADDSAT_VL
Definition: RISCVISelLowering.h:218
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: RISCVISelLowering.cpp:8983
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:192
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:166
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:11606
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:361
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:49
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:6663
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:153
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:11668
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:273
RISCV.h
llvm::RISCVISD::FSRW
@ FSRW
Definition: RISCVISelLowering.h:71
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:41
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:332
llvm::SystemZ::VectorBits
const unsigned VectorBits
Definition: SystemZ.h:154
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:224
llvm::RISCVISD::USUBSAT_VL
@ USUBSAT_VL
Definition: RISCVISelLowering.h:221
llvm::RISCVISD::FCVT_XU
@ FCVT_XU
Definition: RISCVISelLowering.h:94
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1397
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:56
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:193
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVISD::STRICT_FCVT_WU_RV64
@ STRICT_FCVT_WU_RV64
Definition: RISCVISelLowering.h:312
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:136
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:11187
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand
uint8_t ScalarOperand
Definition: RISCVISelLowering.h:705
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVISD::BFPW
@ BFPW
Definition: RISCVISelLowering.h:131
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:245
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::RISCVTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: RISCVISelLowering.cpp:11660
llvm::RISCVISD::FCVT_X
@ FCVT_X
Definition: RISCVISelLowering.h:93
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1287
llvm::RISCVISD::VWADD_VL
@ VWADD_VL
Definition: RISCVISelLowering.h:251
llvm::RISCVISD::VWADDU_VL
@ VWADDU_VL
Definition: RISCVISelLowering.h:252
Node
Definition: ItaniumDemangle.h:155
llvm::RISCVISD::FCVT_WU_RV64
@ FCVT_WU_RV64
Definition: RISCVISelLowering.h:100
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:40
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:225
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:60
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
Definition: RISCVISelLowering.cpp:1344
llvm::RISCVISD::VWMULU_VL
@ VWMULU_VL
Definition: RISCVISelLowering.h:249
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:189
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:1243
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:278
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:50
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
CallingConvLower.h
llvm::RISCVISD::FMV_X_SIGNEXTH
@ FMV_X_SIGNEXTH
Definition: RISCVISelLowering.h:86
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:344
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand
uint8_t VLOperand
Definition: RISCVISelLowering.h:706
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:10886
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:244
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand
bool hasScalarOperand() const
Definition: RISCVISelLowering.h:707
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:283
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:325
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:2935
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:143
llvm::RISCVISD::VP_MERGE_VL
@ VP_MERGE_VL
Definition: RISCVISelLowering.h:269
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:11424
llvm::RISCVTargetLowering::getLMUL
static RISCVII::VLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1318
llvm::RISCVTargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: RISCVISelLowering.cpp:11633
llvm::RISCVISD::FSR
@ FSR
Definition: RISCVISelLowering.h:67
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:140
llvm::RISCVISD::VWMULSU_VL
@ VWMULSU_VL
Definition: RISCVISelLowering.h:250
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:434
llvm::RISCVISD::UADDSAT_VL
@ UADDSAT_VL
Definition: RISCVISelLowering.h:219
llvm::RISCVISD::FP_TO_SINT_VL
@ FP_TO_SINT_VL
Definition: RISCVISelLowering.h:240
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVISD::VWADDU_W_VL
@ VWADDU_W_VL
Definition: RISCVISelLowering.h:256
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:284
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:196
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:11953
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:215
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:43
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:703
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::FCVT_W_RV64
@ FCVT_W_RV64
Definition: RISCVISelLowering.h:99
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:188
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1656
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:235
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:297
llvm::RISCVISD::SHFL
@ SHFL
Definition: RISCVISelLowering.h:113
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:1273
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::RISCVTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: RISCVISelLowering.cpp:11650
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:11699
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:660
llvm::RISCVISD::BDECOMPRESS
@ BDECOMPRESS
Definition: RISCVISelLowering.h:123
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::BCOMPRESSW
@ BCOMPRESSW
Definition: RISCVISelLowering.h:122
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::RISCVTargetLowering::getAddr
SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal=true) const
Definition: RISCVISelLowering.cpp:3527
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:10909
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:445
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:226
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:11021
llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL
@ SPLAT_VECTOR_SPLIT_I64_VL
Definition: RISCVISelLowering.h:151
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:167
llvm::RISCVTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: RISCVISelLowering.cpp:1136
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:922
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:156
llvm::RISCVISD::FMA_VL
@ FMA_VL
Definition: RISCVISelLowering.h:230
llvm::RISCVISD::SSUBSAT_VL
@ SSUBSAT_VL
Definition: RISCVISelLowering.h:220
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:131
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:231
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:1261
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:64
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1580
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:29
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:161
llvm::RISCVTargetLowering::BuildSDIVPow2
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
Definition: RISCVISelLowering.cpp:11896
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:229
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:2807
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:347
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:211
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:11598
llvm::LLT
Definition: LowLevelTypeImpl.h:39