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RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
21 
22 namespace llvm {
23 class RISCVSubtarget;
24 struct RISCVRegisterInfo;
25 namespace RISCVISD {
26 enum NodeType : unsigned {
33  /// Select with condition operator - This selects between a true value and
34  /// a false value (ops #3 and #4) based on the boolean result of comparing
35  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
36  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
37  /// The lhs and rhs are XLenVT integers. The true and false values can be
38  /// integer or floating point.
44  // Multiply high for signedxunsigned.
46  // RV64I shifts, directly matching the semantics of the named RISC-V
47  // instructions.
51  // 32-bit operations from RV64M that can't be simply matched with a pattern
52  // at instruction selection time. These have undefined behavior for division
53  // by 0 or overflow (divw) like their target independent counterparts.
57  // RV64IB rotates, directly matching the semantics of the named RISC-V
58  // instructions.
61  // RV64IZbb bit counting instructions directly matching the semantics of the
62  // named RISC-V instructions.
65  // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
66  // instructions, but the same operand order as fshl/fshr intrinsics.
67  FSR,
68  FSL,
69  // RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
70  // but the same operand order as fshl/fshr intrinsics.
73  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
74  // XLEN is the only legal integer width.
75  //
76  // FMV_H_X matches the semantics of the FMV.H.X.
77  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
78  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
79  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
80  //
81  // This is a more convenient semantic for producing dagcombines that remove
82  // unnecessary GPR->FPR->GPR moves.
87  // FP to 32 bit int conversions for RV64. These are used to keep track of the
88  // result being sign extended to 64 bit.
91  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
92  // (returns (Lo, Hi)). It takes a chain operand.
94  // Generalized Reverse and Generalized Or-Combine - directly matching the
95  // semantics of the named RISC-V instructions. Lowered as custom nodes as
96  // TableGen chokes when faced with commutative permutations in deeply-nested
97  // DAGs. Each node takes an input operand and a control operand and outputs a
98  // bit-manipulated version of input. All operands are i32 or XLenVT.
107  // Bit Compress/Decompress implement the generic bit extract and bit deposit
108  // functions. This operation is also referred to as bit gather/scatter, bit
109  // pack/unpack, parallel extract/deposit, compress/expand, or right
110  // compress/right expand.
115  // Vector Extension
116  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
117  // for the VL value to be used for the operation.
119  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
120  // for the VL value to be used for the operation.
122  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
123  // extended from the vector element size.
125  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
127  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
129  // Splats an i64 scalar to a vector type (with element type i64) where the
130  // scalar is a sign-extended i32.
132  // Splats an 64-bit value that has been split into two i32 parts. This is
133  // expanded late to two scalar stores and a stride 0 vector load.
135  // Read VLENB CSR
137  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
138  // mask and VL operand.
140  // Matches the semantics of vslideup/vslidedown. The first operand is the
141  // pass-thru operand, the second is the source vector, the third is the
142  // XLenVT index (either constant or non-constant), the fourth is the mask
143  // and the fifth the VL.
146  // Matches the semantics of vslide1up/slide1down. The first operand is the
147  // source vector, the second is the XLenVT scalar value. The third and fourth
148  // operands are the mask and VL operands.
151  // Matches the semantics of the vid.v instruction, with a mask and VL
152  // operand.
154  // Matches the semantics of the vfcnvt.rod function (Convert double-width
155  // float to single-width float, rounding towards odd). Takes a double-width
156  // float vector and produces a single-width float vector. Also has a mask and
157  // VL operand.
159  // These nodes match the semantics of the corresponding RVV vector reduction
160  // instructions. They produce a vector result which is the reduction
161  // performed over the first vector operand plus the first element of the
162  // second vector operand. The first operand is an unconstrained vector type,
163  // and the result and second operand's types are expected to be the
164  // corresponding full-width LMUL=1 type for the first operand:
165  // nxv8i8 = vecreduce_add nxv32i8, nxv8i8
166  // nxv2i32 = vecreduce_add nxv8i32, nxv2i32
167  // The different in types does introduce extra vsetvli instructions but
168  // similarly it reduces the number of registers consumed per reduction.
169  // Also has a mask and VL operand.
182 
183  // Vector binary and unary ops with a mask as a third operand, and VL as a
184  // fourth operand.
185  // FIXME: Can we replace these with ISD::VP_*?
222 
223  // Widening instructions
226 
227  // Vector compare producing a mask. Fourth operand is input mask. Fifth
228  // operand is VL.
230 
231  // Vector select with an additional VL operand. This operation is unmasked.
233 
234  // Mask binary operators.
238 
239  // Set mask vector to all zeros or ones.
242 
243  // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand
244  // for VL.
248 
249  // Vector sign/zero extend with additional mask & VL operands.
252 
253  // vpopc.m with additional mask and VL operands.
255 
256  // Reads value of CSR.
257  // The first operand is a chain pointer. The second specifies address of the
258  // required CSR. Two results are produced, the read value and the new chain
259  // pointer.
261  // Write value to CSR.
262  // The first operand is a chain pointer, the second specifies address of the
263  // required CSR and the third is the value to write. The result is the new
264  // chain pointer.
266  // Read and write value of CSR.
267  // The first operand is a chain pointer, the second specifies address of the
268  // required CSR and the third is the value to write. Two results are produced,
269  // the value read before the modification and the new chain pointer.
271 
272  // Memory opcodes start here.
275 
276  // WARNING: Do not add anything in the end unless you want the node to
277  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
278  // opcodes will be thought as target memory ops!
279 };
280 } // namespace RISCVISD
281 
283  const RISCVSubtarget &Subtarget;
284 
285 public:
286  explicit RISCVTargetLowering(const TargetMachine &TM,
287  const RISCVSubtarget &STI);
288 
289  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
290 
291  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
292  MachineFunction &MF,
293  unsigned Intrinsic) const override;
294  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
295  unsigned AS,
296  Instruction *I = nullptr) const override;
297  bool isLegalICmpImmediate(int64_t Imm) const override;
298  bool isLegalAddImmediate(int64_t Imm) const override;
299  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
300  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
301  bool isZExtFree(SDValue Val, EVT VT2) const override;
302  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
303  bool isCheapToSpeculateCttz() const override;
304  bool isCheapToSpeculateCtlz() const override;
305  bool isFPImmLegal(const APFloat &Imm, EVT VT,
306  bool ForCodeSize) const override;
307 
308  bool softPromoteHalfType() const override { return true; }
309 
310  /// Return the register type for a given MVT, ensuring vectors are treated
311  /// as a series of gpr sized integers.
313  EVT VT) const override;
314 
315  /// Return the number of registers for a given MVT, ensuring vectors are
316  /// treated as a series of gpr sized integers.
318  CallingConv::ID CC,
319  EVT VT) const override;
320 
321  /// Return true if the given shuffle mask can be codegen'd directly, or if it
322  /// should be stack expanded.
323  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
324 
325  bool hasBitPreservingFPLogic(EVT VT) const override;
326  bool
328  unsigned DefinedValues) const override;
329 
330  // Provide custom lowering hooks for some operations.
331  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
333  SelectionDAG &DAG) const override;
334 
335  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
336 
338  const APInt &DemandedElts,
339  TargetLoweringOpt &TLO) const override;
340 
342  KnownBits &Known,
343  const APInt &DemandedElts,
344  const SelectionDAG &DAG,
345  unsigned Depth) const override;
347  const APInt &DemandedElts,
348  const SelectionDAG &DAG,
349  unsigned Depth) const override;
350 
351  // This method returns the name of a target specific DAG node.
352  const char *getTargetNodeName(unsigned Opcode) const override;
353 
354  ConstraintType getConstraintType(StringRef Constraint) const override;
355 
356  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
357 
358  std::pair<unsigned, const TargetRegisterClass *>
360  StringRef Constraint, MVT VT) const override;
361 
362  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
363  std::vector<SDValue> &Ops,
364  SelectionDAG &DAG) const override;
365 
368  MachineBasicBlock *BB) const override;
369 
371  EVT VT) const override;
372 
373  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
374  return VT.isScalarInteger();
375  }
376  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
377 
378  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
379  return isa<LoadInst>(I) || isa<StoreInst>(I);
380  }
382  AtomicOrdering Ord) const override;
384  AtomicOrdering Ord) const override;
385 
387  EVT VT) const override;
388 
390  return ISD::SIGN_EXTEND;
391  }
392 
394  return ISD::SIGN_EXTEND;
395  }
396 
397  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
399  return false;
400  return true;
401  }
403  CombineLevel Level) const override;
404 
405  /// If a physical register, this returns the register that receives the
406  /// exception address on entry to an EH pad.
407  Register
408  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
409 
410  /// If a physical register, this returns the register that receives the
411  /// exception typeid on entry to a landing pad.
412  Register
413  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
414 
415  bool shouldExtendTypeInLibCall(EVT Type) const override;
416  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
417 
418  /// Returns the register with the specified architectural or ABI name. This
419  /// method is necessary to lower the llvm.read_register.* and
420  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
421  /// with the clang -ffixed-xX flag for access to be allowed.
422  Register getRegisterByName(const char *RegName, LLT VT,
423  const MachineFunction &MF) const override;
424 
425  // Lower incoming arguments, copy physregs into vregs
427  bool IsVarArg,
429  const SDLoc &DL, SelectionDAG &DAG,
430  SmallVectorImpl<SDValue> &InVals) const override;
432  bool IsVarArg,
434  LLVMContext &Context) const override;
435  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
437  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
438  SelectionDAG &DAG) const override;
440  SmallVectorImpl<SDValue> &InVals) const override;
441 
443  Type *Ty) const override {
444  return true;
445  }
446  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
447  bool shouldConsiderGEPOffsetSplit() const override { return true; }
448 
450  SDValue C) const override;
451 
453  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
455  Value *AlignedAddr, Value *Incr,
456  Value *Mask, Value *ShiftAmt,
457  AtomicOrdering Ord) const override;
461  AtomicCmpXchgInst *CI,
462  Value *AlignedAddr, Value *CmpVal,
463  Value *NewVal, Value *Mask,
464  AtomicOrdering Ord) const override;
465 
466  /// Returns true if the target allows unaligned memory accesses of the
467  /// specified type.
469  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
471  bool *Fast = nullptr) const override;
472 
474  SDValue Val, SDValue *Parts,
475  unsigned NumParts, MVT PartVT,
476  Optional<CallingConv::ID> CC) const override;
477 
478  SDValue
480  const SDValue *Parts, unsigned NumParts,
481  MVT PartVT, EVT ValueVT,
482  Optional<CallingConv::ID> CC) const override;
483 
484  static RISCVII::VLMUL getLMUL(MVT VT);
485  static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
486  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
487  static unsigned getRegClassIDForVecVT(MVT VT);
488  static std::pair<unsigned, unsigned>
490  unsigned InsertExtractIdx,
491  const RISCVRegisterInfo *TRI);
493 
494  bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
495 
496 private:
497  /// RISCVCCAssignFn - This target-specific function extends the default
498  /// CCValAssign with additional information used to lower RISC-V calling
499  /// conventions.
500  typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
501  unsigned ValNo, MVT ValVT, MVT LocVT,
502  CCValAssign::LocInfo LocInfo,
503  ISD::ArgFlagsTy ArgFlags, CCState &State,
504  bool IsFixed, bool IsRet, Type *OrigTy,
505  const RISCVTargetLowering &TLI,
506  Optional<unsigned> FirstMaskArgument);
507 
508  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
509  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
510  RISCVCCAssignFn Fn) const;
511  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
513  bool IsRet, CallLoweringInfo *CLI,
514  RISCVCCAssignFn Fn) const;
515 
516  template <class NodeTy>
517  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
518 
519  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
520  bool UseGOT) const;
521  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
522 
523  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
524  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
525  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
526  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
527  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
528  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
529  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
530  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
531  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
533  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
535  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
538  int64_t ExtTrueVal) const;
539  SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
542  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
543  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
555  SelectionDAG &DAG) const;
556  SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
557  SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
558  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
559  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
560  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
561  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
562  unsigned MaskOpc,
563  unsigned VecOpc) const;
564  SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
565  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
566  SelectionDAG &DAG) const;
567  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
568  bool HasMask = true) const;
569  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
570  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
571  unsigned ExtendOpc) const;
572  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
573  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
574 
575  SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
576  SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
577 
578  bool isEligibleForTailCallOptimization(
579  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
580  const SmallVector<CCValAssign, 16> &ArgLocs) const;
581 
582  /// Generate error diagnostics if any register used by CC has been marked
583  /// reserved.
584  void validateCCReservedRegs(
585  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
586  MachineFunction &MF) const;
587 
588  bool useRVVForFixedLengthVectorVT(MVT VT) const;
589 
590  MVT getVPExplicitVectorLengthTy() const override;
591 
592  /// RVV code generation for fixed length vectors does not lower all
593  /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
594  /// merge. However, merging them creates a BUILD_VECTOR that is just as
595  /// illegal as the original, thus leading to an infinite legalisation loop.
596  /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
597  /// this override can be removed.
598  bool mergeStoresAfterLegalization(EVT VT) const override;
599 };
600 
601 namespace RISCV {
602 // We use 64 bits as the known part in the scalable vector types.
603 static constexpr unsigned RVVBitsPerBlock = 64;
604 } // namespace RISCV
605 
606 namespace RISCVVIntrinsicsTable {
607 
609  unsigned IntrinsicID;
610  uint8_t SplatOperand;
611 };
612 
613 using namespace RISCV;
614 
615 #define GET_RISCVVIntrinsicsTable_DECL
616 #include "RISCVGenSearchableTables.inc"
617 
618 } // end namespace RISCVVIntrinsicsTable
619 
620 } // end namespace llvm
621 
622 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:8874
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:195
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:93
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:187
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:128
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:27
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:181
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:209
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:218
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:48
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:6911
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:975
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:270
llvm::RISCVISD::UNSHFL
@ UNSHFL
Definition: RISCVISelLowering.h:105
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:213
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4133
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.h:442
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:212
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:45
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:83
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:55
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:245
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:173
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:8453
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:235
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:190
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:6487
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:215
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:251
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:878
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::SplatOperand
uint8_t SplatOperand
Definition: RISCVISelLowering.h:610
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:8933
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:8775
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:180
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:188
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RISCVISD::SHFLW
@ SHFLW
Definition: RISCVISelLowering.h:104
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:393
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:191
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:186
llvm::Optional< CallingConv::ID >
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:237
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:8692
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:8702
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:8711
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:176
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1150
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:8949
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:7613
llvm::RISCVISD::VSE_VL
@ VSE_VL
Definition: RISCVISelLowering.h:274
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:983
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:8287
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:153
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:6387
llvm::RISCVISD::VWMUL_VL
@ VWMUL_VL
Definition: RISCVISelLowering.h:224
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:250
TargetLowering.h
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:84
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:5844
llvm::RISCVISD::VPOPC_VL
@ VPOPC_VL
Definition: RISCVISelLowering.h:254
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:208
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:8894
llvm::RISCVISD::VLE_VL
@ VLE_VL
Definition: RISCVISelLowering.h:273
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:1000
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:609
llvm::RISCVISD::SPLAT_VECTOR_I64
@ SPLAT_VECTOR_I64
Definition: RISCVISelLowering.h:131
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:979
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:32
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3165
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:240
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1127
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:199
llvm::RISCVISD::FSL
@ FSL
Definition: RISCVISelLowering.h:68
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:8991
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:7848
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:8879
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:376
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:85
llvm::RISCVISD::FSLW
@ FSLW
Definition: RISCVISelLowering.h:72
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:232
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:210
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::GREVW
@ GREVW
Definition: RISCVISelLowering.h:100
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:937
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:194
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:8901
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:54
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:397
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:63
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:158
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:204
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:203
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:42
llvm::RISCVISD::FP_TO_UINT_VL
@ FP_TO_UINT_VL
Definition: RISCVISelLowering.h:217
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:192
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:603
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:219
llvm::RISCVISD::GREV
@ GREV
Definition: RISCVISelLowering.h:99
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:39
llvm::RISCVISD::GORC
@ GORC
Definition: RISCVISelLowering.h:101
llvm::APFloat
Definition: APFloat.h:701
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:373
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:126
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:86
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:933
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:177
llvm::RISCVISD::BCOMPRESS
@ BCOMPRESS
Definition: RISCVISelLowering.h:111
llvm::RISCVISD::GORCW
@ GORCW
Definition: RISCVISelLowering.h:102
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:229
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:45
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:145
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVISD::BDECOMPRESSW
@ BDECOMPRESSW
Definition: RISCVISelLowering.h:114
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:59
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:944
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:447
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:172
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:8631
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:6588
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVISD::UNSHFLW
@ UNSHFLW
Definition: RISCVISelLowering.h:106
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:265
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3723
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:907
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:961
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:189
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:179
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: RISCVISelLowering.cpp:6339
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:174
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:149
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:8827
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:308
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:49
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:4852
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:136
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:8853
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:236
RISCV.h
llvm::RISCVISD::FSRW
@ FSRW
Definition: RISCVISelLowering.h:71
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:41
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:289
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:200
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1162
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:56
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT VT) const override
Definition: RISCVISelLowering.cpp:8849
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:175
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:118
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:8431
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:221
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::RISCVISD::FCVT_WU_RV64
@ FCVT_WU_RV64
Definition: RISCVISelLowering.h:90
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:40
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:201
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:60
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
Definition: RISCVISelLowering.cpp:1109
llvm::RISCVISD::VWMULU_VL
@ VWMULU_VL
Definition: RISCVISelLowering.h:225
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:171
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:987
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1698
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:588
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:241
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:50
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:8148
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:220
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:246
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:282
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:2079
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:124
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:8645
llvm::RISCVTargetLowering::getLMUL
static RISCVII::VLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1083
llvm::RISCVISD::FSR
@ FSR
Definition: RISCVISelLowering.h:67
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:121
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:378
llvm::RISCVISD::FP_TO_SINT_VL
@ FP_TO_SINT_VL
Definition: RISCVISelLowering.h:216
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:247
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:178
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:9036
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:43
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:608
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::FCVT_W_RV64
@ FCVT_W_RV64
Definition: RISCVISelLowering.h:89
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:170
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1359
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:211
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:260
llvm::RISCVISD::SHFL
@ SHFL
Definition: RISCVISelLowering.h:103
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:1017
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:89
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:8884
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:713
llvm::RISCVISD::BDECOMPRESS
@ BDECOMPRESS
Definition: RISCVISelLowering.h:113
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::BCOMPRESSW
@ BCOMPRESSW
Definition: RISCVISelLowering.h:112
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:8171
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:389
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:202
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:8283
llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL
@ SPLAT_VECTOR_SPLIT_I64_VL
Definition: RISCVISelLowering.h:134
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:150
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:863
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:139
llvm::RISCVISD::FMA_VL
@ FMA_VL
Definition: RISCVISelLowering.h:206
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:207
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:1006
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:64
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1299
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:29
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:144
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:205
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:196
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:1364
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:277
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:193
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:8819
llvm::LLT
Definition: LowLevelTypeImpl.h:40