LLVM  16.0.0git
RISCVISelLowering.h
Go to the documentation of this file.
1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
22 #include <optional>
23 
24 namespace llvm {
25 class RISCVSubtarget;
26 struct RISCVRegisterInfo;
27 namespace RISCVISD {
28 enum NodeType : unsigned {
35  /// Select with condition operator - This selects between a true value and
36  /// a false value (ops #3 and #4) based on the boolean result of comparing
37  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
38  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
39  /// The lhs and rhs are XLenVT integers. The true and false values can be
40  /// integer or floating point.
46 
47  // Add the Lo 12 bits from an address. Selected to ADDI.
49  // Get the Hi 20 bits from an address. Selected to LUI.
50  HI,
51 
52  // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
53  LLA,
54 
55  // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
57 
58  // Load address.
60 
61  // Multiply high for signedxunsigned.
63  // RV64I shifts, directly matching the semantics of the named RISC-V
64  // instructions.
68  // 32-bit operations from RV64M that can't be simply matched with a pattern
69  // at instruction selection time. These have undefined behavior for division
70  // by 0 or overflow (divw) like their target independent counterparts.
74  // RV64IB rotates, directly matching the semantics of the named RISC-V
75  // instructions.
78  // RV64IZbb bit counting instructions directly matching the semantics of the
79  // named RISC-V instructions.
82 
83  // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
85 
86  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
87  // XLEN is the only legal integer width.
88  //
89  // FMV_H_X matches the semantics of the FMV.H.X.
90  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
91  // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
92  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
93  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
94  //
95  // This is a more convenient semantic for producing dagcombines that remove
96  // unnecessary GPR->FPR->GPR moves.
102  // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
103  // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
104  // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
105  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
108  // FP to 32 bit int conversions for RV64. These are used to keep track of the
109  // result being sign extended to 64 bit. These saturate out of range inputs.
110  // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
111  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
114 
115  // Rounds an FP value to its corresponding integer in the same FP format.
116  // First operand is the value to round, the second operand is the largest
117  // integer that can be represented exactly in the FP format. This will be
118  // expanded into multiple instructions and basic blocks with a custom
119  // inserter.
121 
122  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
123  // (returns (Lo, Hi)). It takes a chain operand.
125  // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
126  // XLenVT.
131  // Vector Extension
132  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
133  // for the VL value to be used for the operation. The first operand is
134  // passthru operand.
136  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
137  // for the VL value to be used for the operation. The first operand is
138  // passthru operand.
140  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
141  // extended from the vector element size.
143  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
145  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
147  // Splats an 64-bit value that has been split into two i32 parts. This is
148  // expanded late to two scalar stores and a stride 0 vector load.
149  // The first operand is passthru operand.
151  // Read VLENB CSR
153  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
154  // mask and VL operand.
156  // Matches the semantics of vslideup/vslidedown. The first operand is the
157  // pass-thru operand, the second is the source vector, the third is the
158  // XLenVT index (either constant or non-constant), the fourth is the mask
159  // and the fifth the VL.
162  // Matches the semantics of vslide1up/slide1down. The first operand is
163  // passthru operand, the second is source vector, third is the XLenVT scalar
164  // value. The fourth and fifth operands are the mask and VL operands.
167  // Matches the semantics of the vid.v instruction, with a mask and VL
168  // operand.
170  // Matches the semantics of the vfcnvt.rod function (Convert double-width
171  // float to single-width float, rounding towards odd). Takes a double-width
172  // float vector and produces a single-width float vector. Also has a mask and
173  // VL operand.
175  // These nodes match the semantics of the corresponding RVV vector reduction
176  // instructions. They produce a vector result which is the reduction
177  // performed over the second vector operand plus the first element of the
178  // third vector operand. The first operand is the pass-thru operand. The
179  // second operand is an unconstrained vector type, and the result, first, and
180  // third operand's types are expected to be the corresponding full-width
181  // LMUL=1 type for the second operand:
182  // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
183  // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
184  // The different in types does introduce extra vsetvli instructions but
185  // similarly it reduces the number of registers consumed per reduction.
186  // Also has a mask and VL operand.
199 
200  // Vector binary ops with a merge as a third operand, a mask as a fourth
201  // operand, and VL as a fifth operand.
219 
224 
233 
234  // Vector unary ops with a mask as a second operand and VL as a third operand.
238  FCOPYSIGN_VL, // Has a merge operand
243  VFCVT_RM_X_F_VL, // Has a rounding mode operand.
248 
249  // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
254 
255  // Widening instructions with a merge value a third operand, a mask as a
256  // fourth operand, and VL as a fifth operand.
268 
270 
271  // Vector compare producing a mask. Fourth operand is input mask. Fifth
272  // operand is VL.
274 
275  // Vector select with an additional VL operand. This operation is unmasked.
277  // Vector select with operand #2 (the value when the condition is false) tied
278  // to the destination and an additional VL operand. This operation is
279  // unmasked.
281 
282  // Mask binary operators.
286 
287  // Set mask vector to all zeros or ones.
290 
291  // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
292  // for passthru and VL. Operands are (src, index, mask, passthru, vl).
296 
297  // Vector sign/zero extend with additional mask & VL operands.
300 
301  // vcpop.m with additional mask and VL operands.
303 
304  // Reads value of CSR.
305  // The first operand is a chain pointer. The second specifies address of the
306  // required CSR. Two results are produced, the read value and the new chain
307  // pointer.
309  // Write value to CSR.
310  // The first operand is a chain pointer, the second specifies address of the
311  // required CSR and the third is the value to write. The result is the new
312  // chain pointer.
314  // Read and write value of CSR.
315  // The first operand is a chain pointer, the second specifies address of the
316  // required CSR and the third is the value to write. Two results are produced,
317  // the value read before the modification and the new chain pointer.
319 
320  // FP to 32 bit int conversions for RV64. These are used to keep track of the
321  // result being sign extended to 64 bit. These saturate out of range inputs.
324 
325  // WARNING: Do not add anything in the end unless you want the node to
326  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
327  // opcodes will be thought as target memory ops!
328 
329  // Load address.
332 };
333 } // namespace RISCVISD
334 
336  const RISCVSubtarget &Subtarget;
337 
338 public:
339  explicit RISCVTargetLowering(const TargetMachine &TM,
340  const RISCVSubtarget &STI);
341 
342  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
343 
344  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
345  MachineFunction &MF,
346  unsigned Intrinsic) const override;
347  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
348  unsigned AS,
349  Instruction *I = nullptr) const override;
350  bool isLegalICmpImmediate(int64_t Imm) const override;
351  bool isLegalAddImmediate(int64_t Imm) const override;
352  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
353  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
354  bool isZExtFree(SDValue Val, EVT VT2) const override;
355  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
356  bool signExtendConstant(const ConstantInt *CI) const override;
357  bool isCheapToSpeculateCttz(Type *Ty) const override;
358  bool isCheapToSpeculateCtlz(Type *Ty) const override;
359  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
360  bool hasAndNotCompare(SDValue Y) const override;
361  bool hasBitTest(SDValue X, SDValue Y) const override;
364  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
365  SelectionDAG &DAG) const override;
366  /// Return true if the (vector) instruction I will be lowered to an instruction
367  /// with a scalar splat operand for the given Operand number.
368  bool canSplatOperand(Instruction *I, int Operand) const;
369  /// Return true if a vector instruction will lower to a target instruction
370  /// able to splat the given operand.
371  bool canSplatOperand(unsigned Opcode, int Operand) const;
373  SmallVectorImpl<Use *> &Ops) const override;
374  bool shouldScalarizeBinop(SDValue VecOp) const override;
375  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
376  bool isFPImmLegal(const APFloat &Imm, EVT VT,
377  bool ForCodeSize) const override;
378  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
379  unsigned Index) const override;
380 
381  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
382 
383  bool softPromoteHalfType() const override { return true; }
384 
385  /// Return the register type for a given MVT, ensuring vectors are treated
386  /// as a series of gpr sized integers.
388  EVT VT) const override;
389 
390  /// Return the number of registers for a given MVT, ensuring vectors are
391  /// treated as a series of gpr sized integers.
394  EVT VT) const override;
395 
396  /// Return true if the given shuffle mask can be codegen'd directly, or if it
397  /// should be stack expanded.
398  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
399 
400  bool hasBitPreservingFPLogic(EVT VT) const override;
401  bool
403  unsigned DefinedValues) const override;
404 
405  // Provide custom lowering hooks for some operations.
406  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
408  SelectionDAG &DAG) const override;
409 
410  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
411 
413  const APInt &DemandedElts,
414  TargetLoweringOpt &TLO) const override;
415 
417  KnownBits &Known,
418  const APInt &DemandedElts,
419  const SelectionDAG &DAG,
420  unsigned Depth) const override;
422  const APInt &DemandedElts,
423  const SelectionDAG &DAG,
424  unsigned Depth) const override;
425 
426  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
427 
428  // This method returns the name of a target specific DAG node.
429  const char *getTargetNodeName(unsigned Opcode) const override;
430 
431  ConstraintType getConstraintType(StringRef Constraint) const override;
432 
433  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
434 
435  std::pair<unsigned, const TargetRegisterClass *>
437  StringRef Constraint, MVT VT) const override;
438 
439  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
440  std::vector<SDValue> &Ops,
441  SelectionDAG &DAG) const override;
442 
445  MachineBasicBlock *BB) const override;
446 
448  SDNode *Node) const override;
449 
451  EVT VT) const override;
452 
453  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
454  return VT.isScalarInteger();
455  }
456  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
457 
458  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
459  return isa<LoadInst>(I) || isa<StoreInst>(I);
460  }
462  AtomicOrdering Ord) const override;
464  AtomicOrdering Ord) const override;
465 
467  EVT VT) const override;
468 
470  return ISD::SIGN_EXTEND;
471  }
472 
474  return ISD::SIGN_EXTEND;
475  }
476 
477  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
479  return false;
480  return true;
481  }
483  CombineLevel Level) const override;
484 
485  /// If a physical register, this returns the register that receives the
486  /// exception address on entry to an EH pad.
487  Register
488  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
489 
490  /// If a physical register, this returns the register that receives the
491  /// exception typeid on entry to a landing pad.
492  Register
493  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
494 
495  bool shouldExtendTypeInLibCall(EVT Type) const override;
496  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
497 
498  /// Returns the register with the specified architectural or ABI name. This
499  /// method is necessary to lower the llvm.read_register.* and
500  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
501  /// with the clang -ffixed-xX flag for access to be allowed.
502  Register getRegisterByName(const char *RegName, LLT VT,
503  const MachineFunction &MF) const override;
504 
505  // Lower incoming arguments, copy physregs into vregs
507  bool IsVarArg,
509  const SDLoc &DL, SelectionDAG &DAG,
510  SmallVectorImpl<SDValue> &InVals) const override;
512  bool IsVarArg,
514  LLVMContext &Context) const override;
515  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
517  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
518  SelectionDAG &DAG) const override;
520  SmallVectorImpl<SDValue> &InVals) const override;
521 
523  Type *Ty) const override;
524  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
525  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
526  bool shouldConsiderGEPOffsetSplit() const override { return true; }
527 
529  SDValue C) const override;
530 
532  SDValue ConstNode) const override;
533 
535  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
537  Value *AlignedAddr, Value *Incr,
538  Value *Mask, Value *ShiftAmt,
539  AtomicOrdering Ord) const override;
543  AtomicCmpXchgInst *CI,
544  Value *AlignedAddr, Value *CmpVal,
545  Value *NewVal, Value *Mask,
546  AtomicOrdering Ord) const override;
547 
548  /// Returns true if the target allows unaligned memory accesses of the
549  /// specified type.
551  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
553  unsigned *Fast = nullptr) const override;
554 
556  SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
557  unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
558  const override;
559 
561  SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
562  unsigned NumParts, MVT PartVT, EVT ValueVT,
563  std::optional<CallingConv::ID> CC) const override;
564 
565  static RISCVII::VLMUL getLMUL(MVT VT);
566  inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
567  unsigned MinSize) {
568  // Original equation:
569  // VLMAX = (VectorBits / EltSize) * LMUL
570  // where LMUL = MinSize / RISCV::RVVBitsPerBlock
571  // The following equations have been reordered to prevent loss of precision
572  // when calculating fractional LMUL.
573  return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
574  };
575  static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
576  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
577  static unsigned getRegClassIDForVecVT(MVT VT);
578  static std::pair<unsigned, unsigned>
580  unsigned InsertExtractIdx,
581  const RISCVRegisterInfo *TRI);
583 
584  bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
585 
586  bool isLegalElementTypeForRVV(Type *ScalarTy) const;
587 
588  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
589 
590  unsigned getJumpTableEncoding() const override;
591 
593  const MachineBasicBlock *MBB,
594  unsigned uid,
595  MCContext &Ctx) const override;
596 
597  bool isVScaleKnownToBeAPowerOfTwo() const override;
598 
600  uint64_t ElemSize) const override {
601  // Scaled addressing not supported on indexed load/stores
602  return Scale == 1;
603  }
604 
605 private:
606  /// RISCVCCAssignFn - This target-specific function extends the default
607  /// CCValAssign with additional information used to lower RISC-V calling
608  /// conventions.
609  typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
610  unsigned ValNo, MVT ValVT, MVT LocVT,
611  CCValAssign::LocInfo LocInfo,
612  ISD::ArgFlagsTy ArgFlags, CCState &State,
613  bool IsFixed, bool IsRet, Type *OrigTy,
614  const RISCVTargetLowering &TLI,
615  Optional<unsigned> FirstMaskArgument);
616 
617  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
618  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
619  RISCVCCAssignFn Fn) const;
620  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
622  bool IsRet, CallLoweringInfo *CLI,
623  RISCVCCAssignFn Fn) const;
624 
625  template <class NodeTy>
626  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
627  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
628  bool UseGOT) const;
629  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
630 
631  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
634  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
637  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
638  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
641  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
642  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
643  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
644  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
645  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
646  int64_t ExtTrueVal) const;
647  SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
652  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
653  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
654  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
655  SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
656  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
657  SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
658  bool IsVP) const;
659  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
660  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
661  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
662  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
663  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
664  SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
665  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
666  SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
667  SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
668  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
669  SelectionDAG &DAG) const;
670  SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
671  SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
672  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
673  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
674  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
675  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
676  unsigned MaskOpc,
677  unsigned VecOpc) const;
678  SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
679  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
680  SelectionDAG &DAG) const;
681  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
682  bool HasMergeOp = false, bool HasMask = true) const;
683  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
684  bool HasMergeOp = false) const;
685  SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
686  unsigned VecOpc) const;
687  SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
688  SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
689  SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
690  unsigned RISCVISDOpc) const;
691  SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
692  SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
693  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
694  unsigned ExtendOpc) const;
695  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
696  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
697 
698  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
699 
700  SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
701  SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
702 
703  bool isEligibleForTailCallOptimization(
704  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
705  const SmallVector<CCValAssign, 16> &ArgLocs) const;
706 
707  /// Generate error diagnostics if any register used by CC has been marked
708  /// reserved.
709  void validateCCReservedRegs(
710  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
711  MachineFunction &MF) const;
712 
713  bool useRVVForFixedLengthVectorVT(MVT VT) const;
714 
715  MVT getVPExplicitVectorLengthTy() const override;
716 
717  /// RVV code generation for fixed length vectors does not lower all
718  /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
719  /// merge. However, merging them creates a BUILD_VECTOR that is just as
720  /// illegal as the original, thus leading to an infinite legalisation loop.
721  /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
722  /// this override can be removed.
723  bool mergeStoresAfterLegalization(EVT VT) const override;
724 
725  /// Disable normalizing
726  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
727  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
728  /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
729  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
730  return false;
731  };
732 };
733 namespace RISCVVIntrinsicsTable {
734 
736  unsigned IntrinsicID;
737  uint8_t ScalarOperand;
738  uint8_t VLOperand;
739  bool hasScalarOperand() const {
740  // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
741  return ScalarOperand != 0xF;
742  }
743  bool hasVLOperand() const {
744  // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
745  return VLOperand != 0x1F;
746  }
747 };
748 
749 using namespace RISCV;
750 
751 #define GET_RISCVVIntrinsicsTable_DECL
752 #include "RISCVGenSearchableTables.inc"
753 
754 } // end namespace RISCVVIntrinsicsTable
755 
756 } // end namespace llvm
757 
758 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:13243
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:211
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:124
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:203
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:146
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:29
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::RISCVISD::VFMSUB_VL
@ VFMSUB_VL
Definition: RISCVISelLowering.h:252
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVISD::VWSUBU_W_VL
@ VWSUBU_W_VL
Definition: RISCVISelLowering.h:267
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:216
llvm::RISCVISD::LLA
@ LLA
Definition: RISCVISelLowering.h:53
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:244
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:65
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:11051
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:1179
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:318
llvm::RISCVISD::VWADD_W_VL
@ VWADD_W_VL
Definition: RISCVISelLowering.h:264
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:232
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::RISCVTargetLowering::signExtendConstant
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
Definition: RISCVISelLowering.cpp:1183
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4569
llvm::RISCVTargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: RISCVISelLowering.cpp:1222
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::RISCVISD::VWSUB_VL
@ VWSUB_VL
Definition: RISCVISelLowering.h:262
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:231
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:62
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:97
llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
Definition: RISCVISelLowering.cpp:13210
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVTargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: RISCVISelLowering.cpp:1263
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:72
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::RISCVISD::LA_TLS_IE
@ LA_TLS_IE
Definition: RISCVISelLowering.h:331
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:293
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:190
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:12745
llvm::RISCVISD::VFCVT_RTZ_XU_F_VL
@ VFCVT_RTZ_XU_F_VL
Definition: RISCVISelLowering.h:240
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:283
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:206
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:10219
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:226
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:299
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:1037
llvm::RISCVISD::VNSRL_VL
@ VNSRL_VL
Definition: RISCVISelLowering.h:269
llvm::RISCVISD::VFCVT_RTZ_X_F_VL
@ VFCVT_RTZ_X_F_VL
Definition: RISCVISelLowering.h:239
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::RISCVISD::STRICT_FCVT_W_RV64
@ STRICT_FCVT_W_RV64
Definition: RISCVISelLowering.h:322
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2344
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:13092
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:204
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AttributeList
Definition: Attributes.h:431
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:473
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:207
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:202
llvm::Optional< unsigned >
llvm::RISCVTargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: RISCVISelLowering.cpp:13451
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:285
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:13005
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:13015
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:13024
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:193
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1624
TargetParser.h
llvm::RISCVISD::FROUND
@ FROUND
Definition: RISCVISelLowering.h:120
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:11852
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::RISCVISD::VFMADD_VL
@ VFMADD_VL
Definition: RISCVISelLowering.h:250
llvm::RISCVTargetLowering::canSplatOperand
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
Definition: RISCVISelLowering.cpp:1315
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:13406
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:12557
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:169
llvm::RISCVTargetLowering::computeVLMAX
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
Definition: RISCVISelLowering.h:566
llvm::RISCVISD::ZIP
@ ZIP
Definition: RISCVISelLowering.h:129
llvm::RISCVTargetLowering::isUsedByReturnOnly
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
Definition: RISCVISelLowering.cpp:12521
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:10114
llvm::RISCVISD::VWMUL_VL
@ VWMUL_VL
Definition: RISCVISelLowering.h:257
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:298
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:98
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:9473
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1673
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:215
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:13263
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:1467
llvm::RISCVISD::VCPOP_VL
@ VCPOP_VL
Definition: RISCVISelLowering.h:302
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:736
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:34
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3506
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:288
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1601
llvm::RISCVISD::VWSUBU_VL
@ VWSUBU_VL
Definition: RISCVISelLowering.h:263
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:227
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:225
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:12087
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:1187
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:13332
llvm::Instruction
Definition: Instruction.h:42
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:13248
llvm::RISCVISD::HI
@ HI
Definition: RISCVISelLowering.h:50
llvm::RISCVTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: RISCVISelLowering.cpp:1413
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:456
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:100
llvm::RISCVISD::LA_TLS_GD
@ LA_TLS_GD
Definition: RISCVISelLowering.h:59
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::ABSW
@ ABSW
Definition: RISCVISelLowering.h:84
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:276
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:217
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::VFNMADD_VL
@ VFNMADD_VL
Definition: RISCVISelLowering.h:251
llvm::RISCVISD::VFNMSUB_VL
@ VFNMSUB_VL
Definition: RISCVISelLowering.h:253
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:1136
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:210
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:13270
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:71
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasVLOperand
bool hasVLOperand() const
Definition: RISCVISelLowering.h:743
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:477
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override
Definition: RISCVISelLowering.cpp:13170
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:80
llvm::RISCVTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: RISCVISelLowering.cpp:13309
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:174
llvm::RISCVISD::VFROUND_NOEXCEPT_VL
@ VFROUND_NOEXCEPT_VL
Definition: RISCVISelLowering.h:242
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:236
llvm::RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: RISCVISelLowering.cpp:1195
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:235
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:44
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:208
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: TargetParser.h:161
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:245
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:41
llvm::APFloat
Definition: APFloat.h:716
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:453
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:144
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:101
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:1132
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:13352
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Definition: RISCVISelLowering.cpp:1435
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:194
llvm::RISCVISD::VFCVT_X_F_VL
@ VFCVT_X_F_VL
Definition: RISCVISelLowering.h:241
llvm::RISCVISD::VWSUB_W_VL
@ VWSUB_W_VL
Definition: RISCVISelLowering.h:266
llvm::RISCVTargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: RISCVISelLowering.cpp:1211
llvm::RISCVISD::UNZIP
@ UNZIP
Definition: RISCVISelLowering.h:130
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:273
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1313
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:62
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:161
llvm::DemandedBits
Definition: DemandedBits.h:41
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:33
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: RISCVISelLowering.cpp:11118
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:124
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:76
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:1145
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:526
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:189
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:12944
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:10328
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::RISCVISD::ADD_LO
@ ADD_LO
Definition: RISCVISelLowering.h:48
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:313
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4153
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:1102
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:1164
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:205
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:196
llvm::RISCVISD::BREV8
@ BREV8
Definition: RISCVISelLowering.h:127
llvm::RISCVISD::SADDSAT_VL
@ SADDSAT_VL
Definition: RISCVISelLowering.h:220
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
Definition: RISCVISelLowering.cpp:10062
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:191
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:165
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:13148
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:383
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:66
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:7421
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:152
llvm::RISCVISD::ORC_B
@ ORC_B
Definition: RISCVISelLowering.h:128
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:13222
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:284
RISCV.h
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:43
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:342
llvm::SystemZ::VectorBits
const unsigned VectorBits
Definition: SystemZ.h:154
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:228
llvm::RISCVISD::USUBSAT_VL
@ USUBSAT_VL
Definition: RISCVISelLowering.h:223
llvm::RISCVISD::FCVT_XU
@ FCVT_XU
Definition: RISCVISelLowering.h:107
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1636
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:73
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:192
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RISCVISD::STRICT_FCVT_WU_RV64
@ STRICT_FCVT_WU_RV64
Definition: RISCVISelLowering.h:323
llvm::RISCVTargetLowering::isLegalScaleForGatherScatter
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
Definition: RISCVISelLowering.h:599
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:135
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:12721
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand
uint8_t ScalarOperand
Definition: RISCVISelLowering.h:737
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:247
llvm::RISCVTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: RISCVISelLowering.cpp:13202
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::RISCVISD::FCVT_X
@ FCVT_X
Definition: RISCVISelLowering.h:106
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::RISCVISD::VWADD_VL
@ VWADD_VL
Definition: RISCVISelLowering.h:260
llvm::RISCVISD::VWADDU_VL
@ VWADDU_VL
Definition: RISCVISelLowering.h:261
Node
Definition: ItaniumDemangle.h:156
llvm::RISCVISD::FCVT_WU_RV64
@ FCVT_WU_RV64
Definition: RISCVISelLowering.h:113
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.cpp:1231
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:42
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:330
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:229
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:77
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
Definition: RISCVISelLowering.cpp:1583
llvm::RISCVISD::VWMULU_VL
@ VWMULU_VL
Definition: RISCVISelLowering.h:258
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:188
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:1422
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:289
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:67
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
CallingConvLower.h
llvm::RISCVISD::ADD_TPREL
@ ADD_TPREL
Definition: RISCVISelLowering.h:56
llvm::RISCVISD::FMV_X_SIGNEXTH
@ FMV_X_SIGNEXTH
Definition: RISCVISelLowering.h:99
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand
uint8_t VLOperand
Definition: RISCVISelLowering.h:738
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:12384
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:246
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand
bool hasScalarOperand() const
Definition: RISCVISelLowering.h:739
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:294
llvm::RISCVTargetLowering::getTargetConstantFromLoad
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
Definition: RISCVISelLowering.cpp:10402
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:335
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:3535
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:142
llvm::RISCVISD::VP_MERGE_VL
@ VP_MERGE_VL
Definition: RISCVISelLowering.h:280
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:12958
llvm::RISCVTargetLowering::getLMUL
static RISCVII::VLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1557
llvm::RISCVTargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: RISCVISelLowering.cpp:13175
llvm::RISCVTargetLowering::shouldScalarizeBinop
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
Definition: RISCVISelLowering.cpp:1394
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:139
llvm::RISCVISD::VWMULSU_VL
@ VWMULSU_VL
Definition: RISCVISelLowering.h:259
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:458
llvm::RISCVISD::UADDSAT_VL
@ UADDSAT_VL
Definition: RISCVISelLowering.h:221
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVISD::VWADDU_W_VL
@ VWADDU_W_VL
Definition: RISCVISelLowering.h:265
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:295
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:195
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:13463
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:213
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:45
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:735
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::FCVT_W_RV64
@ FCVT_W_RV64
Definition: RISCVISelLowering.h:112
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:187
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1910
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:218
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1319
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:308
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:1191
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:1485
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::RISCVTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: RISCVISelLowering.cpp:13192
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:13253
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:32
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RISCVISD::VFCVT_RM_X_F_VL
@ VFCVT_RM_X_F_VL
Definition: RISCVISelLowering.h:243
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:466
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:12407
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:469
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:230
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:12553
llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL
@ SPLAT_VECTOR_SPLIT_I64_VL
Definition: RISCVISelLowering.h:150
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:166
llvm::RISCVTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: RISCVISelLowering.cpp:1359
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:1022
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:155
llvm::RISCVISD::SSUBSAT_VL
@ SSUBSAT_VL
Definition: RISCVISelLowering.h:222
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:238
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:1473
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:81
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1819
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:160
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:237
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:212
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:3382
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:372
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:209
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:13136
llvm::LLT
Definition: LowLevelTypeImpl.h:39