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RISCVISelLowering.h
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1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
22#include <optional>
23
24namespace llvm {
25class InstructionCost;
26class RISCVSubtarget;
27struct RISCVRegisterInfo;
28
29namespace RISCVISD {
30// clang-format off
31enum NodeType : unsigned {
37 /// Select with condition operator - This selects between a true value and
38 /// a false value (ops #3 and #4) based on the boolean result of comparing
39 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
40 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
41 /// The lhs and rhs are XLenVT integers. The true and false values can be
42 /// integer or floating point.
48
49 // Add the Lo 12 bits from an address. Selected to ADDI.
51 // Get the Hi 20 bits from an address. Selected to LUI.
53
54 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
56
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
59
60 // Multiply high for signedxunsigned.
62 // RV64I shifts, directly matching the semantics of the named RISC-V
63 // instructions.
67 // 32-bit operations from RV64M that can't be simply matched with a pattern
68 // at instruction selection time. These have undefined behavior for division
69 // by 0 or overflow (divw) like their target independent counterparts.
73 // RV64IB rotates, directly matching the semantics of the named RISC-V
74 // instructions.
77 // RV64IZbb bit counting instructions directly matching the semantics of the
78 // named RISC-V instructions.
81
82 // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
84
85 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
86 // XLEN is the only legal integer width.
87 //
88 // FMV_H_X matches the semantics of the FMV.H.X.
89 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
90 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
91 // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
92 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
93 //
94 // This is a more convenient semantic for producing dagcombines that remove
95 // unnecessary GPR->FPR->GPR moves.
101 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
102 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
103 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
104 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
107 // FP to 32 bit int conversions for RV64. These are used to keep track of the
108 // result being sign extended to 64 bit. These saturate out of range inputs.
109 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
110 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
113
116
117 // Rounds an FP value to its corresponding integer in the same FP format.
118 // First operand is the value to round, the second operand is the largest
119 // integer that can be represented exactly in the FP format. This will be
120 // expanded into multiple instructions and basic blocks with a custom
121 // inserter.
123
125
126 // Floating point fmax and fmin matching the RISC-V instruction semantics.
128
129 // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
130 // It takes a chain operand and another two target constant operands (the
131 // CSR numbers of the low and high parts of the counter).
133
134 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
135 // XLenVT.
140
141 // Scalar cryptography
146
147 // May-Be-Operations
149
150 // Vector Extension
152 // VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
153 // for the VL value to be used for the operation. The first operand is
154 // passthru operand.
156 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
157 // for the VL value to be used for the operation. The first operand is
158 // passthru operand.
160 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
161 // for the VL value to be used for the operation. The first operand is
162 // passthru operand.
164 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
165 // extended from the vector element size.
167 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
169 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
171 // Splats an 64-bit value that has been split into two i32 parts. This is
172 // expanded late to two scalar stores and a stride 0 vector load.
173 // The first operand is passthru operand.
175 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
176 // mask and VL operand.
178 // Matches the semantics of vslideup/vslidedown. The first operand is the
179 // pass-thru operand, the second is the source vector, the third is the XLenVT
180 // index (either constant or non-constant), the fourth is the mask, the fifth
181 // is the VL and the sixth is the policy.
184 // Matches the semantics of vslide1up/slide1down. The first operand is
185 // passthru operand, the second is source vector, third is the XLenVT scalar
186 // value. The fourth and fifth operands are the mask and VL operands.
189 // Matches the semantics of vfslide1up/vfslide1down. The first operand is
190 // passthru operand, the second is source vector, third is a scalar value
191 // whose type matches the element type of the vectors. The fourth and fifth
192 // operands are the mask and VL operands.
195 // Matches the semantics of the vid.v instruction, with a mask and VL
196 // operand.
198 // Matches the semantics of the vfcnvt.rod function (Convert double-width
199 // float to single-width float, rounding towards odd). Takes a double-width
200 // float vector and produces a single-width float vector. Also has a mask and
201 // VL operand.
203 // These nodes match the semantics of the corresponding RVV vector reduction
204 // instructions. They produce a vector result which is the reduction
205 // performed over the second vector operand plus the first element of the
206 // third vector operand. The first operand is the pass-thru operand. The
207 // second operand is an unconstrained vector type, and the result, first, and
208 // third operand's types are expected to be the corresponding full-width
209 // LMUL=1 type for the second operand:
210 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
211 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
212 // The different in types does introduce extra vsetvli instructions but
213 // similarly it reduces the number of registers consumed per reduction.
214 // Also has a mask and VL operand.
227
228 // Vector binary ops with a merge as a third operand, a mask as a fourth
229 // operand, and VL as a fifth operand.
249
255
260
261 // Averaging adds of unsigned integers.
263 // Rounding averaging adds of unsigned integers.
265
274
275 // Vector unary ops with a mask as a second operand and VL as a third operand.
280 FCOPYSIGN_VL, // Has a merge operand
286 VFCVT_RM_X_F_VL, // Has a rounding mode operand.
287 VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
290 VFCVT_RM_F_X_VL, // Has a rounding mode operand.
291 VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
294
295 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
300
301 // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth
302 // operand.
307
308 // Widening instructions with a merge value a third operand, a mask as a
309 // fourth operand, and VL as a fifth operand.
322
328
329 // Widening ternary operations with a mask as the fourth operand and VL as the
330 // fifth operand.
334
335 // Narrowing logical shift right.
336 // Operands are (source, shift, passthru, mask, vl)
338
339 // Vector compare producing a mask. Fourth operand is input mask. Fifth
340 // operand is VL.
342
343 // General vmerge node with mask, true, false, passthru, and vl operands.
344 // Tail agnostic vselect can be implemented by setting passthru to undef.
346
347 // Mask binary operators.
351
352 // Set mask vector to all zeros or ones.
355
356 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
357 // for passthru and VL. Operands are (src, index, mask, passthru, vl).
361
362 // Vector sign/zero extend with additional mask & VL operands.
365
366 // vcpop.m with additional mask and VL operands.
368
369 // vfirst.m with additional mask and VL operands.
371
373
374 // Read VLENB CSR
376 // Reads value of CSR.
377 // The first operand is a chain pointer. The second specifies address of the
378 // required CSR. Two results are produced, the read value and the new chain
379 // pointer.
381 // Write value to CSR.
382 // The first operand is a chain pointer, the second specifies address of the
383 // required CSR and the third is the value to write. The result is the new
384 // chain pointer.
386 // Read and write value of CSR.
387 // The first operand is a chain pointer, the second specifies address of the
388 // required CSR and the third is the value to write. Two results are produced,
389 // the value read before the modification and the new chain pointer.
391
392 // Branchless select operations, matching the semantics of the instructions
393 // defined in Zicond or XVentanaCondOps.
394 CZERO_EQZ, // vt.maskc for XVentanaCondOps.
395 CZERO_NEZ, // vt.maskcn for XVentanaCondOps.
396
397 // FP to 32 bit int conversions for RV64. These are used to keep track of the
398 // result being sign extended to 64 bit. These saturate out of range inputs.
422
449
450 // WARNING: Do not add anything in the end unless you want the node to
451 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
452 // opcodes will be thought as target memory ops!
453
459};
460// clang-format on
461} // namespace RISCVISD
462
464 const RISCVSubtarget &Subtarget;
465
466public:
467 explicit RISCVTargetLowering(const TargetMachine &TM,
468 const RISCVSubtarget &STI);
469
470 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
471
472 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
473 MachineFunction &MF,
474 unsigned Intrinsic) const override;
475 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
476 unsigned AS,
477 Instruction *I = nullptr) const override;
478 bool isLegalICmpImmediate(int64_t Imm) const override;
479 bool isLegalAddImmediate(int64_t Imm) const override;
480 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
481 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
482 bool isZExtFree(SDValue Val, EVT VT2) const override;
483 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
484 bool signExtendConstant(const ConstantInt *CI) const override;
485 bool isCheapToSpeculateCttz(Type *Ty) const override;
486 bool isCheapToSpeculateCtlz(Type *Ty) const override;
487 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
488 bool hasAndNotCompare(SDValue Y) const override;
489 bool hasBitTest(SDValue X, SDValue Y) const override;
492 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
493 SelectionDAG &DAG) const override;
494 /// Return true if the (vector) instruction I will be lowered to an instruction
495 /// with a scalar splat operand for the given Operand number.
496 bool canSplatOperand(Instruction *I, int Operand) const;
497 /// Return true if a vector instruction will lower to a target instruction
498 /// able to splat the given operand.
499 bool canSplatOperand(unsigned Opcode, int Operand) const;
501 SmallVectorImpl<Use *> &Ops) const override;
502 bool shouldScalarizeBinop(SDValue VecOp) const override;
503 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
504 std::pair<int, bool> getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
505 bool isFPImmLegal(const APFloat &Imm, EVT VT,
506 bool ForCodeSize) const override;
507 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
508 unsigned Index) const override;
509
510 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
511
512 bool preferScalarizeSplat(SDNode *N) const override;
513
514 bool softPromoteHalfType() const override { return true; }
515
516 /// Return the register type for a given MVT, ensuring vectors are treated
517 /// as a series of gpr sized integers.
519 EVT VT) const override;
520
521 /// Return the number of registers for a given MVT, ensuring vectors are
522 /// treated as a series of gpr sized integers.
525 EVT VT) const override;
526
529 EVT &IntermediateVT,
530 unsigned &NumIntermediates,
531 MVT &RegisterVT) const override;
532
533 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
534 EVT VT) const override;
535
536 /// Return true if the given shuffle mask can be codegen'd directly, or if it
537 /// should be stack expanded.
538 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
539
540 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
541 // If the pair to store is a mixture of float and int values, we will
542 // save two bitwise instructions and one float-to-int instruction and
543 // increase one store instruction. There is potentially a more
544 // significant benefit because it avoids the float->int domain switch
545 // for input value. So It is more likely a win.
546 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
547 (LTy.isInteger() && HTy.isFloatingPoint()))
548 return true;
549 // If the pair only contains int values, we will save two bitwise
550 // instructions and increase one store instruction (costing one more
551 // store buffer). Since the benefit is more blurred we leave such a pair
552 // out until we get testcase to prove it is a win.
553 return false;
554 }
555
556 bool
558 unsigned DefinedValues) const override;
559
560 /// Return the cost of LMUL for linear operations.
562
567
568 // Provide custom lowering hooks for some operations.
569 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
571 SelectionDAG &DAG) const override;
572
573 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
574
576 const APInt &DemandedElts,
577 TargetLoweringOpt &TLO) const override;
578
580 KnownBits &Known,
581 const APInt &DemandedElts,
582 const SelectionDAG &DAG,
583 unsigned Depth) const override;
585 const APInt &DemandedElts,
586 const SelectionDAG &DAG,
587 unsigned Depth) const override;
588
589 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
590
591 // This method returns the name of a target specific DAG node.
592 const char *getTargetNodeName(unsigned Opcode) const override;
593
595 getTargetMMOFlags(const Instruction &I) const override;
596
598 getTargetMMOFlags(const MemSDNode &Node) const override;
599
600 bool
602 const MemSDNode &NodeY) const override;
603
604 ConstraintType getConstraintType(StringRef Constraint) const override;
605
607 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
608
609 std::pair<unsigned, const TargetRegisterClass *>
611 StringRef Constraint, MVT VT) const override;
612
614 std::vector<SDValue> &Ops,
615 SelectionDAG &DAG) const override;
616
619 MachineBasicBlock *BB) const override;
620
622 SDNode *Node) const override;
623
625 EVT VT) const override;
626
627 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
628 bool MathUsed) const override {
629 if (VT == MVT::i8 || VT == MVT::i16)
630 return false;
631
632 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
633 }
634
635 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
636 unsigned AddrSpace) const override {
637 // If we can replace 4 or more scalar stores, there will be a reduction
638 // in instructions even after we add a vector constant load.
639 return NumElem >= 4;
640 }
641
642 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
643 return VT.isScalarInteger();
644 }
645 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
646
647 bool isCtpopFast(EVT VT) const override;
648
649 unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
650
651 bool preferZeroCompareBranch() const override { return true; }
652
653 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
654 return isa<LoadInst>(I) || isa<StoreInst>(I);
655 }
657 AtomicOrdering Ord) const override;
659 AtomicOrdering Ord) const override;
660
662 EVT VT) const override;
663
665 return ISD::SIGN_EXTEND;
666 }
667
669
671 unsigned KeptBits) const override;
672
675 unsigned ExpansionFactor) const override {
679 ExpansionFactor);
680 }
681
683 CombineLevel Level) const override;
684
685 /// If a physical register, this returns the register that receives the
686 /// exception address on entry to an EH pad.
688 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
689
690 /// If a physical register, this returns the register that receives the
691 /// exception typeid on entry to a landing pad.
693 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
694
695 bool shouldExtendTypeInLibCall(EVT Type) const override;
696 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
697
698 /// Returns the register with the specified architectural or ABI name. This
699 /// method is necessary to lower the llvm.read_register.* and
700 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
701 /// with the clang -ffixed-xX flag for access to be allowed.
702 Register getRegisterByName(const char *RegName, LLT VT,
703 const MachineFunction &MF) const override;
704
705 // Lower incoming arguments, copy physregs into vregs
707 bool IsVarArg,
709 const SDLoc &DL, SelectionDAG &DAG,
710 SmallVectorImpl<SDValue> &InVals) const override;
712 bool IsVarArg,
714 LLVMContext &Context) const override;
715 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
717 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
718 SelectionDAG &DAG) const override;
720 SmallVectorImpl<SDValue> &InVals) const override;
721
723 Type *Ty) const override;
724 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
725 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
726 bool shouldConsiderGEPOffsetSplit() const override { return true; }
727
728 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
729 SDValue C) const override;
730
732 SDValue ConstNode) const override;
733
735 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
737 Value *AlignedAddr, Value *Incr,
738 Value *Mask, Value *ShiftAmt,
739 AtomicOrdering Ord) const override;
744 Value *AlignedAddr, Value *CmpVal,
745 Value *NewVal, Value *Mask,
746 AtomicOrdering Ord) const override;
747
748 /// Returns true if the target allows unaligned memory accesses of the
749 /// specified type.
751 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
753 unsigned *Fast = nullptr) const override;
754
756 const AttributeList &FuncAttributes) const override;
757
759 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
760 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
761 const override;
762
764 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
765 unsigned NumParts, MVT PartVT, EVT ValueVT,
766 std::optional<CallingConv::ID> CC) const override;
767
768 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
769 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
770
771 static RISCVII::VLMUL getLMUL(MVT VT);
772 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
773 unsigned MinSize) {
774 // Original equation:
775 // VLMAX = (VectorBits / EltSize) * LMUL
776 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
777 // The following equations have been reordered to prevent loss of precision
778 // when calculating fractional LMUL.
779 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
780 }
781
782 // Return inclusive (low, high) bounds on the value of VLMAX for the
783 // given scalable container type given known bounds on VLEN.
784 static std::pair<unsigned, unsigned>
785 computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget);
786
787 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
788 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
789 static unsigned getRegClassIDForVecVT(MVT VT);
790 static std::pair<unsigned, unsigned>
792 unsigned InsertExtractIdx,
793 const RISCVRegisterInfo *TRI);
795
796 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
797
798 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
799
800 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
801
802 unsigned getJumpTableEncoding() const override;
803
805 const MachineBasicBlock *MBB,
806 unsigned uid,
807 MCContext &Ctx) const override;
808
809 bool isVScaleKnownToBeAPowerOfTwo() const override;
810
812 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
815 SelectionDAG &DAG) const override;
818 SelectionDAG &DAG) const override;
819
821 uint64_t ElemSize) const override {
822 // Scaled addressing not supported on indexed load/stores
823 return Scale == 1;
824 }
825
826 /// If the target has a standard location for the stack protector cookie,
827 /// returns the address of that location. Otherwise, returns nullptr.
828 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
829
830 /// Returns whether or not generating a interleaved load/store intrinsic for
831 /// this type will be legal.
832 bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
833 Align Alignment, unsigned AddrSpace,
834 const DataLayout &) const;
835
836 /// Return true if a stride load store of the given result type and
837 /// alignment is legal.
838 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
839
840 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
841
842 bool fallBackToDAGISel(const Instruction &Inst) const override;
843
846 ArrayRef<unsigned> Indices,
847 unsigned Factor) const override;
848
850 unsigned Factor) const override;
851
853 LoadInst *LI) const override;
854
856 StoreInst *SI) const override;
857
858 bool supportKCFIBundles() const override { return true; }
859
862 const TargetInstrInfo *TII) const override;
863
864 /// RISCVCCAssignFn - This target-specific function extends the default
865 /// CCValAssign with additional information used to lower RISC-V calling
866 /// conventions.
868 unsigned ValNo, MVT ValVT, MVT LocVT,
869 CCValAssign::LocInfo LocInfo,
870 ISD::ArgFlagsTy ArgFlags, CCState &State,
871 bool IsFixed, bool IsRet, Type *OrigTy,
872 const RISCVTargetLowering &TLI,
873 std::optional<unsigned> FirstMaskArgument);
874
875private:
876 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
877 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
878 RISCVCCAssignFn Fn) const;
879 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
881 bool IsRet, CallLoweringInfo *CLI,
882 RISCVCCAssignFn Fn) const;
883
884 template <class NodeTy>
885 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
886 bool IsExternWeak = false) const;
887 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
888 bool UseGOT) const;
889 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
890 SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
891
892 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
893 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
894 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
895 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
896 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
897 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
898 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
899 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
900 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
901 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
902 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
903 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
904 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
905 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
906 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
907 int64_t ExtTrueVal) const;
908 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
909 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
910 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
911 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
912 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
913 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
914 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
915 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
916 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
917 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
918 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
919 bool IsVP) const;
920 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
921 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
922 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
923 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
924 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
925 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
926 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
927 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
928 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
929 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
930 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
931 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
932 SelectionDAG &DAG) const;
933 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
934 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
935 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
936 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
937 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
938 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
939 SelectionDAG &DAG) const;
940 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
941 SDValue lowerUnsignedAvgFloor(SDValue Op, SelectionDAG &DAG) const;
942 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
943 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
944 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
945 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
946 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
947 SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
948 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
949 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
950 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
951 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
952 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
953 unsigned ExtendOpc) const;
954 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
955 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
956
957 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
958 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
959
960 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
961
962 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
963
964 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
965 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
966
967 bool isEligibleForTailCallOptimization(
968 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
969 const SmallVector<CCValAssign, 16> &ArgLocs) const;
970
971 /// Generate error diagnostics if any register used by CC has been marked
972 /// reserved.
973 void validateCCReservedRegs(
974 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
975 MachineFunction &MF) const;
976
977 bool useRVVForFixedLengthVectorVT(MVT VT) const;
978
979 MVT getVPExplicitVectorLengthTy() const override;
980
981 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
982 bool IsScalable) const override;
983
984 /// RVV code generation for fixed length vectors does not lower all
985 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
986 /// merge. However, merging them creates a BUILD_VECTOR that is just as
987 /// illegal as the original, thus leading to an infinite legalisation loop.
988 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
989 /// this override can be removed.
990 bool mergeStoresAfterLegalization(EVT VT) const override;
991
992 /// Disable normalizing
993 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
994 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
995 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
996 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
997 return false;
998 };
999
1000 /// For available scheduling models FDIV + two independent FMULs are much
1001 /// faster than two FDIVs.
1002 unsigned combineRepeatedFPDivisors() const override;
1003
1004 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1005 SmallVectorImpl<SDNode *> &Created) const override;
1006
1007 bool shouldFoldSelectWithSingleBitTest(EVT VT,
1008 const APInt &AndMask) const override;
1009
1010 unsigned getMinimumJumpTableEntries() const override;
1011};
1012
1013namespace RISCV {
1014
1015bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1016 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1017 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1018 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1019 std::optional<unsigned> FirstMaskArgument);
1020
1021bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1022 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1023 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1024 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1025 std::optional<unsigned> FirstMaskArgument);
1026
1027bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
1028 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
1029 CCState &State);
1030
1031ArrayRef<MCPhysReg> getArgGPRs(const RISCVABI::ABI ABI);
1032
1033} // end namespace RISCV
1034
1035namespace RISCVVIntrinsicsTable {
1036
1038 unsigned IntrinsicID;
1040 uint8_t VLOperand;
1041 bool hasScalarOperand() const {
1042 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
1043 return ScalarOperand != 0xF;
1044 }
1045 bool hasVLOperand() const {
1046 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
1047 return VLOperand != 0x1F;
1048 }
1049};
1050
1051using namespace RISCV;
1052
1053#define GET_RISCVVIntrinsicsTable_DECL
1054#include "RISCVGenSearchableTables.inc"
1055#undef GET_RISCVVIntrinsicsTable_DECL
1056
1057} // end namespace RISCVVIntrinsicsTable
1058
1059} // end namespace llvm
1060
1061#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:539
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:748
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:674
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
This is an abstract virtual class for memory operations.
static std::pair< unsigned, unsigned > computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget)
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
InstructionCost getVRGatherVVCost(MVT VT) const
Return the cost of a vrgather.vv instruction for the type VT.
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
std::pair< int, bool > getLegalZfaFPImm(const APFloat &Imm, EVT VT) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
const RISCVSubtarget & getSubtarget() const
TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI) const override
Lower an interleave intrinsic to a target specific store intrinsic.
bool preferScalarizeSplat(SDNode *N) const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
InstructionCost getVRGatherVICost(MVT VT) const
Return the cost of a vrgather.vi (or vx) instruction for the type VT.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const override
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
InstructionCost getLMULCost(MVT VT) const
Return the cost of LMUL for linear operations.
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
InstructionCost getVSlideVICost(MVT VT) const
Return the cost of a vslidedown.vi or vslideup.vi instruction for the type VT.
bool fallBackToDAGISel(const Instruction &Inst) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vlsegN intrinsic.
bool isCtpopFast(EVT VT) const override
Return true if ctpop instruction is fast.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getContainerForFixedLengthVector(MVT VT) const
static unsigned getRegClassIDForVecVT(MVT VT)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
InstructionCost getVSlideVXCost(MVT VT) const
Return the cost of a vslidedown.vx or vslideup.vx instruction for the type VT.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool softPromoteHalfType() const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vssegN intrinsic.
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isLegalElementTypeForRVV(EVT ScalarTy) const
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II, LoadInst *LI) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
static RISCVII::VLMUL getLMUL(MVT VT)
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool shouldConsiderGEPOffsetSplit() const override
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const
Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const
Return true if a stride load store of the given result type and alignment is legal.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1389
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1401
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1461
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1395
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1512
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
ArrayRef< MCPhysReg > getArgGPRs(const RISCVABI::ABI ABI)
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static constexpr unsigned RVVBitsPerBlock
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
AtomicOrdering
Atomic ordering for LLVM's memory model.
CombineLevel
Definition: DAGCombine.h:15
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:139
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
This structure contains all information that is necessary for lowering calls.