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RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
21 
22 namespace llvm {
23 class RISCVSubtarget;
24 struct RISCVRegisterInfo;
25 namespace RISCVISD {
26 enum NodeType : unsigned {
33  /// Select with condition operator - This selects between a true value and
34  /// a false value (ops #3 and #4) based on the boolean result of comparing
35  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
36  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
37  /// The lhs and rhs are XLenVT integers. The true and false values can be
38  /// integer or floating point.
44  // Multiply high for signedxunsigned.
46  // RV64I shifts, directly matching the semantics of the named RISC-V
47  // instructions.
51  // 32-bit operations from RV64M that can't be simply matched with a pattern
52  // at instruction selection time. These have undefined behavior for division
53  // by 0 or overflow (divw) like their target independent counterparts.
57  // RV64IB rotates, directly matching the semantics of the named RISC-V
58  // instructions.
61  // RV64IZbb bit counting instructions directly matching the semantics of the
62  // named RISC-V instructions.
65  // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
66  // instructions, but the same operand order as fshl/fshr intrinsics.
67  FSR,
68  FSL,
69  // RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
70  // but the same operand order as fshl/fshr intrinsics.
73  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
74  // XLEN is the only legal integer width.
75  //
76  // FMV_H_X matches the semantics of the FMV.H.X.
77  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
78  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
79  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
80  //
81  // This is a more convenient semantic for producing dagcombines that remove
82  // unnecessary GPR->FPR->GPR moves.
87  // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
88  // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
89  // range inputs. These are used for FP_TO_S/UINT_SAT lowering.
92  // FP to 32 bit int conversions for RV64. These are used to keep track of the
93  // result being sign extended to 64 bit. These saturate out of range inputs.
94  // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering.
97  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
98  // (returns (Lo, Hi)). It takes a chain operand.
100  // Generalized Reverse and Generalized Or-Combine - directly matching the
101  // semantics of the named RISC-V instructions. Lowered as custom nodes as
102  // TableGen chokes when faced with commutative permutations in deeply-nested
103  // DAGs. Each node takes an input operand and a control operand and outputs a
104  // bit-manipulated version of input. All operands are i32 or XLenVT.
113  // Bit Compress/Decompress implement the generic bit extract and bit deposit
114  // functions. This operation is also referred to as bit gather/scatter, bit
115  // pack/unpack, parallel extract/deposit, compress/expand, or right
116  // compress/right expand.
121  // Vector Extension
122  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
123  // for the VL value to be used for the operation.
125  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
126  // for the VL value to be used for the operation.
128  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
129  // extended from the vector element size.
131  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
133  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
135  // Splats an i64 scalar to a vector type (with element type i64) where the
136  // scalar is a sign-extended i32.
138  // Splats an 64-bit value that has been split into two i32 parts. This is
139  // expanded late to two scalar stores and a stride 0 vector load.
141  // Read VLENB CSR
143  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
144  // mask and VL operand.
146  // Matches the semantics of vslideup/vslidedown. The first operand is the
147  // pass-thru operand, the second is the source vector, the third is the
148  // XLenVT index (either constant or non-constant), the fourth is the mask
149  // and the fifth the VL.
152  // Matches the semantics of vslide1up/slide1down. The first operand is the
153  // source vector, the second is the XLenVT scalar value. The third and fourth
154  // operands are the mask and VL operands.
157  // Matches the semantics of the vid.v instruction, with a mask and VL
158  // operand.
160  // Matches the semantics of the vfcnvt.rod function (Convert double-width
161  // float to single-width float, rounding towards odd). Takes a double-width
162  // float vector and produces a single-width float vector. Also has a mask and
163  // VL operand.
165  // These nodes match the semantics of the corresponding RVV vector reduction
166  // instructions. They produce a vector result which is the reduction
167  // performed over the second vector operand plus the first element of the
168  // third vector operand. The first operand is the pass-thru operand. The
169  // second operand is an unconstrained vector type, and the result, first, and
170  // third operand's types are expected to be the corresponding full-width
171  // LMUL=1 type for the second operand:
172  // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
173  // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
174  // The different in types does introduce extra vsetvli instructions but
175  // similarly it reduces the number of registers consumed per reduction.
176  // Also has a mask and VL operand.
189 
190  // Vector binary and unary ops with a mask as a third operand, and VL as a
191  // fourth operand.
192  // FIXME: Can we replace these with ISD::VP_*?
206 
211 
235 
236  // Widening instructions
239 
240  // Vector compare producing a mask. Fourth operand is input mask. Fifth
241  // operand is VL.
243 
244  // Vector select with an additional VL operand. This operation is unmasked.
246 
247  // Mask binary operators.
251 
252  // Set mask vector to all zeros or ones.
255 
256  // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand
257  // for VL.
261 
262  // Vector sign/zero extend with additional mask & VL operands.
265 
266  // vpopc.m with additional mask and VL operands.
268 
269  // Reads value of CSR.
270  // The first operand is a chain pointer. The second specifies address of the
271  // required CSR. Two results are produced, the read value and the new chain
272  // pointer.
274  // Write value to CSR.
275  // The first operand is a chain pointer, the second specifies address of the
276  // required CSR and the third is the value to write. The result is the new
277  // chain pointer.
279  // Read and write value of CSR.
280  // The first operand is a chain pointer, the second specifies address of the
281  // required CSR and the third is the value to write. Two results are produced,
282  // the value read before the modification and the new chain pointer.
284 
285  // Memory opcodes start here.
288 
289  // WARNING: Do not add anything in the end unless you want the node to
290  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
291  // opcodes will be thought as target memory ops!
292 };
293 } // namespace RISCVISD
294 
296  const RISCVSubtarget &Subtarget;
297 
298 public:
299  explicit RISCVTargetLowering(const TargetMachine &TM,
300  const RISCVSubtarget &STI);
301 
302  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
303 
304  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
305  MachineFunction &MF,
306  unsigned Intrinsic) const override;
307  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
308  unsigned AS,
309  Instruction *I = nullptr) const override;
310  bool isLegalICmpImmediate(int64_t Imm) const override;
311  bool isLegalAddImmediate(int64_t Imm) const override;
312  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
313  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
314  bool isZExtFree(SDValue Val, EVT VT2) const override;
315  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
316  bool isCheapToSpeculateCttz() const override;
317  bool isCheapToSpeculateCtlz() const override;
319  SmallVectorImpl<Use *> &Ops) const override;
320  bool isFPImmLegal(const APFloat &Imm, EVT VT,
321  bool ForCodeSize) const override;
322 
323  bool softPromoteHalfType() const override { return true; }
324 
325  /// Return the register type for a given MVT, ensuring vectors are treated
326  /// as a series of gpr sized integers.
328  EVT VT) const override;
329 
330  /// Return the number of registers for a given MVT, ensuring vectors are
331  /// treated as a series of gpr sized integers.
333  CallingConv::ID CC,
334  EVT VT) const override;
335 
336  /// Return true if the given shuffle mask can be codegen'd directly, or if it
337  /// should be stack expanded.
338  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
339 
340  bool hasBitPreservingFPLogic(EVT VT) const override;
341  bool
343  unsigned DefinedValues) const override;
344 
345  // Provide custom lowering hooks for some operations.
346  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
348  SelectionDAG &DAG) const override;
349 
350  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
351 
353  const APInt &DemandedElts,
354  TargetLoweringOpt &TLO) const override;
355 
357  KnownBits &Known,
358  const APInt &DemandedElts,
359  const SelectionDAG &DAG,
360  unsigned Depth) const override;
362  const APInt &DemandedElts,
363  const SelectionDAG &DAG,
364  unsigned Depth) const override;
365 
366  // This method returns the name of a target specific DAG node.
367  const char *getTargetNodeName(unsigned Opcode) const override;
368 
369  ConstraintType getConstraintType(StringRef Constraint) const override;
370 
371  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
372 
373  std::pair<unsigned, const TargetRegisterClass *>
375  StringRef Constraint, MVT VT) const override;
376 
377  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
378  std::vector<SDValue> &Ops,
379  SelectionDAG &DAG) const override;
380 
383  MachineBasicBlock *BB) const override;
384 
386  EVT VT) const override;
387 
388  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
389  return VT.isScalarInteger();
390  }
391  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
392 
393  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
394  return isa<LoadInst>(I) || isa<StoreInst>(I);
395  }
397  AtomicOrdering Ord) const override;
399  AtomicOrdering Ord) const override;
400 
402  EVT VT) const override;
403 
405  return ISD::SIGN_EXTEND;
406  }
407 
409  return ISD::SIGN_EXTEND;
410  }
411 
412  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
414  return false;
415  return true;
416  }
418  CombineLevel Level) const override;
419 
420  /// If a physical register, this returns the register that receives the
421  /// exception address on entry to an EH pad.
422  Register
423  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
424 
425  /// If a physical register, this returns the register that receives the
426  /// exception typeid on entry to a landing pad.
427  Register
428  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
429 
430  bool shouldExtendTypeInLibCall(EVT Type) const override;
431  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
432 
433  /// Returns the register with the specified architectural or ABI name. This
434  /// method is necessary to lower the llvm.read_register.* and
435  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
436  /// with the clang -ffixed-xX flag for access to be allowed.
437  Register getRegisterByName(const char *RegName, LLT VT,
438  const MachineFunction &MF) const override;
439 
440  // Lower incoming arguments, copy physregs into vregs
442  bool IsVarArg,
444  const SDLoc &DL, SelectionDAG &DAG,
445  SmallVectorImpl<SDValue> &InVals) const override;
447  bool IsVarArg,
449  LLVMContext &Context) const override;
450  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
452  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
453  SelectionDAG &DAG) const override;
455  SmallVectorImpl<SDValue> &InVals) const override;
456 
458  Type *Ty) const override {
459  return true;
460  }
461  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
462  bool shouldConsiderGEPOffsetSplit() const override { return true; }
463 
465  SDValue C) const override;
466 
467  bool isMulAddWithConstProfitable(const SDValue &AddNode,
468  const SDValue &ConstNode) const override;
469 
471  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
473  Value *AlignedAddr, Value *Incr,
474  Value *Mask, Value *ShiftAmt,
475  AtomicOrdering Ord) const override;
479  AtomicCmpXchgInst *CI,
480  Value *AlignedAddr, Value *CmpVal,
481  Value *NewVal, Value *Mask,
482  AtomicOrdering Ord) const override;
483 
484  /// Returns true if the target allows unaligned memory accesses of the
485  /// specified type.
487  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
489  bool *Fast = nullptr) const override;
490 
492  SDValue Val, SDValue *Parts,
493  unsigned NumParts, MVT PartVT,
494  Optional<CallingConv::ID> CC) const override;
495 
496  SDValue
498  const SDValue *Parts, unsigned NumParts,
499  MVT PartVT, EVT ValueVT,
500  Optional<CallingConv::ID> CC) const override;
501 
502  static RISCVII::VLMUL getLMUL(MVT VT);
503  static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
504  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
505  static unsigned getRegClassIDForVecVT(MVT VT);
506  static std::pair<unsigned, unsigned>
508  unsigned InsertExtractIdx,
509  const RISCVRegisterInfo *TRI);
511 
512  bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
513 
514  bool isLegalElementTypeForRVV(Type *ScalarTy) const;
515 
516 private:
517  /// RISCVCCAssignFn - This target-specific function extends the default
518  /// CCValAssign with additional information used to lower RISC-V calling
519  /// conventions.
520  typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
521  unsigned ValNo, MVT ValVT, MVT LocVT,
522  CCValAssign::LocInfo LocInfo,
523  ISD::ArgFlagsTy ArgFlags, CCState &State,
524  bool IsFixed, bool IsRet, Type *OrigTy,
525  const RISCVTargetLowering &TLI,
526  Optional<unsigned> FirstMaskArgument);
527 
528  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
529  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
530  RISCVCCAssignFn Fn) const;
531  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
533  bool IsRet, CallLoweringInfo *CLI,
534  RISCVCCAssignFn Fn) const;
535 
536  template <class NodeTy>
537  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
538 
539  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
540  bool UseGOT) const;
541  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
542 
543  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
555  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
556  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
557  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
558  int64_t ExtTrueVal) const;
559  SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
560  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
561  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
562  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
563  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
564  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
565  SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
566  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
567  SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
568  bool IsVP) const;
569  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
570  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
571  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
572  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
573  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
574  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
575  SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
576  SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
577  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
578  SelectionDAG &DAG) const;
579  SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
580  SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
581  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
582  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
583  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
584  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
585  unsigned MaskOpc,
586  unsigned VecOpc) const;
587  SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
588  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
589  SelectionDAG &DAG) const;
590  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
591  bool HasMask = true) const;
592  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
593  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
594  unsigned ExtendOpc) const;
595  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
596  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
597 
598  SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
599  SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
600 
601  bool isEligibleForTailCallOptimization(
602  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
603  const SmallVector<CCValAssign, 16> &ArgLocs) const;
604 
605  /// Generate error diagnostics if any register used by CC has been marked
606  /// reserved.
607  void validateCCReservedRegs(
608  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
609  MachineFunction &MF) const;
610 
611  bool useRVVForFixedLengthVectorVT(MVT VT) const;
612 
613  MVT getVPExplicitVectorLengthTy() const override;
614 
615  /// RVV code generation for fixed length vectors does not lower all
616  /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
617  /// merge. However, merging them creates a BUILD_VECTOR that is just as
618  /// illegal as the original, thus leading to an infinite legalisation loop.
619  /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
620  /// this override can be removed.
621  bool mergeStoresAfterLegalization(EVT VT) const override;
622 };
623 
624 namespace RISCV {
625 // We use 64 bits as the known part in the scalable vector types.
626 static constexpr unsigned RVVBitsPerBlock = 64;
627 } // namespace RISCV
628 
629 namespace RISCVVIntrinsicsTable {
630 
632  unsigned IntrinsicID;
633  uint8_t SplatOperand;
634 };
635 
636 using namespace RISCV;
637 
638 #define GET_RISCVVIntrinsicsTable_DECL
639 #include "RISCVGenSearchableTables.inc"
640 
641 } // end namespace RISCVVIntrinsicsTable
642 
643 } // end namespace llvm
644 
645 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:9707
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:202
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:99
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:194
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:134
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:27
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:188
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:222
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:231
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:48
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:7733
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:1073
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:283
llvm::RISCVISD::UNSHFL
@ UNSHFL
Definition: RISCVISelLowering.h:111
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:226
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4155
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.h:457
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:225
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:47
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:83
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:55
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:258
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:180
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:9283
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:248
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:7304
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:228
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:264
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:956
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::SplatOperand
uint8_t SplatOperand
Definition: RISCVISelLowering.h:633
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:9794
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:9608
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:187
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:195
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RISCVISD::SHFLW
@ SHFLW
Definition: RISCVISelLowering.h:110
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:408
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:193
llvm::Optional< CallingConv::ID >
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:250
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:9525
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:9535
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:9544
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:183
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1296
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:9810
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:8435
llvm::RISCVISD::VSE_VL
@ VSE_VL
Definition: RISCVISelLowering.h:287
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:1081
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:9109
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:159
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:7204
llvm::RISCVISD::VWMUL_VL
@ VWMUL_VL
Definition: RISCVISelLowering.h:237
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:263
TargetLowering.h
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:84
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:6668
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1345
llvm::RISCVISD::VPOPC_VL
@ VPOPC_VL
Definition: RISCVISelLowering.h:267
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:221
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:9727
llvm::RISCVISD::VLE_VL
@ VLE_VL
Definition: RISCVISelLowering.h:286
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:1168
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:632
llvm::RISCVISD::SPLAT_VECTOR_I64
@ SPLAT_VECTOR_I64
Definition: RISCVISelLowering.h:137
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:1077
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:32
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:253
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1273
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:212
llvm::RISCVISD::FSL
@ FSL
Definition: RISCVISelLowering.h:68
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:227
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:9852
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:8670
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:9712
llvm::RISCVISD::FCVT_X_RTZ
@ FCVT_X_RTZ
Definition: RISCVISelLowering.h:90
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:391
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:85
llvm::RISCVISD::FSLW
@ FSLW
Definition: RISCVISelLowering.h:72
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:245
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:223
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::GREVW
@ GREVW
Definition: RISCVISelLowering.h:106
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:1035
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:201
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:9734
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:54
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:412
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:63
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:164
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:217
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:216
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:42
llvm::RISCVISD::FP_TO_UINT_VL
@ FP_TO_UINT_VL
Definition: RISCVISelLowering.h:230
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:199
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:626
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:232
llvm::RISCVISD::GREV
@ GREV
Definition: RISCVISelLowering.h:105
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:39
llvm::RISCVISD::GORC
@ GORC
Definition: RISCVISelLowering.h:107
llvm::APFloat
Definition: APFloat.h:701
llvm::RISCVTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(const SDValue &AddNode, const SDValue &ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: RISCVISelLowering.cpp:9771
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:388
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:132
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:86
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:1031
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:184
llvm::RISCVISD::BCOMPRESS
@ BCOMPRESS
Definition: RISCVISelLowering.h:117
llvm::RISCVISD::GORCW
@ GORCW
Definition: RISCVISelLowering.h:108
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:242
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:45
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:151
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:205
llvm::RISCVISD::BDECOMPRESSW
@ BDECOMPRESSW
Definition: RISCVISelLowering.h:120
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:59
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:1042
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:462
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:179
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:9464
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:7405
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVISD::UNSHFLW
@ UNSHFLW
Definition: RISCVISelLowering.h:112
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:278
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3745
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:1005
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:1059
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:196
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:186
llvm::RISCVISD::SADDSAT_VL
@ SADDSAT_VL
Definition: RISCVISelLowering.h:207
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: RISCVISelLowering.cpp:7156
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:181
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:155
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:9660
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:323
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:49
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:5442
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:142
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:9686
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:249
RISCV.h
llvm::RISCVISD::FSRW
@ FSRW
Definition: RISCVISelLowering.h:71
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:41
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:302
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:213
llvm::RISCVISD::USUBSAT_VL
@ USUBSAT_VL
Definition: RISCVISelLowering.h:210
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1308
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:56
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT VT) const override
Definition: RISCVISelLowering.cpp:9682
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:182
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:124
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:9259
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:234
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:40
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:60
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
Definition: RISCVISelLowering.cpp:1255
llvm::RISCVISD::VWMULU_VL
@ VWMULU_VL
Definition: RISCVISelLowering.h:238
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:178
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:1155
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:254
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:50
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:8970
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:233
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:259
llvm::RISCVISD::FCVT_XU_RTZ
@ FCVT_XU_RTZ
Definition: RISCVISelLowering.h:91
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:295
llvm::RISCVISD::FCVT_W_RTZ_RV64
@ FCVT_W_RTZ_RV64
Definition: RISCVISelLowering.h:95
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:2345
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:130
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:9478
llvm::RISCVTargetLowering::getLMUL
static RISCVII::VLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1229
llvm::RISCVISD::FSR
@ FSR
Definition: RISCVISelLowering.h:67
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:127
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:393
llvm::RISCVISD::UADDSAT_VL
@ UADDSAT_VL
Definition: RISCVISelLowering.h:208
llvm::RISCVISD::FP_TO_SINT_VL
@ FP_TO_SINT_VL
Definition: RISCVISelLowering.h:229
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:260
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:185
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:9897
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:204
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:43
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:631
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:177
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1532
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:224
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:273
llvm::RISCVISD::SHFL
@ SHFL
Definition: RISCVISelLowering.h:109
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:1185
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:95
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:9717
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:669
llvm::RISCVISD::BDECOMPRESS
@ BDECOMPRESS
Definition: RISCVISelLowering.h:119
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::BCOMPRESSW
@ BCOMPRESSW
Definition: RISCVISelLowering.h:118
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:8993
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:404
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:215
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:9105
llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL
@ SPLAT_VECTOR_SPLIT_I64_VL
Definition: RISCVISelLowering.h:140
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:156
llvm::RISCVTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: RISCVISelLowering.cpp:1088
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:941
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:145
llvm::RISCVISD::FMA_VL
@ FMA_VL
Definition: RISCVISelLowering.h:219
llvm::RISCVISD::SSUBSAT_VL
@ SSUBSAT_VL
Definition: RISCVISelLowering.h:209
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:220
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:1174
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:64
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1472
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:29
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:150
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:218
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:203
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:1537
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:295
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:200
llvm::RISCVISD::FCVT_WU_RTZ_RV64
@ FCVT_WU_RTZ_RV64
Definition: RISCVISelLowering.h:96
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:9652
llvm::LLT
Definition: LowLevelTypeImpl.h:40