LLVM  13.0.0git
RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
20 
21 namespace llvm {
22 class RISCVSubtarget;
23 struct RISCVRegisterInfo;
24 namespace RISCVISD {
25 enum NodeType : unsigned {
32  /// Select with condition operator - This selects between a true value and
33  /// a false value (ops #3 and #4) based on the boolean result of comparing
34  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
35  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
36  /// The lhs and rhs are XLenVT integers. The true and false values can be
37  /// integer or floating point.
43  // Multiply high for signedxunsigned.
45  // RV64I shifts, directly matching the semantics of the named RISC-V
46  // instructions.
50  // 32-bit operations from RV64M that can't be simply matched with a pattern
51  // at instruction selection time. These have undefined behavior for division
52  // by 0 or overflow (divw) like their target independent counterparts.
56  // RV64IB rotates, directly matching the semantics of the named RISC-V
57  // instructions.
60  // RV64IZbb bit counting instructions directly matching the semantics of the
61  // named RISC-V instructions.
64  // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
65  // instructions, but the same operand order as fshl/fshr intrinsics.
66  FSR,
67  FSL,
68  // RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
69  // but the same operand order as fshl/fshr intrinsics.
72  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
73  // XLEN is the only legal integer width.
74  //
75  // FMV_H_X matches the semantics of the FMV.H.X.
76  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
77  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
78  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
79  //
80  // This is a more convenient semantic for producing dagcombines that remove
81  // unnecessary GPR->FPR->GPR moves.
86  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
87  // (returns (Lo, Hi)). It takes a chain operand.
89  // Generalized Reverse and Generalized Or-Combine - directly matching the
90  // semantics of the named RISC-V instructions. Lowered as custom nodes as
91  // TableGen chokes when faced with commutative permutations in deeply-nested
92  // DAGs. Each node takes an input operand and a control operand and outputs a
93  // bit-manipulated version of input. All operands are i32 or XLenVT.
102  // Bit Compress/Decompress implement the generic bit extract and bit deposit
103  // functions. This operation is also referred to as bit gather/scatter, bit
104  // pack/unpack, parallel extract/deposit, compress/expand, or right
105  // compress/right expand.
110  // Vector Extension
111  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
112  // for the VL value to be used for the operation.
114  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
115  // for the VL value to be used for the operation.
117  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
118  // extended from the vector element size.
120  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
122  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
124  // Splats an i64 scalar to a vector type (with element type i64) where the
125  // scalar is a sign-extended i32.
127  // Read VLENB CSR
129  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
130  // mask and VL operand.
132  // Unit-stride fault-only-first load
135  // Matches the semantics of vslideup/vslidedown. The first operand is the
136  // pass-thru operand, the second is the source vector, the third is the
137  // XLenVT index (either constant or non-constant), the fourth is the mask
138  // and the fifth the VL.
141  // Matches the semantics of vslide1up/slide1down. The first operand is the
142  // source vector, the second is the XLenVT scalar value. The third and fourth
143  // operands are the mask and VL operands.
146  // Matches the semantics of the vid.v instruction, with a mask and VL
147  // operand.
149  // Matches the semantics of the vfcnvt.rod function (Convert double-width
150  // float to single-width float, rounding towards odd). Takes a double-width
151  // float vector and produces a single-width float vector. Also has a mask and
152  // VL operand.
154  // These nodes match the semantics of the corresponding RVV vector reduction
155  // instructions. They produce a vector result which is the reduction
156  // performed over the first vector operand plus the first element of the
157  // second vector operand. The first operand is an unconstrained vector type,
158  // and the result and second operand's types are expected to be the
159  // corresponding full-width LMUL=1 type for the first operand:
160  // nxv8i8 = vecreduce_add nxv32i8, nxv8i8
161  // nxv2i32 = vecreduce_add nxv8i32, nxv2i32
162  // The different in types does introduce extra vsetvli instructions but
163  // similarly it reduces the number of registers consumed per reduction.
164  // Also has a mask and VL operand.
177 
178  // Vector binary and unary ops with a mask as a third operand, and VL as a
179  // fourth operand.
180  // FIXME: Can we replace these with ISD::VP_*?
217 
218  // Vector compare producing a mask. Fourth operand is input mask. Fifth
219  // operand is VL.
221 
222  // Vector select with an additional VL operand. This operation is unmasked.
224 
225  // Mask binary operators.
229 
230  // Set mask vector to all zeros or ones.
233 
234  // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand
235  // for VL.
239 
240  // Vector sign/zero extend with additional mask & VL operands.
243  // vpopc.m with additional mask and VL operands.
245 
246  // Reads value of CSR.
247  // The first operand is a chain pointer. The second specifies address of the
248  // required CSR. Two results are produced, the read value and the new chain
249  // pointer.
251  // Write value to CSR.
252  // The first operand is a chain pointer, the second specifies address of the
253  // required CSR and the third is the value to write. The result is the new
254  // chain pointer.
256  // Read and write value of CSR.
257  // The first operand is a chain pointer, the second specifies address of the
258  // required CSR and the third is the value to write. Two results are produced,
259  // the value read before the modification and the new chain pointer.
261 
262  // Memory opcodes start here.
265 
266  // WARNING: Do not add anything in the end unless you want the node to
267  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
268  // opcodes will be thought as target memory ops!
269 };
270 } // namespace RISCVISD
271 
273  const RISCVSubtarget &Subtarget;
274 
275 public:
276  explicit RISCVTargetLowering(const TargetMachine &TM,
277  const RISCVSubtarget &STI);
278 
279  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
280 
281  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
282  MachineFunction &MF,
283  unsigned Intrinsic) const override;
284  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
285  unsigned AS,
286  Instruction *I = nullptr) const override;
287  bool isLegalICmpImmediate(int64_t Imm) const override;
288  bool isLegalAddImmediate(int64_t Imm) const override;
289  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
290  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
291  bool isZExtFree(SDValue Val, EVT VT2) const override;
292  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
293  bool isCheapToSpeculateCttz() const override;
294  bool isCheapToSpeculateCtlz() const override;
295  bool isFPImmLegal(const APFloat &Imm, EVT VT,
296  bool ForCodeSize) const override;
297 
298  bool softPromoteHalfType() const override { return true; }
299 
300  /// Return the register type for a given MVT, ensuring vectors are treated
301  /// as a series of gpr sized integers.
303  EVT VT) const override;
304 
305  /// Return the number of registers for a given MVT, ensuring vectors are
306  /// treated as a series of gpr sized integers.
308  CallingConv::ID CC,
309  EVT VT) const override;
310 
311  /// Return true if the given shuffle mask can be codegen'd directly, or if it
312  /// should be stack expanded.
313  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
314 
315  bool hasBitPreservingFPLogic(EVT VT) const override;
316  bool
318  unsigned DefinedValues) const override;
319 
320  // Provide custom lowering hooks for some operations.
321  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
323  SelectionDAG &DAG) const override;
324 
325  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
326 
328  const APInt &DemandedElts,
329  TargetLoweringOpt &TLO) const override;
330 
332  KnownBits &Known,
333  const APInt &DemandedElts,
334  const SelectionDAG &DAG,
335  unsigned Depth) const override;
337  const APInt &DemandedElts,
338  const SelectionDAG &DAG,
339  unsigned Depth) const override;
340 
341  // This method returns the name of a target specific DAG node.
342  const char *getTargetNodeName(unsigned Opcode) const override;
343 
344  ConstraintType getConstraintType(StringRef Constraint) const override;
345 
346  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
347 
348  std::pair<unsigned, const TargetRegisterClass *>
350  StringRef Constraint, MVT VT) const override;
351 
352  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
353  std::vector<SDValue> &Ops,
354  SelectionDAG &DAG) const override;
355 
358  MachineBasicBlock *BB) const override;
359 
361  EVT VT) const override;
362 
363  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
364  return VT.isScalarInteger();
365  }
366  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
367 
368  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
369  return isa<LoadInst>(I) || isa<StoreInst>(I);
370  }
372  AtomicOrdering Ord) const override;
374  AtomicOrdering Ord) const override;
375 
377  EVT VT) const override;
378 
380  return ISD::SIGN_EXTEND;
381  }
382 
384  return ISD::SIGN_EXTEND;
385  }
386 
387  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
389  return false;
390  return true;
391  }
393  CombineLevel Level) const override;
394 
395  /// If a physical register, this returns the register that receives the
396  /// exception address on entry to an EH pad.
397  Register
398  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
399 
400  /// If a physical register, this returns the register that receives the
401  /// exception typeid on entry to a landing pad.
402  Register
403  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
404 
405  bool shouldExtendTypeInLibCall(EVT Type) const override;
406  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
407 
408  /// Returns the register with the specified architectural or ABI name. This
409  /// method is necessary to lower the llvm.read_register.* and
410  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
411  /// with the clang -ffixed-xX flag for access to be allowed.
412  Register getRegisterByName(const char *RegName, LLT VT,
413  const MachineFunction &MF) const override;
414 
415  // Lower incoming arguments, copy physregs into vregs
417  bool IsVarArg,
419  const SDLoc &DL, SelectionDAG &DAG,
420  SmallVectorImpl<SDValue> &InVals) const override;
422  bool IsVarArg,
424  LLVMContext &Context) const override;
425  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
427  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
428  SelectionDAG &DAG) const override;
430  SmallVectorImpl<SDValue> &InVals) const override;
431 
433  Type *Ty) const override {
434  return true;
435  }
436  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
437  bool shouldConsiderGEPOffsetSplit() const override { return true; }
438 
440  SDValue C) const override;
441 
443  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
445  Value *AlignedAddr, Value *Incr,
446  Value *Mask, Value *ShiftAmt,
447  AtomicOrdering Ord) const override;
451  AtomicCmpXchgInst *CI,
452  Value *AlignedAddr, Value *CmpVal,
453  Value *NewVal, Value *Mask,
454  AtomicOrdering Ord) const override;
455 
456  /// Returns true if the target allows unaligned memory accesses of the
457  /// specified type.
459  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
461  bool *Fast = nullptr) const override;
462 
464  SDValue Val, SDValue *Parts,
465  unsigned NumParts, MVT PartVT,
466  Optional<CallingConv::ID> CC) const override;
467 
468  SDValue
470  const SDValue *Parts, unsigned NumParts,
471  MVT PartVT, EVT ValueVT,
472  Optional<CallingConv::ID> CC) const override;
473 
474  static RISCVVLMUL getLMUL(MVT VT);
475  static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul);
476  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
477  static unsigned getRegClassIDForVecVT(MVT VT);
478  static std::pair<unsigned, unsigned>
480  unsigned InsertExtractIdx,
481  const RISCVRegisterInfo *TRI);
483 
484  bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
485 
486 private:
487  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
489  bool IsRet) const;
490  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
492  bool IsRet, CallLoweringInfo *CLI) const;
493 
494  template <class NodeTy>
495  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
496 
497  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
498  bool UseGOT) const;
499  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
500 
501  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
502  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
503  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
504  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
505  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
506  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
507  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
508  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
509  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
510  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
511  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
512  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
513  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
514  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
515  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
516  int64_t ExtTrueVal) const;
517  SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
518  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
519  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
520  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
521  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
522  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
523  SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
524  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
525  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
526  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
527  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
528  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
529  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
530  SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
531  SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
533  SelectionDAG &DAG) const;
534  SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
540  unsigned MaskOpc,
541  unsigned VecOpc) const;
542  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
543  SelectionDAG &DAG) const;
544  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
545  bool HasMask = true) const;
546  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
547  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
548  unsigned ExtendOpc) const;
549  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
551 
552  bool isEligibleForTailCallOptimization(
553  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
554  const SmallVector<CCValAssign, 16> &ArgLocs) const;
555 
556  /// Generate error diagnostics if any register used by CC has been marked
557  /// reserved.
558  void validateCCReservedRegs(
559  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
560  MachineFunction &MF) const;
561 
562  bool useRVVForFixedLengthVectorVT(MVT VT) const;
563 };
564 
565 namespace RISCV {
566 // We use 64 bits as the known part in the scalable vector types.
567 static constexpr unsigned RVVBitsPerBlock = 64;
568 } // namespace RISCV
569 
570 namespace RISCVVIntrinsicsTable {
571 
573  unsigned IntrinsicID;
574  uint8_t SplatOperand;
575 };
576 
577 using namespace RISCV;
578 
579 #define GET_RISCVVIntrinsicsTable_DECL
580 #include "RISCVGenSearchableTables.inc"
581 
582 } // end namespace RISCVVIntrinsicsTable
583 
584 } // end namespace llvm
585 
586 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:8415
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:190
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:88
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:182
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:123
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:176
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:204
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:213
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:47
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:6510
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:915
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:144
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:260
llvm::RISCVISD::UNSHFL
@ UNSHFL
Definition: RISCVISelLowering.h:100
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:208
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4103
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.h:432
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:8233
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:207
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:45
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:82
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:54
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:236
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:168
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:8003
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:226
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:185
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:6019
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:210
llvm::IRBuilder<>
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:242
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:819
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::SplatOperand
uint8_t SplatOperand
Definition: RISCVISelLowering.h:574
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:8474
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:175
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:183
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RISCVISD::SHFLW
@ SHFLW
Definition: RISCVISelLowering.h:99
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:383
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:186
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:181
llvm::Optional< CallingConv::ID >
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:228
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:8252
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:171
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1088
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:8490
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:7171
llvm::RISCVISD::VSE_VL
@ VSE_VL
Definition: RISCVISelLowering.h:264
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:923
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:7842
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:148
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:5937
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:241
TargetLowering.h
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:83
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:5479
llvm::RISCVISD::VPOPC_VL
@ VPOPC_VL
Definition: RISCVISelLowering.h:244
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:203
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:8435
llvm::RISCVISD::VLE_VL
@ VLE_VL
Definition: RISCVISelLowering.h:263
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:940
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:573
llvm::RISCVISD::SPLAT_VECTOR_I64
@ SPLAT_VECTOR_I64
Definition: RISCVISelLowering.h:126
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:919
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:31
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:231
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1067
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:194
llvm::RISCVISD::VLEFF
@ VLEFF
Definition: RISCVISelLowering.h:133
llvm::RISCVISD::FSL
@ FSL
Definition: RISCVISelLowering.h:67
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:209
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:8532
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:7404
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:8420
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:366
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:84
llvm::RISCVISD::FSLW
@ FSLW
Definition: RISCVISelLowering.h:71
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:223
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:205
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::GREVW
@ GREVW
Definition: RISCVISelLowering.h:95
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:877
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:189
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:8442
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:53
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul)
Definition: RISCVISelLowering.cpp:1049
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:387
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:62
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:153
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:199
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:41
llvm::RISCVISD::FP_TO_UINT_VL
@ FP_TO_UINT_VL
Definition: RISCVISelLowering.h:212
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:187
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:567
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVISD::GREV
@ GREV
Definition: RISCVISelLowering.h:94
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:38
llvm::RISCVISD::GORC
@ GORC
Definition: RISCVISelLowering.h:96
llvm::APFloat
Definition: APFloat.h:701
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:363
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:121
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:85
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:873
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:172
llvm::RISCVISD::BCOMPRESS
@ BCOMPRESS
Definition: RISCVISelLowering.h:106
llvm::RISCVISD::GORCW
@ GORCW
Definition: RISCVISelLowering.h:97
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:220
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:44
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:140
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:193
llvm::RISCVISD::BDECOMPRESSW
@ BDECOMPRESSW
Definition: RISCVISelLowering.h:109
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:58
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:884
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:437
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:167
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:8181
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:6104
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVISD::UNSHFLW
@ UNSHFLW
Definition: RISCVISelLowering.h:101
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:255
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3694
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:847
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:901
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:184
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVTargetLowering::getLMUL
static RISCVVLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1023
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:174
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: RISCVISelLowering.cpp:5891
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:169
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:144
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:298
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:48
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:4582
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:128
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:8394
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:227
RISCV.h
llvm::RISCVISD::FSRW
@ FSRW
Definition: RISCVISelLowering.h:70
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:649
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:40
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:279
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:195
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1100
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:55
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT VT) const override
Definition: RISCVISelLowering.cpp:8390
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:170
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:113
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:7983
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:216
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:39
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:196
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:59
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:8316
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:166
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:927
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1692
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:232
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:49
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:247
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:7701
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:27
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:215
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:237
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:272
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:1886
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:119
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:8368
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:8195
llvm::RISCVISD::FSR
@ FSR
Definition: RISCVISelLowering.h:66
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:116
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:368
llvm::RISCVISD::FP_TO_SINT_VL
@ FP_TO_SINT_VL
Definition: RISCVISelLowering.h:211
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:238
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:173
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:8577
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:192
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:42
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:572
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::VLEFF_MASK
@ VLEFF_MASK
Definition: RISCVISelLowering.h:134
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:25
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:165
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1294
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:206
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1247
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:250
llvm::RISCVISD::SHFL
@ SHFL
Definition: RISCVISelLowering.h:98
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:8243
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:957
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:8425
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:713
llvm::RISCVVLMUL
RISCVVLMUL
Definition: RISCVBaseInfo.h:274
llvm::RISCVISD::BDECOMPRESS
@ BDECOMPRESS
Definition: RISCVISelLowering.h:108
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:29
llvm::RISCVISD::BCOMPRESSW
@ BCOMPRESSW
Definition: RISCVISelLowering.h:107
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:7724
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:379
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:7838
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:145
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:808
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:131
llvm::RISCVISD::FMA_VL
@ FMA_VL
Definition: RISCVISelLowering.h:201
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:202
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:946
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:63
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1234
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:139
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:200
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:191
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:1299
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:188
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:8360
llvm::LLT
Definition: LowLevelTypeImpl.h:40