LLVM  14.0.0git
Enumerations
llvm::RISCVISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END, RET_FLAG, URET_FLAG, SRET_FLAG,
  MRET_FLAG, CALL, SELECT_CC, BR_CC,
  BuildPairF64, SplitF64, TAIL, MULHSU,
  SLLW, SRAW, SRLW, DIVW,
  DIVUW, REMUW, ROLW, RORW,
  CLZW, CTZW, FSR, FSL,
  FSRW, FSLW, FMV_H_X, FMV_X_ANYEXTH,
  FMV_W_X_RV64, FMV_X_ANYEXTW_RV64, FCVT_X_RTZ, FCVT_XU_RTZ,
  FCVT_W_RTZ_RV64, FCVT_WU_RTZ_RV64, READ_CYCLE_WIDE, GREV,
  GREVW, GORC, GORCW, SHFL,
  SHFLW, UNSHFL, UNSHFLW, BCOMPRESS,
  BCOMPRESSW, BDECOMPRESS, BDECOMPRESSW, VMV_V_X_VL,
  VFMV_V_F_VL, VMV_X_S, VMV_S_X_VL, VFMV_S_F_VL,
  SPLAT_VECTOR_I64, SPLAT_VECTOR_SPLIT_I64_VL, READ_VLENB, TRUNCATE_VECTOR_VL,
  VSLIDEUP_VL, VSLIDEDOWN_VL, VSLIDE1UP_VL, VSLIDE1DOWN_VL,
  VID_VL, VFNCVT_ROD_VL, VECREDUCE_ADD_VL, VECREDUCE_UMAX_VL,
  VECREDUCE_SMAX_VL, VECREDUCE_UMIN_VL, VECREDUCE_SMIN_VL, VECREDUCE_AND_VL,
  VECREDUCE_OR_VL, VECREDUCE_XOR_VL, VECREDUCE_FADD_VL, VECREDUCE_SEQ_FADD_VL,
  VECREDUCE_FMIN_VL, VECREDUCE_FMAX_VL, ADD_VL, AND_VL,
  MUL_VL, OR_VL, SDIV_VL, SHL_VL,
  SREM_VL, SRA_VL, SRL_VL, SUB_VL,
  UDIV_VL, UREM_VL, XOR_VL, SADDSAT_VL,
  UADDSAT_VL, SSUBSAT_VL, USUBSAT_VL, FADD_VL,
  FSUB_VL, FMUL_VL, FDIV_VL, FNEG_VL,
  FABS_VL, FSQRT_VL, FMA_VL, FCOPYSIGN_VL,
  SMIN_VL, SMAX_VL, UMIN_VL, UMAX_VL,
  FMINNUM_VL, FMAXNUM_VL, MULHS_VL, MULHU_VL,
  FP_TO_SINT_VL, FP_TO_UINT_VL, SINT_TO_FP_VL, UINT_TO_FP_VL,
  FP_ROUND_VL, FP_EXTEND_VL, VWMUL_VL, VWMULU_VL,
  SETCC_VL, VSELECT_VL, VMAND_VL, VMOR_VL,
  VMXOR_VL, VMCLR_VL, VMSET_VL, VRGATHER_VX_VL,
  VRGATHER_VV_VL, VRGATHEREI16_VV_VL, VSEXT_VL, VZEXT_VL,
  VPOPC_VL, READ_CSR, WRITE_CSR, SWAP_CSR,
  VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, VSE_VL
}
 

Enumeration Type Documentation

◆ NodeType

enum llvm::RISCVISD::NodeType : unsigned
Enumerator
FIRST_NUMBER 
RET_FLAG 
URET_FLAG 
SRET_FLAG 
MRET_FLAG 
CALL 
SELECT_CC 

Select with condition operator - This selects between a true value and a false value (ops #3 and #4) based on the boolean result of comparing the lhs and rhs (ops #0 and #1) of a conditional expression with the condition code in op #2, a XLenVT constant from the ISD::CondCode enum.

The lhs and rhs are XLenVT integers. The true and false values can be integer or floating point.

BR_CC 
BuildPairF64 
SplitF64 
TAIL 
MULHSU 
SLLW 
SRAW 
SRLW 
DIVW 
DIVUW 
REMUW 
ROLW 
RORW 
CLZW 
CTZW 
FSR 
FSL 
FSRW 
FSLW 
FMV_H_X 
FMV_X_ANYEXTH 
FMV_W_X_RV64 
FMV_X_ANYEXTW_RV64 
FCVT_X_RTZ 
FCVT_XU_RTZ 
FCVT_W_RTZ_RV64 
FCVT_WU_RTZ_RV64 
READ_CYCLE_WIDE 
GREV 
GREVW 
GORC 
GORCW 
SHFL 
SHFLW 
UNSHFL 
UNSHFLW 
BCOMPRESS 
BCOMPRESSW 
BDECOMPRESS 
BDECOMPRESSW 
VMV_V_X_VL 
VFMV_V_F_VL 
VMV_X_S 
VMV_S_X_VL 
VFMV_S_F_VL 
SPLAT_VECTOR_I64 
SPLAT_VECTOR_SPLIT_I64_VL 
READ_VLENB 
TRUNCATE_VECTOR_VL 
VSLIDEUP_VL 
VSLIDEDOWN_VL 
VSLIDE1UP_VL 
VSLIDE1DOWN_VL 
VID_VL 
VFNCVT_ROD_VL 
VECREDUCE_ADD_VL 
VECREDUCE_UMAX_VL 
VECREDUCE_SMAX_VL 
VECREDUCE_UMIN_VL 
VECREDUCE_SMIN_VL 
VECREDUCE_AND_VL 
VECREDUCE_OR_VL 
VECREDUCE_XOR_VL 
VECREDUCE_FADD_VL 
VECREDUCE_SEQ_FADD_VL 
VECREDUCE_FMIN_VL 
VECREDUCE_FMAX_VL 
ADD_VL 
AND_VL 
MUL_VL 
OR_VL 
SDIV_VL 
SHL_VL 
SREM_VL 
SRA_VL 
SRL_VL 
SUB_VL 
UDIV_VL 
UREM_VL 
XOR_VL 
SADDSAT_VL 
UADDSAT_VL 
SSUBSAT_VL 
USUBSAT_VL 
FADD_VL 
FSUB_VL 
FMUL_VL 
FDIV_VL 
FNEG_VL 
FABS_VL 
FSQRT_VL 
FMA_VL 
FCOPYSIGN_VL 
SMIN_VL 
SMAX_VL 
UMIN_VL 
UMAX_VL 
FMINNUM_VL 
FMAXNUM_VL 
MULHS_VL 
MULHU_VL 
FP_TO_SINT_VL 
FP_TO_UINT_VL 
SINT_TO_FP_VL 
UINT_TO_FP_VL 
FP_ROUND_VL 
FP_EXTEND_VL 
VWMUL_VL 
VWMULU_VL 
SETCC_VL 
VSELECT_VL 
VMAND_VL 
VMOR_VL 
VMXOR_VL 
VMCLR_VL 
VMSET_VL 
VRGATHER_VX_VL 
VRGATHER_VV_VL 
VRGATHEREI16_VV_VL 
VSEXT_VL 
VZEXT_VL 
VPOPC_VL 
READ_CSR 
WRITE_CSR 
SWAP_CSR 
VLE_VL 
VSE_VL 

Definition at line 26 of file RISCVISelLowering.h.