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LLVM 22.0.0git
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Enumerations | |
| enum | : uint8_t { IsVRegClassShift = 0 , IsVRegClassShiftMask = 0b1 << IsVRegClassShift , VLMulShift = IsVRegClassShift + 1 , VLMulShiftMask = 0b11 << VLMulShift , NFShift = VLMulShift + 2 , NFShiftMask = 0b111 << NFShift } |
| enum | { RegPairOdd = 1 , RegPairEven = 2 } |
| Register allocation hints for Zilsd register pairs. More... | |
Functions | |
| static bool | isVRegClass (uint8_t TSFlags) |
| static RISCVVType::VLMUL | getLMul (uint8_t TSFlags) |
| static unsigned | getNF (uint8_t TSFlags) |
| anonymous enum : uint8_t |
| Enumerator | |
|---|---|
| IsVRegClassShift | |
| IsVRegClassShiftMask | |
| VLMulShift | |
| VLMulShiftMask | |
| NFShift | |
| NFShiftMask | |
Definition at line 25 of file RISCVRegisterInfo.h.
| anonymous enum |
Register allocation hints for Zilsd register pairs.
| Enumerator | |
|---|---|
| RegPairOdd | |
| RegPairEven | |
Definition at line 41 of file RISCVRegisterInfo.h.
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inlinestatic |
Definition at line 53 of file RISCVRegisterInfo.h.
References VLMulShift, and VLMulShiftMask.
Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVRegisterInfo::findVRegWithEncoding(), and isTupleInsertInstr().
Definition at line 59 of file RISCVRegisterInfo.h.
References NFShift, and NFShiftMask.
Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), isTupleInsertInstr(), llvm::RISCVRegisterInfo::isVRNRegClass(), and llvm::RISCVRegisterInfo::isVRRegClass().
Definition at line 48 of file RISCVRegisterInfo.h.
References IsVRegClassShift, and IsVRegClassShiftMask.
Referenced by llvm::RISCVRegisterInfo::isRVVRegClass(), isTupleInsertInstr(), llvm::RISCVRegisterInfo::isVRNRegClass(), and llvm::RISCVRegisterInfo::isVRRegClass().