LLVM  16.0.0git
RISCVRegisterInfo.cpp
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1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
16 #include "RISCVSubtarget.h"
26 
27 #define GET_REGINFO_TARGET_DESC
28 #include "RISCVGenRegisterInfo.inc"
29 
30 using namespace llvm;
31 
32 static cl::opt<bool>
33  DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
34  cl::init(false),
35  cl::desc("Disable two address hints for register "
36  "allocation"));
37 
38 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
39 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
40 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
41 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
42  "Register list not consecutive");
43 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
44 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
45  "Register list not consecutive");
46 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
47 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
48  "Register list not consecutive");
49 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
50 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
51 
53  : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
54  /*PC*/0, HwMode) {}
55 
56 const MCPhysReg *
58  auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
60  return CSR_NoRegs_SaveList;
61  if (MF->getFunction().hasFnAttribute("interrupt")) {
62  if (Subtarget.hasStdExtD())
63  return CSR_XLEN_F64_Interrupt_SaveList;
64  if (Subtarget.hasStdExtF())
65  return CSR_XLEN_F32_Interrupt_SaveList;
66  return CSR_Interrupt_SaveList;
67  }
68 
69  switch (Subtarget.getTargetABI()) {
70  default:
71  llvm_unreachable("Unrecognized ABI");
73  case RISCVABI::ABI_LP64:
74  return CSR_ILP32_LP64_SaveList;
77  return CSR_ILP32F_LP64F_SaveList;
80  return CSR_ILP32D_LP64D_SaveList;
81  }
82 }
83 
85  const RISCVFrameLowering *TFI = getFrameLowering(MF);
86  BitVector Reserved(getNumRegs());
87 
88  // Mark any registers requested to be reserved as such
89  for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
91  markSuperRegs(Reserved, Reg);
92  }
93 
94  // Use markSuperRegs to ensure any register aliases are also reserved
95  markSuperRegs(Reserved, RISCV::X0); // zero
96  markSuperRegs(Reserved, RISCV::X2); // sp
97  markSuperRegs(Reserved, RISCV::X3); // gp
98  markSuperRegs(Reserved, RISCV::X4); // tp
99  if (TFI->hasFP(MF))
100  markSuperRegs(Reserved, RISCV::X8); // fp
101  // Reserve the base register if we need to realign the stack and allocate
102  // variable-sized objects at runtime.
103  if (TFI->hasBP(MF))
104  markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
105 
106  // V registers for code generation. We handle them manually.
107  markSuperRegs(Reserved, RISCV::VL);
108  markSuperRegs(Reserved, RISCV::VTYPE);
109  markSuperRegs(Reserved, RISCV::VXSAT);
110  markSuperRegs(Reserved, RISCV::VXRM);
111  markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
112 
113  // Floating point environment registers.
114  markSuperRegs(Reserved, RISCV::FRM);
115  markSuperRegs(Reserved, RISCV::FFLAGS);
116 
117  assert(checkAllSuperRegsMarked(Reserved));
118  return Reserved;
119 }
120 
122  MCRegister PhysReg) const {
123  return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
124 }
125 
127  return CSR_NoRegs_RegMask;
128 }
129 
130 // Frame indexes representing locations of CSRs which are given a fixed location
131 // by save/restore libcalls.
132 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
133  {/*ra*/ RISCV::X1, -1},
134  {/*s0*/ RISCV::X8, -2},
135  {/*s1*/ RISCV::X9, -3},
136  {/*s2*/ RISCV::X18, -4},
137  {/*s3*/ RISCV::X19, -5},
138  {/*s4*/ RISCV::X20, -6},
139  {/*s5*/ RISCV::X21, -7},
140  {/*s6*/ RISCV::X22, -8},
141  {/*s7*/ RISCV::X23, -9},
142  {/*s8*/ RISCV::X24, -10},
143  {/*s9*/ RISCV::X25, -11},
144  {/*s10*/ RISCV::X26, -12},
145  {/*s11*/ RISCV::X27, -13}
146 };
147 
149  Register Reg,
150  int &FrameIdx) const {
151  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
152  if (!RVFI->useSaveRestoreLibCalls(MF))
153  return false;
154 
155  const auto *FII =
156  llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == Reg; });
157  if (FII == std::end(FixedCSRFIMap))
158  return false;
159 
160  FrameIdx = FII->second;
161  return true;
162 }
163 
165  int SPAdj, unsigned FIOperandNum,
166  RegScavenger *RS) const {
167  assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
168 
169  MachineInstr &MI = *II;
170  MachineFunction &MF = *MI.getParent()->getParent();
173  const RISCVInstrInfo *TII = ST.getInstrInfo();
174  DebugLoc DL = MI.getDebugLoc();
175 
176  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
177  Register FrameReg;
178  StackOffset Offset =
179  getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
180  bool IsRVVSpill = RISCV::isRVVSpill(MI);
181  if (!IsRVVSpill)
182  Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
183 
184  if (Offset.getScalable() &&
185  ST.getRealMinVLen() == ST.getRealMaxVLen()) {
186  // For an exact VLEN value, scalable offsets become constant and thus
187  // can be converted entirely into fixed offsets.
188  int64_t FixedValue = Offset.getFixed();
189  int64_t ScalableValue = Offset.getScalable();
190  assert(ScalableValue % 8 == 0 &&
191  "Scalable offset is not a multiple of a single vector size.");
192  int64_t NumOfVReg = ScalableValue / 8;
193  int64_t VLENB = ST.getRealMinVLen() / 8;
194  Offset = StackOffset::getFixed(FixedValue + NumOfVReg * VLENB);
195  }
196 
197  if (!isInt<32>(Offset.getFixed())) {
199  "Frame offsets outside of the signed 32-bit range not supported");
200  }
201 
202  MachineBasicBlock &MBB = *MI.getParent();
203  bool FrameRegIsKill = false;
204 
205  // If the instruction is an ADDI, we can use it's destination as a scratch
206  // register. Load instructions might have an FP or vector destination and
207  // stores don't have a destination register.
208  Register DestReg;
209  if (MI.getOpcode() == RISCV::ADDI)
210  DestReg = MI.getOperand(0).getReg();
211 
212  // If required, pre-compute the scalable factor amount which will be used in
213  // later offset computation. Since this sequence requires up to two scratch
214  // registers -- after which one is made free -- this grants us better
215  // scavenging of scratch registers as only up to two are live at one time,
216  // rather than three.
217  unsigned ScalableAdjOpc = RISCV::ADD;
218  if (Offset.getScalable()) {
219  int64_t ScalableValue = Offset.getScalable();
220  if (ScalableValue < 0) {
221  ScalableValue = -ScalableValue;
222  ScalableAdjOpc = RISCV::SUB;
223  }
224  // Use DestReg if it exists, otherwise create a new register.
225  if (!DestReg)
226  DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
227  // Get vlenb and multiply vlen with the number of vector registers.
228  TII->getVLENFactoredAmount(MF, MBB, II, DL, DestReg, ScalableValue);
229  }
230 
231  if (!isInt<12>(Offset.getFixed())) {
232  // The offset won't fit in an immediate, so use a scratch register instead
233  // Modify Offset and FrameReg appropriately.
234 
235  // Reuse destination register if it exists and is not holding a scalable
236  // offset.
237  Register ScratchReg = DestReg;
238  if (!DestReg || Offset.getScalable()) {
239  ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
240  // Also save to DestReg if it doesn't exist.
241  if (!DestReg)
242  DestReg = ScratchReg;
243  }
244 
245  TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
246  BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
247  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
248  .addReg(ScratchReg, RegState::Kill);
249  // If this was an ADDI and there is no scalable offset, we can remove it.
250  if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
251  assert(MI.getOperand(0).getReg() == ScratchReg &&
252  "Expected to have written ADDI destination register");
253  MI.eraseFromParent();
254  return true;
255  }
256 
257  Offset = StackOffset::get(0, Offset.getScalable());
258  FrameReg = ScratchReg;
259  FrameRegIsKill = true;
260  }
261 
262  // Add in the scalable offset which has already been computed in DestReg.
263  if (Offset.getScalable()) {
264  assert(DestReg && "DestReg should be valid");
265  BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
266  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
267  .addReg(DestReg, RegState::Kill);
268  // If this was an ADDI and there is no fixed offset, we can remove it.
269  if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
270  assert(MI.getOperand(0).getReg() == DestReg &&
271  "Expected to have written ADDI destination register");
272  MI.eraseFromParent();
273  return true;
274  }
275  FrameReg = DestReg;
276  FrameRegIsKill = true;
277  }
278 
279  // Handle the fixed offset which might be zero.
280  if (IsRVVSpill) {
281  // RVVSpills don't have an immediate. Add an ADDI if the fixed offset is
282  // needed.
283  if (Offset.getFixed()) {
284  // Reuse DestReg if it exists, otherwise create a new register.
285  if (!DestReg)
286  DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
287  BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
288  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
289  .addImm(Offset.getFixed());
290  FrameReg = DestReg;
291  FrameRegIsKill = true;
292  }
293  } else {
294  // Otherwise we can replace the original immediate.
295  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
296  }
297 
298  // Finally, replace the frame index operand.
299  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false,
300  FrameRegIsKill);
301 
302  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
303  if (ZvlssegInfo) {
304  Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
305  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
306  uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
307  if (ShiftAmount != 0)
308  BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
309  .addReg(VL)
310  .addImm(ShiftAmount);
311  // The last argument of pseudo spilling opcode for zvlsseg is the length of
312  // one element of zvlsseg types. For example, for vint32m2x2_t, it will be
313  // the length of vint32m2_t.
314  MI.getOperand(FIOperandNum + 1).ChangeToRegister(VL, /*isDef=*/false);
315  }
316  return false;
317 }
318 
320  const TargetFrameLowering *TFI = getFrameLowering(MF);
321  return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
322 }
323 
324 const uint32_t *
326  CallingConv::ID CC) const {
327  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
328 
329  if (CC == CallingConv::GHC)
330  return CSR_NoRegs_RegMask;
331  switch (Subtarget.getTargetABI()) {
332  default:
333  llvm_unreachable("Unrecognized ABI");
334  case RISCVABI::ABI_ILP32:
335  case RISCVABI::ABI_LP64:
336  return CSR_ILP32_LP64_RegMask;
338  case RISCVABI::ABI_LP64F:
339  return CSR_ILP32F_LP64F_RegMask;
341  case RISCVABI::ABI_LP64D:
342  return CSR_ILP32D_LP64D_RegMask;
343  }
344 }
345 
346 const TargetRegisterClass *
348  const MachineFunction &) const {
349  if (RC == &RISCV::VMV0RegClass)
350  return &RISCV::VRRegClass;
351  return RC;
352 }
353 
355  SmallVectorImpl<uint64_t> &Ops) const {
356  // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
357  // to represent one vector register. The dwarf offset is
358  // VLENB * scalable_offset / 8.
359  assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
360 
361  // Add fixed-sized offset using existing DIExpression interface.
362  DIExpression::appendOffset(Ops, Offset.getFixed());
363 
364  unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
365  int64_t VLENBSized = Offset.getScalable() / 8;
366  if (VLENBSized > 0) {
367  Ops.push_back(dwarf::DW_OP_constu);
368  Ops.push_back(VLENBSized);
369  Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
370  Ops.push_back(dwarf::DW_OP_mul);
371  Ops.push_back(dwarf::DW_OP_plus);
372  } else if (VLENBSized < 0) {
373  Ops.push_back(dwarf::DW_OP_constu);
374  Ops.push_back(-VLENBSized);
375  Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
376  Ops.push_back(dwarf::DW_OP_mul);
377  Ops.push_back(dwarf::DW_OP_minus);
378  }
379 }
380 
381 unsigned
383  return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
384 }
385 
386 // Add two address hints to improve chances of being able to use a compressed
387 // instruction.
389  Register VirtReg, ArrayRef<MCPhysReg> Order,
391  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
392  const MachineRegisterInfo *MRI = &MF.getRegInfo();
393 
394  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
395  VirtReg, Order, Hints, MF, VRM, Matrix);
396 
397  if (!VRM || DisableRegAllocHints)
398  return BaseImplRetVal;
399 
400  // Add any two address hints after any copy hints.
401  SmallSet<unsigned, 4> TwoAddrHints;
402 
403  auto tryAddHint = [&](const MachineOperand &VRRegMO,
404  const MachineOperand &MO) -> void {
405  Register Reg = MO.getReg();
406  Register PhysReg =
408  if (PhysReg) {
409  assert(!MO.getSubReg() && !VRRegMO.getSubReg() && "Unexpected subreg!");
410  if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
411  TwoAddrHints.insert(PhysReg);
412  }
413  };
414 
415  // For now we support the compressible instructions which can encode all
416  // registers and have a single register source.
417  // TODO: Add more compressed instructions.
418  auto isCompressible = [](const MachineInstr &MI) {
419  switch (MI.getOpcode()) {
420  default:
421  return false;
422  case RISCV::ADD:
423  case RISCV::SLLI:
424  return true;
425  case RISCV::ADDI:
426  case RISCV::ADDIW:
427  return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm());
428  }
429  };
430 
431  for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
432  const MachineInstr &MI = *MO.getParent();
433  if (isCompressible(MI)) {
434  unsigned OpIdx = MI.getOperandNo(&MO);
435  if (OpIdx == 0 && MI.getOperand(1).isReg()) {
436  tryAddHint(MO, MI.getOperand(1));
437  if (MI.isCommutable() && MI.getOperand(2).isReg())
438  tryAddHint(MO, MI.getOperand(2));
439  } else if (OpIdx == 1) {
440  tryAddHint(MO, MI.getOperand(0));
441  } else if (MI.isCommutable() && OpIdx == 2) {
442  tryAddHint(MO, MI.getOperand(0));
443  }
444  }
445  }
446 
447  for (MCPhysReg OrderReg : Order)
448  if (TwoAddrHints.count(OrderReg))
449  Hints.push_back(OrderReg);
450 
451  return BaseImplRetVal;
452 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:378
llvm::RISCVRegisterInfo::getRegisterCostTableIndex
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:382
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
TargetFrameLowering.h
llvm::RISCVRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:319
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::RISCVRegisterInfo::RISCVRegisterInfo
RISCVRegisterInfo(unsigned HwMode)
Definition: RISCVRegisterInfo.cpp:52
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:235
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
getDwarfRegNum
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:178
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
llvm::RISCVRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: RISCVRegisterInfo.cpp:57
llvm::RISCVRegisterInfo::eliminateFrameIndex
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: RISCVRegisterInfo.cpp:164
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:373
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:377
llvm::RISCVRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: RISCVRegisterInfo.cpp:388
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
llvm::RISCVRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: RISCVRegisterInfo.cpp:325
llvm::RISCVRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
Definition: RISCVRegisterInfo.cpp:347
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:345
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:547
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:375
llvm::RISCVRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:84
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::BitVector
Definition: BitVector.h:75
llvm::SmallVectorImpl::append
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::cl::opt< bool >
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::RISCVRegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: RISCVRegisterInfo.cpp:354
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1843
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
Dwarf.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::RISCVFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: RISCVFrameLowering.cpp:229
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: RISCVRegisterInfo.cpp:148
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1421
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:379
llvm::CallingConv::GHC
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
uint16_t
MachineFrameInfo.h
RISCVGenRegisterInfo
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::RISCV::isRVVSpill
bool isRVVSpill(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2398
FixedCSRFIMap
static const std::pair< unsigned, int > FixedCSRFIMap[]
Definition: RISCVRegisterInfo.cpp:132
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
DisableRegAllocHints
static cl::opt< bool > DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden, cl::init(false), cl::desc("Disable two address hints for register " "allocation"))
RISCVSubtarget.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
MachineInstrBuilder.h
RISCVMachineFunctionInfo.h
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::SmallVectorImpl< uint64_t >
llvm::RISCV::isRVVSpillForZvlsseg
Optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
Definition: RISCVInstrInfo.cpp:2409
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:374
llvm::RISCVRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: RISCVRegisterInfo.cpp:126
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:413
RegisterScavenging.h
llvm::RISCVFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:238
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
RISCVRegisterInfo.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::RISCVRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: RISCVRegisterInfo.cpp:121
llvm::StackOffset::get
static StackOffset get(ScalarTy Fixed, ScalarTy Scalable)
Definition: TypeSize.h:145