13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
30#define GET_SUBTARGETINFO_HEADER
31#include "AArch64GenSubtargetInfo.inc"
42#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
43#include "llvm/TargetParser/AArch64TargetParserDef.inc"
44#undef ARM_PROCESSOR_FAMILY
55#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
56 bool ATTRIBUTE = DEFAULT;
57#include "AArch64GenSubtargetInfo.inc"
114 void initializeProperties(
bool HasMinSize);
121 unsigned MinSVEVectorSizeInBitsOverride = 0,
122 unsigned MaxSVEVectorSizeInBitsOverride = 0,
125 bool HasMinSize =
false);
128#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
129 bool GETTER() const { return ATTRIBUTE; }
130#include "AArch64GenSubtargetInfo.inc"
196 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
199 return AllReservedX.
count();
208 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
209 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
210 hasFuseAdrpAdd() || hasFuseLiterals();
218 unsigned NumStridedMemAccesses,
219 unsigned NumPrefetches,
220 bool HasCall)
const override {
263 bool useAA()
const override;
304 unsigned NumRegionInstrs)
const override;
336 unsigned Major = TT.getOSVersion().getMajor();
361 "Tried to get SVE vector length without SVE support!");
367 "Tried to get SVE vector length without SVE support!");
394 return "#__chkstk_arm64ec";
400 return "#__security_check_cookie_arm64ec";
401 return "__security_check_cookie";
408 return AddressCheckPSV.get();
422 bool isConstant(
const MachineFrameInfo *)
const override {
return false; }
423 bool isAliased(
const MachineFrameInfo *)
const override {
return true; }
424 bool mayAlias(
const MachineFrameInfo *)
const override {
return true; }
425 void printCustom(raw_ostream &
OS)
const override {
OS <<
"AddressCheck"; }
428 std::unique_ptr<AddressCheckPseudoSourceValue> AddressCheckPSV;
This file describes how to lower LLVM calls to machine code calls.
This file describes how to lower LLVM inline asm to machine code INLINEASM.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool isTargetWindows() const
BitVector ReserveXRegisterForRA
BitVector ReserveXRegister
const CallLowering * getCallLowering() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
BitVector CustomCallSavedXRegs
bool addrSinkUsingGEPs() const override
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMinimumJumpTableEntries() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSVEForFixedLengthVectors(EVT VT) const
const AArch64InstrInfo * getInstrInfo() const override
bool useSmallAddressing() const
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
AArch64SelectionDAGInfo TSInfo
const char * getSecurityCheckCookieName() const
unsigned getMaximumJumpTableSize() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool isTargetDarwin() const
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned MaxPrefetchIterationsAhead
unsigned getCacheLineSize() const override
bool isTargetILP32() const
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool hasSVE2orSME() const
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
uint8_t VectorInsertExtractBaseCost
const AArch64TargetLowering * getTargetLowering() const override
Align getPrefLoopAlignment() const
Align getPrefFunctionAlignment() const
bool isTargetMachO() const
unsigned getMaxBytesForLoopAlignment() const
uint16_t PrefetchDistance
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
unsigned getMaxInterleaveFactor() const
bool isTargetAndroid() const
bool StreamingCompatibleSVEMode
Align PrefFunctionAlignment
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
const Triple & getTargetTriple() const
unsigned MinVectorRegisterBitWidth
const PseudoSourceValue * getAddressCheckPSV() const
bool isCallingConvWin64(CallingConv::ID CC) const
const char * getChkStkName() const
bool isXRegCustomCalleeSaved(size_t i) const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
uint16_t MinPrefetchStride
TailFoldingOpts getSVETailFoldingDefaultOpts() const
bool useSVEForFixedLengthVectors() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
bool isLittleEndian() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned MaxJumpTableSize
unsigned getMinVectorRegisterBitWidth() const
bool isWindowsArm64EC() const
bool isStreaming() const
Returns true if the function has a streaming body.
unsigned MinSVEVectorSizeInBits
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
bool isXRegisterReserved(size_t i) const
unsigned getMaxPrefetchIterationsAhead() const override
bool isTargetFuchsia() const
bool useDFAforSMS() const override
unsigned MinimumJumpTableEntries
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
unsigned MaxSVEVectorSizeInBits
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
uint8_t MaxInterleaveFactor
unsigned getMaxSVEVectorSizeInBits() const
unsigned getVScaleForTuning() const
bool isTargetLinux() const
unsigned getMinSVEVectorSizeInBits() const
AArch64InstrInfo InstrInfo
AArch64TargetLowering TLInfo
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned MaxBytesForLoopAlignment
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool isTargetCOFF() const
bool isXRaySupported() const override
bool hasCustomCallingConv() const
const AArch64FrameLowering * getFrameLowering() const override
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned getPrefetchDistance() const override
size_type count() const
count - Returns the number of bits which are set.
bool any() const
any - Returns true if any bit is set.
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
Scheduling unit. This is a node in the scheduling DAG.
StringRef - Represent a constant reference to a string, i.e.
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
Provide an instruction scheduling machine model to CodeGen passes.
Triple - Helper class for working with autoconf configuration names.
bool isAndroid() const
Tests whether the target is Android.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSLinux() const
Tests whether the OS is Linux.
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
bool isWindowsArm64EC() const
bool isiOS() const
Is this an iOS triple.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
A Use represents the edge between a Value definition and its users.
AuthCheckMethod
Variants of check performed on an authenticated pointer.
static constexpr unsigned SVEBitsPerBlock
@ Swift
Calling convention for Swift.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isFixedLengthVector() const
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.