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HexagonMCCodeEmitter.cpp
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1 //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "Hexagon.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/Endian.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstdint>
35 #include <map>
36 #include <string>
37 #include <vector>
38 
39 #define DEBUG_TYPE "mccodeemitter"
40 
41 using namespace llvm;
42 using namespace Hexagon;
43 
44 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
45 
46 static const unsigned fixup_Invalid = ~0u;
47 
48 #define _ fixup_Invalid
49 #define P(x) Hexagon::fixup_Hexagon##x
50 static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
52  { _, _, _, _,
53  _, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
54  P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
55  P(_DTPREL_16_X), _, _, _,
56  P(_DTPREL_16_X), _, _, _,
57  _, _, _, _,
58  _, _, _, _,
59  _, _, _, _,
60  P(_DTPREL_32_6_X) }},
62  { _, _, _, _,
63  _, _, P(_GOT_11_X), _ /* [1] */,
64  _ /* [1] */, P(_9_X), _, P(_GOT_11_X),
65  P(_GOT_16_X), _, _, _,
66  P(_GOT_16_X), _, _, _,
67  _, _, _, _,
68  _, _, _, _,
69  _, _, _, _,
70  P(_GOT_32_6_X) }},
72  { _, _, _, _,
73  _, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
74  P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
75  P(_GOTREL_16_X), _, _, _,
76  P(_GOTREL_16_X), _, _, _,
77  _, _, _, _,
78  _, _, _, _,
79  _, _, _, _,
80  P(_GOTREL_32_6_X) }},
82  { _, _, _, _,
83  _, _, P(_TPREL_16_X), P(_TPREL_11_X),
84  P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
85  P(_TPREL_16_X), _, _, _,
86  P(_TPREL_16_X), _, _, _,
87  _, _, _, _,
88  _, _, _, _,
89  _, _, _, _,
90  P(_TPREL_32_6_X) }},
92  { _, _, _, _,
93  _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
94  P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
95  P(_GD_GOT_16_X), _, _, _,
96  P(_GD_GOT_16_X), _, _, _,
97  _, _, _, _,
98  _, _, _, _,
99  _, _, _, _,
100  P(_GD_GOT_32_6_X) }},
102  { _, _, _, _,
103  _, _, _, _,
104  _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
105  _, _, _, _,
106  _, _, _, _,
107  _, _, P(_GD_PLT_B22_PCREL_X), _,
108  _, _, _, _,
109  _, _, _, _,
110  _ }},
112  { _, _, _, _,
113  _, _, P(_IE_16_X), _,
114  _, P(_9_X), _, _,
115  P(_IE_16_X), _, _, _,
116  P(_IE_16_X), _, _, _,
117  _, _, _, _,
118  _, _, _, _,
119  _, _, _, _,
120  P(_IE_32_6_X) }},
122  { _, _, _, _,
123  _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
124  P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
125  P(_IE_GOT_16_X), _, _, _,
126  P(_IE_GOT_16_X), _, _, _,
127  _, _, _, _,
128  _, _, _, _,
129  _, _, _, _,
130  P(_IE_GOT_32_6_X) }},
132  { _, _, _, _,
133  _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
134  P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
135  P(_LD_GOT_16_X), _, _, _,
136  P(_LD_GOT_16_X), _, _, _,
137  _, _, _, _,
138  _, _, _, _,
139  _, _, _, _,
140  P(_LD_GOT_32_6_X) }},
142  { _, _, _, _,
143  _, _, _, _,
144  _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
145  _, _, _, _,
146  _, _, _, _,
147  _, _, P(_LD_PLT_B22_PCREL_X), _,
148  _, _, _, _,
149  _, _, _, _,
150  _ }},
152  { _, _, _, _,
153  _, _, P(_6_PCREL_X), _,
154  _, P(_9_X), _, _,
155  _, _, _, _,
156  _, _, _, _,
157  _, _, _, _,
158  _, _, _, _,
159  _, _, _, _,
160  P(_32_PCREL) }},
162  { _, _, _, _,
163  _, _, P(_6_X), P(_8_X),
164  P(_8_X), P(_9_X), P(_10_X), P(_11_X),
165  P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
166  P(_16_X), _, _, _,
167  _, _, P(_B22_PCREL_X), _,
168  _, _, _, _,
169  _, _, _, _,
170  P(_32_6_X) }},
171 };
172 // [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
173 
174 static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
176  { _, _, _, _,
177  _, _, _, _,
178  _, _, _, _,
179  _, _, _, _,
180  P(_DTPREL_16), _, _, _,
181  _, _, _, _,
182  _, _, _, _,
183  _, _, _, _,
184  P(_DTPREL_32) }},
186  { _, _, _, _,
187  _, _, _, _,
188  _, _, _, _,
189  _, _, _, _,
190  _, _, _, _,
191  _, _, _, _,
192  _, _, _, _,
193  _, _, _, _,
194  P(_GOT_32) }},
196  { _, _, _, _,
197  _, _, _, _,
198  _, _, _, _,
199  _, _, _, _,
200  _ /* [2] */, _, _, _,
201  _, _, _, _,
202  _, _, _, _,
203  _, _, _, _,
204  P(_GOTREL_32) }},
206  { _, _, _, _,
207  _, _, _, _,
208  _, _, _, _,
209  _, _, _, _,
210  _, _, _, _,
211  _, _, P(_PLT_B22_PCREL), _,
212  _, _, _, _,
213  _, _, _, _,
214  _ }},
216  { _, _, _, _,
217  _, _, _, _,
218  _, _, _, P(_TPREL_11_X),
219  _, _, _, _,
220  P(_TPREL_16), _, _, _,
221  _, _, _, _,
222  _, _, _, _,
223  _, _, _, _,
224  P(_TPREL_32) }},
226  { _, _, _, _,
227  _, _, _, _,
228  _, _, _, _,
229  _, _, _, _,
230  P(_GD_GOT_16), _, _, _,
231  _, _, _, _,
232  _, _, _, _,
233  _, _, _, _,
234  P(_GD_GOT_32) }},
236  { _, _, _, _,
237  _, _, _, _,
238  _, _, _, _,
239  _, _, _, _,
240  _, _, _, _,
241  _, _, P(_GD_PLT_B22_PCREL), _,
242  _, _, _, _,
243  _, _, _, _,
244  _ }},
246  { _, _, _, _,
247  _, _, _, _,
248  _, _, _, _,
249  _, _, _, _,
250  P(_GPREL16_0), _, _, _,
251  _, _, _, _,
252  _, _, _, _,
253  _, _, _, _,
254  _ }},
256  { _, _, _, _,
257  _, _, _, _,
258  _, _, _, _,
259  _, _, _, _,
260  P(_HI16), _, _, _,
261  _, _, _, _,
262  _, _, _, _,
263  _, _, _, _,
264  _ }},
266  { _, _, _, _,
267  _, _, _, _,
268  _, _, _, _,
269  _, _, _, _,
270  _, _, _, _,
271  _, _, _, _,
272  _, _, _, _,
273  _, _, _, _,
274  P(_IE_32) }},
276  { _, _, _, _,
277  _, _, _, _,
278  _, _, _, _,
279  _, _, _, _,
280  P(_IE_GOT_16), _, _, _,
281  _, _, _, _,
282  _, _, _, _,
283  _, _, _, _,
284  P(_IE_GOT_32) }},
286  { _, _, _, _,
287  _, _, _, _,
288  _, _, _, _,
289  _, _, _, _,
290  P(_LD_GOT_16), _, _, _,
291  _, _, _, _,
292  _, _, _, _,
293  _, _, _, _,
294  P(_LD_GOT_32) }},
296  { _, _, _, _,
297  _, _, _, _,
298  _, _, _, _,
299  _, _, _, _,
300  _, _, _, _,
301  _, _, P(_LD_PLT_B22_PCREL), _,
302  _, _, _, _,
303  _, _, _, _,
304  _ }},
306  { _, _, _, _,
307  _, _, _, _,
308  _, _, _, _,
309  _, _, _, _,
310  P(_LO16), _, _, _,
311  _, _, _, _,
312  _, _, _, _,
313  _, _, _, _,
314  _ }},
316  { _, _, _, _,
317  _, _, _, _,
318  _, _, _, _,
319  _, _, _, _,
320  _, _, _, _,
321  _, _, _, _,
322  _, _, _, _,
323  _, _, _, _,
324  P(_32_PCREL) }},
326  { _, _, _, _,
327  _, _, _, _,
328  _, _, _, _,
329  _, P(_B13_PCREL), _, P(_B15_PCREL),
330  _, _, _, _,
331  _, _, P(_B22_PCREL), _,
332  _, _, _, _,
333  _, _, _, _,
334  P(_32) }},
335 };
336 //
337 // [2] The actual fixup is LO16 or HI16, depending on the instruction.
338 #undef P
339 #undef _
340 
341 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
342  MCInst const &MCI) const {
343  bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
344  if (State.Index == 0) {
346  assert(!Duplex);
347  assert(State.Index != Last);
349  }
350  }
351  if (State.Index == 1) {
353  assert(!Duplex);
354  assert(State.Index != Last);
356  }
357  }
358  if (Duplex) {
359  assert(State.Index == Last);
361  }
362  if (State.Index == Last)
365 }
366 
367 /// Emit the bundle.
370  const MCSubtargetInfo &STI) const {
371  MCInst &HMB = const_cast<MCInst &>(MI);
372 
374  LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
375  State.Addend = 0;
376  State.Extended = false;
377  State.Bundle = &MI;
378  State.Index = 0;
379  size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
380  FeatureBitset Features = computeAvailableFeatures(STI.getFeatureBits());
381 
382  for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
383  MCInst &HMI = const_cast<MCInst &>(*I.getInst());
384  verifyInstructionPredicates(HMI, Features);
385 
386  EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
387  State.Extended = HexagonMCInstrInfo::isImmext(HMI);
388  State.Addend += HEXAGON_INSTR_SIZE;
389  ++State.Index;
390  }
391 }
392 
393 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
394  unsigned Producer2) {
395  if (Consumer == Producer)
396  return true;
397  if (Consumer == Producer2)
398  return true;
399  // Calculate if we're a single vector consumer referencing a double producer
400  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
401  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
402  return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
403  return false;
404 }
405 
406 /// EncodeSingleInstruction - Emit a single
409  const MCSubtargetInfo &STI, uint32_t Parse) const {
411  uint64_t Binary;
412 
413  // Pseudo instructions don't get encoded and shouldn't be here
414  // in the first place!
415  assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
416  "pseudo-instruction found");
417  LLVM_DEBUG(dbgs() << "Encoding insn `"
418  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
419 
420  Binary = getBinaryCodeForInstr(MI, Fixups, STI);
421  unsigned Opc = MI.getOpcode();
422 
423  // Check for unimplemented instructions. Immediate extenders
424  // are encoded as zero, so they need to be accounted for.
425  if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
426  LLVM_DEBUG(dbgs() << "Unimplemented inst `"
427  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
428  llvm_unreachable("Unimplemented Instruction");
429  }
430  Binary |= Parse;
431 
432  // if we need to emit a duplexed instruction
433  if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
435  "Emitting duplex without duplex parse bits");
436  unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
437  // 29 is the bit position.
438  // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
439  // Last bit is moved to bit position 13
440  Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
441 
442  const MCInst *Sub0 = MI.getOperand(0).getInst();
443  const MCInst *Sub1 = MI.getOperand(1).getInst();
444 
445  // Get subinstruction slot 0.
446  unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
447  // Get subinstruction slot 1.
448  State.SubInst1 = true;
449  unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
450  State.SubInst1 = false;
451 
452  Binary |= SubBits0 | (SubBits1 << 16);
453  }
454  support::endian::write<uint32_t>(OS, Binary, support::little);
455  ++MCNumEmitted;
456 }
457 
459 static void raise_relocation_error(unsigned Width, unsigned Kind) {
460  std::string Text;
461  raw_string_ostream Stream(Text);
462  Stream << "Unrecognized relocation combination: width=" << Width
463  << " kind=" << Kind;
464  report_fatal_error(Stream.str());
465 }
466 
467 /// Some insns are not extended and thus have no bits. These cases require
468 /// a more brute force method for determining the correct relocation.
469 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
470  MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
471  const MCSymbolRefExpr::VariantKind VarKind) const {
472  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
473  unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
474  using namespace Hexagon;
475 
476  if (InsnType == HexagonII::TypeEXTENDER) {
477  if (VarKind == MCSymbolRefExpr::VK_None) {
478  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
479  for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
480  if (I->getInst() != &MI)
481  continue;
482  assert(I+1 != N && "Extender cannot be last in packet");
483  const MCInst &NextI = *(I+1)->getInst();
484  const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
485  if (NextD.isBranch() || NextD.isCall() ||
488  return fixup_Hexagon_32_6_X;
489  }
490  }
491 
492  static const std::map<unsigned,unsigned> Relocs = {
504  };
505 
506  auto F = Relocs.find(VarKind);
507  if (F != Relocs.end())
508  return Hexagon::Fixups(F->second);
509  raise_relocation_error(0, VarKind);
510  }
511 
512  if (MCID.isBranch())
514 
515  static const std::map<unsigned,unsigned> RelocsLo = {
525  };
526 
527  static const std::map<unsigned,unsigned> RelocsHi = {
537  };
538 
539  switch (MCID.getOpcode()) {
540  case Hexagon::LO:
541  case Hexagon::A2_tfril: {
542  auto F = RelocsLo.find(VarKind);
543  if (F != RelocsLo.end())
544  return Hexagon::Fixups(F->second);
545  break;
546  }
547  case Hexagon::HI:
548  case Hexagon::A2_tfrih: {
549  auto F = RelocsHi.find(VarKind);
550  if (F != RelocsHi.end())
551  return Hexagon::Fixups(F->second);
552  break;
553  }
554  }
555 
556  raise_relocation_error(0, VarKind);
557 }
558 
559 static bool isPCRel(unsigned Kind) {
560  switch (Kind){
579  return true;
580  default:
581  return false;
582  }
583 }
584 
585 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
586  const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
587  const MCSubtargetInfo &STI) const {
588  if (isa<HexagonMCExpr>(ME))
589  ME = &HexagonMCInstrInfo::getExpr(*ME);
590  int64_t Value;
591  if (ME->evaluateAsAbsolute(Value)) {
592  bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
594  // Only sub-instruction #1 can be extended in a duplex. If MI is a
595  // sub-instruction #0, it is not extended even if Extended is true
596  // (it can be true for the duplex as a whole).
597  bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
598  if (State.Extended && InstExtendable && !IsSub0) {
599  unsigned OpIdx = ~0u;
600  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
601  if (&MO != &MI.getOperand(I))
602  continue;
603  OpIdx = I;
604  break;
605  }
606  assert(OpIdx != ~0u);
607  if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
608  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
609  Value = (Value & 0x3f) << Shift;
610  }
611  }
612  return Value;
613  }
614  assert(ME->getKind() == MCExpr::SymbolRef ||
615  ME->getKind() == MCExpr::Binary);
616  if (ME->getKind() == MCExpr::Binary) {
617  MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
618  getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
619  getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
620  return 0;
621  }
622 
623  unsigned FixupKind = fixup_Invalid;
624  const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
625  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
626  unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
628  MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind();
629  unsigned Opc = MCID.getOpcode();
630  unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
631 
632  LLVM_DEBUG(dbgs() << "----------------------------------------\n"
633  << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
634  << "\nOpcode: " << Opc << "\nRelocation bits: "
635  << FixupWidth << "\nAddend: " << State.Addend
636  << "\nVariant: " << unsigned(VarKind)
637  << "\n----------------------------------------\n");
638 
639  // Pick the applicable fixup kind for the symbol.
640  // Handle special cases first, the rest will be looked up in the tables.
641 
642  if (FixupWidth == 16 && !State.Extended) {
643  if (VarKind == MCSymbolRefExpr::VK_None) {
645  // A2_iconst.
646  FixupKind = Hexagon::fixup_Hexagon_27_REG;
647  } else {
648  // Look for GP-relative fixups.
649  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
650  static const Hexagon::Fixups GPRelFixups[] = {
653  };
654  assert(Shift < array_lengthof(GPRelFixups));
655  auto UsesGP = [] (const MCInstrDesc &D) {
656  for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
657  if (*U == Hexagon::GP)
658  return true;
659  return false;
660  };
661  if (UsesGP(MCID))
662  FixupKind = GPRelFixups[Shift];
663  }
664  } else if (VarKind == MCSymbolRefExpr::VK_GOTREL) {
665  // Select between LO/HI.
666  if (Opc == Hexagon::LO)
668  else if (Opc == Hexagon::HI)
670  }
671  } else {
672  bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
673  switch (FixupWidth) {
674  case 9:
675  if (BranchOrCR)
676  FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
678  break;
679  case 8:
680  case 7:
681  if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT)
682  FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI)
685  else if (FixupWidth == 7 && BranchOrCR)
686  FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
688  break;
689  case 0:
690  FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
691  break;
692  }
693  }
694 
695  if (FixupKind == fixup_Invalid) {
696  const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
697 
698  auto FindVK = FixupTable.find(VarKind);
699  if (FindVK != FixupTable.end())
700  FixupKind = FindVK->second[FixupWidth];
701  }
702 
703  if (FixupKind == fixup_Invalid)
704  raise_relocation_error(FixupWidth, VarKind);
705 
706  const MCExpr *FixupExpr = MO.getExpr();
707  if (State.Addend != 0 && isPCRel(FixupKind)) {
708  const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
709  FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
710  }
711 
712  MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
713  MCFixupKind(FixupKind), MI.getLoc());
714  Fixups.push_back(Fixup);
715  // All of the information is in the fixup.
716  return 0;
717 }
718 
719 unsigned
721  SmallVectorImpl<MCFixup> &Fixups,
722  MCSubtargetInfo const &STI) const {
723 #ifndef NDEBUG
724  size_t OperandNumber = ~0U;
725  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
726  if (&MI.getOperand(i) == &MO) {
727  OperandNumber = i;
728  break;
729  }
730  assert((OperandNumber != ~0U) && "Operand not found");
731 #endif
732 
733  if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
734  &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) {
735  // Calculate the new value distance to the associated producer
736  unsigned SOffset = 0;
737  unsigned VOffset = 0;
738  unsigned UseReg = MO.getReg();
739  unsigned DefReg1, DefReg2;
740 
741  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
742  const MCOperand *I = Instrs.begin() + State.Index - 1;
743 
744  for (;; --I) {
745  assert(I != Instrs.begin() - 1 && "Couldn't find producer");
746  MCInst const &Inst = *I->getInst();
748  continue;
749 
750  DefReg1 = DefReg2 = 0;
751  ++SOffset;
752  if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
753  // Vector instructions don't count scalars.
754  ++VOffset;
755  }
756  if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
757  DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
758  if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
759  DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
760  if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
761  // This isn't the register we're looking for
762  continue;
763  }
764  if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
765  // Producer is unpredicated
766  break;
767  }
769  "Unpredicated consumer depending on predicated producer");
770  if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
772  // Producer predicate sense matched ours.
773  break;
774  }
775  // Hexagon PRM 10.11 Construct Nt from distance
776  unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
777  : SOffset;
778  Offset <<= 1;
779  Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
780  return Offset;
781  }
782 
783  assert(!MO.isImm());
784  if (MO.isReg()) {
785  unsigned Reg = MO.getReg();
789  return MCT.getRegisterInfo()->getEncodingValue(Reg);
790  }
791 
792  return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
793 }
794 
796  MCRegisterInfo const &MRI,
797  MCContext &MCT) {
798  return new HexagonMCCodeEmitter(MII, MCT);
799 }
800 
801 #define ENABLE_INSTR_PREDICATE_VERIFIER
802 #include "HexagonGenMCCodeEmitter.inc"
static LLVM_ATTRIBUTE_NORETURN void raise_relocation_error(unsigned Width, unsigned Kind)
uint64_t CallInst * C
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImm() const
Definition: MCInst.h:58
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
VariantKind getKind() const
Definition: MCExpr.h:336
static const std::map< unsigned, std::vector< unsigned > > StdFixups
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:57
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:562
#define HEXAGON_INSTR_SIZE
STATISTIC(NumFunctions, "Total number of functions")
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isOuterLoop(MCInst const &MCI)
static Lanai::Fixups FixupKind(const MCExpr *Expr)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
static const unsigned fixup_Invalid
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:276
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:74
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
bool isImmext(MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool s27_2_reloc(MCExpr const &Expr)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:565
const MCInst * getInst() const
Definition: MCInst.h:105
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
const MCExpr * getExpr() const
Definition: MCInst.h:95
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumOperands() const
Definition: MCInst.h:181
Definition for classes that emit Hexagon machine code from MCInsts.
Binary assembler expressions.
Definition: MCExpr.h:415
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
PowerPC TLS Dynamic Call Fixup
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
ExprKind getKind() const
Definition: MCExpr.h:72
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
#define LLVM_ATTRIBUTE_NORETURN
Definition: Compiler.h:221
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
SMLoc getLoc() const
Definition: MCInst.h:177
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
#define P(x)
static unsigned UseReg(const MachineOperand &MO)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:257
Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:40
size_t bundleSize(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
LLVM Value Representation.
Definition: Value.h:72
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
Binary expressions.
Definition: MCExpr.h:38
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
static bool isPCRel(unsigned Kind)
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
unsigned getOpcode() const
Definition: MCInst.h:171
#define LLVM_DEBUG(X)
Definition: Debug.h:122
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
#define _
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)