LLVM  9.0.0svn
HexagonMCTargetDesc.cpp
Go to the documentation of this file.
1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "Hexagon.h"
15 #include "HexagonDepArch.h"
16 #include "HexagonTargetStreamer.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/BinaryFormat/ELF.h"
25 #include "llvm/MC/MCAsmBackend.h"
26 #include "llvm/MC/MCCodeEmitter.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/MC/MCELFStreamer.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectWriter.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCStreamer.h"
39 #include <cassert>
40 #include <cstdint>
41 #include <new>
42 #include <string>
43 
44 using namespace llvm;
45 
46 #define GET_INSTRINFO_MC_DESC
47 #include "HexagonGenInstrInfo.inc"
48 
49 #define GET_SUBTARGETINFO_MC_DESC
50 #include "HexagonGenSubtargetInfo.inc"
51 
52 #define GET_REGINFO_MC_DESC
53 #include "HexagonGenRegisterInfo.inc"
54 
56  ("mno-compound",
57  cl::desc("Disable looking for compound instructions for Hexagon"));
58 
60  ("mno-pairing",
61  cl::desc("Disable looking for duplex instructions for Hexagon"));
62 
63 namespace { // These flags are to be deprecated
64 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
65  cl::init(false));
66 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
67  cl::init(false));
68 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
69  cl::init(false));
70 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
71  cl::init(false));
72 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
73  cl::init(false));
74 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
75  cl::init(false));
76 } // namespace
77 
79  EnableHVX("mhvx",
80  cl::desc("Enable Hexagon Vector eXtensions"),
81  cl::values(
82  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
83  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
84  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
85  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
86  // Sentinel for no value specified.
88  // Sentinel for flag not present.
90 
91 static cl::opt<bool>
92  DisableHVX("mno-hvx", cl::Hidden,
93  cl::desc("Disable Hexagon Vector eXtensions"));
94 
95 
96 static StringRef DefaultArch = "hexagonv60";
97 
99  if (MV5)
100  return "hexagonv5";
101  if (MV55)
102  return "hexagonv55";
103  if (MV60)
104  return "hexagonv60";
105  if (MV62)
106  return "hexagonv62";
107  if (MV65)
108  return "hexagonv65";
109  if (MV66)
110  return "hexagonv66";
111  return "";
112 }
113 
116  if (!ArchV.empty() && !CPU.empty()) {
117  if (ArchV != CPU)
118  report_fatal_error("conflicting architectures specified.");
119  return CPU;
120  }
121  if (ArchV.empty()) {
122  if (CPU.empty())
123  CPU = DefaultArch;
124  return CPU;
125  }
126  return ArchV;
127 }
128 
129 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
130 
131 namespace {
132 
133 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
134 public:
135  HexagonTargetAsmStreamer(MCStreamer &S,
137  bool isVerboseAsm,
138  MCInstPrinter &IP)
139  : HexagonTargetStreamer(S) {}
140 
141  void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
142  const MCInst &Inst, const MCSubtargetInfo &STI) override {
145  std::string Buffer;
146  {
147  raw_string_ostream TempStream(Buffer);
148  InstPrinter.printInst(&Inst, TempStream, "", STI);
149  }
150  StringRef Contents(Buffer);
151  auto PacketBundle = Contents.rsplit('\n');
152  auto HeadTail = PacketBundle.first.split('\n');
153  StringRef Separator = "\n";
154  StringRef Indent = "\t";
155  OS << "\t{\n";
156  while (!HeadTail.first.empty()) {
157  StringRef InstTxt;
158  auto Duplex = HeadTail.first.split('\v');
159  if (!Duplex.second.empty()) {
160  OS << Indent << Duplex.first << Separator;
161  InstTxt = Duplex.second;
162  } else if (!HeadTail.first.trim().startswith("immext")) {
163  InstTxt = Duplex.first;
164  }
165  if (!InstTxt.empty())
166  OS << Indent << InstTxt << Separator;
167  HeadTail = HeadTail.second.split('\n');
168  }
169 
171  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
172  else
173  OS << "\t}" << PacketBundle.second;
174  }
175 };
176 
177 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
178 public:
179  MCELFStreamer &getStreamer() {
180  return static_cast<MCELFStreamer &>(Streamer);
181  }
182  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
183  : HexagonTargetStreamer(S) {
184  MCAssembler &MCA = getStreamer().getAssembler();
186  }
187 
188 
189  void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
190  unsigned ByteAlignment,
191  unsigned AccessSize) override {
192  HexagonMCELFStreamer &HexagonELFStreamer =
193  static_cast<HexagonMCELFStreamer &>(getStreamer());
194  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
195  AccessSize);
196  }
197 
198  void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
199  unsigned ByteAlignment,
200  unsigned AccessSize) override {
201  HexagonMCELFStreamer &HexagonELFStreamer =
202  static_cast<HexagonMCELFStreamer &>(getStreamer());
203  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
204  Symbol, Size, ByteAlignment, AccessSize);
205  }
206 };
207 
208 } // end anonymous namespace
209 
211  MCInstrInfo *X = new MCInstrInfo();
212  InitHexagonMCInstrInfo(X);
213  return X;
214 }
215 
218  InitHexagonMCRegisterInfo(X, Hexagon::R31);
219  return X;
220 }
221 
223  const Triple &TT) {
224  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
225 
226  // VirtualFP = (R30 + #0).
227  MCCFIInstruction Inst =
229  MRI.getDwarfRegNum(Hexagon::R30, true), 0);
230  MAI->addInitialFrameState(Inst);
231 
232  return MAI;
233 }
234 
236  unsigned SyntaxVariant,
237  const MCAsmInfo &MAI,
238  const MCInstrInfo &MII,
239  const MCRegisterInfo &MRI)
240 {
241  if (SyntaxVariant == 0)
242  return new HexagonInstPrinter(MAI, MII, MRI);
243  else
244  return nullptr;
245 }
246 
247 static MCTargetStreamer *
249  MCInstPrinter *IP, bool IsVerboseAsm) {
250  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
251 }
252 
254  std::unique_ptr<MCAsmBackend> &&MAB,
255  std::unique_ptr<MCObjectWriter> &&OW,
256  std::unique_ptr<MCCodeEmitter> &&Emitter,
257  bool RelaxAll) {
258  return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
259  std::move(Emitter));
260 }
261 
262 static MCTargetStreamer *
264  return new HexagonTargetELFStreamer(S, STI);
265 }
266 
268  uint64_t FB = STI->getFeatureBits().to_ullong();
269  if (FB & (1ULL << F))
270  STI->ToggleFeature(F);
271 }
272 
274  uint64_t FB = STI->getFeatureBits().to_ullong();
275  return (FB & (1ULL << F)) != 0;
276 }
277 
278 namespace {
279 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
281  if (!FS.empty())
282  Result.push_back(FS);
283 
284  switch (EnableHVX) {
287  break;
289  Result.push_back("+hvxv60");
290  break;
292  Result.push_back("+hvxv62");
293  break;
295  Result.push_back("+hvxv65");
296  break;
298  Result.push_back("+hvxv66");
299  break;
302  .Case("hexagonv60", "+hvxv60")
303  .Case("hexagonv62", "+hvxv62")
304  .Case("hexagonv65", "+hvxv65")
305  .Case("hexagonv66", "+hvxv66"));
306  break;
307  }
309  // Sentinal if -mhvx isn't specified
310  break;
311  }
312  return join(Result.begin(), Result.end(), ",");
313 }
314 }
315 
316 static bool isCPUValid(std::string CPU)
317 {
318  std::vector<std::string> table {
319  "generic", "hexagonv5", "hexagonv55", "hexagonv60",
320  "hexagonv62", "hexagonv65", "hexagonv66",
321  };
322 
323  return std::find(table.begin(), table.end(), CPU) != table.end();
324 }
325 
326 namespace {
327 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
328  StringRef FS) {
329  std::pair<std::string, std::string> Result;
330  Result.first = Hexagon_MC::selectHexagonCPU(CPU);
331  Result.second = selectHexagonFS(Result.first, FS);
332  return Result;
333 }
334 }
335 
337  using namespace Hexagon;
338  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
339  // turns on hvxvNN, corresponding to the existing ArchVNN.
340  FeatureBitset FB = S;
341  unsigned CpuArch = ArchV5;
342  for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
343  if (!FB.test(F))
344  continue;
345  CpuArch = F;
346  break;
347  }
348  bool UseHvx = false;
349  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
350  if (!FB.test(F))
351  continue;
352  UseHvx = true;
353  break;
354  }
355  bool HasHvxVer = false;
356  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
357  ExtensionHVXV66}) {
358  if (!FB.test(F))
359  continue;
360  HasHvxVer = true;
361  UseHvx = true;
362  break;
363  }
364 
365  if (!UseHvx || HasHvxVer)
366  return FB;
367 
368  // HasHvxVer is false, and UseHvx is true.
369  switch (CpuArch) {
370  case ArchV66:
371  FB.set(ExtensionHVXV66);
373  case ArchV65:
374  FB.set(ExtensionHVXV65);
376  case ArchV62:
377  FB.set(ExtensionHVXV62);
379  case ArchV60:
380  FB.set(ExtensionHVXV60);
381  break;
382  }
383  return FB;
384 }
385 
387  StringRef CPU,
388  StringRef FS) {
389  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
390  StringRef CPUName = Features.first;
391  StringRef ArchFS = Features.second;
392 
393  if (!isCPUValid(CPUName.str())) {
394  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
395  << "\" specified\n";
396  return nullptr;
397  }
398 
399  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
400  if (HexagonDisableDuplex) {
401  llvm::FeatureBitset Features = X->getFeatureBits();
402  X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
403  }
404 
406  return X;
407 }
408 
410  static std::map<StringRef,unsigned> ElfFlags = {
411  {"hexagonv5", ELF::EF_HEXAGON_MACH_V5},
412  {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
413  {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
414  {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
415  {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
416  {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
417  };
418 
419  auto F = ElfFlags.find(STI.getCPU());
420  assert(F != ElfFlags.end() && "Unrecognized Architecture");
421  return F->second;
422 }
423 
424 namespace {
425 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
426 public:
427  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
428 
429  bool isUnconditionalBranch(MCInst const &Inst) const override {
430  //assert(!HexagonMCInstrInfo::isBundle(Inst));
432  }
433 
434  bool isConditionalBranch(MCInst const &Inst) const override {
435  //assert(!HexagonMCInstrInfo::isBundle(Inst));
437  }
438 
439  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
440  uint64_t Size, uint64_t &Target) const override {
441  //assert(!HexagonMCInstrInfo::isBundle(Inst));
442  if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
443  return false;
444  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
445  assert(Extended.isExpr());
446  int64_t Value;
447  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
448  return false;
449  Target = Value;
450  return true;
451  }
452 };
453 }
454 
456  return new HexagonMCInstrAnalysis(Info);
457 }
458 
459 // Force static initialization.
460 extern "C" void LLVMInitializeHexagonTargetMC() {
461  // Register the MC asm info.
463 
464  // Register the MC instruction info.
467 
468  // Register the MC register info.
471 
472  // Register the MC subtarget info.
475 
476  // Register the MC Code Emitter
479 
480  // Register the asm backend
483 
484 
485  // Register the MC instruction analyzer.
488 
489  // Register the obj streamer
492 
493  // Register the obj target streamer
496 
497  // Register the asm streamer
500 
501  // Register the MC Inst Printer
504 }
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
LLVMContext & Context
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setFeatureBits(const FeatureBitset &FeatureBits_)
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Target specific streamer interface.
Definition: MCStreamer.h:83
virtual bool isConditionalBranch(const MCInst &Inst) const
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
LLVM_NODISCARD std::pair< StringRef, StringRef > rsplit(StringRef Separator) const
Split into two substrings around the last occurrence of a separator string.
Definition: StringRef.h:729
F(f)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
void LLVMInitializeHexagonTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
const FeatureBitset & getFeatureBits() const
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
std::string join(IteratorT Begin, IteratorT End, StringRef Separator)
Joins the strings in the range [Begin, End), adding Separator between the elements.
Definition: StringExtras.h:370
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Context object for machine code objects.
Definition: MCContext.h:62
virtual bool isUnconditionalBranch(const MCInst &Inst) const
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
static StringRef DefaultArch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:208
MCInstrInfo * createHexagonMCInstrInfo()
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
StringRef selectHexagonCPU(StringRef CPU)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Streaming machine code generation interface.
Definition: MCStreamer.h:188
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:477
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:652
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
cl::opt< bool > HexagonDisableCompound
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1206
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
static bool isCPUValid(std::string CPU)
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:73
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
StringRef getCPU() const
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
bool isMemReorderDisabled(MCInst const &MCI)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:627
static StringRef HexagonGetArchVariant()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
size_t bundleSize(MCInst const &MCI)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
#define HEXAGON_PACKET_SIZE
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
LLVM Value Representation.
Definition: Value.h:72
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
cl::opt< Hexagon::ArchEnum > EnableHVX("mhvx", cl::desc("Enable Hexagon Vector eXtensions"), cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::Generic, "", "")), cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)