LLVM  10.0.0svn
LanaiInstrInfo.h
Go to the documentation of this file.
1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Lanai implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
14 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
15 
16 #include "LanaiRegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "LanaiGenInstrInfo.inc"
22 
23 namespace llvm {
24 
26  const LanaiRegisterInfo RegisterInfo;
27 
28 public:
30 
31  // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32  // such, whenever a client has an instance of instruction info, it should
33  // always be able to get register info as well (through this method).
34  virtual const LanaiRegisterInfo &getRegisterInfo() const {
35  return RegisterInfo;
36  }
37 
39  const MachineInstr &MIb,
40  AliasAnalysis *AA) const override;
41 
42  unsigned isLoadFromStackSlot(const MachineInstr &MI,
43  int &FrameIndex) const override;
44 
45  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
46  int &FrameIndex) const override;
47 
48  unsigned isStoreToStackSlot(const MachineInstr &MI,
49  int &FrameIndex) const override;
50 
52  const DebugLoc &DL, unsigned DestinationRegister,
53  unsigned SourceRegister, bool KillSource) const override;
54 
55  void
58  unsigned SourceRegister, bool IsKill, int FrameIndex,
59  const TargetRegisterClass *RegisterClass,
60  const TargetRegisterInfo *RegisterInfo) const override;
61 
62  void
65  unsigned DestinationRegister, int FrameIndex,
66  const TargetRegisterClass *RegisterClass,
67  const TargetRegisterInfo *RegisterInfo) const override;
68 
69  bool expandPostRAPseudo(MachineInstr &MI) const override;
70 
71  bool getMemOperandWithOffset(const MachineInstr &LdSt,
72  const MachineOperand *&BaseOp,
73  int64_t &Offset,
74  const TargetRegisterInfo *TRI) const override;
75 
77  const MachineOperand *&BaseOp,
78  int64_t &Offset, unsigned &Width,
79  const TargetRegisterInfo *TRI) const;
80 
81  std::pair<unsigned, unsigned>
82  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
83 
86 
87  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
88  MachineBasicBlock *&FalseBlock,
90  bool AllowModify) const override;
91 
92  unsigned removeBranch(MachineBasicBlock &MBB,
93  int *BytesRemoved = nullptr) const override;
94 
95  // For a comparison instruction, return the source registers in SrcReg and
96  // SrcReg2 if having two register operands, and the value it compares against
97  // in CmpValue. Return true if the comparison instruction can be analyzed.
98  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
99  unsigned &SrcReg2, int &CmpMask,
100  int &CmpValue) const override;
101 
102  // See if the comparison instruction can be converted into something more
103  // efficient. E.g., on Lanai register-register instructions can set the flag
104  // register, obviating the need for a separate compare.
105  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
106  unsigned SrcReg2, int CmpMask, int CmpValue,
107  const MachineRegisterInfo *MRI) const override;
108 
109  // Analyze the given select instruction, returning true if it cannot be
110  // understood. It is assumed that MI->isSelect() is true.
111  //
112  // When successful, return the controlling condition and the operands that
113  // determine the true and false result values.
114  //
115  // Result = SELECT Cond, TrueOp, FalseOp
116  //
117  // Lanai can optimize certain select instructions, for example by predicating
118  // the instruction defining one of the operands and sets Optimizable to true.
119  bool analyzeSelect(const MachineInstr &MI,
120  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
121  unsigned &FalseOp, bool &Optimizable) const override;
122 
123  // Given a select instruction that was understood by analyzeSelect and
124  // returned Optimizable = true, attempt to optimize MI by merging it with one
125  // of its operands. Returns NULL on failure.
126  //
127  // When successful, returns the new select instruction. The client is
128  // responsible for deleting MI.
129  //
130  // If both sides of the select can be optimized, the TrueOp is modifed.
131  // PreferFalse is not used.
134  bool PreferFalse) const override;
135 
137  SmallVectorImpl<MachineOperand> &Condition) const override;
138 
139  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
140  MachineBasicBlock *FalseBlock,
141  ArrayRef<MachineOperand> Condition,
142  const DebugLoc &DL,
143  int *BytesAdded = nullptr) const override;
144 };
145 
146 static inline bool isSPLSOpcode(unsigned Opcode) {
147  switch (Opcode) {
148  case Lanai::LDBs_RI:
149  case Lanai::LDBz_RI:
150  case Lanai::LDHs_RI:
151  case Lanai::LDHz_RI:
152  case Lanai::STB_RI:
153  case Lanai::STH_RI:
154  return true;
155  default:
156  return false;
157  }
158 }
159 
160 static inline bool isRMOpcode(unsigned Opcode) {
161  switch (Opcode) {
162  case Lanai::LDW_RI:
163  case Lanai::SW_RI:
164  return true;
165  default:
166  return false;
167  }
168 }
169 
170 static inline bool isRRMOpcode(unsigned Opcode) {
171  switch (Opcode) {
172  case Lanai::LDBs_RR:
173  case Lanai::LDBz_RR:
174  case Lanai::LDHs_RR:
175  case Lanai::LDHz_RR:
176  case Lanai::LDWz_RR:
177  case Lanai::LDW_RR:
178  case Lanai::STB_RR:
179  case Lanai::STH_RR:
180  case Lanai::SW_RR:
181  return true;
182  default:
183  return false;
184  }
185 }
186 
187 } // namespace llvm
188 
189 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static bool isRRMOpcode(unsigned Opcode)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool expandPostRAPseudo(MachineInstr &MI) const override
Position
Position to insert a new instruction relative to an existing instruction.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool PreferFalse) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned const MachineRegisterInfo * MRI
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isRMOpcode(unsigned Opcode)
virtual const LanaiRegisterInfo & getRegisterInfo() const
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, unsigned DestinationRegister, unsigned SourceRegister, bool KillSource) const override
static bool isSPLSOpcode(unsigned Opcode)
IRTranslator LLVM IR MI
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool getMemOperandWithOffset(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override