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MachineOperand.h
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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/DataTypes.h"
21 #include <cassert>
22 
23 namespace llvm {
24 
25 class BlockAddress;
26 class Constant;
27 class ConstantFP;
28 class ConstantInt;
29 class GlobalValue;
30 class MachineBasicBlock;
31 class MachineInstr;
32 class MachineRegisterInfo;
33 class MCCFIInstruction;
34 class MDNode;
35 class ModuleSlotTracker;
36 class TargetMachine;
37 class TargetIntrinsicInfo;
38 class TargetRegisterInfo;
39 class hash_code;
40 class raw_ostream;
41 class MCSymbol;
42 
43 /// MachineOperand class - Representation of each machine instruction operand.
44 ///
45 /// This class isn't a POD type because it has a private constructor, but its
46 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
47 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
48 /// not having to call the MachineOperand destructor.
49 ///
51 public:
52  enum MachineOperandType : unsigned char {
53  MO_Register, ///< Register operand.
54  MO_Immediate, ///< Immediate operand
55  MO_CImmediate, ///< Immediate >64bit operand
56  MO_FPImmediate, ///< Floating-point immediate operand
57  MO_MachineBasicBlock, ///< MachineBasicBlock reference
58  MO_FrameIndex, ///< Abstract Stack Frame Index
59  MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
60  MO_TargetIndex, ///< Target-dependent index+offset operand.
61  MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
62  MO_ExternalSymbol, ///< Name of external global symbol
63  MO_GlobalAddress, ///< Address of a global value
64  MO_BlockAddress, ///< Address of a basic block
65  MO_RegisterMask, ///< Mask of preserved registers.
66  MO_RegisterLiveOut, ///< Mask of live-out registers.
67  MO_Metadata, ///< Metadata reference (for debug info)
68  MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
69  MO_CFIIndex, ///< MCCFIInstruction index.
70  MO_IntrinsicID, ///< Intrinsic ID for ISel
71  MO_Predicate, ///< Generic predicate for ISel
72  MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
74  };
75 
76 private:
77  /// OpKind - Specify what kind of operand this is. This discriminates the
78  /// union.
79  unsigned OpKind : 8;
80 
81  /// Subregister number for MO_Register. A value of 0 indicates the
82  /// MO_Register has no subReg.
83  ///
84  /// For all other kinds of operands, this field holds target-specific flags.
85  unsigned SubReg_TargetFlags : 12;
86 
87  /// TiedTo - Non-zero when this register operand is tied to another register
88  /// operand. The encoding of this field is described in the block comment
89  /// before MachineInstr::tieOperands().
90  unsigned TiedTo : 4;
91 
92  /// IsDef - True if this is a def, false if this is a use of the register.
93  /// This is only valid on register operands.
94  ///
95  unsigned IsDef : 1;
96 
97  /// IsImp - True if this is an implicit def or use, false if it is explicit.
98  /// This is only valid on register opderands.
99  ///
100  unsigned IsImp : 1;
101 
102  /// IsDeadOrKill
103  /// For uses: IsKill - True if this instruction is the last use of the
104  /// register on this path through the function.
105  /// For defs: IsDead - True if this register is never used by a subsequent
106  /// instruction.
107  /// This is only valid on register operands.
108  unsigned IsDeadOrKill : 1;
109 
110  /// See isRenamable().
111  unsigned IsRenamable : 1;
112 
113  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
114  /// read value doesn't matter. This flag can be set on both use and def
115  /// operands. On a sub-register def operand, it refers to the part of the
116  /// register that isn't written. On a full-register def operand, it is a
117  /// noop. See readsReg().
118  ///
119  /// This is only valid on registers.
120  ///
121  /// Note that an instruction may have multiple <undef> operands referring to
122  /// the same register. In that case, the instruction may depend on those
123  /// operands reading the same dont-care value. For example:
124  ///
125  /// %1 = XOR undef %2, undef %2
126  ///
127  /// Any register can be used for %2, and its value doesn't matter, but
128  /// the two operands must be the same register.
129  ///
130  unsigned IsUndef : 1;
131 
132  /// IsInternalRead - True if this operand reads a value that was defined
133  /// inside the same instruction or bundle. This flag can be set on both use
134  /// and def operands. On a sub-register def operand, it refers to the part
135  /// of the register that isn't written. On a full-register def operand, it
136  /// is a noop.
137  ///
138  /// When this flag is set, the instruction bundle must contain at least one
139  /// other def of the register. If multiple instructions in the bundle define
140  /// the register, the meaning is target-defined.
141  unsigned IsInternalRead : 1;
142 
143  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
144  /// by the MachineInstr before all input registers are read. This is used to
145  /// model the GCC inline asm '&' constraint modifier.
146  unsigned IsEarlyClobber : 1;
147 
148  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
149  /// not a real instruction. Such uses should be ignored during codegen.
150  unsigned IsDebug : 1;
151 
152  /// SmallContents - This really should be part of the Contents union, but
153  /// lives out here so we can get a better packed struct.
154  /// MO_Register: Register number.
155  /// OffsetedInfo: Low bits of offset.
156  union {
157  unsigned RegNo; // For MO_Register.
158  unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
159  } SmallContents;
160 
161  /// ParentMI - This is the instruction that this operand is embedded into.
162  /// This is valid for all operand types, when the operand is in an instr.
163  MachineInstr *ParentMI;
164 
165  /// Contents union - This contains the payload for the various operand types.
166  union {
167  MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
168  const ConstantFP *CFP; // For MO_FPImmediate.
169  const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
170  int64_t ImmVal; // For MO_Immediate.
171  const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
172  const MDNode *MD; // For MO_Metadata.
173  MCSymbol *Sym; // For MO_MCSymbol.
174  unsigned CFIIndex; // For MO_CFI.
175  Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
176  unsigned Pred; // For MO_Predicate
177  const Constant *ShuffleMask; // For MO_ShuffleMask
178 
179  struct { // For MO_Register.
180  // Register number is in SmallContents.RegNo.
181  MachineOperand *Prev; // Access list for register. See MRI.
183  } Reg;
184 
185  /// OffsetedInfo - This struct contains the offset and an object identifier.
186  /// this represent the object as with an optional offset from it.
187  struct {
188  union {
189  int Index; // For MO_*Index - The index itself.
190  const char *SymbolName; // For MO_ExternalSymbol.
191  const GlobalValue *GV; // For MO_GlobalAddress.
192  const BlockAddress *BA; // For MO_BlockAddress.
193  } Val;
194  // Low bits of offset are in SmallContents.OffsetLo.
195  int OffsetHi; // An offset from the object, high 32 bits.
196  } OffsetedInfo;
197  } Contents;
198 
200  : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
201  // Assert that the layout is what we expect. It's easy to grow this object.
202  static_assert(alignof(MachineOperand) <= alignof(int64_t),
203  "MachineOperand shouldn't be more than 8 byte aligned");
204  static_assert(sizeof(Contents) <= 2 * sizeof(void *),
205  "Contents should be at most two pointers");
206  static_assert(sizeof(MachineOperand) <=
207  alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
208  3 * sizeof(void *)),
209  "MachineOperand too big. Should be Kind, SmallContents, "
210  "ParentMI, and Contents");
211  }
212 
213 public:
214  /// getType - Returns the MachineOperandType for this operand.
215  ///
216  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
217 
218  unsigned getTargetFlags() const {
219  return isReg() ? 0 : SubReg_TargetFlags;
220  }
221  void setTargetFlags(unsigned F) {
222  assert(!isReg() && "Register operands can't have target flags");
223  SubReg_TargetFlags = F;
224  assert(SubReg_TargetFlags == F && "Target flags out of range");
225  }
226  void addTargetFlag(unsigned F) {
227  assert(!isReg() && "Register operands can't have target flags");
228  SubReg_TargetFlags |= F;
229  assert((SubReg_TargetFlags & F) && "Target flags out of range");
230  }
231 
232 
233  /// getParent - Return the instruction that this operand belongs to.
234  ///
235  MachineInstr *getParent() { return ParentMI; }
236  const MachineInstr *getParent() const { return ParentMI; }
237 
238  /// clearParent - Reset the parent pointer.
239  ///
240  /// The MachineOperand copy constructor also copies ParentMI, expecting the
241  /// original to be deleted. If a MachineOperand is ever stored outside a
242  /// MachineInstr, the parent pointer must be cleared.
243  ///
244  /// Never call clearParent() on an operand in a MachineInstr.
245  ///
246  void clearParent() { ParentMI = nullptr; }
247 
248  /// Print a subreg index operand.
249  /// MO_Immediate operands can also be subreg idices. If it's the case, the
250  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
251  /// called to check this.
252  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
253  const TargetRegisterInfo *TRI);
254 
255  /// Print operand target flags.
256  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
257 
258  /// Print a MCSymbol as an operand.
259  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
260 
261  /// Print a stack object reference.
262  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
263  bool IsFixed, StringRef Name);
264 
265  /// Print the offset with explicit +/- signs.
266  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
267 
268  /// Print an IRSlotNumber.
269  static void printIRSlotNumber(raw_ostream &OS, int Slot);
270 
271  /// Print the MachineOperand to \p os.
272  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
273  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
274  /// function will try to pick it up from the parent.
275  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
276  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
277 
278  /// More complex way of printing a MachineOperand.
279  /// \param TypeToPrint specifies the generic type to be printed on uses and
280  /// defs. It can be determined using MachineInstr::getTypeToPrint.
281  /// \param PrintDef - whether we want to print `def` on an operand which
282  /// isDef. Sometimes, if the operand is printed before '=', we don't print
283  /// `def`.
284  /// \param IsStandalone - whether we want a verbose output of the MO. This
285  /// prints extra information that can be easily inferred when printing the
286  /// whole function, but not when printing only a fragment of it.
287  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
288  /// Sometimes they are easily determined by the instruction's descriptor
289  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
290  /// \param TiedOperandIdx - if we need to print register ties this needs to
291  /// provide the index of the tied register. If not, it will be ignored.
292  /// \param TRI - provide more target-specific information to the printer.
293  /// Unlike the previous function, this one will not try and get the
294  /// information from it's parent.
295  /// \param IntrinsicInfo - same as \p TRI.
296  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
297  bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
298  unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
299  const TargetIntrinsicInfo *IntrinsicInfo) const;
300 
301  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
302  /// type to be printed the same way the full version of print(...) does it.
303  void print(raw_ostream &os, LLT TypeToPrint,
304  const TargetRegisterInfo *TRI = nullptr,
305  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
306 
307  void dump() const;
308 
309  //===--------------------------------------------------------------------===//
310  // Accessors that tell you what kind of MachineOperand you're looking at.
311  //===--------------------------------------------------------------------===//
312 
313  /// isReg - Tests if this is a MO_Register operand.
314  bool isReg() const { return OpKind == MO_Register; }
315  /// isImm - Tests if this is a MO_Immediate operand.
316  bool isImm() const { return OpKind == MO_Immediate; }
317  /// isCImm - Test if this is a MO_CImmediate operand.
318  bool isCImm() const { return OpKind == MO_CImmediate; }
319  /// isFPImm - Tests if this is a MO_FPImmediate operand.
320  bool isFPImm() const { return OpKind == MO_FPImmediate; }
321  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
322  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
323  /// isFI - Tests if this is a MO_FrameIndex operand.
324  bool isFI() const { return OpKind == MO_FrameIndex; }
325  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
326  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
327  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
328  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
329  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
330  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
331  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
332  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
333  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
334  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
335  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
336  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
337  /// isRegMask - Tests if this is a MO_RegisterMask operand.
338  bool isRegMask() const { return OpKind == MO_RegisterMask; }
339  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
340  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
341  /// isMetadata - Tests if this is a MO_Metadata operand.
342  bool isMetadata() const { return OpKind == MO_Metadata; }
343  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
344  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
345  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
346  bool isPredicate() const { return OpKind == MO_Predicate; }
347  bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
348  //===--------------------------------------------------------------------===//
349  // Accessors for Register Operands
350  //===--------------------------------------------------------------------===//
351 
352  /// getReg - Returns the register number.
353  Register getReg() const {
354  assert(isReg() && "This is not a register operand!");
355  return Register(SmallContents.RegNo);
356  }
357 
358  unsigned getSubReg() const {
359  assert(isReg() && "Wrong MachineOperand accessor");
360  return SubReg_TargetFlags;
361  }
362 
363  bool isUse() const {
364  assert(isReg() && "Wrong MachineOperand accessor");
365  return !IsDef;
366  }
367 
368  bool isDef() const {
369  assert(isReg() && "Wrong MachineOperand accessor");
370  return IsDef;
371  }
372 
373  bool isImplicit() const {
374  assert(isReg() && "Wrong MachineOperand accessor");
375  return IsImp;
376  }
377 
378  bool isDead() const {
379  assert(isReg() && "Wrong MachineOperand accessor");
380  return IsDeadOrKill & IsDef;
381  }
382 
383  bool isKill() const {
384  assert(isReg() && "Wrong MachineOperand accessor");
385  return IsDeadOrKill & !IsDef;
386  }
387 
388  bool isUndef() const {
389  assert(isReg() && "Wrong MachineOperand accessor");
390  return IsUndef;
391  }
392 
393  /// isRenamable - Returns true if this register may be renamed, i.e. it does
394  /// not generate a value that is somehow read in a way that is not represented
395  /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
396  /// valid on physical register operands. Virtual registers are assumed to
397  /// always be renamable regardless of the value of this field.
398  ///
399  /// Operands that are renamable can freely be changed to any other register
400  /// that is a member of the register class returned by
401  /// MI->getRegClassConstraint().
402  ///
403  /// isRenamable can return false for several different reasons:
404  ///
405  /// - ABI constraints (since liveness is not always precisely modeled). We
406  /// conservatively handle these cases by setting all physical register
407  /// operands that didn’t start out as virtual regs to not be renamable.
408  /// Also any physical register operands created after register allocation or
409  /// whose register is changed after register allocation will not be
410  /// renamable. This state is tracked in the MachineOperand::IsRenamable
411  /// bit.
412  ///
413  /// - Opcode/target constraints: for opcodes that have complex register class
414  /// requirements (e.g. that depend on other operands/instructions), we set
415  /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
416  /// description. Operands belonging to instructions with opcodes that are
417  /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
418  /// isRenamable(). Additionally, the AllowRegisterRenaming target property
419  /// prevents any operands from being marked renamable for targets that don't
420  /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
421  /// values.
422  bool isRenamable() const;
423 
424  bool isInternalRead() const {
425  assert(isReg() && "Wrong MachineOperand accessor");
426  return IsInternalRead;
427  }
428 
429  bool isEarlyClobber() const {
430  assert(isReg() && "Wrong MachineOperand accessor");
431  return IsEarlyClobber;
432  }
433 
434  bool isTied() const {
435  assert(isReg() && "Wrong MachineOperand accessor");
436  return TiedTo;
437  }
438 
439  bool isDebug() const {
440  assert(isReg() && "Wrong MachineOperand accessor");
441  return IsDebug;
442  }
443 
444  /// readsReg - Returns true if this operand reads the previous value of its
445  /// register. A use operand with the <undef> flag set doesn't read its
446  /// register. A sub-register def implicitly reads the other parts of the
447  /// register being redefined unless the <undef> flag is set.
448  ///
449  /// This refers to reading the register value from before the current
450  /// instruction or bundle. Internal bundle reads are not included.
451  bool readsReg() const {
452  assert(isReg() && "Wrong MachineOperand accessor");
453  return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
454  }
455 
456  //===--------------------------------------------------------------------===//
457  // Mutators for Register Operands
458  //===--------------------------------------------------------------------===//
459 
460  /// Change the register this operand corresponds to.
461  ///
462  void setReg(Register Reg);
463 
464  void setSubReg(unsigned subReg) {
465  assert(isReg() && "Wrong MachineOperand mutator");
466  SubReg_TargetFlags = subReg;
467  assert(SubReg_TargetFlags == subReg && "SubReg out of range");
468  }
469 
470  /// substVirtReg - Substitute the current register with the virtual
471  /// subregister Reg:SubReg. Take any existing SubReg index into account,
472  /// using TargetRegisterInfo to compose the subreg indices if necessary.
473  /// Reg must be a virtual register, SubIdx can be 0.
474  ///
475  void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
476 
477  /// substPhysReg - Substitute the current register with the physical register
478  /// Reg, taking any existing SubReg into account. For instance,
479  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
480  ///
481  void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
482 
483  void setIsUse(bool Val = true) { setIsDef(!Val); }
484 
485  /// Change a def to a use, or a use to a def.
486  void setIsDef(bool Val = true);
487 
488  void setImplicit(bool Val = true) {
489  assert(isReg() && "Wrong MachineOperand mutator");
490  IsImp = Val;
491  }
492 
493  void setIsKill(bool Val = true) {
494  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
495  assert((!Val || !isDebug()) && "Marking a debug operation as kill");
496  IsDeadOrKill = Val;
497  }
498 
499  void setIsDead(bool Val = true) {
500  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
501  IsDeadOrKill = Val;
502  }
503 
504  void setIsUndef(bool Val = true) {
505  assert(isReg() && "Wrong MachineOperand mutator");
506  IsUndef = Val;
507  }
508 
509  void setIsRenamable(bool Val = true);
510 
511  void setIsInternalRead(bool Val = true) {
512  assert(isReg() && "Wrong MachineOperand mutator");
513  IsInternalRead = Val;
514  }
515 
516  void setIsEarlyClobber(bool Val = true) {
517  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
518  IsEarlyClobber = Val;
519  }
520 
521  void setIsDebug(bool Val = true) {
522  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
523  IsDebug = Val;
524  }
525 
526  //===--------------------------------------------------------------------===//
527  // Accessors for various operand types.
528  //===--------------------------------------------------------------------===//
529 
530  int64_t getImm() const {
531  assert(isImm() && "Wrong MachineOperand accessor");
532  return Contents.ImmVal;
533  }
534 
535  const ConstantInt *getCImm() const {
536  assert(isCImm() && "Wrong MachineOperand accessor");
537  return Contents.CI;
538  }
539 
540  const ConstantFP *getFPImm() const {
541  assert(isFPImm() && "Wrong MachineOperand accessor");
542  return Contents.CFP;
543  }
544 
546  assert(isMBB() && "Wrong MachineOperand accessor");
547  return Contents.MBB;
548  }
549 
550  int getIndex() const {
551  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
552  "Wrong MachineOperand accessor");
553  return Contents.OffsetedInfo.Val.Index;
554  }
555 
556  const GlobalValue *getGlobal() const {
557  assert(isGlobal() && "Wrong MachineOperand accessor");
558  return Contents.OffsetedInfo.Val.GV;
559  }
560 
561  const BlockAddress *getBlockAddress() const {
562  assert(isBlockAddress() && "Wrong MachineOperand accessor");
563  return Contents.OffsetedInfo.Val.BA;
564  }
565 
567  assert(isMCSymbol() && "Wrong MachineOperand accessor");
568  return Contents.Sym;
569  }
570 
571  unsigned getCFIIndex() const {
572  assert(isCFIIndex() && "Wrong MachineOperand accessor");
573  return Contents.CFIIndex;
574  }
575 
577  assert(isIntrinsicID() && "Wrong MachineOperand accessor");
578  return Contents.IntrinsicID;
579  }
580 
581  unsigned getPredicate() const {
582  assert(isPredicate() && "Wrong MachineOperand accessor");
583  return Contents.Pred;
584  }
585 
586  const Constant *getShuffleMask() const {
587  assert(isShuffleMask() && "Wrong MachineOperand accessor");
588  return Contents.ShuffleMask;
589  }
590 
591  /// Return the offset from the symbol in this operand. This always returns 0
592  /// for ExternalSymbol operands.
593  int64_t getOffset() const {
594  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
595  isTargetIndex() || isBlockAddress()) &&
596  "Wrong MachineOperand accessor");
597  return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
598  SmallContents.OffsetLo;
599  }
600 
601  const char *getSymbolName() const {
602  assert(isSymbol() && "Wrong MachineOperand accessor");
603  return Contents.OffsetedInfo.Val.SymbolName;
604  }
605 
606  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
607  /// It is sometimes necessary to detach the register mask pointer from its
608  /// machine operand. This static method can be used for such detached bit
609  /// mask pointers.
610  static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
611  // See TargetRegisterInfo.h.
612  assert(PhysReg < (1u << 30) && "Not a physical register");
613  return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
614  }
615 
616  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
617  bool clobbersPhysReg(unsigned PhysReg) const {
618  return clobbersPhysReg(getRegMask(), PhysReg);
619  }
620 
621  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
622  /// operand.
623  const uint32_t *getRegMask() const {
624  assert(isRegMask() && "Wrong MachineOperand accessor");
625  return Contents.RegMask;
626  }
627 
628  /// Returns number of elements needed for a regmask array.
629  static unsigned getRegMaskSize(unsigned NumRegs) {
630  return (NumRegs + 31) / 32;
631  }
632 
633  /// getRegLiveOut - Returns a bit mask of live-out registers.
634  const uint32_t *getRegLiveOut() const {
635  assert(isRegLiveOut() && "Wrong MachineOperand accessor");
636  return Contents.RegMask;
637  }
638 
639  const MDNode *getMetadata() const {
640  assert(isMetadata() && "Wrong MachineOperand accessor");
641  return Contents.MD;
642  }
643 
644  //===--------------------------------------------------------------------===//
645  // Mutators for various operand types.
646  //===--------------------------------------------------------------------===//
647 
648  void setImm(int64_t immVal) {
649  assert(isImm() && "Wrong MachineOperand mutator");
650  Contents.ImmVal = immVal;
651  }
652 
653  void setCImm(const ConstantInt *CI) {
654  assert(isCImm() && "Wrong MachineOperand mutator");
655  Contents.CI = CI;
656  }
657 
658  void setFPImm(const ConstantFP *CFP) {
659  assert(isFPImm() && "Wrong MachineOperand mutator");
660  Contents.CFP = CFP;
661  }
662 
663  void setOffset(int64_t Offset) {
664  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
665  isTargetIndex() || isBlockAddress()) &&
666  "Wrong MachineOperand mutator");
667  SmallContents.OffsetLo = unsigned(Offset);
668  Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
669  }
670 
671  void setIndex(int Idx) {
672  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
673  "Wrong MachineOperand mutator");
674  Contents.OffsetedInfo.Val.Index = Idx;
675  }
676 
677  void setMetadata(const MDNode *MD) {
678  assert(isMetadata() && "Wrong MachineOperand mutator");
679  Contents.MD = MD;
680  }
681 
683  assert(isMBB() && "Wrong MachineOperand mutator");
684  Contents.MBB = MBB;
685  }
686 
687  /// Sets value of register mask operand referencing Mask. The
688  /// operand does not take ownership of the memory referenced by Mask, it must
689  /// remain valid for the lifetime of the operand. See CreateRegMask().
690  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
691  void setRegMask(const uint32_t *RegMaskPtr) {
692  assert(isRegMask() && "Wrong MachineOperand mutator");
693  Contents.RegMask = RegMaskPtr;
694  }
695 
696  void setPredicate(unsigned Predicate) {
697  assert(isPredicate() && "Wrong MachineOperand mutator");
698  Contents.Pred = Predicate;
699  }
700 
701  //===--------------------------------------------------------------------===//
702  // Other methods.
703  //===--------------------------------------------------------------------===//
704 
705  /// Returns true if this operand is identical to the specified operand except
706  /// for liveness related flags (isKill, isUndef and isDead). Note that this
707  /// should stay in sync with the hash_value overload below.
708  bool isIdenticalTo(const MachineOperand &Other) const;
709 
710  /// MachineOperand hash_value overload.
711  ///
712  /// Note that this includes the same information in the hash that
713  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
714  /// tables which use that function for equality comparisons only. This must
715  /// stay exactly in sync with isIdenticalTo above.
716  friend hash_code hash_value(const MachineOperand &MO);
717 
718  /// ChangeToImmediate - Replace this operand with a new immediate operand of
719  /// the specified value. If an operand is known to be an immediate already,
720  /// the setImm method should be used.
721  void ChangeToImmediate(int64_t ImmVal);
722 
723  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
724  /// of the specified value. If an operand is known to be an FP immediate
725  /// already, the setFPImm method should be used.
726  void ChangeToFPImmediate(const ConstantFP *FPImm);
727 
728  /// ChangeToES - Replace this operand with a new external symbol operand.
729  void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
730 
731  /// ChangeToGA - Replace this operand with a new global address operand.
732  void ChangeToGA(const GlobalValue *GV, int64_t Offset,
733  unsigned TargetFlags = 0);
734 
735  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
736  void ChangeToMCSymbol(MCSymbol *Sym);
737 
738  /// Replace this operand with a frame index.
739  void ChangeToFrameIndex(int Idx);
740 
741  /// Replace this operand with a target index.
742  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
743  unsigned TargetFlags = 0);
744 
745  /// ChangeToRegister - Replace this operand with a new register operand of
746  /// the specified value. If an operand is known to be an register already,
747  /// the setReg method should be used.
748  void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
749  bool isKill = false, bool isDead = false,
750  bool isUndef = false, bool isDebug = false);
751 
752  //===--------------------------------------------------------------------===//
753  // Construction methods.
754  //===--------------------------------------------------------------------===//
755 
756  static MachineOperand CreateImm(int64_t Val) {
758  Op.setImm(Val);
759  return Op;
760  }
761 
764  Op.Contents.CI = CI;
765  return Op;
766  }
767 
770  Op.Contents.CFP = CFP;
771  return Op;
772  }
773 
774  static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
775  bool isKill = false, bool isDead = false,
776  bool isUndef = false,
777  bool isEarlyClobber = false,
778  unsigned SubReg = 0, bool isDebug = false,
779  bool isInternalRead = false,
780  bool isRenamable = false) {
781  assert(!(isDead && !isDef) && "Dead flag on non-def");
782  assert(!(isKill && isDef) && "Kill flag on def");
784  Op.IsDef = isDef;
785  Op.IsImp = isImp;
786  Op.IsDeadOrKill = isKill | isDead;
787  Op.IsRenamable = isRenamable;
788  Op.IsUndef = isUndef;
789  Op.IsInternalRead = isInternalRead;
790  Op.IsEarlyClobber = isEarlyClobber;
791  Op.TiedTo = 0;
792  Op.IsDebug = isDebug;
793  Op.SmallContents.RegNo = Reg;
794  Op.Contents.Reg.Prev = nullptr;
795  Op.Contents.Reg.Next = nullptr;
796  Op.setSubReg(SubReg);
797  return Op;
798  }
800  unsigned TargetFlags = 0) {
802  Op.setMBB(MBB);
803  Op.setTargetFlags(TargetFlags);
804  return Op;
805  }
806  static MachineOperand CreateFI(int Idx) {
808  Op.setIndex(Idx);
809  return Op;
810  }
811  static MachineOperand CreateCPI(unsigned Idx, int Offset,
812  unsigned TargetFlags = 0) {
814  Op.setIndex(Idx);
815  Op.setOffset(Offset);
816  Op.setTargetFlags(TargetFlags);
817  return Op;
818  }
819  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
820  unsigned TargetFlags = 0) {
822  Op.setIndex(Idx);
823  Op.setOffset(Offset);
824  Op.setTargetFlags(TargetFlags);
825  return Op;
826  }
827  static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
829  Op.setIndex(Idx);
830  Op.setTargetFlags(TargetFlags);
831  return Op;
832  }
833  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
834  unsigned TargetFlags = 0) {
836  Op.Contents.OffsetedInfo.Val.GV = GV;
837  Op.setOffset(Offset);
838  Op.setTargetFlags(TargetFlags);
839  return Op;
840  }
841  static MachineOperand CreateES(const char *SymName,
842  unsigned TargetFlags = 0) {
844  Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
845  Op.setOffset(0); // Offset is always 0.
846  Op.setTargetFlags(TargetFlags);
847  return Op;
848  }
849  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
850  unsigned TargetFlags = 0) {
852  Op.Contents.OffsetedInfo.Val.BA = BA;
853  Op.setOffset(Offset);
854  Op.setTargetFlags(TargetFlags);
855  return Op;
856  }
857  /// CreateRegMask - Creates a register mask operand referencing Mask. The
858  /// operand does not take ownership of the memory referenced by Mask, it
859  /// must remain valid for the lifetime of the operand.
860  ///
861  /// A RegMask operand represents a set of non-clobbered physical registers
862  /// on an instruction that clobbers many registers, typically a call. The
863  /// bit mask has a bit set for each physreg that is preserved by this
864  /// instruction, as described in the documentation for
865  /// TargetRegisterInfo::getCallPreservedMask().
866  ///
867  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
868  ///
870  assert(Mask && "Missing register mask");
872  Op.Contents.RegMask = Mask;
873  return Op;
874  }
876  assert(Mask && "Missing live-out register mask");
878  Op.Contents.RegMask = Mask;
879  return Op;
880  }
881  static MachineOperand CreateMetadata(const MDNode *Meta) {
883  Op.Contents.MD = Meta;
884  return Op;
885  }
886 
888  unsigned TargetFlags = 0) {
890  Op.Contents.Sym = Sym;
891  Op.setOffset(0);
892  Op.setTargetFlags(TargetFlags);
893  return Op;
894  }
895 
898  Op.Contents.CFIIndex = CFIIndex;
899  return Op;
900  }
901 
904  Op.Contents.IntrinsicID = ID;
905  return Op;
906  }
907 
910  Op.Contents.Pred = Pred;
911  return Op;
912  }
913 
916  Op.Contents.ShuffleMask = C;
917  return Op;
918  }
919 
920  friend class MachineInstr;
921  friend class MachineRegisterInfo;
922 
923 private:
924  // If this operand is currently a register operand, and if this is in a
925  // function, deregister the operand from the register's use/def list.
926  void removeRegFromUses();
927 
928  /// Artificial kinds for DenseMap usage.
929  enum : unsigned char {
930  MO_Empty = MO_Last + 1,
931  MO_Tombstone,
932  };
933 
934  friend struct DenseMapInfo<MachineOperand>;
935 
936  //===--------------------------------------------------------------------===//
937  // Methods for handling register use/def lists.
938  //===--------------------------------------------------------------------===//
939 
940  /// isOnRegUseList - Return true if this operand is on a register use/def
941  /// list or false if not. This can only be called for register operands
942  /// that are part of a machine instruction.
943  bool isOnRegUseList() const {
944  assert(isReg() && "Can only add reg operand to use lists");
945  return Contents.Reg.Prev != nullptr;
946  }
947 };
948 
949 template <> struct DenseMapInfo<MachineOperand> {
951  return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
952  MachineOperand::MO_Empty));
953  }
955  return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
956  MachineOperand::MO_Tombstone));
957  }
958  static unsigned getHashValue(const MachineOperand &MO) {
959  return hash_value(MO);
960  }
961  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
962  if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
963  MachineOperand::MO_Empty) ||
964  LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
965  MachineOperand::MO_Tombstone))
966  return LHS.getType() == RHS.getType();
967  return LHS.isIdenticalTo(RHS);
968  }
969 };
970 
972  MO.print(OS);
973  return OS;
974 }
975 
976 // See friend declaration above. This additional declaration is required in
977 // order to compile LLVM with IBM xlC compiler.
979 } // namespace llvm
980 
981 #endif
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
uint64_t CallInst * C
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
static MachineOperand getTombstoneKey()
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachineOperand CreateCImm(const ConstantInt *CI)
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setTargetFlags(unsigned F)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
const uint32_t * RegMask
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void setFPImm(const ConstantFP *CFP)
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
bool isShuffleMask() const
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void setIsUndef(bool Val=true)
Intrinsic::ID IntrinsicID
Address of indexed Jump Table for switch.
unsigned getSubReg() const
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:953
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
MachineBasicBlock reference.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
const ConstantFP * CFP
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Mask of preserved registers.
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
bool isIntrinsicID() const
The address of a basic block.
Definition: Constants.h:839
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool isCFIIndex() const
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
Target-dependent index+offset operand.
void setImplicit(bool Val=true)
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
const char * getSymbolName() const
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
unsigned getCFIIndex() const
void setIsEarlyClobber(bool Val=true)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
Immediate >64bit operand.
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
void clearParent()
clearParent - Reset the parent pointer.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool isPredicate() const
void setReg(Register Reg)
Change the register this operand corresponds to.
static MachineOperand CreatePredicate(unsigned Pred)
const GlobalValue * GV
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Address of a global value.
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
This is an important base class in LLVM.
Definition: Constant.h:41
const GlobalValue * getGlobal() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
void setMBB(MachineBasicBlock *MBB)
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
void setImm(int64_t immVal)
void setIsInternalRead(bool Val=true)
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
void setOffset(int64_t Offset)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool clobbersPhysReg(unsigned PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isMCSymbol() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
const Constant * getShuffleMask() const
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void setIsKill(bool Val=true)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
TargetIntrinsicInfo - Interface to description of machine instruction set.
struct llvm::MachineOperand::@173::@175 Reg
const ConstantInt * CI
static MachineOperand getEmptyKey()
static MachineOperand CreateMetadata(const MDNode *Meta)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineBasicBlock * MBB
MachineOperand class - Representation of each machine instruction operand.
Intrinsic::ID getIntrinsicID() const
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
Promote Memory to Register
Definition: Mem2Reg.cpp:109
struct llvm::MachineOperand::@173::@176 OffsetedInfo
OffsetedInfo - This struct contains the offset and an object identifier.
int64_t getImm() const
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
void setMetadata(const MDNode *MD)
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
const Constant * ShuffleMask
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:70
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void setPredicate(unsigned Predicate)
Representation of each machine instruction.
Definition: MachineInstr.h:63
void addTargetFlag(unsigned F)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:163
union llvm::MachineOperand::@173::@176::@177 Val
MachineOperand * Prev
static unsigned getHashValue(const MachineOperand &MO)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
static MachineOperand CreateImm(int64_t Val)
void setIsUse(bool Val=true)
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void setCImm(const ConstantInt *CI)
Abstract Stack Frame Index.
static MachineOperand CreateShuffleMask(const Constant *C)
const BlockAddress * BA
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2047
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSymbol * getMCSymbol() const
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Floating-point immediate operand.
const char * SymbolName
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
MachineOperand * Next
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
Register getReg() const
getReg - Returns the register number.
void setIsDebug(bool Val=true)
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Other IR Constant for ISel (shuffle masks)
static MachineOperand CreateFI(int Idx)
const MDNode * getMetadata() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
bool isImplicit() const
Metadata reference (for debug info)
const MachineInstr * getParent() const
unsigned getPredicate() const