LLVM  10.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
27 #include "llvm/MC/MCDwarf.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<int>
34  PrintRegMaskNumRegs("print-regmask-num-regs",
35  cl::desc("Number of registers to limit to when "
36  "printing regmask operands in IR dumps. "
37  "unlimited = -1"),
38  cl::init(32), cl::Hidden);
39 
41  if (const MachineInstr *MI = MO.getParent())
42  if (const MachineBasicBlock *MBB = MI->getParent())
43  if (const MachineFunction *MF = MBB->getParent())
44  return MF;
45  return nullptr;
46 }
48  return const_cast<MachineFunction *>(
49  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50 }
51 
53  if (getReg() == Reg)
54  return; // No change.
55 
56  // Clear the IsRenamable bit to keep it conservatively correct.
57  IsRenamable = false;
58 
59  // Otherwise, we have to change the register. If this operand is embedded
60  // into a machine function, we need to update the old and new register's
61  // use/def lists.
62  if (MachineFunction *MF = getMFIfAvailable(*this)) {
63  MachineRegisterInfo &MRI = MF->getRegInfo();
65  SmallContents.RegNo = Reg;
66  MRI.addRegOperandToUseList(this);
67  return;
68  }
69 
70  // Otherwise, just change the register, no problem. :)
71  SmallContents.RegNo = Reg;
72 }
73 
75  const TargetRegisterInfo &TRI) {
76  assert(Reg.isVirtual());
77  if (SubIdx && getSubReg())
78  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79  setReg(Reg);
80  if (SubIdx)
81  setSubReg(SubIdx);
82 }
83 
85  assert(Reg.isPhysical());
86  if (getSubReg()) {
87  Reg = TRI.getSubReg(Reg, getSubReg());
88  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89  // That won't happen in legal code.
90  setSubReg(0);
91  if (isDef())
92  setIsUndef(false);
93  }
94  setReg(Reg);
95 }
96 
97 /// Change a def to a use, or a use to a def.
99  assert(isReg() && "Wrong MachineOperand accessor");
100  assert((!Val || !isDebug()) && "Marking a debug operation as def");
101  if (IsDef == Val)
102  return;
103  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104  // MRI may keep uses and defs in different list positions.
105  if (MachineFunction *MF = getMFIfAvailable(*this)) {
106  MachineRegisterInfo &MRI = MF->getRegInfo();
107  MRI.removeRegOperandFromUseList(this);
108  IsDef = Val;
109  MRI.addRegOperandToUseList(this);
110  return;
111  }
112  IsDef = Val;
113 }
114 
116  assert(isReg() && "Wrong MachineOperand accessor");
118  "isRenamable should only be checked on physical registers");
119  if (!IsRenamable)
120  return false;
121 
122  const MachineInstr *MI = getParent();
123  if (!MI)
124  return true;
125 
126  if (isDef())
128 
129  assert(isUse() && "Reg is not def or use");
131 }
132 
134  assert(isReg() && "Wrong MachineOperand accessor");
136  "setIsRenamable should only be called on physical registers");
137  IsRenamable = Val;
138 }
139 
140 // If this operand is currently a register operand, and if this is in a
141 // function, deregister the operand from the register's use/def list.
142 void MachineOperand::removeRegFromUses() {
143  if (!isReg() || !isOnRegUseList())
144  return;
145 
146  if (MachineFunction *MF = getMFIfAvailable(*this))
147  MF->getRegInfo().removeRegOperandFromUseList(this);
148 }
149 
150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 /// the specified value. If an operand is known to be an immediate already,
152 /// the setImm method should be used.
154  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155 
156  removeRegFromUses();
157 
158  OpKind = MO_Immediate;
159  Contents.ImmVal = ImmVal;
160 }
161 
163  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164 
165  removeRegFromUses();
166 
167  OpKind = MO_FPImmediate;
168  Contents.CFP = FPImm;
169 }
170 
171 void MachineOperand::ChangeToES(const char *SymName,
172  unsigned TargetFlags) {
173  assert((!isReg() || !isTied()) &&
174  "Cannot change a tied operand into an external symbol");
175 
176  removeRegFromUses();
177 
178  OpKind = MO_ExternalSymbol;
179  Contents.OffsetedInfo.Val.SymbolName = SymName;
180  setOffset(0); // Offset is always 0.
181  setTargetFlags(TargetFlags);
182 }
183 
185  unsigned TargetFlags) {
186  assert((!isReg() || !isTied()) &&
187  "Cannot change a tied operand into a global address");
188 
189  removeRegFromUses();
190 
191  OpKind = MO_GlobalAddress;
192  Contents.OffsetedInfo.Val.GV = GV;
193  setOffset(Offset);
194  setTargetFlags(TargetFlags);
195 }
196 
198  assert((!isReg() || !isTied()) &&
199  "Cannot change a tied operand into an MCSymbol");
200 
201  removeRegFromUses();
202 
203  OpKind = MO_MCSymbol;
204  Contents.Sym = Sym;
205 }
206 
208  assert((!isReg() || !isTied()) &&
209  "Cannot change a tied operand into a FrameIndex");
210 
211  removeRegFromUses();
212 
213  OpKind = MO_FrameIndex;
214  setIndex(Idx);
215 }
216 
217 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
218  unsigned TargetFlags) {
219  assert((!isReg() || !isTied()) &&
220  "Cannot change a tied operand into a FrameIndex");
221 
222  removeRegFromUses();
223 
224  OpKind = MO_TargetIndex;
225  setIndex(Idx);
226  setOffset(Offset);
227  setTargetFlags(TargetFlags);
228 }
229 
230 /// ChangeToRegister - Replace this operand with a new register operand of
231 /// the specified value. If an operand is known to be an register already,
232 /// the setReg method should be used.
234  bool isKill, bool isDead, bool isUndef,
235  bool isDebug) {
236  MachineRegisterInfo *RegInfo = nullptr;
237  if (MachineFunction *MF = getMFIfAvailable(*this))
238  RegInfo = &MF->getRegInfo();
239  // If this operand is already a register operand, remove it from the
240  // register's use/def lists.
241  bool WasReg = isReg();
242  if (RegInfo && WasReg)
243  RegInfo->removeRegOperandFromUseList(this);
244 
245  // Change this to a register and set the reg#.
246  assert(!(isDead && !isDef) && "Dead flag on non-def");
247  assert(!(isKill && isDef) && "Kill flag on def");
248  OpKind = MO_Register;
249  SmallContents.RegNo = Reg;
250  SubReg_TargetFlags = 0;
251  IsDef = isDef;
252  IsImp = isImp;
253  IsDeadOrKill = isKill | isDead;
254  IsRenamable = false;
255  IsUndef = isUndef;
256  IsInternalRead = false;
257  IsEarlyClobber = false;
258  IsDebug = isDebug;
259  // Ensure isOnRegUseList() returns false.
260  Contents.Reg.Prev = nullptr;
261  // Preserve the tie when the operand was already a register.
262  if (!WasReg)
263  TiedTo = 0;
264 
265  // If this operand is embedded in a function, add the operand to the
266  // register's use/def list.
267  if (RegInfo)
268  RegInfo->addRegOperandToUseList(this);
269 }
270 
271 /// isIdenticalTo - Return true if this operand is identical to the specified
272 /// operand. Note that this should stay in sync with the hash_value overload
273 /// below.
275  if (getType() != Other.getType() ||
276  getTargetFlags() != Other.getTargetFlags())
277  return false;
278 
279  switch (getType()) {
281  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
282  getSubReg() == Other.getSubReg();
284  return getImm() == Other.getImm();
286  return getCImm() == Other.getCImm();
288  return getFPImm() == Other.getFPImm();
290  return getMBB() == Other.getMBB();
292  return getIndex() == Other.getIndex();
295  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
297  return getIndex() == Other.getIndex();
299  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
301  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
302  getOffset() == Other.getOffset();
304  return getBlockAddress() == Other.getBlockAddress() &&
305  getOffset() == Other.getOffset();
308  // Shallow compare of the two RegMasks
309  const uint32_t *RegMask = getRegMask();
310  const uint32_t *OtherRegMask = Other.getRegMask();
311  if (RegMask == OtherRegMask)
312  return true;
313 
314  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
315  // Calculate the size of the RegMask
316  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
318 
319  // Deep compare of the two RegMasks
320  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
321  }
322  // We don't know the size of the RegMask, so we can't deep compare the two
323  // reg masks.
324  return false;
325  }
327  return getMCSymbol() == Other.getMCSymbol();
329  return getCFIIndex() == Other.getCFIIndex();
331  return getMetadata() == Other.getMetadata();
333  return getIntrinsicID() == Other.getIntrinsicID();
335  return getPredicate() == Other.getPredicate();
337  return getShuffleMask() == Other.getShuffleMask();
338  }
339  llvm_unreachable("Invalid machine operand type");
340 }
341 
342 // Note: this must stay exactly in sync with isIdenticalTo above.
344  switch (MO.getType()) {
346  // Register operands don't have target flags.
347  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
349  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
351  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
353  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
355  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
357  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
360  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
361  MO.getOffset());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
366  StringRef(MO.getSymbolName()));
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
369  MO.getOffset());
371  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
372  MO.getOffset());
375  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
377  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
381  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
383  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
385  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
387  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
388  }
389  llvm_unreachable("Invalid machine operand type");
390 }
391 
392 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
393 // it.
394 static void tryToGetTargetInfo(const MachineOperand &MO,
395  const TargetRegisterInfo *&TRI,
396  const TargetIntrinsicInfo *&IntrinsicInfo) {
397  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
398  TRI = MF->getSubtarget().getRegisterInfo();
399  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
400  }
401 }
402 
403 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
404  const auto *TII = MF.getSubtarget().getInstrInfo();
405  assert(TII && "expected instruction info");
406  auto Indices = TII->getSerializableTargetIndices();
407  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
408  return I.first == Index;
409  });
410  if (Found != Indices.end())
411  return Found->second;
412  return nullptr;
413 }
414 
415 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
417  for (const auto &I : Flags) {
418  if (I.first == TF) {
419  return I.second;
420  }
421  }
422  return nullptr;
423 }
424 
425 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
426  const TargetRegisterInfo *TRI) {
427  if (!TRI) {
428  OS << "%dwarfreg." << DwarfReg;
429  return;
430  }
431 
432  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
433  OS << printReg(*Reg, TRI);
434  else
435  OS << "<badreg>";
436 }
437 
438 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
439  ModuleSlotTracker &MST) {
440  OS << "%ir-block.";
441  if (BB.hasName()) {
443  return;
444  }
445  Optional<int> Slot;
446  if (const Function *F = BB.getParent()) {
447  if (F == MST.getCurrentFunction()) {
448  Slot = MST.getLocalSlot(&BB);
449  } else if (const Module *M = F->getParent()) {
450  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
451  CustomMST.incorporateFunction(*F);
452  Slot = CustomMST.getLocalSlot(&BB);
453  }
454  }
455  if (Slot)
457  else
458  OS << "<unknown>";
459 }
460 
461 static void printIRValueReference(raw_ostream &OS, const Value &V,
462  ModuleSlotTracker &MST) {
463  if (isa<GlobalValue>(V)) {
464  V.printAsOperand(OS, /*PrintType=*/false, MST);
465  return;
466  }
467  if (isa<Constant>(V)) {
468  // Machine memory operands can load/store to/from constant value pointers.
469  OS << '`';
470  V.printAsOperand(OS, /*PrintType=*/true, MST);
471  OS << '`';
472  return;
473  }
474  OS << "%ir.";
475  if (V.hasName()) {
477  return;
478  }
479  int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
481 }
482 
484  SyncScope::ID SSID,
486  switch (SSID) {
487  case SyncScope::System:
488  break;
489  default:
490  if (SSNs.empty())
491  Context.getSyncScopeNames(SSNs);
492 
493  OS << "syncscope(\"";
494  printEscapedString(SSNs[SSID], OS);
495  OS << "\") ";
496  break;
497  }
498 }
499 
500 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
501  unsigned TMMOFlag) {
503  for (const auto &I : Flags) {
504  if (I.first == TMMOFlag) {
505  return I.second;
506  }
507  }
508  return nullptr;
509 }
510 
511 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
512  const MachineFrameInfo *MFI) {
513  StringRef Name;
514  if (MFI) {
515  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
516  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
517  if (Alloca->hasName())
518  Name = Alloca->getName();
519  if (IsFixed)
520  FrameIndex -= MFI->getObjectIndexBegin();
521  }
522  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
523 }
524 
526  const TargetRegisterInfo *TRI) {
527  OS << "%subreg.";
528  if (TRI)
529  OS << TRI->getSubRegIndexName(Index);
530  else
531  OS << Index;
532 }
533 
535  const MachineOperand &Op) {
536  if (!Op.getTargetFlags())
537  return;
538  const MachineFunction *MF = getMFIfAvailable(Op);
539  if (!MF)
540  return;
541 
542  const auto *TII = MF->getSubtarget().getInstrInfo();
543  assert(TII && "expected instruction info");
545  OS << "target-flags(";
546  const bool HasDirectFlags = Flags.first;
547  const bool HasBitmaskFlags = Flags.second;
548  if (!HasDirectFlags && !HasBitmaskFlags) {
549  OS << "<unknown>) ";
550  return;
551  }
552  if (HasDirectFlags) {
553  if (const auto *Name = getTargetFlagName(TII, Flags.first))
554  OS << Name;
555  else
556  OS << "<unknown target flag>";
557  }
558  if (!HasBitmaskFlags) {
559  OS << ") ";
560  return;
561  }
562  bool IsCommaNeeded = HasDirectFlags;
563  unsigned BitMask = Flags.second;
565  for (const auto &Mask : BitMasks) {
566  // Check if the flag's bitmask has the bits of the current mask set.
567  if ((BitMask & Mask.first) == Mask.first) {
568  if (IsCommaNeeded)
569  OS << ", ";
570  IsCommaNeeded = true;
571  OS << Mask.second;
572  // Clear the bits which were serialized from the flag's bitmask.
573  BitMask &= ~(Mask.first);
574  }
575  }
576  if (BitMask) {
577  // When the resulting flag's bitmask isn't zero, we know that we didn't
578  // serialize all of the bit flags.
579  if (IsCommaNeeded)
580  OS << ", ";
581  OS << "<unknown bitmask target flag>";
582  }
583  OS << ") ";
584 }
585 
587  OS << "<mcsymbol " << Sym << ">";
588 }
589 
591  unsigned FrameIndex,
592  bool IsFixed, StringRef Name) {
593  if (IsFixed) {
594  OS << "%fixed-stack." << FrameIndex;
595  return;
596  }
597 
598  OS << "%stack." << FrameIndex;
599  if (!Name.empty())
600  OS << '.' << Name;
601 }
602 
604  if (Offset == 0)
605  return;
606  if (Offset < 0) {
607  OS << " - " << -Offset;
608  return;
609  }
610  OS << " + " << Offset;
611 }
612 
614  if (Slot == -1)
615  OS << "<badref>";
616  else
617  OS << Slot;
618 }
619 
620 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
621  const TargetRegisterInfo *TRI) {
622  switch (CFI.getOperation()) {
624  OS << "same_value ";
625  if (MCSymbol *Label = CFI.getLabel())
626  MachineOperand::printSymbol(OS, *Label);
627  printCFIRegister(CFI.getRegister(), OS, TRI);
628  break;
630  OS << "remember_state ";
631  if (MCSymbol *Label = CFI.getLabel())
632  MachineOperand::printSymbol(OS, *Label);
633  break;
635  OS << "restore_state ";
636  if (MCSymbol *Label = CFI.getLabel())
637  MachineOperand::printSymbol(OS, *Label);
638  break;
640  OS << "offset ";
641  if (MCSymbol *Label = CFI.getLabel())
642  MachineOperand::printSymbol(OS, *Label);
643  printCFIRegister(CFI.getRegister(), OS, TRI);
644  OS << ", " << CFI.getOffset();
645  break;
647  OS << "def_cfa_register ";
648  if (MCSymbol *Label = CFI.getLabel())
649  MachineOperand::printSymbol(OS, *Label);
650  printCFIRegister(CFI.getRegister(), OS, TRI);
651  break;
653  OS << "def_cfa_offset ";
654  if (MCSymbol *Label = CFI.getLabel())
655  MachineOperand::printSymbol(OS, *Label);
656  OS << CFI.getOffset();
657  break;
659  OS << "def_cfa ";
660  if (MCSymbol *Label = CFI.getLabel())
661  MachineOperand::printSymbol(OS, *Label);
662  printCFIRegister(CFI.getRegister(), OS, TRI);
663  OS << ", " << CFI.getOffset();
664  break;
666  OS << "rel_offset ";
667  if (MCSymbol *Label = CFI.getLabel())
668  MachineOperand::printSymbol(OS, *Label);
669  printCFIRegister(CFI.getRegister(), OS, TRI);
670  OS << ", " << CFI.getOffset();
671  break;
673  OS << "adjust_cfa_offset ";
674  if (MCSymbol *Label = CFI.getLabel())
675  MachineOperand::printSymbol(OS, *Label);
676  OS << CFI.getOffset();
677  break;
679  OS << "restore ";
680  if (MCSymbol *Label = CFI.getLabel())
681  MachineOperand::printSymbol(OS, *Label);
682  printCFIRegister(CFI.getRegister(), OS, TRI);
683  break;
685  OS << "escape ";
686  if (MCSymbol *Label = CFI.getLabel())
687  MachineOperand::printSymbol(OS, *Label);
688  if (!CFI.getValues().empty()) {
689  size_t e = CFI.getValues().size() - 1;
690  for (size_t i = 0; i < e; ++i)
691  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
692  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
693  }
694  break;
695  }
697  OS << "undefined ";
698  if (MCSymbol *Label = CFI.getLabel())
699  MachineOperand::printSymbol(OS, *Label);
700  printCFIRegister(CFI.getRegister(), OS, TRI);
701  break;
703  OS << "register ";
704  if (MCSymbol *Label = CFI.getLabel())
705  MachineOperand::printSymbol(OS, *Label);
706  printCFIRegister(CFI.getRegister(), OS, TRI);
707  OS << ", ";
708  printCFIRegister(CFI.getRegister2(), OS, TRI);
709  break;
711  OS << "window_save ";
712  if (MCSymbol *Label = CFI.getLabel())
713  MachineOperand::printSymbol(OS, *Label);
714  break;
716  OS << "negate_ra_sign_state ";
717  if (MCSymbol *Label = CFI.getLabel())
718  MachineOperand::printSymbol(OS, *Label);
719  break;
720  default:
721  // TODO: Print the other CFI Operations.
722  OS << "<unserializable cfi directive>";
723  break;
724  }
725 }
726 
728  const TargetIntrinsicInfo *IntrinsicInfo) const {
729  print(OS, LLT{}, TRI, IntrinsicInfo);
730 }
731 
732 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
733  const TargetRegisterInfo *TRI,
734  const TargetIntrinsicInfo *IntrinsicInfo) const {
735  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
736  ModuleSlotTracker DummyMST(nullptr);
737  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
738  /*ShouldPrintRegisterTies=*/true,
739  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
740 }
741 
743  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
744  bool ShouldPrintRegisterTies,
745  unsigned TiedOperandIdx,
746  const TargetRegisterInfo *TRI,
747  const TargetIntrinsicInfo *IntrinsicInfo) const {
748  printTargetFlags(OS, *this);
749  switch (getType()) {
751  Register Reg = getReg();
752  if (isImplicit())
753  OS << (isDef() ? "implicit-def " : "implicit ");
754  else if (PrintDef && isDef())
755  // Print the 'def' flag only when the operand is defined after '='.
756  OS << "def ";
757  if (isInternalRead())
758  OS << "internal ";
759  if (isDead())
760  OS << "dead ";
761  if (isKill())
762  OS << "killed ";
763  if (isUndef())
764  OS << "undef ";
765  if (isEarlyClobber())
766  OS << "early-clobber ";
768  OS << "renamable ";
769  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
770  // simply infer it when parsing and do not need to print it.
771 
772  const MachineRegisterInfo *MRI = nullptr;
773  if (Register::isVirtualRegister(Reg)) {
774  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
775  MRI = &MF->getRegInfo();
776  }
777  }
778 
779  OS << printReg(Reg, TRI, 0, MRI);
780  // Print the sub register.
781  if (unsigned SubReg = getSubReg()) {
782  if (TRI)
783  OS << '.' << TRI->getSubRegIndexName(SubReg);
784  else
785  OS << ".subreg" << SubReg;
786  }
787  // Print the register class / bank.
788  if (Register::isVirtualRegister(Reg)) {
789  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
790  const MachineRegisterInfo &MRI = MF->getRegInfo();
791  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
792  OS << ':';
793  OS << printRegClassOrBank(Reg, MRI, TRI);
794  }
795  }
796  }
797  // Print ties.
798  if (ShouldPrintRegisterTies && isTied() && !isDef())
799  OS << "(tied-def " << TiedOperandIdx << ")";
800  // Print types.
801  if (TypeToPrint.isValid())
802  OS << '(' << TypeToPrint << ')';
803  break;
804  }
806  OS << getImm();
807  break;
809  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
810  break;
812  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
813  break;
815  OS << printMBBReference(*getMBB());
816  break;
818  int FrameIndex = getIndex();
819  bool IsFixed = false;
820  const MachineFrameInfo *MFI = nullptr;
821  if (const MachineFunction *MF = getMFIfAvailable(*this))
822  MFI = &MF->getFrameInfo();
823  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
824  break;
825  }
827  OS << "%const." << getIndex();
829  break;
831  OS << "target-index(";
832  const char *Name = "<unknown>";
833  if (const MachineFunction *MF = getMFIfAvailable(*this))
834  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
835  Name = TargetIndexName;
836  OS << Name << ')';
838  break;
839  }
842  break;
844  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
846  break;
849  OS << '&';
850  if (Name.empty()) {
851  OS << "\"\"";
852  } else {
853  printLLVMNameWithoutPrefix(OS, Name);
854  }
856  break;
857  }
859  OS << "blockaddress(";
860  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
861  MST);
862  OS << ", ";
863  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
864  OS << ')';
866  break;
867  }
869  OS << "<regmask";
870  if (TRI) {
871  unsigned NumRegsInMask = 0;
872  unsigned NumRegsEmitted = 0;
873  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
874  unsigned MaskWord = i / 32;
875  unsigned MaskBit = i % 32;
876  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
877  if (PrintRegMaskNumRegs < 0 ||
878  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
879  OS << " " << printReg(i, TRI);
880  NumRegsEmitted++;
881  }
882  NumRegsInMask++;
883  }
884  }
885  if (NumRegsEmitted != NumRegsInMask)
886  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
887  } else {
888  OS << " ...";
889  }
890  OS << ">";
891  break;
892  }
894  const uint32_t *RegMask = getRegLiveOut();
895  OS << "liveout(";
896  if (!TRI) {
897  OS << "<unknown>";
898  } else {
899  bool IsCommaNeeded = false;
900  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
901  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
902  if (IsCommaNeeded)
903  OS << ", ";
904  OS << printReg(Reg, TRI);
905  IsCommaNeeded = true;
906  }
907  }
908  }
909  OS << ")";
910  break;
911  }
913  getMetadata()->printAsOperand(OS, MST);
914  break;
916  printSymbol(OS, *getMCSymbol());
917  break;
919  if (const MachineFunction *MF = getMFIfAvailable(*this))
920  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
921  else
922  OS << "<cfi directive>";
923  break;
924  }
927  if (ID < Intrinsic::num_intrinsics)
928  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
929  else if (IntrinsicInfo)
930  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
931  else
932  OS << "intrinsic(" << ID << ')';
933  break;
934  }
936  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
937  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
938  << CmpInst::getPredicateName(Pred) << ')';
939  break;
940  }
942  OS << "shufflemask(";
943  const Constant* C = getShuffleMask();
944  const int NumElts = C->getType()->getVectorNumElements();
945 
946  StringRef Separator;
947  for (int I = 0; I != NumElts; ++I) {
948  OS << Separator;
949  C->getAggregateElement(I)->printAsOperand(OS, false, MST);
950  Separator = ", ";
951  }
952 
953  OS << ')';
954  break;
955  }
956 }
957 
958 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
959 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
960 #endif
961 
962 //===----------------------------------------------------------------------===//
963 // MachineMemOperand Implementation
964 //===----------------------------------------------------------------------===//
965 
966 /// getAddrSpace - Return the LLVM IR address space number that this pointer
967 /// points into.
968 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
969 
970 /// isDereferenceable - Return true if V is always dereferenceable for
971 /// Offset + Size byte.
973  const DataLayout &DL) const {
974  if (!V.is<const Value *>())
975  return false;
976 
977  const Value *BasePtr = V.get<const Value *>();
978  if (BasePtr == nullptr)
979  return false;
980 
982  BasePtr, Align::None(), APInt(DL.getPointerSizeInBits(), Offset + Size),
983  DL);
984 }
985 
986 /// getConstantPool - Return a MachinePointerInfo record that refers to the
987 /// constant pool.
990 }
991 
992 /// getFixedStack - Return a MachinePointerInfo record that refers to the
993 /// the specified FrameIndex.
995  int FI, int64_t Offset) {
997 }
998 
1001 }
1002 
1004  return MachinePointerInfo(MF.getPSVManager().getGOT());
1005 }
1006 
1008  int64_t Offset, uint8_t ID) {
1010 }
1011 
1014 }
1015 
1017  uint64_t s, uint64_t a,
1018  const AAMDNodes &AAInfo,
1019  const MDNode *Ranges, SyncScope::ID SSID,
1020  AtomicOrdering Ordering,
1021  AtomicOrdering FailureOrdering)
1022  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1023  AAInfo(AAInfo), Ranges(Ranges) {
1024  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1025  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1026  "invalid pointer value");
1027  assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1028  assert((isLoad() || isStore()) && "Not a load/store!");
1029 
1030  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1031  assert(getSyncScopeID() == SSID && "Value truncated");
1032  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1033  assert(getOrdering() == Ordering && "Value truncated");
1034  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1035  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1036 }
1037 
1038 /// Profile - Gather unique data for the object.
1039 ///
1041  ID.AddInteger(getOffset());
1042  ID.AddInteger(Size);
1043  ID.AddPointer(getOpaqueValue());
1044  ID.AddInteger(getFlags());
1046 }
1047 
1049  // The Value and Offset may differ due to CSE. But the flags and size
1050  // should be the same.
1051  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1052  assert(MMO->getSize() == getSize() && "Size mismatch!");
1053 
1054  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1055  // Update the alignment value.
1056  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1057  // Also update the base and offset, because the new alignment may
1058  // not be applicable with the old ones.
1059  PtrInfo = MMO->PtrInfo;
1060  }
1061 }
1062 
1063 /// getAlignment - Return the minimum known alignment in bytes of the
1064 /// actual memory reference.
1066  return MinAlign(getBaseAlignment(), getOffset());
1067 }
1068 
1071  const LLVMContext &Context,
1072  const MachineFrameInfo *MFI,
1073  const TargetInstrInfo *TII) const {
1074  OS << '(';
1075  if (isVolatile())
1076  OS << "volatile ";
1077  if (isNonTemporal())
1078  OS << "non-temporal ";
1079  if (isDereferenceable())
1080  OS << "dereferenceable ";
1081  if (isInvariant())
1082  OS << "invariant ";
1085  << "\" ";
1088  << "\" ";
1091  << "\" ";
1092 
1093  assert((isLoad() || isStore()) &&
1094  "machine memory operand must be a load or store (or both)");
1095  if (isLoad())
1096  OS << "load ";
1097  if (isStore())
1098  OS << "store ";
1099 
1100  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1101 
1103  OS << toIRString(getOrdering()) << ' ';
1105  OS << toIRString(getFailureOrdering()) << ' ';
1106 
1108  OS << "unknown-size";
1109  else
1110  OS << getSize();
1111 
1112  if (const Value *Val = getValue()) {
1113  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1114  printIRValueReference(OS, *Val, MST);
1115  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1116  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1117  assert(PVal && "Expected a pseudo source value");
1118  switch (PVal->kind()) {
1120  OS << "stack";
1121  break;
1123  OS << "got";
1124  break;
1126  OS << "jump-table";
1127  break;
1129  OS << "constant-pool";
1130  break;
1132  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1133  bool IsFixed = true;
1134  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1135  break;
1136  }
1138  OS << "call-entry ";
1139  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1140  OS, /*PrintType=*/false, MST);
1141  break;
1143  OS << "call-entry &";
1145  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1146  break;
1147  default:
1148  // FIXME: This is not necessarily the correct MIR serialization format for
1149  // a custom pseudo source value, but at least it allows
1150  // -print-machineinstrs to work on a target with custom pseudo source
1151  // values.
1152  OS << "custom ";
1153  PVal->printCustom(OS);
1154  break;
1155  }
1156  }
1158  if (getBaseAlignment() != getSize())
1159  OS << ", align " << getBaseAlignment();
1160  auto AAInfo = getAAInfo();
1161  if (AAInfo.TBAA) {
1162  OS << ", !tbaa ";
1163  AAInfo.TBAA->printAsOperand(OS, MST);
1164  }
1165  if (AAInfo.Scope) {
1166  OS << ", !alias.scope ";
1167  AAInfo.Scope->printAsOperand(OS, MST);
1168  }
1169  if (AAInfo.NoAlias) {
1170  OS << ", !noalias ";
1171  AAInfo.NoAlias->printAsOperand(OS, MST);
1172  }
1173  if (getRanges()) {
1174  OS << ", !range ";
1175  getRanges()->printAsOperand(OS, MST);
1176  }
1177  // FIXME: Implement addrspace printing/parsing in MIR.
1178  // For now, print this even though parsing it is not available in MIR.
1179  if (unsigned AS = getAddrSpace())
1180  OS << ", addrspace " << AS;
1181 
1182  OS << ')';
1183 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:51
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
LLVMContext & Context
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
MachineBasicBlock * getMBB() const
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:660
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:484
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:657
void setTargetFlags(unsigned F)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:66
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:961
const uint32_t * RegMask
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void setIsUndef(bool Val=true)
Address of indexed Jump Table for switch.
unsigned Reg
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:858
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, MaybeAlign Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:138
uint64_t getSize() const
Return the size in bytes of the memory reference.
void printEscapedString(StringRef Name, raw_ostream &Out)
Print each character of the specified string, escaping it if it is not printable or if it is an escap...
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, uint64_t a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:392
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:863
F(f)
Manage lifetime of a slot tracker for printing IR.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Mask of live-out registers.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void setIsRenamable(bool Val=true)
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:194
bool isInternalRead() const
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:865
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:273
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
A description of a memory reference used in the backend.
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:640
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
const MDNode * getRanges() const
Return the range tag for the memory reference.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:60
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
const char * getSymbolName() const
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: MCRegister.h:59
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
unsigned getCFIIndex() const
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:179
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
Immediate >64bit operand.
PseudoSourceValueManager & getPSVManager() const
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Register getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4470
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:89
void setReg(Register Reg)
Change the register this operand corresponds to.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:578
const GlobalValue * GV
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
Definition: Constants.cpp:359
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:305
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:661
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:252
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
unsigned getRegister2() const
Definition: MCDwarf.h:588
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
int getOffset() const
Definition: MCDwarf.h:593
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:577
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
constexpr double e
Definition: MathExtras.h:57
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1193
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:600
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:844
static constexpr const Align None()
Returns a default constructed Align which corresponds to no alignment.
Definition: Alignment.h:93
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4356
const Constant * getShuffleMask() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:580
struct llvm::MachineOperand::@173::@175 Reg
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:398
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:663
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:585
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:566
bool isIntPredicate() const
Definition: InstrTypes.h:825
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:599
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:54
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:70
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
union llvm::MachineOperand::@173::@176::@177 Val
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
This file provides utility analysis objects describing memory locations.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
const BlockAddress * getBlockAddress() const
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:951
Flags getFlags() const
Return the raw flags of the source value,.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void setSubReg(unsigned subReg)
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:184
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
uint32_t Size
Definition: Profile.cpp:46
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4398
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:74
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Address of indexed Constant in Constant Pool.
Register getReg() const
getReg - Returns the register number.
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Other IR Constant for ISel (shuffle masks)
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
const MDNode * getMetadata() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:59
static void printIRValueReference(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.