LLVM  9.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
27 #include "llvm/MC/MCDwarf.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<int>
34  PrintRegMaskNumRegs("print-regmask-num-regs",
35  cl::desc("Number of registers to limit to when "
36  "printing regmask operands in IR dumps. "
37  "unlimited = -1"),
38  cl::init(32), cl::Hidden);
39 
41  if (const MachineInstr *MI = MO.getParent())
42  if (const MachineBasicBlock *MBB = MI->getParent())
43  if (const MachineFunction *MF = MBB->getParent())
44  return MF;
45  return nullptr;
46 }
48  return const_cast<MachineFunction *>(
49  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50 }
51 
52 void MachineOperand::setReg(unsigned Reg) {
53  if (getReg() == Reg)
54  return; // No change.
55 
56  // Clear the IsRenamable bit to keep it conservatively correct.
57  IsRenamable = false;
58 
59  // Otherwise, we have to change the register. If this operand is embedded
60  // into a machine function, we need to update the old and new register's
61  // use/def lists.
62  if (MachineFunction *MF = getMFIfAvailable(*this)) {
63  MachineRegisterInfo &MRI = MF->getRegInfo();
65  SmallContents.RegNo = Reg;
66  MRI.addRegOperandToUseList(this);
67  return;
68  }
69 
70  // Otherwise, just change the register, no problem. :)
71  SmallContents.RegNo = Reg;
72 }
73 
74 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75  const TargetRegisterInfo &TRI) {
77  if (SubIdx && getSubReg())
78  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79  setReg(Reg);
80  if (SubIdx)
81  setSubReg(SubIdx);
82 }
83 
86  if (getSubReg()) {
87  Reg = TRI.getSubReg(Reg, getSubReg());
88  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89  // That won't happen in legal code.
90  setSubReg(0);
91  if (isDef())
92  setIsUndef(false);
93  }
94  setReg(Reg);
95 }
96 
97 /// Change a def to a use, or a use to a def.
99  assert(isReg() && "Wrong MachineOperand accessor");
100  assert((!Val || !isDebug()) && "Marking a debug operation as def");
101  if (IsDef == Val)
102  return;
103  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104  // MRI may keep uses and defs in different list positions.
105  if (MachineFunction *MF = getMFIfAvailable(*this)) {
106  MachineRegisterInfo &MRI = MF->getRegInfo();
107  MRI.removeRegOperandFromUseList(this);
108  IsDef = Val;
109  MRI.addRegOperandToUseList(this);
110  return;
111  }
112  IsDef = Val;
113 }
114 
116  assert(isReg() && "Wrong MachineOperand accessor");
118  "isRenamable should only be checked on physical registers");
119  if (!IsRenamable)
120  return false;
121 
122  const MachineInstr *MI = getParent();
123  if (!MI)
124  return true;
125 
126  if (isDef())
128 
129  assert(isUse() && "Reg is not def or use");
131 }
132 
134  assert(isReg() && "Wrong MachineOperand accessor");
136  "setIsRenamable should only be called on physical registers");
137  IsRenamable = Val;
138 }
139 
140 // If this operand is currently a register operand, and if this is in a
141 // function, deregister the operand from the register's use/def list.
142 void MachineOperand::removeRegFromUses() {
143  if (!isReg() || !isOnRegUseList())
144  return;
145 
146  if (MachineFunction *MF = getMFIfAvailable(*this))
147  MF->getRegInfo().removeRegOperandFromUseList(this);
148 }
149 
150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 /// the specified value. If an operand is known to be an immediate already,
152 /// the setImm method should be used.
154  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155 
156  removeRegFromUses();
157 
158  OpKind = MO_Immediate;
159  Contents.ImmVal = ImmVal;
160 }
161 
163  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164 
165  removeRegFromUses();
166 
167  OpKind = MO_FPImmediate;
168  Contents.CFP = FPImm;
169 }
170 
171 void MachineOperand::ChangeToES(const char *SymName,
172  unsigned char TargetFlags) {
173  assert((!isReg() || !isTied()) &&
174  "Cannot change a tied operand into an external symbol");
175 
176  removeRegFromUses();
177 
178  OpKind = MO_ExternalSymbol;
179  Contents.OffsetedInfo.Val.SymbolName = SymName;
180  setOffset(0); // Offset is always 0.
181  setTargetFlags(TargetFlags);
182 }
183 
185  unsigned char TargetFlags) {
186  assert((!isReg() || !isTied()) &&
187  "Cannot change a tied operand into a global address");
188 
189  removeRegFromUses();
190 
191  OpKind = MO_GlobalAddress;
192  Contents.OffsetedInfo.Val.GV = GV;
193  setOffset(Offset);
194  setTargetFlags(TargetFlags);
195 }
196 
198  assert((!isReg() || !isTied()) &&
199  "Cannot change a tied operand into an MCSymbol");
200 
201  removeRegFromUses();
202 
203  OpKind = MO_MCSymbol;
204  Contents.Sym = Sym;
205 }
206 
208  assert((!isReg() || !isTied()) &&
209  "Cannot change a tied operand into a FrameIndex");
210 
211  removeRegFromUses();
212 
213  OpKind = MO_FrameIndex;
214  setIndex(Idx);
215 }
216 
217 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
218  unsigned char TargetFlags) {
219  assert((!isReg() || !isTied()) &&
220  "Cannot change a tied operand into a FrameIndex");
221 
222  removeRegFromUses();
223 
224  OpKind = MO_TargetIndex;
225  setIndex(Idx);
226  setOffset(Offset);
227  setTargetFlags(TargetFlags);
228 }
229 
230 /// ChangeToRegister - Replace this operand with a new register operand of
231 /// the specified value. If an operand is known to be an register already,
232 /// the setReg method should be used.
233 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
234  bool isKill, bool isDead, bool isUndef,
235  bool isDebug) {
236  MachineRegisterInfo *RegInfo = nullptr;
237  if (MachineFunction *MF = getMFIfAvailable(*this))
238  RegInfo = &MF->getRegInfo();
239  // If this operand is already a register operand, remove it from the
240  // register's use/def lists.
241  bool WasReg = isReg();
242  if (RegInfo && WasReg)
243  RegInfo->removeRegOperandFromUseList(this);
244 
245  // Change this to a register and set the reg#.
246  assert(!(isDead && !isDef) && "Dead flag on non-def");
247  assert(!(isKill && isDef) && "Kill flag on def");
248  OpKind = MO_Register;
249  SmallContents.RegNo = Reg;
250  SubReg_TargetFlags = 0;
251  IsDef = isDef;
252  IsImp = isImp;
253  IsDeadOrKill = isKill | isDead;
254  IsRenamable = false;
255  IsUndef = isUndef;
256  IsInternalRead = false;
257  IsEarlyClobber = false;
258  IsDebug = isDebug;
259  // Ensure isOnRegUseList() returns false.
260  Contents.Reg.Prev = nullptr;
261  // Preserve the tie when the operand was already a register.
262  if (!WasReg)
263  TiedTo = 0;
264 
265  // If this operand is embedded in a function, add the operand to the
266  // register's use/def list.
267  if (RegInfo)
268  RegInfo->addRegOperandToUseList(this);
269 }
270 
271 /// isIdenticalTo - Return true if this operand is identical to the specified
272 /// operand. Note that this should stay in sync with the hash_value overload
273 /// below.
275  if (getType() != Other.getType() ||
276  getTargetFlags() != Other.getTargetFlags())
277  return false;
278 
279  switch (getType()) {
281  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
282  getSubReg() == Other.getSubReg();
284  return getImm() == Other.getImm();
286  return getCImm() == Other.getCImm();
288  return getFPImm() == Other.getFPImm();
290  return getMBB() == Other.getMBB();
292  return getIndex() == Other.getIndex();
295  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
297  return getIndex() == Other.getIndex();
299  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
301  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
302  getOffset() == Other.getOffset();
304  return getBlockAddress() == Other.getBlockAddress() &&
305  getOffset() == Other.getOffset();
308  // Shallow compare of the two RegMasks
309  const uint32_t *RegMask = getRegMask();
310  const uint32_t *OtherRegMask = Other.getRegMask();
311  if (RegMask == OtherRegMask)
312  return true;
313 
314  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
315  // Calculate the size of the RegMask
316  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
318 
319  // Deep compare of the two RegMasks
320  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
321  }
322  // We don't know the size of the RegMask, so we can't deep compare the two
323  // reg masks.
324  return false;
325  }
327  return getMCSymbol() == Other.getMCSymbol();
329  return getCFIIndex() == Other.getCFIIndex();
331  return getMetadata() == Other.getMetadata();
333  return getIntrinsicID() == Other.getIntrinsicID();
335  return getPredicate() == Other.getPredicate();
336  }
337  llvm_unreachable("Invalid machine operand type");
338 }
339 
340 // Note: this must stay exactly in sync with isIdenticalTo above.
342  switch (MO.getType()) {
344  // Register operands don't have target flags.
345  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
347  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
349  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
351  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
353  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
355  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
358  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
359  MO.getOffset());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
364  MO.getSymbolName());
366  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
367  MO.getOffset());
369  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
370  MO.getOffset());
373  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
375  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
377  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
381  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
383  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
384  }
385  llvm_unreachable("Invalid machine operand type");
386 }
387 
388 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
389 // it.
390 static void tryToGetTargetInfo(const MachineOperand &MO,
391  const TargetRegisterInfo *&TRI,
392  const TargetIntrinsicInfo *&IntrinsicInfo) {
393  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
394  TRI = MF->getSubtarget().getRegisterInfo();
395  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
396  }
397 }
398 
399 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
400  const auto *TII = MF.getSubtarget().getInstrInfo();
401  assert(TII && "expected instruction info");
402  auto Indices = TII->getSerializableTargetIndices();
403  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
404  return I.first == Index;
405  });
406  if (Found != Indices.end())
407  return Found->second;
408  return nullptr;
409 }
410 
411 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
413  for (const auto &I : Flags) {
414  if (I.first == TF) {
415  return I.second;
416  }
417  }
418  return nullptr;
419 }
420 
421 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
422  const TargetRegisterInfo *TRI) {
423  if (!TRI) {
424  OS << "%dwarfreg." << DwarfReg;
425  return;
426  }
427 
428  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
429  if (Reg == -1) {
430  OS << "<badreg>";
431  return;
432  }
433  OS << printReg(Reg, TRI);
434 }
435 
436 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
437  ModuleSlotTracker &MST) {
438  OS << "%ir-block.";
439  if (BB.hasName()) {
441  return;
442  }
443  Optional<int> Slot;
444  if (const Function *F = BB.getParent()) {
445  if (F == MST.getCurrentFunction()) {
446  Slot = MST.getLocalSlot(&BB);
447  } else if (const Module *M = F->getParent()) {
448  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
449  CustomMST.incorporateFunction(*F);
450  Slot = CustomMST.getLocalSlot(&BB);
451  }
452  }
453  if (Slot)
455  else
456  OS << "<unknown>";
457 }
458 
459 static void printIRValueReference(raw_ostream &OS, const Value &V,
460  ModuleSlotTracker &MST) {
461  if (isa<GlobalValue>(V)) {
462  V.printAsOperand(OS, /*PrintType=*/false, MST);
463  return;
464  }
465  if (isa<Constant>(V)) {
466  // Machine memory operands can load/store to/from constant value pointers.
467  OS << '`';
468  V.printAsOperand(OS, /*PrintType=*/true, MST);
469  OS << '`';
470  return;
471  }
472  OS << "%ir.";
473  if (V.hasName()) {
475  return;
476  }
477  int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
479 }
480 
482  SyncScope::ID SSID,
484  switch (SSID) {
485  case SyncScope::System:
486  break;
487  default:
488  if (SSNs.empty())
489  Context.getSyncScopeNames(SSNs);
490 
491  OS << "syncscope(\"";
492  printEscapedString(SSNs[SSID], OS);
493  OS << "\") ";
494  break;
495  }
496 }
497 
498 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
499  unsigned TMMOFlag) {
501  for (const auto &I : Flags) {
502  if (I.first == TMMOFlag) {
503  return I.second;
504  }
505  }
506  return nullptr;
507 }
508 
509 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
510  const MachineFrameInfo *MFI) {
511  StringRef Name;
512  if (MFI) {
513  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
514  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
515  if (Alloca->hasName())
516  Name = Alloca->getName();
517  if (IsFixed)
518  FrameIndex -= MFI->getObjectIndexBegin();
519  }
520  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
521 }
522 
524  const TargetRegisterInfo *TRI) {
525  OS << "%subreg.";
526  if (TRI)
527  OS << TRI->getSubRegIndexName(Index);
528  else
529  OS << Index;
530 }
531 
533  const MachineOperand &Op) {
534  if (!Op.getTargetFlags())
535  return;
536  const MachineFunction *MF = getMFIfAvailable(Op);
537  if (!MF)
538  return;
539 
540  const auto *TII = MF->getSubtarget().getInstrInfo();
541  assert(TII && "expected instruction info");
543  OS << "target-flags(";
544  const bool HasDirectFlags = Flags.first;
545  const bool HasBitmaskFlags = Flags.second;
546  if (!HasDirectFlags && !HasBitmaskFlags) {
547  OS << "<unknown>) ";
548  return;
549  }
550  if (HasDirectFlags) {
551  if (const auto *Name = getTargetFlagName(TII, Flags.first))
552  OS << Name;
553  else
554  OS << "<unknown target flag>";
555  }
556  if (!HasBitmaskFlags) {
557  OS << ") ";
558  return;
559  }
560  bool IsCommaNeeded = HasDirectFlags;
561  unsigned BitMask = Flags.second;
563  for (const auto &Mask : BitMasks) {
564  // Check if the flag's bitmask has the bits of the current mask set.
565  if ((BitMask & Mask.first) == Mask.first) {
566  if (IsCommaNeeded)
567  OS << ", ";
568  IsCommaNeeded = true;
569  OS << Mask.second;
570  // Clear the bits which were serialized from the flag's bitmask.
571  BitMask &= ~(Mask.first);
572  }
573  }
574  if (BitMask) {
575  // When the resulting flag's bitmask isn't zero, we know that we didn't
576  // serialize all of the bit flags.
577  if (IsCommaNeeded)
578  OS << ", ";
579  OS << "<unknown bitmask target flag>";
580  }
581  OS << ") ";
582 }
583 
585  OS << "<mcsymbol " << Sym << ">";
586 }
587 
589  unsigned FrameIndex,
590  bool IsFixed, StringRef Name) {
591  if (IsFixed) {
592  OS << "%fixed-stack." << FrameIndex;
593  return;
594  }
595 
596  OS << "%stack." << FrameIndex;
597  if (!Name.empty())
598  OS << '.' << Name;
599 }
600 
602  if (Offset == 0)
603  return;
604  if (Offset < 0) {
605  OS << " - " << -Offset;
606  return;
607  }
608  OS << " + " << Offset;
609 }
610 
612  if (Slot == -1)
613  OS << "<badref>";
614  else
615  OS << Slot;
616 }
617 
618 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
619  const TargetRegisterInfo *TRI) {
620  switch (CFI.getOperation()) {
622  OS << "same_value ";
623  if (MCSymbol *Label = CFI.getLabel())
624  MachineOperand::printSymbol(OS, *Label);
625  printCFIRegister(CFI.getRegister(), OS, TRI);
626  break;
628  OS << "remember_state ";
629  if (MCSymbol *Label = CFI.getLabel())
630  MachineOperand::printSymbol(OS, *Label);
631  break;
633  OS << "restore_state ";
634  if (MCSymbol *Label = CFI.getLabel())
635  MachineOperand::printSymbol(OS, *Label);
636  break;
638  OS << "offset ";
639  if (MCSymbol *Label = CFI.getLabel())
640  MachineOperand::printSymbol(OS, *Label);
641  printCFIRegister(CFI.getRegister(), OS, TRI);
642  OS << ", " << CFI.getOffset();
643  break;
645  OS << "def_cfa_register ";
646  if (MCSymbol *Label = CFI.getLabel())
647  MachineOperand::printSymbol(OS, *Label);
648  printCFIRegister(CFI.getRegister(), OS, TRI);
649  break;
651  OS << "def_cfa_offset ";
652  if (MCSymbol *Label = CFI.getLabel())
653  MachineOperand::printSymbol(OS, *Label);
654  OS << CFI.getOffset();
655  break;
657  OS << "def_cfa ";
658  if (MCSymbol *Label = CFI.getLabel())
659  MachineOperand::printSymbol(OS, *Label);
660  printCFIRegister(CFI.getRegister(), OS, TRI);
661  OS << ", " << CFI.getOffset();
662  break;
664  OS << "rel_offset ";
665  if (MCSymbol *Label = CFI.getLabel())
666  MachineOperand::printSymbol(OS, *Label);
667  printCFIRegister(CFI.getRegister(), OS, TRI);
668  OS << ", " << CFI.getOffset();
669  break;
671  OS << "adjust_cfa_offset ";
672  if (MCSymbol *Label = CFI.getLabel())
673  MachineOperand::printSymbol(OS, *Label);
674  OS << CFI.getOffset();
675  break;
677  OS << "restore ";
678  if (MCSymbol *Label = CFI.getLabel())
679  MachineOperand::printSymbol(OS, *Label);
680  printCFIRegister(CFI.getRegister(), OS, TRI);
681  break;
683  OS << "escape ";
684  if (MCSymbol *Label = CFI.getLabel())
685  MachineOperand::printSymbol(OS, *Label);
686  if (!CFI.getValues().empty()) {
687  size_t e = CFI.getValues().size() - 1;
688  for (size_t i = 0; i < e; ++i)
689  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
690  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
691  }
692  break;
693  }
695  OS << "undefined ";
696  if (MCSymbol *Label = CFI.getLabel())
697  MachineOperand::printSymbol(OS, *Label);
698  printCFIRegister(CFI.getRegister(), OS, TRI);
699  break;
701  OS << "register ";
702  if (MCSymbol *Label = CFI.getLabel())
703  MachineOperand::printSymbol(OS, *Label);
704  printCFIRegister(CFI.getRegister(), OS, TRI);
705  OS << ", ";
706  printCFIRegister(CFI.getRegister2(), OS, TRI);
707  break;
709  OS << "window_save ";
710  if (MCSymbol *Label = CFI.getLabel())
711  MachineOperand::printSymbol(OS, *Label);
712  break;
714  OS << "negate_ra_sign_state ";
715  if (MCSymbol *Label = CFI.getLabel())
716  MachineOperand::printSymbol(OS, *Label);
717  break;
718  default:
719  // TODO: Print the other CFI Operations.
720  OS << "<unserializable cfi directive>";
721  break;
722  }
723 }
724 
726  const TargetIntrinsicInfo *IntrinsicInfo) const {
727  print(OS, LLT{}, TRI, IntrinsicInfo);
728 }
729 
730 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
731  const TargetRegisterInfo *TRI,
732  const TargetIntrinsicInfo *IntrinsicInfo) const {
733  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
734  ModuleSlotTracker DummyMST(nullptr);
735  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
736  /*ShouldPrintRegisterTies=*/true,
737  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
738 }
739 
741  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
742  bool ShouldPrintRegisterTies,
743  unsigned TiedOperandIdx,
744  const TargetRegisterInfo *TRI,
745  const TargetIntrinsicInfo *IntrinsicInfo) const {
746  printTargetFlags(OS, *this);
747  switch (getType()) {
749  unsigned Reg = getReg();
750  if (isImplicit())
751  OS << (isDef() ? "implicit-def " : "implicit ");
752  else if (PrintDef && isDef())
753  // Print the 'def' flag only when the operand is defined after '='.
754  OS << "def ";
755  if (isInternalRead())
756  OS << "internal ";
757  if (isDead())
758  OS << "dead ";
759  if (isKill())
760  OS << "killed ";
761  if (isUndef())
762  OS << "undef ";
763  if (isEarlyClobber())
764  OS << "early-clobber ";
766  OS << "renamable ";
767  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
768  // simply infer it when parsing and do not need to print it.
769 
770  const MachineRegisterInfo *MRI = nullptr;
772  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
773  MRI = &MF->getRegInfo();
774  }
775  }
776 
777  OS << printReg(Reg, TRI, 0, MRI);
778  // Print the sub register.
779  if (unsigned SubReg = getSubReg()) {
780  if (TRI)
781  OS << '.' << TRI->getSubRegIndexName(SubReg);
782  else
783  OS << ".subreg" << SubReg;
784  }
785  // Print the register class / bank.
787  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
788  const MachineRegisterInfo &MRI = MF->getRegInfo();
789  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
790  OS << ':';
791  OS << printRegClassOrBank(Reg, MRI, TRI);
792  }
793  }
794  }
795  // Print ties.
796  if (ShouldPrintRegisterTies && isTied() && !isDef())
797  OS << "(tied-def " << TiedOperandIdx << ")";
798  // Print types.
799  if (TypeToPrint.isValid())
800  OS << '(' << TypeToPrint << ')';
801  break;
802  }
804  OS << getImm();
805  break;
807  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
808  break;
810  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
811  break;
813  OS << printMBBReference(*getMBB());
814  break;
816  int FrameIndex = getIndex();
817  bool IsFixed = false;
818  const MachineFrameInfo *MFI = nullptr;
819  if (const MachineFunction *MF = getMFIfAvailable(*this))
820  MFI = &MF->getFrameInfo();
821  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
822  break;
823  }
825  OS << "%const." << getIndex();
827  break;
829  OS << "target-index(";
830  const char *Name = "<unknown>";
831  if (const MachineFunction *MF = getMFIfAvailable(*this))
832  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
833  Name = TargetIndexName;
834  OS << Name << ')';
836  break;
837  }
840  break;
842  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
844  break;
847  OS << '&';
848  if (Name.empty()) {
849  OS << "\"\"";
850  } else {
851  printLLVMNameWithoutPrefix(OS, Name);
852  }
854  break;
855  }
857  OS << "blockaddress(";
858  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
859  MST);
860  OS << ", ";
861  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
862  OS << ')';
864  break;
865  }
867  OS << "<regmask";
868  if (TRI) {
869  unsigned NumRegsInMask = 0;
870  unsigned NumRegsEmitted = 0;
871  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
872  unsigned MaskWord = i / 32;
873  unsigned MaskBit = i % 32;
874  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
875  if (PrintRegMaskNumRegs < 0 ||
876  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
877  OS << " " << printReg(i, TRI);
878  NumRegsEmitted++;
879  }
880  NumRegsInMask++;
881  }
882  }
883  if (NumRegsEmitted != NumRegsInMask)
884  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
885  } else {
886  OS << " ...";
887  }
888  OS << ">";
889  break;
890  }
892  const uint32_t *RegMask = getRegLiveOut();
893  OS << "liveout(";
894  if (!TRI) {
895  OS << "<unknown>";
896  } else {
897  bool IsCommaNeeded = false;
898  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
899  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
900  if (IsCommaNeeded)
901  OS << ", ";
902  OS << printReg(Reg, TRI);
903  IsCommaNeeded = true;
904  }
905  }
906  }
907  OS << ")";
908  break;
909  }
911  getMetadata()->printAsOperand(OS, MST);
912  break;
914  printSymbol(OS, *getMCSymbol());
915  break;
917  if (const MachineFunction *MF = getMFIfAvailable(*this))
918  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
919  else
920  OS << "<cfi directive>";
921  break;
922  }
925  if (ID < Intrinsic::num_intrinsics)
926  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
927  else if (IntrinsicInfo)
928  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
929  else
930  OS << "intrinsic(" << ID << ')';
931  break;
932  }
934  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
935  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
936  << CmpInst::getPredicateName(Pred) << ')';
937  break;
938  }
939  }
940 }
941 
942 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
943 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
944 #endif
945 
946 //===----------------------------------------------------------------------===//
947 // MachineMemOperand Implementation
948 //===----------------------------------------------------------------------===//
949 
950 /// getAddrSpace - Return the LLVM IR address space number that this pointer
951 /// points into.
952 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
953 
954 /// isDereferenceable - Return true if V is always dereferenceable for
955 /// Offset + Size byte.
957  const DataLayout &DL) const {
958  if (!V.is<const Value *>())
959  return false;
960 
961  const Value *BasePtr = V.get<const Value *>();
962  if (BasePtr == nullptr)
963  return false;
964 
966  BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
967 }
968 
969 /// getConstantPool - Return a MachinePointerInfo record that refers to the
970 /// constant pool.
973 }
974 
975 /// getFixedStack - Return a MachinePointerInfo record that refers to the
976 /// the specified FrameIndex.
978  int FI, int64_t Offset) {
980 }
981 
984 }
985 
987  return MachinePointerInfo(MF.getPSVManager().getGOT());
988 }
989 
991  int64_t Offset, uint8_t ID) {
993 }
994 
997 }
998 
1000  uint64_t s, uint64_t a,
1001  const AAMDNodes &AAInfo,
1002  const MDNode *Ranges, SyncScope::ID SSID,
1003  AtomicOrdering Ordering,
1004  AtomicOrdering FailureOrdering)
1005  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1006  AAInfo(AAInfo), Ranges(Ranges) {
1007  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1008  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1009  "invalid pointer value");
1010  assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1011  assert((isLoad() || isStore()) && "Not a load/store!");
1012 
1013  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1014  assert(getSyncScopeID() == SSID && "Value truncated");
1015  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1016  assert(getOrdering() == Ordering && "Value truncated");
1017  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1018  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1019 }
1020 
1021 /// Profile - Gather unique data for the object.
1022 ///
1024  ID.AddInteger(getOffset());
1025  ID.AddInteger(Size);
1026  ID.AddPointer(getOpaqueValue());
1027  ID.AddInteger(getFlags());
1029 }
1030 
1032  // The Value and Offset may differ due to CSE. But the flags and size
1033  // should be the same.
1034  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1035  assert(MMO->getSize() == getSize() && "Size mismatch!");
1036 
1037  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1038  // Update the alignment value.
1039  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1040  // Also update the base and offset, because the new alignment may
1041  // not be applicable with the old ones.
1042  PtrInfo = MMO->PtrInfo;
1043  }
1044 }
1045 
1046 /// getAlignment - Return the minimum known alignment in bytes of the
1047 /// actual memory reference.
1049  return MinAlign(getBaseAlignment(), getOffset());
1050 }
1051 
1053  ModuleSlotTracker DummyMST(nullptr);
1054  print(OS, DummyMST);
1055 }
1056 
1059  LLVMContext Ctx;
1060  print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1061 }
1062 
1065  const LLVMContext &Context,
1066  const MachineFrameInfo *MFI,
1067  const TargetInstrInfo *TII) const {
1068  OS << '(';
1069  if (isVolatile())
1070  OS << "volatile ";
1071  if (isNonTemporal())
1072  OS << "non-temporal ";
1073  if (isDereferenceable())
1074  OS << "dereferenceable ";
1075  if (isInvariant())
1076  OS << "invariant ";
1079  << "\" ";
1082  << "\" ";
1085  << "\" ";
1086 
1087  assert((isLoad() || isStore()) &&
1088  "machine memory operand must be a load or store (or both)");
1089  if (isLoad())
1090  OS << "load ";
1091  if (isStore())
1092  OS << "store ";
1093 
1094  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1095 
1097  OS << toIRString(getOrdering()) << ' ';
1099  OS << toIRString(getFailureOrdering()) << ' ';
1100 
1102  OS << "unknown-size";
1103  else
1104  OS << getSize();
1105 
1106  if (const Value *Val = getValue()) {
1107  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1108  printIRValueReference(OS, *Val, MST);
1109  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1110  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1111  assert(PVal && "Expected a pseudo source value");
1112  switch (PVal->kind()) {
1114  OS << "stack";
1115  break;
1117  OS << "got";
1118  break;
1120  OS << "jump-table";
1121  break;
1123  OS << "constant-pool";
1124  break;
1126  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1127  bool IsFixed = true;
1128  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1129  break;
1130  }
1132  OS << "call-entry ";
1133  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1134  OS, /*PrintType=*/false, MST);
1135  break;
1137  OS << "call-entry &";
1139  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1140  break;
1142  // FIXME: This is not necessarily the correct MIR serialization format for
1143  // a custom pseudo source value, but at least it allows
1144  // -print-machineinstrs to work on a target with custom pseudo source
1145  // values.
1146  OS << "custom ";
1147  PVal->printCustom(OS);
1148  break;
1149  }
1150  }
1152  if (getBaseAlignment() != getSize())
1153  OS << ", align " << getBaseAlignment();
1154  auto AAInfo = getAAInfo();
1155  if (AAInfo.TBAA) {
1156  OS << ", !tbaa ";
1157  AAInfo.TBAA->printAsOperand(OS, MST);
1158  }
1159  if (AAInfo.Scope) {
1160  OS << ", !alias.scope ";
1161  AAInfo.Scope->printAsOperand(OS, MST);
1162  }
1163  if (AAInfo.NoAlias) {
1164  OS << ", !noalias ";
1165  AAInfo.NoAlias->printAsOperand(OS, MST);
1166  }
1167  if (getRanges()) {
1168  OS << ", !range ";
1169  getRanges()->printAsOperand(OS, MST);
1170  }
1171  // FIXME: Implement addrspace printing/parsing in MIR.
1172  // For now, print this even though parsing it is not available in MIR.
1173  if (unsigned AS = getAddrSpace())
1174  OS << ", addrspace " << AS;
1175 
1176  OS << ')';
1177 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:51
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
LLVMContext & Context
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
MachineBasicBlock * getMBB() const
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:660
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:473
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:657
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:926
const uint32_t * RegMask
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned Reg
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:854
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
uint64_t getSize() const
Return the size in bytes of the memory reference.
void printEscapedString(StringRef Name, raw_ostream &Out)
Print each character of the specified string, escaping it if it is not printable or if it is an escap...
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, uint64_t a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:863
F(f)
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void print(raw_ostream &OS) const
Support for operator<<.
void setIsRenamable(bool Val=true)
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:205
bool isInternalRead() const
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:865
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:269
A description of a memory reference used in the backend.
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:629
const HexagonInstrInfo * TII
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:60
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
const char * getSymbolName() const
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:54
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getCFIIndex() const
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:185
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
Immediate >64bit operand.
PseudoSourceValueManager & getPSVManager() const
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
struct llvm::MachineOperand::@168::@170 Reg
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4433
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:575
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:334
const GlobalValue * GV
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:305
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:250
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
unsigned getRegister2() const
Definition: MCDwarf.h:585
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getOffset() const
Definition: MCDwarf.h:590
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:574
bool isValid() const
union llvm::MachineOperand::@168::@171::@172 Val
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:709
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:597
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:840
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4289
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:577
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:397
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:663
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
bool isIntPredicate() const
Definition: InstrTypes.h:802
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:600
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:71
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
This file provides utility analysis objects describing memory locations.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:916
Flags getFlags() const
Return the raw flags of the source value,.
void setSubReg(unsigned subReg)
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:195
uint32_t Size
Definition: Profile.cpp:46
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4331
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:72
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Address of indexed Constant in Constant Pool.
bool isDereferenceableAndAlignedPointer(const Value *V, unsigned Align, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:128
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MDNode * getMetadata() const
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:59
static void printIRValueReference(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.