41 static bool inRange(
const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43 int64_t
Value = CE->getValue();
44 return Value >= MinValue && Value <= MaxValue;
88 SMLoc StartLoc, EndLoc;
117 unsigned MemKind : 4;
145 else if (
auto *CE = dyn_cast<MCConstantExpr>(Expr))
152 SystemZOperand(OperandKind kind,
SMLoc startLoc,
SMLoc endLoc)
153 :
Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
156 static std::unique_ptr<SystemZOperand> createInvalid(
SMLoc StartLoc,
158 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
161 static std::unique_ptr<SystemZOperand> createToken(
StringRef Str,
SMLoc Loc) {
162 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
163 Op->Token.Data = Str.
data();
164 Op->Token.Length = Str.
size();
168 static std::unique_ptr<SystemZOperand>
170 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
176 static std::unique_ptr<SystemZOperand>
178 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
183 static std::unique_ptr<SystemZOperand>
186 unsigned LengthReg,
SMLoc StartLoc,
SMLoc EndLoc) {
187 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188 Op->Mem.MemKind = MemKind;
193 if (MemKind == BDLMem)
194 Op->Mem.Length.Imm = LengthImm;
195 if (MemKind == BDRMem)
196 Op->Mem.Length.Reg = LengthReg;
200 static std::unique_ptr<SystemZOperand>
203 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204 Op->ImmTLS.Imm = Imm;
205 Op->ImmTLS.Sym = Sym;
210 bool isToken()
const override {
211 return Kind == KindToken;
214 assert(Kind == KindToken &&
"Not a token");
215 return StringRef(Token.Data, Token.Length);
219 bool isReg()
const override {
220 return Kind == KindReg;
223 return Kind == KindReg &&
Reg.Kind ==
RegKind;
225 unsigned getReg()
const override {
226 assert(Kind == KindReg &&
"Not a register");
231 bool isImm()
const override {
232 return Kind == KindImm;
234 bool isImm(int64_t MinValue, int64_t MaxValue)
const {
235 return Kind == KindImm &&
inRange(Imm, MinValue, MaxValue);
237 const MCExpr *getImm()
const {
238 assert(Kind == KindImm &&
"Not an immediate");
243 bool isImmTLS()
const {
244 return Kind == KindImmTLS;
247 const ImmTLSOp getImmTLS()
const {
248 assert(Kind == KindImmTLS &&
"Not a TLS immediate");
253 bool isMem()
const override {
254 return Kind == KindMem;
257 return (Kind == KindMem &&
258 (Mem.MemKind == MemKind ||
261 (Mem.MemKind == BDMem && MemKind == BDXMem)));
267 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, 0, 0xfff);
270 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, -524288, 524287);
273 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length.Imm, 1, 0x10);
276 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length.Imm, 1, 0x100);
279 const MemOp& getMem()
const {
280 assert(Kind == KindMem &&
"Not a Mem operand");
285 SMLoc getStartLoc()
const override {
return StartLoc; }
286 SMLoc getEndLoc()
const override {
return EndLoc; }
295 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
296 assert(N == 1 &&
"Invalid number of operands");
299 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
300 assert(N == 1 &&
"Invalid number of operands");
301 addExpr(Inst, getImm());
303 void addBDAddrOperands(
MCInst &Inst,
unsigned N)
const {
304 assert(N == 2 &&
"Invalid number of operands");
307 addExpr(Inst, Mem.Disp);
309 void addBDXAddrOperands(
MCInst &Inst,
unsigned N)
const {
310 assert(N == 3 &&
"Invalid number of operands");
313 addExpr(Inst, Mem.Disp);
316 void addBDLAddrOperands(
MCInst &Inst,
unsigned N)
const {
317 assert(N == 3 &&
"Invalid number of operands");
320 addExpr(Inst, Mem.Disp);
321 addExpr(Inst, Mem.Length.Imm);
323 void addBDRAddrOperands(
MCInst &Inst,
unsigned N)
const {
324 assert(N == 3 &&
"Invalid number of operands");
327 addExpr(Inst, Mem.Disp);
330 void addBDVAddrOperands(
MCInst &Inst,
unsigned N)
const {
331 assert(N == 3 &&
"Invalid number of operands");
334 addExpr(Inst, Mem.Disp);
337 void addImmTLSOperands(
MCInst &Inst,
unsigned N)
const {
338 assert(N == 2 &&
"Invalid number of operands");
339 assert(Kind == KindImmTLS &&
"Invalid operand type");
340 addExpr(Inst, ImmTLS.Imm);
342 addExpr(Inst, ImmTLS.Sym);
346 bool isGR32()
const {
return isReg(GR32Reg); }
347 bool isGRH32()
const {
return isReg(GRH32Reg); }
348 bool isGRX32()
const {
return false; }
349 bool isGR64()
const {
return isReg(GR64Reg); }
350 bool isGR128()
const {
return isReg(GR128Reg); }
351 bool isADDR32()
const {
return isReg(ADDR32Reg); }
352 bool isADDR64()
const {
return isReg(ADDR64Reg); }
353 bool isADDR128()
const {
return false; }
354 bool isFP32()
const {
return isReg(FP32Reg); }
355 bool isFP64()
const {
return isReg(FP64Reg); }
356 bool isFP128()
const {
return isReg(FP128Reg); }
357 bool isVR32()
const {
return isReg(VR32Reg); }
358 bool isVR64()
const {
return isReg(VR64Reg); }
359 bool isVF128()
const {
return false; }
360 bool isVR128()
const {
return isReg(VR128Reg); }
361 bool isAR32()
const {
return isReg(AR32Reg); }
362 bool isCR64()
const {
return isReg(CR64Reg); }
363 bool isAnyReg()
const {
return (
isReg() || isImm(0, 15)); }
364 bool isBDAddr32Disp12()
const {
return isMemDisp12(BDMem, ADDR32Reg); }
365 bool isBDAddr32Disp20()
const {
return isMemDisp20(BDMem, ADDR32Reg); }
366 bool isBDAddr64Disp12()
const {
return isMemDisp12(BDMem, ADDR64Reg); }
367 bool isBDAddr64Disp20()
const {
return isMemDisp20(BDMem, ADDR64Reg); }
368 bool isBDXAddr64Disp12()
const {
return isMemDisp12(BDXMem, ADDR64Reg); }
369 bool isBDXAddr64Disp20()
const {
return isMemDisp20(BDXMem, ADDR64Reg); }
370 bool isBDLAddr64Disp12Len4()
const {
return isMemDisp12Len4(ADDR64Reg); }
371 bool isBDLAddr64Disp12Len8()
const {
return isMemDisp12Len8(ADDR64Reg); }
372 bool isBDRAddr64Disp12()
const {
return isMemDisp12(BDRMem, ADDR64Reg); }
373 bool isBDVAddr64Disp12()
const {
return isMemDisp12(BDVMem, ADDR64Reg); }
374 bool isU1Imm()
const {
return isImm(0, 1); }
375 bool isU2Imm()
const {
return isImm(0, 3); }
376 bool isU3Imm()
const {
return isImm(0, 7); }
377 bool isU4Imm()
const {
return isImm(0, 15); }
378 bool isU6Imm()
const {
return isImm(0, 63); }
379 bool isU8Imm()
const {
return isImm(0, 255); }
380 bool isS8Imm()
const {
return isImm(-128, 127); }
381 bool isU12Imm()
const {
return isImm(0, 4095); }
382 bool isU16Imm()
const {
return isImm(0, 65535); }
383 bool isS16Imm()
const {
return isImm(-32768, 32767); }
384 bool isU32Imm()
const {
return isImm(0, (1LL << 32) - 1); }
385 bool isS32Imm()
const {
return isImm(-(1LL << 31), (1LL << 31) - 1); }
386 bool isU48Imm()
const {
return isImm(0, (1LL << 48) - 1); }
390 #define GET_ASSEMBLER_HEADER 391 #include "SystemZGenAsmMatcher.inc" 405 SMLoc StartLoc, EndLoc;
410 bool parseRegister(
Register &Reg, RegisterGroup Group,
const unsigned *Regs,
411 bool IsAddress =
false);
414 RegisterGroup Group,
const unsigned *Regs,
419 bool parseAddress(
bool &HaveReg1,
Register &Reg1,
422 bool parseAddressRegister(
Register &Reg);
424 bool ParseDirectiveInsn(
SMLoc L);
431 int64_t MaxVal,
bool AllowTLS);
446 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
450 bool ParseDirective(
AsmToken DirectiveID)
override;
451 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
454 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
457 bool MatchingInlineAsm)
override;
512 return parseAnyRegister(Operands);
533 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1,
false);
536 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
false);
539 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1,
false);
542 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
false);
545 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
true);
548 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
true);
554 #define GET_REGISTER_MATCHER 555 #define GET_SUBTARGET_FEATURE_NAME 556 #define GET_MATCHER_IMPLEMENTATION 557 #define GET_MNEMONIC_SPELL_CHECKER 558 #include "SystemZGenAsmMatcher.inc" 566 MatchClassKind OperandKinds[5];
585 {
"e", SystemZ::InsnE, 1,
587 {
"ri", SystemZ::InsnRI, 3,
588 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
589 {
"rie", SystemZ::InsnRIE, 4,
590 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
591 {
"ril", SystemZ::InsnRIL, 3,
592 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
593 {
"rilu", SystemZ::InsnRILU, 3,
594 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
595 {
"ris", SystemZ::InsnRIS, 5,
596 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
597 {
"rr", SystemZ::InsnRR, 3,
598 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
599 {
"rre", SystemZ::InsnRRE, 3,
600 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
601 {
"rrf", SystemZ::InsnRRF, 5,
602 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
603 {
"rrs", SystemZ::InsnRRS, 5,
604 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
605 {
"rs", SystemZ::InsnRS, 4,
606 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
607 {
"rse", SystemZ::InsnRSE, 4,
608 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609 {
"rsi", SystemZ::InsnRSI, 4,
610 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
611 {
"rsy", SystemZ::InsnRSY, 4,
612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
613 {
"rx", SystemZ::InsnRX, 3,
614 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
615 {
"rxe", SystemZ::InsnRXE, 3,
616 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617 {
"rxf", SystemZ::InsnRXF, 4,
618 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619 {
"rxy", SystemZ::InsnRXY, 3,
620 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
621 {
"s", SystemZ::InsnS, 2,
622 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
623 {
"si", SystemZ::InsnSI, 3,
624 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
625 {
"sil", SystemZ::InsnSIL, 3,
626 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
627 {
"siy", SystemZ::InsnSIY, 3,
628 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
629 {
"ss", SystemZ::InsnSS, 4,
630 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
631 {
"sse", SystemZ::InsnSSE, 3,
632 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
633 {
"ssf", SystemZ::InsnSSF, 4,
634 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
640 if (
auto *CE = dyn_cast<MCConstantExpr>(E))
642 else if (
auto *UE = dyn_cast<MCUnaryExpr>(E))
644 else if (
auto *BE = dyn_cast<MCBinaryExpr>(E))
646 else if (
auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
667 if (getImmTLS().Sym) {
673 const MemOp &
Op = getMem();
674 OS <<
"Mem:" << *cast<MCConstantExpr>(Op.Disp);
677 if (Op.MemKind == BDLMem)
678 OS << *cast<MCConstantExpr>(Op.Length.Imm) <<
",";
679 else if (Op.MemKind == BDRMem)
694 bool SystemZAsmParser::parseRegister(
Register &
Reg) {
695 Reg.StartLoc = Parser.getTok().getLoc();
699 return Error(Parser.getTok().getLoc(),
"register expected");
704 return Error(Reg.StartLoc,
"invalid register");
709 return Error(Reg.StartLoc,
"invalid register");
714 return Error(Reg.StartLoc,
"invalid register");
717 if (Prefix ==
'r' && Reg.Num < 16)
719 else if (Prefix ==
'f' && Reg.Num < 16)
721 else if (Prefix ==
'v' && Reg.Num < 32)
723 else if (Prefix ==
'a' && Reg.Num < 16)
725 else if (Prefix ==
'c' && Reg.Num < 16)
728 return Error(Reg.StartLoc,
"invalid register");
730 Reg.EndLoc = Parser.getTok().getLoc();
741 bool SystemZAsmParser::parseRegister(
Register &Reg, RegisterGroup Group,
742 const unsigned *Regs,
bool IsAddress) {
743 if (parseRegister(Reg))
745 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
746 return Error(Reg.StartLoc,
"invalid operand for instruction");
747 if (Regs && Regs[Reg.Num] == 0)
748 return Error(Reg.StartLoc,
"invalid register pair");
749 if (Reg.Num == 0 && IsAddress)
750 return Error(Reg.StartLoc,
"%r0 used in an address");
752 Reg.Num = Regs[Reg.Num];
764 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
765 if (parseRegister(Reg, Group, Regs, IsAddress))
768 Operands.
push_back(SystemZOperand::createReg(Kind, Reg.Num,
769 Reg.StartLoc, Reg.EndLoc));
775 SystemZAsmParser::parseAnyRegister(
OperandVector &Operands) {
779 SMLoc StartLoc = Parser.getTok().getLoc();
780 if (Parser.parseExpression(Register))
783 if (
auto *CE = dyn_cast<MCConstantExpr>(Register)) {
784 int64_t
Value = CE->getValue();
786 Error(StartLoc,
"invalid register");
794 Operands.
push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
798 if (parseRegister(Reg))
804 if (Reg.Group == RegGR) {
808 else if (Reg.Group == RegFP) {
812 else if (Reg.Group == RegV) {
816 else if (Reg.Group == RegAR) {
820 else if (Reg.Group == RegCR) {
828 Operands.
push_back(SystemZOperand::createReg(Kind, RegNo,
829 Reg.StartLoc, Reg.EndLoc));
835 bool SystemZAsmParser::parseAddress(
bool &HaveReg1,
Register &Reg1,
840 if (getParser().parseExpression(Disp))
853 if (parseRegister(Reg1))
857 if (getParser().parseExpression(Length))
865 if (parseRegister(Reg2))
871 return Error(Parser.getTok().getLoc(),
"unexpected token in address");
879 SystemZAsmParser::parseAddressRegister(
Register &Reg) {
880 if (Reg.Group == RegV) {
881 Error(Reg.StartLoc,
"invalid use of vector addressing");
883 }
else if (Reg.Group != RegGR) {
884 Error(Reg.StartLoc,
"invalid address register");
886 }
else if (Reg.Num == 0) {
887 Error(Reg.StartLoc,
"%r0 used in an address");
898 SMLoc StartLoc = Parser.getTok().getLoc();
899 unsigned Base = 0,
Index = 0, LengthReg = 0;
901 bool HaveReg1, HaveReg2;
904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
911 if (parseAddressRegister(Reg1))
913 Base = Regs[Reg1.Num];
917 Error(StartLoc,
"invalid use of length addressing");
921 Error(StartLoc,
"invalid use of indexed addressing");
928 if (parseAddressRegister(Reg1))
933 Index = Regs[Reg1.Num];
935 Base = Regs[Reg1.Num];
939 if (parseAddressRegister(Reg2))
941 Base = Regs[Reg2.Num];
945 Error(StartLoc,
"invalid use of length addressing");
952 if (parseAddressRegister(Reg2))
954 Base = Regs[Reg2.Num];
957 if (HaveReg1 && HaveReg2) {
958 Error(StartLoc,
"invalid use of indexed addressing");
963 Error(StartLoc,
"missing length in address");
969 if (!HaveReg1 || Reg1.Group != RegGR) {
970 Error(StartLoc,
"invalid operand for instruction");
976 if (parseAddressRegister(Reg2))
978 Base = Regs[Reg2.Num];
982 Error(StartLoc,
"invalid use of length addressing");
988 if (!HaveReg1 || Reg1.Group != RegV) {
989 Error(StartLoc,
"vector index required in address");
995 if (parseAddressRegister(Reg2))
997 Base = Regs[Reg2.Num];
1001 Error(StartLoc,
"invalid use of length addressing");
1009 Operands.
push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1010 Index, Length, LengthReg,
1015 bool SystemZAsmParser::ParseDirective(
AsmToken DirectiveID) {
1018 if (IDVal ==
".insn")
1019 return ParseDirectiveInsn(DirectiveID.
getLoc());
1026 bool SystemZAsmParser::ParseDirectiveInsn(
SMLoc L) {
1033 return Error(ErrorLoc,
"expected instruction format");
1043 if (EntryRange.first == EntryRange.second)
1044 return Error(ErrorLoc,
"unrecognized format");
1059 return Error(StartLoc,
"unexpected token in directive");
1064 if (Kind == MCK_AnyReg)
1065 ResTy = parseAnyReg(Operands);
1066 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1067 ResTy = parseBDXAddr64(Operands);
1068 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1069 ResTy = parseBDAddr64(Operands);
1070 else if (Kind == MCK_PCRel32)
1071 ResTy = parsePCRel32(Operands);
1072 else if (Kind == MCK_PCRel16)
1073 ResTy = parsePCRel16(Operands);
1081 return Error(StartLoc,
"unexpected token in directive");
1086 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1097 for (
size_t i = 0; i < Operands.
size(); i++) {
1102 unsigned Res = validateOperandClass(Operand, Kind);
1103 if (Res != Match_Success)
1107 SystemZOperand &ZOperand =
static_cast<SystemZOperand &
>(Operand);
1108 if (ZOperand.isReg())
1109 ZOperand.addRegOperands(Inst, 1);
1110 else if (ZOperand.isMem(BDMem))
1111 ZOperand.addBDAddrOperands(Inst, 2);
1112 else if (ZOperand.isMem(BDXMem))
1113 ZOperand.addBDXAddrOperands(Inst, 3);
1114 else if (ZOperand.isImm())
1115 ZOperand.addImmOperands(Inst, 1);
1126 bool SystemZAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
1129 if (parseRegister(Reg))
1131 if (Reg.Group == RegGR)
1133 else if (Reg.Group == RegFP)
1135 else if (Reg.Group == RegV)
1137 else if (Reg.Group == RegAR)
1139 else if (Reg.Group == RegCR)
1141 StartLoc = Reg.StartLoc;
1142 EndLoc = Reg.EndLoc;
1149 Operands.
push_back(SystemZOperand::createToken(Name, NameLoc));
1154 if (parseOperand(Operands, Name)) {
1161 if (parseOperand(Operands, Name)) {
1166 SMLoc Loc = getLexer().getLoc();
1167 return Error(Loc,
"unexpected token in argument list");
1176 bool SystemZAsmParser::parseOperand(
OperandVector &Operands,
1186 setAvailableFeatures(All);
1188 setAvailableFeatures(AvailableFeatures);
1204 if (parseRegister(Reg))
1206 Operands.
push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1213 SMLoc StartLoc = Parser.getTok().getLoc();
1215 bool HaveReg1, HaveReg2;
1218 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1222 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1223 && parseAddressRegister(Reg1))
1225 if (HaveReg2 && parseAddressRegister(Reg2))
1230 if (HaveReg1 || HaveReg2 || Length)
1231 Operands.
push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1233 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1239 unsigned VariantID = 0);
1241 bool SystemZAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &
Opcode,
1245 bool MatchingInlineAsm) {
1247 unsigned MatchResult;
1250 MatchResult = MatchInstructionImpl(Operands, Inst,
ErrorInfo,
1251 MissingFeatures, MatchingInlineAsm);
1252 switch (MatchResult) {
1258 case Match_MissingFeature: {
1259 assert(MissingFeatures.
any() &&
"Unknown missing feature!");
1262 std::string Msg =
"instruction requires:";
1263 for (
unsigned I = 0,
E = MissingFeatures.
size();
I !=
E; ++
I) {
1264 if (MissingFeatures[
I]) {
1269 return Error(IDLoc, Msg);
1272 case Match_InvalidOperand: {
1273 SMLoc ErrorLoc = IDLoc;
1276 return Error(IDLoc,
"too few operands for instruction");
1278 ErrorLoc = ((SystemZOperand &)*Operands[
ErrorInfo]).getStartLoc();
1279 if (ErrorLoc ==
SMLoc())
1282 return Error(ErrorLoc,
"invalid operand for instruction");
1285 case Match_MnemonicFail: {
1286 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1288 ((SystemZOperand &)*Operands[0]).
getToken(), FBS);
1289 return Error(IDLoc,
"invalid instruction" + Suggestion,
1290 ((SystemZOperand &)*Operands[0]).getLocRange());
1298 SystemZAsmParser::parsePCRel(
OperandVector &Operands, int64_t MinVal,
1299 int64_t MaxVal,
bool AllowTLS) {
1303 SMLoc StartLoc = Parser.getTok().getLoc();
1304 if (getParser().parseExpression(Expr))
1309 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1310 int64_t
Value = CE->getValue();
1312 Error(StartLoc,
"offset out of range");
1323 const MCExpr *Sym =
nullptr;
1328 Error(Parser.getTok().getLoc(),
"unexpected token");
1333 StringRef Name = Parser.getTok().getString();
1334 if (Name ==
"tls_gdcall")
1336 else if (Name ==
"tls_ldcall")
1339 Error(Parser.getTok().getLoc(),
"unknown TLS tag");
1345 Error(Parser.getTok().getLoc(),
"unexpected token");
1351 Error(Parser.getTok().getLoc(),
"unexpected token");
1365 Operands.
push_back(SystemZOperand::createImmTLS(Expr, Sym,
1368 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
static bool isReg(const MCInst &MI, unsigned OpNo)
Represents a range in source code.
const_iterator end(StringRef path)
Get end iterator over path.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const unsigned GR32Regs[16]
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
This class represents lattice values for constants.
const unsigned FP128Regs[16]
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Generic assembler parser interface, for use by target specific assembly parsers.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
void push_back(const T &Elt)
constexpr size_t size() const
MatchClassKind OperandKinds[5]
const unsigned FP32Regs[16]
static struct InsnMatchEntry InsnMatchTable[]
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
const unsigned VR64Regs[32]
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
static MCOperand createReg(unsigned Reg)
const unsigned AR32Regs[16]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Target independent representation for an assembler token.
const unsigned GRH32Regs[16]
mir Rename Register Operands
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
static bool isMem(const MachineInstr &MI, unsigned Op)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
Context object for machine code objects.
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
LLVM_NODISCARD size_t size() const
size - Get the string size.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
const unsigned CR64Regs[16]
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
const char * getPointer() const
Streaming machine code generation interface.
static const char * getRegisterName(unsigned RegNo)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Container class for subtarget features.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
Interface to description of machine instruction set.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static std::string SystemZMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
static void printMCExpr(const MCExpr *E, raw_ostream &OS)
void LLVMInitializeSystemZAsmParser()
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const unsigned FP64Regs[16]
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
Promote Memory to Register
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
static SMLoc getFromPointer(const char *Ptr)
Target & getTheSystemZTarget()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Generic base class for all target subtargets.
const unsigned VR32Regs[32]
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
static const char * getSubtargetFeatureName(uint64_t Val)
static MCOperand createImm(int64_t Val)
const unsigned VR128Regs[32]
Wrapper class representing virtual and physical registers.