LLVM 17.0.0git
Classes | Namespaces | Enumerations | Functions | Variables
AMDGPU.h File Reference
#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
Include dependency graph for AMDGPU.h:

Go to the source code of this file.

Classes

struct  llvm::AMDGPUSimplifyLibCallsPass
 
struct  llvm::AMDGPUUseNativeCallsPass
 
struct  llvm::AMDGPUPromoteKernelArgumentsPass
 
struct  llvm::AMDGPULowerKernelAttributesPass
 
struct  llvm::AMDGPUPropagateAttributesEarlyPass
 
struct  llvm::AMDGPUPropagateAttributesLatePass
 
struct  llvm::AMDGPUReplaceLDSUseWithPointerPass
 
struct  llvm::AMDGPULowerModuleLDSPass
 
struct  llvm::AMDGPUPromoteAllocaPass
 
struct  llvm::AMDGPUPromoteAllocaToVectorPass
 
struct  llvm::AMDGPUAlwaysInlinePass
 
struct  llvm::AMDGPUPrintfRuntimeBindingPass
 
struct  llvm::AMDGPUUnifyMetadataPass
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::AMDGPU
 
namespace  llvm::AMDGPUAS
 OpenCL uses address spaces to differentiate between various memory regions on the hardware.
 

Enumerations

enum  llvm::AMDGPU::TargetIndex {
  llvm::AMDGPU::TI_CONSTDATA_START , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0 , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1 , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2 ,
  llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
}
 
enum  : unsigned {
  llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS = 7 , llvm::AMDGPUAS::FLAT_ADDRESS = 0 , llvm::AMDGPUAS::GLOBAL_ADDRESS = 1 , llvm::AMDGPUAS::REGION_ADDRESS = 2 ,
  llvm::AMDGPUAS::CONSTANT_ADDRESS = 4 , llvm::AMDGPUAS::LOCAL_ADDRESS = 3 , llvm::AMDGPUAS::PRIVATE_ADDRESS = 5 , llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT = 6 ,
  llvm::AMDGPUAS::BUFFER_FAT_POINTER = 7 , llvm::AMDGPUAS::PARAM_D_ADDRESS = 6 , llvm::AMDGPUAS::PARAM_I_ADDRESS = 7 , llvm::AMDGPUAS::CONSTANT_BUFFER_0 = 8 ,
  llvm::AMDGPUAS::CONSTANT_BUFFER_1 = 9 , llvm::AMDGPUAS::CONSTANT_BUFFER_2 = 10 , llvm::AMDGPUAS::CONSTANT_BUFFER_3 = 11 , llvm::AMDGPUAS::CONSTANT_BUFFER_4 = 12 ,
  llvm::AMDGPUAS::CONSTANT_BUFFER_5 = 13 , llvm::AMDGPUAS::CONSTANT_BUFFER_6 = 14 , llvm::AMDGPUAS::CONSTANT_BUFFER_7 = 15 , llvm::AMDGPUAS::CONSTANT_BUFFER_8 = 16 ,
  llvm::AMDGPUAS::CONSTANT_BUFFER_9 = 17 , llvm::AMDGPUAS::CONSTANT_BUFFER_10 = 18 , llvm::AMDGPUAS::CONSTANT_BUFFER_11 = 19 , llvm::AMDGPUAS::CONSTANT_BUFFER_12 = 20 ,
  llvm::AMDGPUAS::CONSTANT_BUFFER_13 = 21 , llvm::AMDGPUAS::CONSTANT_BUFFER_14 = 22 , llvm::AMDGPUAS::CONSTANT_BUFFER_15 = 23 , llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE = ~0u
}
 

Functions

void llvm::initializeAMDGPUPreLegalizerCombinerPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPreLegalizeCombiner (bool IsOptNone)
 
void llvm::initializeAMDGPUPostLegalizerCombinerPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPostLegalizeCombiner (bool IsOptNone)
 
FunctionPass * llvm::createAMDGPURegBankCombiner (bool IsOptNone)
 
void llvm::initializeAMDGPURegBankCombinerPass (PassRegistry &)
 
void llvm::initializeAMDGPURegBankSelectPass (PassRegistry &)
 
FunctionPass * llvm::createGCNDPPCombinePass ()
 
FunctionPass * llvm::createSIAnnotateControlFlowPass ()
 Create the annotation pass.
 
FunctionPass * llvm::createSIFoldOperandsPass ()
 
FunctionPass * llvm::createSIPeepholeSDWAPass ()
 
FunctionPass * llvm::createSILowerI1CopiesPass ()
 
FunctionPass * llvm::createSIShrinkInstructionsPass ()
 
FunctionPass * llvm::createSILoadStoreOptimizerPass ()
 
FunctionPass * llvm::createSIWholeQuadModePass ()
 
FunctionPass * llvm::createSIFixControlFlowLiveIntervalsPass ()
 
FunctionPass * llvm::createSIOptimizeExecMaskingPreRAPass ()
 
FunctionPass * llvm::createSIOptimizeVGPRLiveRangePass ()
 
FunctionPass * llvm::createSIFixSGPRCopiesPass ()
 
FunctionPass * llvm::createSIMemoryLegalizerPass ()
 
FunctionPass * llvm::createSIInsertWaitcntsPass ()
 
FunctionPass * llvm::createSIPreAllocateWWMRegsPass ()
 
FunctionPass * llvm::createSIFormMemoryClausesPass ()
 
FunctionPass * llvm::createSIPostRABundlerPass ()
 
FunctionPass * llvm::createAMDGPUSimplifyLibCallsPass (const TargetMachine *)
 
FunctionPass * llvm::createAMDGPUUseNativeCallsPass ()
 
FunctionPass * llvm::createAMDGPUCodeGenPreparePass ()
 
FunctionPass * llvm::createAMDGPULateCodeGenPreparePass ()
 
FunctionPass * llvm::createAMDGPUMachineCFGStructurizerPass ()
 
FunctionPass * llvm::createAMDGPUPropagateAttributesEarlyPass (const TargetMachine *)
 
ModulePass * llvm::createAMDGPUPropagateAttributesLatePass (const TargetMachine *)
 
FunctionPass * llvm::createAMDGPURewriteOutArgumentsPass ()
 
ModulePass * llvm::createAMDGPUReplaceLDSUseWithPointerPass ()
 
ModulePass * llvm::createAMDGPULowerModuleLDSPass ()
 
FunctionPass * llvm::createSIModeRegisterPass ()
 
FunctionPass * llvm::createGCNPreRAOptimizationsPass ()
 
void llvm::initializeAMDGPUDAGToDAGISelPass (PassRegistry &)
 
void llvm::initializeAMDGPUMachineCFGStructurizerPass (PassRegistry &)
 
void llvm::initializeAMDGPUAlwaysInlinePass (PassRegistry &)
 
Pass * llvm::createAMDGPUAnnotateKernelFeaturesPass ()
 
Pass * llvm::createAMDGPUAttributorPass ()
 
void llvm::initializeAMDGPUAttributorPass (PassRegistry &)
 
void llvm::initializeAMDGPUAnnotateKernelFeaturesPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUAtomicOptimizerPass ()
 
void llvm::initializeAMDGPUAtomicOptimizerPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPULowerIntrinsicsPass ()
 
void llvm::initializeAMDGPULowerIntrinsicsPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPUCtorDtorLoweringLegacyPass ()
 
void llvm::initializeAMDGPUCtorDtorLoweringLegacyPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPULowerKernelArgumentsPass ()
 
void llvm::initializeAMDGPULowerKernelArgumentsPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPromoteKernelArgumentsPass ()
 
void llvm::initializeAMDGPUPromoteKernelArgumentsPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPULowerKernelAttributesPass ()
 
void llvm::initializeAMDGPULowerKernelAttributesPass (PassRegistry &)
 
void llvm::initializeAMDGPUPropagateAttributesEarlyPass (PassRegistry &)
 
void llvm::initializeAMDGPUPropagateAttributesLatePass (PassRegistry &)
 
void llvm::initializeAMDGPUReplaceLDSUseWithPointerPass (PassRegistry &)
 
void llvm::initializeAMDGPULowerModuleLDSPass (PassRegistry &)
 
void llvm::initializeAMDGPURewriteOutArgumentsPass (PassRegistry &)
 
void llvm::initializeGCNDPPCombinePass (PassRegistry &)
 
void llvm::initializeSIFoldOperandsPass (PassRegistry &)
 
void llvm::initializeSIPeepholeSDWAPass (PassRegistry &)
 
void llvm::initializeSIShrinkInstructionsPass (PassRegistry &)
 
void llvm::initializeSIFixSGPRCopiesPass (PassRegistry &)
 
void llvm::initializeSIFixVGPRCopiesPass (PassRegistry &)
 
void llvm::initializeSILowerI1CopiesPass (PassRegistry &)
 
void llvm::initializeSILowerSGPRSpillsPass (PassRegistry &)
 
void llvm::initializeSILoadStoreOptimizerPass (PassRegistry &)
 
void llvm::initializeSIWholeQuadModePass (PassRegistry &)
 
void llvm::initializeSILowerControlFlowPass (PassRegistry &)
 
void llvm::initializeSIPreEmitPeepholePass (PassRegistry &)
 
void llvm::initializeSILateBranchLoweringPass (PassRegistry &)
 
void llvm::initializeSIOptimizeExecMaskingPass (PassRegistry &)
 
void llvm::initializeSIPreAllocateWWMRegsPass (PassRegistry &)
 
void llvm::initializeAMDGPUSimplifyLibCallsPass (PassRegistry &)
 
void llvm::initializeAMDGPUUseNativeCallsPass (PassRegistry &)
 
void llvm::initializeAMDGPUPerfHintAnalysisPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPromoteAlloca ()
 
void llvm::initializeAMDGPUPromoteAllocaPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPromoteAllocaToVector ()
 
void llvm::initializeAMDGPUPromoteAllocaToVectorPass (PassRegistry &)
 
Pass * llvm::createAMDGPUStructurizeCFGPass ()
 
FunctionPass * llvm::createAMDGPUISelDag (TargetMachine &TM, CodeGenOpt::Level OptLevel)
 This pass converts a legalized DAG into a AMDGPU-specific.
 
ModulePass * llvm::createAMDGPUAlwaysInlinePass (bool GlobalOpt=true)
 
FunctionPass * llvm::createAMDGPUAnnotateUniformValues ()
 
ModulePass * llvm::createAMDGPUPrintfRuntimeBinding ()
 
void llvm::initializeAMDGPUPrintfRuntimeBindingPass (PassRegistry &)
 
void llvm::initializeAMDGPUResourceUsageAnalysisPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPUUnifyMetadataPass ()
 
void llvm::initializeAMDGPUUnifyMetadataPass (PassRegistry &)
 
void llvm::initializeSIOptimizeExecMaskingPreRAPass (PassRegistry &)
 
void llvm::initializeSIOptimizeVGPRLiveRangePass (PassRegistry &)
 
void llvm::initializeAMDGPUAnnotateUniformValuesPass (PassRegistry &)
 
void llvm::initializeAMDGPUCodeGenPreparePass (PassRegistry &)
 
void llvm::initializeAMDGPULateCodeGenPreparePass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPURewriteUndefForPHIPass ()
 
void llvm::initializeAMDGPURewriteUndefForPHIPass (PassRegistry &)
 
void llvm::initializeSIAnnotateControlFlowPass (PassRegistry &)
 
void llvm::initializeSIMemoryLegalizerPass (PassRegistry &)
 
void llvm::initializeSIModeRegisterPass (PassRegistry &)
 
void llvm::initializeAMDGPUReleaseVGPRsPass (PassRegistry &)
 
void llvm::initializeAMDGPUInsertDelayAluPass (PassRegistry &)
 
void llvm::initializeSIInsertHardClausesPass (PassRegistry &)
 
void llvm::initializeSIInsertWaitcntsPass (PassRegistry &)
 
void llvm::initializeSIFormMemoryClausesPass (PassRegistry &)
 
void llvm::initializeSIPostRABundlerPass (PassRegistry &)
 
void llvm::initializeGCNCreateVOPDPass (PassRegistry &)
 
void llvm::initializeAMDGPUUnifyDivergentExitNodesPass (PassRegistry &)
 
ImmutablePass * llvm::createAMDGPUAAWrapperPass ()
 
void llvm::initializeAMDGPUAAWrapperPassPass (PassRegistry &)
 
ImmutablePass * llvm::createAMDGPUExternalAAWrapperPass ()
 
void llvm::initializeAMDGPUExternalAAWrapperPass (PassRegistry &)
 
void llvm::initializeAMDGPUArgumentUsageInfoPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass ()
 
void llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass (PassRegistry &)
 
void llvm::initializeGCNNSAReassignPass (PassRegistry &)
 
void llvm::initializeGCNPreRAOptimizationsPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUSetWavePriorityPass ()
 
void llvm::initializeAMDGPUSetWavePriorityPass (PassRegistry &)
 
bool llvm::AMDGPU::isFlatGlobalAddrSpace (unsigned AS)
 

Variables

char & llvm::AMDGPUMachineCFGStructurizerID
 
char & llvm::AMDGPUAnnotateKernelFeaturesID = AMDGPUAnnotateKernelFeatures::ID
 
char & llvm::AMDGPUAtomicOptimizerID = AMDGPUAtomicOptimizer::ID
 
char & llvm::AMDGPULowerIntrinsicsID = AMDGPULowerIntrinsics::ID
 
char & llvm::AMDGPUCtorDtorLoweringLegacyPassID
 
char & llvm::AMDGPULowerKernelArgumentsID
 
char & llvm::AMDGPUPromoteKernelArgumentsID
 
char & llvm::AMDGPULowerKernelAttributesID
 
char & llvm::AMDGPUPropagateAttributesEarlyID
 
char & llvm::AMDGPUPropagateAttributesLateID
 
char & llvm::AMDGPUReplaceLDSUseWithPointerID
 
char & llvm::AMDGPULowerModuleLDSID = AMDGPULowerModuleLDS::ID
 
char & llvm::AMDGPURewriteOutArgumentsID
 
char & llvm::GCNDPPCombineID = GCNDPPCombine::ID
 
char & llvm::SIFoldOperandsID
 
char & llvm::SIPeepholeSDWAID = SIPeepholeSDWA::ID
 
char & llvm::SIShrinkInstructionsID
 
char & llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID
 
char & llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID
 
char & llvm::SILowerI1CopiesID = SILowerI1Copies::ID
 
char & llvm::SILowerSGPRSpillsID = SILowerSGPRSpills::ID
 
char & llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID
 
char & llvm::SIWholeQuadModeID = SIWholeQuadMode::ID
 
char & llvm::SILowerControlFlowID = SILowerControlFlow::ID
 
char & llvm::SIPreEmitPeepholeID
 
char & llvm::SILateBranchLoweringPassID = SILateBranchLowering::ID
 
char & llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID
 
char & llvm::SIPreAllocateWWMRegsID = SIPreAllocateWWMRegs::ID
 
char & llvm::AMDGPUSimplifyLibCallsID
 
char & llvm::AMDGPUUseNativeCallsID
 
char & llvm::AMDGPUPerfHintAnalysisID = AMDGPUPerfHintAnalysis::ID
 
char & llvm::AMDGPUPromoteAllocaID
 
char & llvm::AMDGPUPromoteAllocaToVectorID
 
char & llvm::AMDGPUPrintfRuntimeBindingID = AMDGPUPrintfRuntimeBinding::ID
 
char & llvm::AMDGPUResourceUsageAnalysisID = AMDGPUResourceUsageAnalysis::ID
 
char & llvm::AMDGPUUnifyMetadataID = AMDGPUUnifyMetadata::ID
 
char & llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID
 
char & llvm::SIOptimizeVGPRLiveRangeID = SIOptimizeVGPRLiveRange::ID
 
char & llvm::AMDGPUAnnotateUniformValuesPassID
 
char & llvm::AMDGPUCodeGenPrepareID
 
char & llvm::AMDGPULateCodeGenPrepareID
 
char & llvm::AMDGPURewriteUndefForPHIPassID
 
char & llvm::SIAnnotateControlFlowPassID
 
char & llvm::SIMemoryLegalizerID = SIMemoryLegalizer::ID
 
char & llvm::SIModeRegisterID
 
char & llvm::AMDGPUReleaseVGPRsID = AMDGPUReleaseVGPRs::ID
 
char & llvm::AMDGPUInsertDelayAluID = AMDGPUInsertDelayAlu::ID
 
char & llvm::SIInsertHardClausesID = SIInsertHardClauses::ID
 
char & llvm::SIInsertWaitcntsID = SIInsertWaitcnts::ID
 
char & llvm::SIFormMemoryClausesID = SIFormMemoryClauses::ID
 
char & llvm::SIPostRABundlerID = SIPostRABundler::ID
 
char & llvm::GCNCreateVOPDID = GCNCreateVOPD::ID
 
char & llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID
 
char & llvm::AMDGPUOpenCLEnqueuedBlockLoweringID
 
char & llvm::GCNNSAReassignID = GCNNSAReassign::ID
 
char & llvm::GCNPreRAOptimizationsID = GCNPreRAOptimizations::ID
 
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