LLVM  14.0.0git
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Support/CodeGen.h"
15 
16 namespace llvm {
17 
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ImmutablePass;
21 class MachineFunctionPass;
22 class ModulePass;
23 class Pass;
24 class Target;
25 class TargetMachine;
26 class TargetOptions;
27 class PassRegistry;
28 class Module;
29 
30 // GlobalISel passes
31 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
32 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
34 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
35 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
36 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
37 
38 // R600 Passes
39 FunctionPass *createR600VectorRegMerger();
40 FunctionPass *createR600ExpandSpecialInstrsPass();
41 FunctionPass *createR600EmitClauseMarkers();
42 FunctionPass *createR600ClauseMergePass();
43 FunctionPass *createR600Packetizer();
44 FunctionPass *createR600ControlFlowFinalizer();
45 FunctionPass *createAMDGPUCFGStructurizerPass();
46 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
47 
48 // SI Passes
49 FunctionPass *createGCNDPPCombinePass();
50 FunctionPass *createSIAnnotateControlFlowPass();
51 FunctionPass *createSIFoldOperandsPass();
52 FunctionPass *createSIPeepholeSDWAPass();
53 FunctionPass *createSILowerI1CopiesPass();
54 FunctionPass *createSIShrinkInstructionsPass();
55 FunctionPass *createSILoadStoreOptimizerPass();
56 FunctionPass *createSIWholeQuadModePass();
59 FunctionPass *createSIOptimizeVGPRLiveRangePass();
60 FunctionPass *createSIFixSGPRCopiesPass();
61 FunctionPass *createSIMemoryLegalizerPass();
62 FunctionPass *createSIInsertWaitcntsPass();
63 FunctionPass *createSIPreAllocateWWMRegsPass();
64 FunctionPass *createSIFormMemoryClausesPass();
65 
66 FunctionPass *createSIPostRABundlerPass();
67 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
68 FunctionPass *createAMDGPUUseNativeCallsPass();
69 FunctionPass *createAMDGPUCodeGenPreparePass();
72 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
73 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
76 ModulePass *createAMDGPULowerModuleLDSPass();
77 FunctionPass *createSIModeRegisterPass();
78 FunctionPass *createGCNPreRAOptimizationsPass();
79 
80 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
83 
84 private:
85  TargetMachine &TM;
86 };
87 
88 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
90 };
91 
93 
96 
98 
103 extern char &AMDGPUAnnotateKernelFeaturesID;
104 
107 extern char &AMDGPUAtomicOptimizerID;
108 
111 extern char &AMDGPULowerIntrinsicsID;
112 
115 extern char &AMDGPUFixFunctionBitcastsID;
116 
119 extern char &AMDGPULowerKernelArgumentsID;
120 
123 extern char &AMDGPULowerKernelAttributesID;
124 
126  : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
128 };
129 
132 
134  : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
137 
138 private:
139  TargetMachine &TM;
140 };
141 
144 
146  : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
149 
150 private:
151  TargetMachine &TM;
152 };
153 
156 
158  : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> {
160 };
161 
163 extern char &AMDGPULowerModuleLDSID;
164 
165 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
167 };
168 
170 extern char &AMDGPURewriteOutArgumentsID;
171 
173 extern char &GCNDPPCombineID;
174 
176 extern char &R600ClauseMergePassID;
177 
179 extern char &R600ControlFlowFinalizerID;
180 
182 extern char &R600ExpandSpecialInstrsPassID;
183 
185 extern char &R600VectorRegMergerID;
186 
188 extern char &R600PacketizerID;
189 
191 extern char &SIFoldOperandsID;
192 
194 extern char &SIPeepholeSDWAID;
195 
197 extern char &SIShrinkInstructionsID;
198 
200 extern char &SIFixSGPRCopiesID;
201 
203 extern char &SIFixVGPRCopiesID;
204 
206 extern char &SILowerI1CopiesID;
207 
209 extern char &SILowerSGPRSpillsID;
210 
212 extern char &SILoadStoreOptimizerID;
213 
215 extern char &SIWholeQuadModeID;
216 
218 extern char &SILowerControlFlowID;
219 
221 extern char &SIPreEmitPeepholeID;
222 
224 extern char &SILateBranchLoweringPassID;
225 
227 extern char &SIOptimizeExecMaskingID;
228 
230 extern char &SIPreAllocateWWMRegsID;
231 
233 extern char &AMDGPUSimplifyLibCallsID;
234 
236 extern char &AMDGPUUseNativeCallsID;
237 
239 extern char &AMDGPUPerfHintAnalysisID;
240 
241 // Passes common to R600 and SI
244 extern char &AMDGPUPromoteAllocaID;
245 
248 extern char &AMDGPUPromoteAllocaToVectorID;
249 
250 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
253 
254 private:
255  TargetMachine &TM;
256 };
257 
259  : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
262 
263 private:
264  TargetMachine &TM;
265 };
266 
268 FunctionPass *createAMDGPUISelDag(
269  TargetMachine *TM = nullptr,
271 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
272 
273 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
274  AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
276 
277 private:
278  bool GlobalOpt;
279 };
280 
282 FunctionPass *createAMDGPUAnnotateUniformValues();
283 
285 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
286 extern char &AMDGPUPrintfRuntimeBindingID;
287 
288 void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
289 extern char &AMDGPUResourceUsageAnalysisID;
290 
292  : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
294 };
295 
298 extern char &AMDGPUUnifyMetadataID;
299 
300 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
302 };
303 
305 extern char &SIOptimizeExecMaskingPreRAID;
306 
308 extern char &SIOptimizeVGPRLiveRangeID;
309 
312 
314 extern char &AMDGPUCodeGenPrepareID;
315 
317 extern char &AMDGPULateCodeGenPrepareID;
318 
320 extern char &SIAnnotateControlFlowPassID;
321 
323 extern char &SIMemoryLegalizerID;
324 
326 extern char &SIModeRegisterID;
327 
329 extern char &SIInsertHardClausesID;
330 
332 extern char &SIInsertWaitcntsID;
333 
335 extern char &SIFormMemoryClausesID;
336 
338 extern char &SIPostRABundlerID;
339 
342 
347 
349 
353 
355 extern char &GCNNSAReassignID;
356 
358 extern char &GCNPreRAOptimizationsID;
359 
360 namespace AMDGPU {
367 };
368 }
369 
370 /// OpenCL uses address spaces to differentiate between
371 /// various memory regions on the hardware. On the CPU
372 /// all of the address spaces point to the same memory,
373 /// however on the GPU, each address space points to
374 /// a separate piece of memory that is unique from other
375 /// memory locations.
376 namespace AMDGPUAS {
377  enum : unsigned {
378  // The maximum value for flat, generic, local, private, constant and region.
380 
381  FLAT_ADDRESS = 0, ///< Address space for flat memory.
382  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
383  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
384 
385  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
386  LOCAL_ADDRESS = 3, ///< Address space for local memory.
387  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
388 
389  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
390 
391  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
392 
393  /// Address space for direct addressible parameter memory (CONST0).
395  /// Address space for indirect addressible parameter memory (VTX1).
397 
398  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
399  // this order to be able to dynamically index a constant buffer, for
400  // example:
401  //
402  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
403 
420 
421  // Some places use this if the address space can't be determined.
423  };
424 }
425 
426 namespace AMDGPU {
427 
428 // FIXME: Missing constant_32bit
429 inline bool isFlatGlobalAddrSpace(unsigned AS) {
430  return AS == AMDGPUAS::GLOBAL_ADDRESS ||
431  AS == AMDGPUAS::FLAT_ADDRESS ||
434 }
435 }
436 
437 } // End namespace llvm
438 
439 #endif
llvm::AMDGPUAS::CONSTANT_BUFFER_2
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:406
llvm::initializeR600ControlFlowFinalizerPass
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
llvm::R600ControlFlowFinalizerID
char & R600ControlFlowFinalizerID
Definition: R600ControlFlowFinalizer.cpp:687
llvm::AMDGPUAS::CONSTANT_BUFFER_8
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:412
llvm::createR600ExpandSpecialInstrsPass
FunctionPass * createR600ExpandSpecialInstrsPass()
Definition: R600ExpandSpecialInstrs.cpp:57
llvm::PreservedAnalyses
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:155
llvm::AMDGPUAS::CONSTANT_BUFFER_3
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:407
llvm::initializeR600PacketizerPass
void initializeR600PacketizerPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesEarlyPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:415
llvm::createSIPostRABundlerPass
FunctionPass * createSIPostRABundlerPass()
Definition: SIPostRABundler.cpp:71
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::AMDGPUPromoteAllocaToVectorPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:1135
llvm::createAMDGPUAttributorPass
Pass * createAMDGPUAttributorPass()
Definition: AMDGPUAttributor.cpp:527
llvm::createSIFixControlFlowLiveIntervalsPass
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AMDGPUMachineCFGStructurizerID
char & AMDGPUMachineCFGStructurizerID
Definition: AMDGPUMachineCFGStructurizer.cpp:2878
Pass
print lazy value Lazy Value Info Printer Pass
Definition: LazyValueInfo.cpp:1966
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:165
llvm::initializeR600ExpandSpecialInstrsPassPass
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:1865
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:73
llvm::ModulePass
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:238
llvm::AMDGPUAS::PARAM_D_ADDRESS
@ PARAM_D_ADDRESS
Address space for direct addressible parameter memory (CONST0).
Definition: AMDGPU.h:394
llvm::createSIFixSGPRCopiesPass
FunctionPass * createSIFixSGPRCopiesPass()
Definition: SIFixSGPRCopies.cpp:123
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:273
llvm::PassInfoMixin
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:374
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPrintfRuntimeBinding.cpp:591
llvm::Function
Definition: Function.h:61
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesEarlyPass::AMDGPUPropagateAttributesEarlyPass
AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM)
Definition: AMDGPU.h:135
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:258
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUReplaceLDSUseWithPointerID
char & AMDGPUReplaceLDSUseWithPointerID
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:433
llvm::AMDGPULowerModuleLDSID
char & AMDGPULowerModuleLDSID
Definition: AMDGPULowerModuleLDSPass.cpp:386
llvm::R600PacketizerID
char & R600PacketizerID
Definition: R600Packetizer.cpp:409
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:195
llvm::AMDGPUUnifyMetadataID
char & AMDGPUUnifyMetadataID
Definition: AMDGPUUnifyMetadata.cpp:127
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::createSIWholeQuadModePass
FunctionPass * createSIWholeQuadModePass()
Definition: SIWholeQuadMode.cpp:267
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:400
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:165
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:572
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
llvm::AMDGPUSimplifyLibCallsID
char & AMDGPUSimplifyLibCallsID
llvm::AMDGPUFixFunctionBitcastsID
char & AMDGPUFixFunctionBitcastsID
Definition: AMDGPUFixFunctionBitcasts.cpp:52
llvm::AMDGPUAS::CONSTANT_BUFFER_7
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:411
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
llvm::SIInsertWaitcntsID
char & SIInsertWaitcntsID
Definition: SIInsertWaitcnts.cpp:800
llvm::createSILoadStoreOptimizerPass
FunctionPass * createSILoadStoreOptimizerPass()
Definition: SILoadStoreOptimizer.cpp:578
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:384
llvm::initializeAMDGPUMachineCFGStructurizerPass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
llvm::createSIPreAllocateWWMRegsPass
FunctionPass * createSIPreAllocateWWMRegsPass()
Definition: SIPreAllocateWWMRegs.cpp:83
llvm::AMDGPUAS::CONSTANT_BUFFER_11
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:415
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::createR600ClauseMergePass
FunctionPass * createR600ClauseMergePass()
Definition: R600ClauseMergePass.cpp:209
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:88
llvm::AMDGPULowerKernelAttributesPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULowerKernelAttributes.cpp:263
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:81
llvm::AMDGPUAS::CONSTANT_BUFFER_4
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:408
llvm::AMDGPUResourceUsageAnalysisID
char & AMDGPUResourceUsageAnalysisID
Definition: AMDGPUResourceUsageAnalysis.cpp:40
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::AMDGPUAS::CONSTANT_BUFFER_9
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:413
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
llvm::createAMDGPUStructurizeCFGPass
Pass * createAMDGPUStructurizeCFGPass()
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:36
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:300
llvm::AMDGPUPromoteAllocaPass::AMDGPUPromoteAllocaPass
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:251
llvm::AMDGPUUnifyMetadataPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUUnifyMetadata.cpp:140
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:389
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:52
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
llvm::AMDGPUCodeGenPrepareID
char & AMDGPUCodeGenPrepareID
llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:379
llvm::AMDGPU::TargetIndex
TargetIndex
Definition: AMDGPU.h:361
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_1
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:405
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1703
llvm::createR600Packetizer
FunctionPass * createR600Packetizer()
Definition: R600Packetizer.cpp:411
llvm::SILowerI1CopiesID
char & SILowerI1CopiesID
Definition: SILowerI1Copies.cpp:411
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::createGCNPreRAOptimizationsPass
FunctionPass * createGCNPreRAOptimizationsPass()
Definition: GCNPreRAOptimizations.cpp:80
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
llvm::createSIOptimizeVGPRLiveRangePass
FunctionPass * createSIOptimizeVGPRLiveRangePass()
Definition: SIOptimizeVGPRLiveRange.cpp:574
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:802
llvm::AMDGPUAtomicOptimizerID
char & AMDGPUAtomicOptimizerID
Definition: AMDGPUAtomicOptimizer.cpp:80
llvm::AMDGPUAS::CONSTANT_BUFFER_10
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:414
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:150
llvm::AMDGPUPropagateAttributesEarlyID
char & AMDGPUPropagateAttributesEarlyID
llvm::createR600EmitClauseMarkers
FunctionPass * createR600EmitClauseMarkers()
Definition: R600EmitClauseMarkers.cpp:336
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:250
llvm::AMDGPUAS::CONSTANT_BUFFER_13
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:417
llvm::AMDGPUOpenCLEnqueuedBlockLoweringID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
Definition: AMDGPUOpenCLEnqueuedBlockLowering.cpp:64
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createSIPeepholeSDWAPass
FunctionPass * createSIPeepholeSDWAPass()
Definition: SIPeepholeSDWA.cpp:193
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:383
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:125
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:410
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:180
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:426
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
llvm::AMDGPUReplaceLDSUseWithPointerPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:456
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:576
llvm::AMDGPUSimplifyLibCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1739
llvm::SIMemoryLegalizerID
char & SIMemoryLegalizerID
Definition: SIMemoryLegalizer.cpp:1863
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:32
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:92
llvm::createSIFoldOperandsPass
FunctionPass * createSIFoldOperandsPass()
Definition: SIFoldOperands.cpp:198
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:158
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:422
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::AMDGPUAS::BUFFER_FAT_POINTER
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:391
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:387
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:364
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
llvm::AMDGPU::TI_CONSTDATA_START
@ TI_CONSTDATA_START
Definition: AMDGPU.h:362
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:80
llvm::AMDGPUUseNativeCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1796
llvm::AMDGPUPropagateAttributesLateID
char & AMDGPUPropagateAttributesLateID
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::SIAnnotateControlFlowPassID
char & SIAnnotateControlFlowPassID
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::AMDGPUPrintfRuntimeBindingID
char & AMDGPUPrintfRuntimeBindingID
Definition: AMDGPUPrintfRuntimeBinding.cpp:89
llvm::R600VectorRegMergerID
char & R600VectorRegMergerID
Definition: R600OptimizeVectorRegisters.cpp:134
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:209
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:429
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::SIModeRegisterID
char & SIModeRegisterID
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesLatePass::AMDGPUPropagateAttributesLatePass
AMDGPUPropagateAttributesLatePass(TargetMachine &TM)
Definition: AMDGPU.h:147
llvm::AMDGPUAS::CONSTANT_BUFFER_6
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:410
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2886
llvm::createSIFormMemoryClausesPass
FunctionPass * createSIFormMemoryClausesPass()
Definition: SIFormMemoryClauses.cpp:93
llvm::SIShrinkInstructionsID
char & SIShrinkInstructionsID
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:386
llvm::AMDGPUAlwaysInlinePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUAlwaysInlinePass.cpp:162
llvm::AMDGPUPromoteAllocaToVectorPass::AMDGPUPromoteAllocaToVectorPass
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:260
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
llvm::createAMDGPURewriteOutArgumentsPass
FunctionPass * createAMDGPURewriteOutArgumentsPass()
Definition: AMDGPURewriteOutArguments.cpp:462
llvm::AMDGPUSimplifyLibCallsPass::AMDGPUSimplifyLibCallsPass
AMDGPUSimplifyLibCallsPass(TargetMachine &TM)
Definition: AMDGPU.h:81
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
llvm::AMDGPUAlwaysInlinePass::AMDGPUAlwaysInlinePass
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:274
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:273
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:153
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:291
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:157
llvm::createGCNDPPCombinePass
FunctionPass * createGCNDPPCombinePass()
Definition: GCNDPPCombine.cpp:113
llvm::AMDGPUAS::CONSTANT_BUFFER_0
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:404
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:258
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1149
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:366
llvm::createR600VectorRegMerger
FunctionPass * createR600VectorRegMerger()
Definition: R600OptimizeVectorRegisters.cpp:385
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
llvm::AMDGPULowerKernelAttributesID
char & AMDGPULowerKernelAttributesID
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
llvm::R600ExpandSpecialInstrsPassID
char & R600ExpandSpecialInstrsPassID
Definition: R600ExpandSpecialInstrs.cpp:55
llvm::createR600ControlFlowFinalizer
FunctionPass * createR600ControlFlowFinalizer()
Definition: R600ControlFlowFinalizer.cpp:689
llvm::R600ClauseMergePassID
char & R600ClauseMergePassID
Definition: R600ClauseMergePass.cpp:73
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:405
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:133
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:385
llvm::createSIOptimizeExecMaskingPreRAPass
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
Definition: SIOptimizeExecMaskingPreRA.cpp:77
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:249
llvm::AMDGPUPromoteAllocaID
char & AMDGPUPromoteAllocaID
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:157
llvm::AMDGPUAS::CONSTANT_BUFFER_5
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:409
PassManager.h
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:451
llvm::AMDGPUPropagateAttributesLatePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:426
llvm::AMDGPURewriteOutArgumentsID
char & AMDGPURewriteOutArgumentsID
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:381
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:363
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1145
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1445
CodeGen.h
llvm::AMDGPUAS::CONSTANT_BUFFER_12
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:416
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
llvm::AMDGPULowerModuleLDSPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPULowerModuleLDSPass.cpp:396
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createAMDGPUFixFunctionBitcastsPass
ModulePass * createAMDGPUFixFunctionBitcastsPass()
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:104
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:298
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:365
llvm::initializeAMDGPUFixFunctionBitcastsPass
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_15
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:419
llvm::AMDGPUPromoteAllocaToVectorID
char & AMDGPUPromoteAllocaToVectorID
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:78
llvm::AMDGPUAnnotateUniformValuesPassID
char & AMDGPUAnnotateUniformValuesPassID
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:375
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::AMDGPUUseNativeCallsID
char & AMDGPUUseNativeCallsID
llvm::createAMDGPUCFGStructurizerPass
FunctionPass * createAMDGPUCFGStructurizerPass()
Definition: AMDILCFGStructurizer.cpp:1654
llvm::createR600ISelDag
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
Definition: AMDGPUISelDAGToDAG.cpp:391
llvm::AMDGPUAnnotateKernelFeaturesID
char & AMDGPUAnnotateKernelFeaturesID
Definition: AMDGPUAnnotateKernelFeatures.cpp:73
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
llvm::AMDGPUAS::CONSTANT_BUFFER_14
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:418
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:145
llvm::AMDGPUAS::PARAM_I_ADDRESS
@ PARAM_I_ADDRESS
Address space for indirect addressible parameter memory (VTX1).
Definition: AMDGPU.h:396
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::AMDGPULateCodeGenPrepareID
char & AMDGPULateCodeGenPrepareID
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:382
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::initializeAMDGPUPerfHintAnalysisPass
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
llvm::AMDGPULowerKernelArgumentsID
char & AMDGPULowerKernelArgumentsID
llvm::AMDGPULowerIntrinsicsID
char & AMDGPULowerIntrinsicsID
Definition: AMDGPULowerIntrinsics.cpp:63
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1699