LLVM 17.0.0git
AMDGPU.h
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1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/IR/PassManager.h"
14#include "llvm/Pass.h"
16
17namespace llvm {
18
19class TargetMachine;
20
21// GlobalISel passes
28
30
31// SI Passes
48
62
63struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
66
67private:
68 TargetMachine &TM;
69};
70
71struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
73};
74
76
79
81
87
90extern char &AMDGPUAtomicOptimizerID;
91
94extern char &AMDGPULowerIntrinsicsID;
95
99
103
107
109 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
111};
112
116
118 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
120};
121
124
126 : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
129
130private:
131 TargetMachine &TM;
132};
133
136
138 : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
141
142private:
143 TargetMachine &TM;
144};
145
148
150 : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> {
152};
153
155extern char &AMDGPULowerModuleLDSID;
156
157struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
159};
160
162extern char &AMDGPURewriteOutArgumentsID;
163
165extern char &GCNDPPCombineID;
166
168extern char &SIFoldOperandsID;
169
171extern char &SIPeepholeSDWAID;
172
174extern char &SIShrinkInstructionsID;
175
177extern char &SIFixSGPRCopiesID;
178
180extern char &SIFixVGPRCopiesID;
181
183extern char &SILowerI1CopiesID;
184
186extern char &SILowerSGPRSpillsID;
187
189extern char &SILoadStoreOptimizerID;
190
192extern char &SIWholeQuadModeID;
193
195extern char &SILowerControlFlowID;
196
198extern char &SIPreEmitPeepholeID;
199
201extern char &SILateBranchLoweringPassID;
202
204extern char &SIOptimizeExecMaskingID;
205
207extern char &SIPreAllocateWWMRegsID;
208
210extern char &AMDGPUSimplifyLibCallsID;
211
213extern char &AMDGPUUseNativeCallsID;
214
216extern char &AMDGPUPerfHintAnalysisID;
217
218// Passes common to R600 and SI
221extern char &AMDGPUPromoteAllocaID;
222
226
227struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
230
231private:
232 TargetMachine &TM;
233};
234
236 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
239
240private:
241 TargetMachine &TM;
242};
243
246 CodeGenOpt::Level OptLevel);
247ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
248
249struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
250 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
252
253private:
254 bool GlobalOpt;
255};
256
258
262
265
267 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
269};
270
273extern char &AMDGPUUnifyMetadataID;
274
275struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
277};
278
281
283extern char &SIOptimizeVGPRLiveRangeID;
284
287
289extern char &AMDGPUCodeGenPrepareID;
290
292extern char &AMDGPULateCodeGenPrepareID;
293
297
299extern char &SIAnnotateControlFlowPassID;
300
302extern char &SIMemoryLegalizerID;
303
305extern char &SIModeRegisterID;
306
308extern char &AMDGPUReleaseVGPRsID;
309
311extern char &AMDGPUInsertDelayAluID;
312
314extern char &SIInsertHardClausesID;
315
317extern char &SIInsertWaitcntsID;
318
320extern char &SIFormMemoryClausesID;
321
323extern char &SIPostRABundlerID;
324
326extern char &GCNCreateVOPDID;
327
330
335
337
341
343extern char &GCNNSAReassignID;
344
346extern char &GCNPreRAOptimizationsID;
347
350
351namespace AMDGPU {
359}
360
361/// OpenCL uses address spaces to differentiate between
362/// various memory regions on the hardware. On the CPU
363/// all of the address spaces point to the same memory,
364/// however on the GPU, each address space points to
365/// a separate piece of memory that is unique from other
366/// memory locations.
367namespace AMDGPUAS {
368 enum : unsigned {
369 // The maximum value for flat, generic, local, private, constant and region.
371
372 FLAT_ADDRESS = 0, ///< Address space for flat memory.
373 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
374 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
375
376 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
377 LOCAL_ADDRESS = 3, ///< Address space for local memory.
378 PRIVATE_ADDRESS = 5, ///< Address space for private memory.
379
380 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
381
382 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
383
384 /// Address space for direct addressable parameter memory (CONST0).
386 /// Address space for indirect addressable parameter memory (VTX1).
388
389 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
390 // this order to be able to dynamically index a constant buffer, for
391 // example:
392 //
393 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
394
411
412 // Some places use this if the address space can't be determined.
414 };
415}
416
417namespace AMDGPU {
418
419// FIXME: Missing constant_32bit
420inline bool isFlatGlobalAddrSpace(unsigned AS) {
421 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
425}
426}
427
428} // End namespace llvm
429
430#endif
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef TM
This header defines various interfaces for pass management in LLVM.
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:620
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:248
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:152
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:400
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:410
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:370
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:380
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:406
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:401
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:407
@ PARAM_D_ADDRESS
Address space for direct addressable parameter memory (CONST0).
Definition: AMDGPU.h:385
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:374
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:397
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:396
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:395
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:377
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:403
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:399
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:398
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:405
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
Definition: AMDGPU.h:387
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:376
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:413
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:372
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:373
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:409
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:404
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:402
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:408
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:382
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:378
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:420
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:355
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:357
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:354
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:356
@ TI_CONSTDATA_START
Definition: AMDGPU.h:353
Level
Code generation optimization level.
Definition: CodeGen.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFormMemoryClausesPass(PassRegistry &)
char & SIPreAllocateWWMRegsID
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createSIPreAllocateWWMRegsPass()
FunctionPass * createAMDGPUSetWavePriorityPass()
char & AMDGPUCtorDtorLoweringLegacyPassID
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeGCNCreateVOPDPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
char & AMDGPUAnnotateKernelFeaturesID
char & GCNPreRAOptimizationsID
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
char & AMDGPUPropagateAttributesEarlyID
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
char & SIMemoryLegalizerID
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIPostRABundlerID
FunctionPass * createSIModeRegisterPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeSIModeRegisterPass(PassRegistry &)
ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
char & AMDGPUSimplifyLibCallsID
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
char & AMDGPUPromoteKernelArgumentsID
void initializeAMDGPUAttributorPass(PassRegistry &)
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeSIShrinkInstructionsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
char & SILowerI1CopiesID
char & AMDGPUResourceUsageAnalysisID
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
char & AMDGPULowerModuleLDSID
char & SILoadStoreOptimizerID
FunctionPass * createSIWholeQuadModePass()
ModulePass * createAMDGPULowerKernelAttributesPass()
char & AMDGPUReleaseVGPRsID
ModulePass * createAMDGPULowerIntrinsicsPass()
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
void initializeSIPreEmitPeepholePass(PassRegistry &)
FunctionPass * createSILoadStoreOptimizerPass()
void initializeSIFixVGPRCopiesPass(PassRegistry &)
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & SIFormMemoryClausesID
void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSILateBranchLoweringPass(PassRegistry &)
void initializeSIPeepholeSDWAPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAllocaToVector()
char & AMDGPULateCodeGenPrepareID
char & AMDGPUUnifyDivergentExitNodesID
ModulePass * createAMDGPULowerModuleLDSPass()
char & SIInsertWaitcntsID
char & AMDGPUReplaceLDSUseWithPointerID
char & AMDGPUPrintfRuntimeBindingID
char & GCNNSAReassignID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
char & AMDGPUPerfHintAnalysisID
char & SILowerSGPRSpillsID
char & SILateBranchLoweringPassID
char & SIModeRegisterID
char & AMDGPULowerIntrinsicsID
void initializeAMDGPURewriteUndefForPHIPass(PassRegistry &)
FunctionPass * createGCNPreRAOptimizationsPass()
FunctionPass * createSIShrinkInstructionsPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeSIPostRABundlerPass(PassRegistry &)
FunctionPass * createAMDGPUAtomicOptimizerPass()
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUInsertDelayAluID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
char & SIOptimizeVGPRLiveRangeID
char & SIOptimizeExecMaskingPreRAID
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
void initializeSIInsertHardClausesPass(PassRegistry &)
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
FunctionPass * createSIPostRABundlerPass()
FunctionPass * createSIFormMemoryClausesPass()
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
Pass * createAMDGPUStructurizeCFGPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
ModulePass * createAMDGPUPrintfRuntimeBinding()
void initializeSIMemoryLegalizerPass(PassRegistry &)
char & AMDGPUUnifyMetadataID
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
char & SIPreEmitPeepholeID
FunctionPass * createSILowerI1CopiesPass()
char & AMDGPURewriteOutArgumentsID
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
FunctionPass * createAMDGPUCodeGenPreparePass()
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & AMDGPUMachineCFGStructurizerID
char & AMDGPULowerKernelAttributesID
char & GCNDPPCombineID
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createAMDGPURewriteUndefForPHIPass()
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
char & AMDGPUPromoteAllocaID
FunctionPass * createAMDGPUUseNativeCallsPass()
FunctionPass * createSIFoldOperandsPass()
char & SIWholeQuadModeID
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
ImmutablePass * createAMDGPUExternalAAWrapperPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
void initializeSILowerSGPRSpillsPass(PassRegistry &)
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
char & SIInsertHardClausesID
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
char & GCNCreateVOPDID
Pass * createAMDGPUAttributorPass()
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SILowerControlFlowID
char & AMDGPUAtomicOptimizerID
char & SIAnnotateControlFlowPassID
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIMemoryLegalizerPass()
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
void initializeSIFoldOperandsPass(PassRegistry &)
void initializeSILowerControlFlowPass(PassRegistry &)
char & SIPeepholeSDWAID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
char & SIFixVGPRCopiesID
void initializeAMDGPUReleaseVGPRsPass(PassRegistry &)
void initializeAMDGPURegBankSelectPass(PassRegistry &)
FunctionPass * createSIOptimizeVGPRLiveRangePass()
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
FunctionPass * createSIInsertWaitcntsPass()
void initializeGCNDPPCombinePass(PassRegistry &)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createGCNDPPCombinePass()
FunctionPass * createAMDGPULateCodeGenPreparePass()
FunctionPass * createSIFixSGPRCopiesPass()
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
char & AMDGPUPromoteAllocaToVectorID
char & AMDGPURewriteUndefForPHIPassID
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
char & SIOptimizeExecMaskingID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & SIFixSGPRCopiesID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
char & AMDGPUUseNativeCallsID
char & AMDGPULowerKernelArgumentsID
char & AMDGPUPropagateAttributesLateID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUSetWavePriorityPass(PassRegistry &)
char & SIShrinkInstructionsID
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:250
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:228
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:237
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM)
Definition: AMDGPU.h:127
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUPropagateAttributesLatePass(TargetMachine &TM)
Definition: AMDGPU.h:139
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUSimplifyLibCallsPass(TargetMachine &TM)
Definition: AMDGPU.h:64
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:371