LLVM  15.0.0git
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Support/CodeGen.h"
16 
17 namespace llvm {
18 
19 class TargetMachine;
20 
21 // GlobalISel passes
22 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
23 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
25 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
26 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
27 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
28 
29 // SI Passes
30 FunctionPass *createGCNDPPCombinePass();
31 FunctionPass *createSIAnnotateControlFlowPass();
32 FunctionPass *createSIFoldOperandsPass();
33 FunctionPass *createSIPeepholeSDWAPass();
34 FunctionPass *createSILowerI1CopiesPass();
35 FunctionPass *createSIShrinkInstructionsPass();
36 FunctionPass *createSILoadStoreOptimizerPass();
37 FunctionPass *createSIWholeQuadModePass();
40 FunctionPass *createSIOptimizeVGPRLiveRangePass();
41 FunctionPass *createSIFixSGPRCopiesPass();
42 FunctionPass *createSIMemoryLegalizerPass();
43 FunctionPass *createSIInsertWaitcntsPass();
44 FunctionPass *createSIPreAllocateWWMRegsPass();
45 FunctionPass *createSIFormMemoryClausesPass();
46 
47 FunctionPass *createSIPostRABundlerPass();
48 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
49 FunctionPass *createAMDGPUUseNativeCallsPass();
50 FunctionPass *createAMDGPUCodeGenPreparePass();
53 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
54 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
57 ModulePass *createAMDGPULowerModuleLDSPass();
58 FunctionPass *createSIModeRegisterPass();
59 FunctionPass *createGCNPreRAOptimizationsPass();
60 
61 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
64 
65 private:
66  TargetMachine &TM;
67 };
68 
69 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
71 };
72 
74 
77 
79 
85 
88 extern char &AMDGPUAtomicOptimizerID;
89 
92 extern char &AMDGPULowerIntrinsicsID;
93 
96 extern char &AMDGPUCtorDtorLoweringID;
97 
100 extern char &AMDGPULowerKernelArgumentsID;
101 
104 extern char &AMDGPUPromoteKernelArgumentsID;
105 
107  : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
109 };
110 
113 extern char &AMDGPULowerKernelAttributesID;
114 
116  : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
118 };
119 
122 
124  : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
127 
128 private:
129  TargetMachine &TM;
130 };
131 
134 
136  : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
139 
140 private:
141  TargetMachine &TM;
142 };
143 
146 
148  : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> {
150 };
151 
153 extern char &AMDGPULowerModuleLDSID;
154 
155 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
157 };
158 
160 extern char &AMDGPURewriteOutArgumentsID;
161 
163 extern char &GCNDPPCombineID;
164 
166 extern char &SIFoldOperandsID;
167 
169 extern char &SIPeepholeSDWAID;
170 
172 extern char &SIShrinkInstructionsID;
173 
175 extern char &SIFixSGPRCopiesID;
176 
178 extern char &SIFixVGPRCopiesID;
179 
181 extern char &SILowerI1CopiesID;
182 
184 extern char &SILowerSGPRSpillsID;
185 
187 extern char &SILoadStoreOptimizerID;
188 
190 extern char &SIWholeQuadModeID;
191 
193 extern char &SILowerControlFlowID;
194 
196 extern char &SIPreEmitPeepholeID;
197 
199 extern char &SILateBranchLoweringPassID;
200 
202 extern char &SIOptimizeExecMaskingID;
203 
205 extern char &SIPreAllocateWWMRegsID;
206 
208 extern char &AMDGPUSimplifyLibCallsID;
209 
211 extern char &AMDGPUUseNativeCallsID;
212 
214 extern char &AMDGPUPerfHintAnalysisID;
215 
216 // Passes common to R600 and SI
219 extern char &AMDGPUPromoteAllocaID;
220 
223 extern char &AMDGPUPromoteAllocaToVectorID;
224 
225 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
228 
229 private:
230  TargetMachine &TM;
231 };
232 
234  : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
237 
238 private:
239  TargetMachine &TM;
240 };
241 
243 FunctionPass *createAMDGPUISelDag(
244  TargetMachine *TM = nullptr,
246 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
247 
248 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
249  AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
251 
252 private:
253  bool GlobalOpt;
254 };
255 
256 FunctionPass *createAMDGPUAnnotateUniformValues();
257 
259 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
260 extern char &AMDGPUPrintfRuntimeBindingID;
261 
262 void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
263 extern char &AMDGPUResourceUsageAnalysisID;
264 
266  : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
268 };
269 
272 extern char &AMDGPUUnifyMetadataID;
273 
274 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
276 };
277 
279 extern char &SIOptimizeExecMaskingPreRAID;
280 
282 extern char &SIOptimizeVGPRLiveRangeID;
283 
286 
288 extern char &AMDGPUCodeGenPrepareID;
289 
291 extern char &AMDGPULateCodeGenPrepareID;
292 
294 extern char &SIAnnotateControlFlowPassID;
295 
297 extern char &SIMemoryLegalizerID;
298 
300 extern char &SIModeRegisterID;
301 
303 extern char &SIInsertHardClausesID;
304 
306 extern char &SIInsertWaitcntsID;
307 
309 extern char &SIFormMemoryClausesID;
310 
312 extern char &SIPostRABundlerID;
313 
316 
321 
323 
327 
329 extern char &GCNNSAReassignID;
330 
332 extern char &GCNPreRAOptimizationsID;
333 
336 
337 namespace AMDGPU {
344 };
345 }
346 
347 /// OpenCL uses address spaces to differentiate between
348 /// various memory regions on the hardware. On the CPU
349 /// all of the address spaces point to the same memory,
350 /// however on the GPU, each address space points to
351 /// a separate piece of memory that is unique from other
352 /// memory locations.
353 namespace AMDGPUAS {
354  enum : unsigned {
355  // The maximum value for flat, generic, local, private, constant and region.
357 
358  FLAT_ADDRESS = 0, ///< Address space for flat memory.
359  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
360  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
361 
362  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
363  LOCAL_ADDRESS = 3, ///< Address space for local memory.
364  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
365 
366  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
367 
368  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
369 
370  /// Address space for direct addressable parameter memory (CONST0).
372  /// Address space for indirect addressable parameter memory (VTX1).
374 
375  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
376  // this order to be able to dynamically index a constant buffer, for
377  // example:
378  //
379  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
380 
397 
398  // Some places use this if the address space can't be determined.
400  };
401 }
402 
403 namespace AMDGPU {
404 
405 // FIXME: Missing constant_32bit
406 inline bool isFlatGlobalAddrSpace(unsigned AS) {
407  return AS == AMDGPUAS::GLOBAL_ADDRESS ||
408  AS == AMDGPUAS::FLAT_ADDRESS ||
411 }
412 }
413 
414 } // End namespace llvm
415 
416 #endif
llvm::PreservedAnalyses
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:152
llvm::AMDGPUPropagateAttributesEarlyPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:411
llvm::createSIPostRABundlerPass
FunctionPass * createSIPostRABundlerPass()
Definition: SIPostRABundler.cpp:71
llvm::createAMDGPUCtorDtorLoweringPass
ModulePass * createAMDGPUCtorDtorLoweringPass()
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AMDGPUPromoteAllocaToVectorPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:1132
llvm::createAMDGPUAttributorPass
Pass * createAMDGPUAttributorPass()
Definition: AMDGPUAttributor.cpp:777
llvm::createSIFixControlFlowLiveIntervalsPass
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AMDGPUMachineCFGStructurizerID
char & AMDGPUMachineCFGStructurizerID
Definition: AMDGPUMachineCFGStructurizer.cpp:2843
Pass
print lazy value Lazy Value Info Printer Pass
Definition: LazyValueInfo.cpp:1978
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:155
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:2240
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:73
llvm::createAMDGPUSetWavePriorityPass
FunctionPass * createAMDGPUSetWavePriorityPass()
llvm::ModulePass
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:248
llvm::AMDGPUAS::CONSTANT_BUFFER_11
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:392
llvm::createSIFixSGPRCopiesPass
FunctionPass * createSIFixSGPRCopiesPass()
Definition: SIFixSGPRCopies.cpp:123
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:248
llvm::PassInfoMixin
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:371
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPrintfRuntimeBinding.cpp:583
llvm::Function
Definition: Function.h:60
Pass.h
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesEarlyPass::AMDGPUPropagateAttributesEarlyPass
AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM)
Definition: AMDGPU.h:125
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:233
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUPromoteKernelArgumentsID
char & AMDGPUPromoteKernelArgumentsID
llvm::AMDGPUReplaceLDSUseWithPointerID
char & AMDGPUReplaceLDSUseWithPointerID
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:621
llvm::AMDGPULowerModuleLDSID
char & AMDGPULowerModuleLDSID
Definition: AMDGPULowerModuleLDSPass.cpp:464
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:193
llvm::AMDGPUUnifyMetadataID
char & AMDGPUUnifyMetadataID
Definition: AMDGPUUnifyMetadata.cpp:127
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::createSIWholeQuadModePass
FunctionPass * createSIWholeQuadModePass()
Definition: SIWholeQuadMode.cpp:267
llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:356
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:448
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:174
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:618
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
llvm::initializeAMDGPUSetWavePriorityPass
void initializeAMDGPUSetWavePriorityPass(PassRegistry &)
llvm::AMDGPUSimplifyLibCallsID
char & AMDGPUSimplifyLibCallsID
llvm::AMDGPUAS::CONSTANT_BUFFER_5
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:386
llvm::SIInsertWaitcntsID
char & SIInsertWaitcntsID
Definition: SIInsertWaitcnts.cpp:801
llvm::createSILoadStoreOptimizerPass
FunctionPass * createSILoadStoreOptimizerPass()
Definition: SILoadStoreOptimizer.cpp:736
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:112
llvm::initializeAMDGPUMachineCFGStructurizerPass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:358
llvm::AMDGPUAS::CONSTANT_BUFFER_9
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:390
llvm::createSIPreAllocateWWMRegsPass
FunctionPass * createSIPreAllocateWWMRegsPass()
Definition: SIPreAllocateWWMRegs.cpp:86
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:69
llvm::AMDGPULowerKernelAttributesPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULowerKernelAttributes.cpp:253
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:84
llvm::initializeAMDGPUPromoteKernelArgumentsPass
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
llvm::AMDGPUResourceUsageAnalysisID
char & AMDGPUResourceUsageAnalysisID
Definition: AMDGPUResourceUsageAnalysis.cpp:43
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_3
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:384
llvm::AMDGPUAS::CONSTANT_BUFFER_14
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:395
llvm::createAMDGPUStructurizeCFGPass
Pass * createAMDGPUStructurizeCFGPass()
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:37
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:274
llvm::AMDGPUPromoteAllocaPass::AMDGPUPromoteAllocaPass
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:226
llvm::AMDGPUUnifyMetadataPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUUnifyMetadata.cpp:140
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:360
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:53
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
llvm::AMDGPUCodeGenPrepareID
char & AMDGPUCodeGenPrepareID
llvm::AMDGPU::TargetIndex
TargetIndex
Definition: AMDGPU.h:338
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1663
llvm::SILowerI1CopiesID
char & SILowerI1CopiesID
Definition: SILowerI1Copies.cpp:411
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::createGCNPreRAOptimizationsPass
FunctionPass * createGCNPreRAOptimizationsPass()
Definition: GCNPreRAOptimizations.cpp:81
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
llvm::createSIOptimizeVGPRLiveRangePass
FunctionPass * createSIOptimizeVGPRLiveRangePass()
Definition: SIOptimizeVGPRLiveRange.cpp:620
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:803
llvm::AMDGPUAtomicOptimizerID
char & AMDGPUAtomicOptimizerID
Definition: AMDGPUAtomicOptimizer.cpp:80
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:122
llvm::AMDGPUPropagateAttributesEarlyID
char & AMDGPUPropagateAttributesEarlyID
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:225
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:366
llvm::AMDGPUOpenCLEnqueuedBlockLoweringID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
Definition: AMDGPUOpenCLEnqueuedBlockLowering.cpp:65
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createSIPeepholeSDWAPass
FunctionPass * createSIPeepholeSDWAPass()
Definition: SIPeepholeSDWA.cpp:193
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:115
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:406
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:175
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:137
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
llvm::AMDGPUReplaceLDSUseWithPointerPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:644
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:734
llvm::AMDGPUSimplifyLibCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1700
llvm::SIMemoryLegalizerID
char & SIMemoryLegalizerID
Definition: SIMemoryLegalizer.cpp:2238
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
llvm::AMDGPUAS::PARAM_D_ADDRESS
@ PARAM_D_ADDRESS
Address space for direct addressable parameter memory (CONST0).
Definition: AMDGPU.h:371
llvm::AMDGPUAS::CONSTANT_BUFFER_10
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:391
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:33
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:93
llvm::createSIFoldOperandsPass
FunctionPass * createSIFoldOperandsPass()
Definition: SIFoldOperands.cpp:174
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:163
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_13
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:394
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:359
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_0
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:381
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:341
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
llvm::AMDGPU::TI_CONSTDATA_START
@ TI_CONSTDATA_START
Definition: AMDGPU.h:339
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:61
llvm::AMDGPUUseNativeCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1758
llvm::AMDGPUPropagateAttributesLateID
char & AMDGPUPropagateAttributesLateID
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::SIAnnotateControlFlowPassID
char & SIAnnotateControlFlowPassID
llvm::AMDGPUPromoteKernelArgumentsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteKernelArguments.cpp:208
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::AMDGPUPrintfRuntimeBindingID
char & AMDGPUPrintfRuntimeBindingID
Definition: AMDGPUPrintfRuntimeBinding.cpp:90
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:221
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:406
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::AMDGPUCtorDtorLoweringID
char & AMDGPUCtorDtorLoweringID
Definition: AMDGPUCtorDtorLowering.cpp:78
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::SIModeRegisterID
char & SIModeRegisterID
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesLatePass::AMDGPUPropagateAttributesLatePass
AMDGPUPropagateAttributesLatePass(TargetMachine &TM)
Definition: AMDGPU.h:137
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::AMDGPUAS::CONSTANT_BUFFER_7
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:388
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2851
llvm::createSIFormMemoryClausesPass
FunctionPass * createSIFormMemoryClausesPass()
Definition: SIFormMemoryClauses.cpp:93
llvm::SIShrinkInstructionsID
char & SIShrinkInstructionsID
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:399
llvm::AMDGPUAlwaysInlinePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUAlwaysInlinePass.cpp:167
llvm::AMDGPUPromoteAllocaToVectorPass::AMDGPUPromoteAllocaToVectorPass
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:235
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
llvm::createAMDGPURewriteOutArgumentsPass
FunctionPass * createAMDGPURewriteOutArgumentsPass()
Definition: AMDGPURewriteOutArguments.cpp:408
llvm::AMDGPUSimplifyLibCallsPass::AMDGPUSimplifyLibCallsPass
AMDGPUSimplifyLibCallsPass(TargetMachine &TM)
Definition: AMDGPU.h:62
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
llvm::AMDGPUAlwaysInlinePass::AMDGPUAlwaysInlinePass
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:249
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:486
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:155
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:265
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:147
llvm::AMDGPUAS::CONSTANT_BUFFER_2
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:383
llvm::createGCNDPPCombinePass
FunctionPass * createGCNDPPCombinePass()
Definition: GCNDPPCombine.cpp:113
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:248
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1146
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:343
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
llvm::AMDGPUPromoteKernelArgumentsPass
Definition: AMDGPU.h:106
llvm::AMDGPULowerKernelAttributesID
char & AMDGPULowerKernelAttributesID
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:401
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:123
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_8
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:389
llvm::AMDGPUAS::CONSTANT_BUFFER_1
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:382
llvm::createSIOptimizeExecMaskingPreRAPass
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
Definition: SIOptimizeExecMaskingPreRA.cpp:77
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUPromoteAllocaID
char & AMDGPUPromoteAllocaID
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:158
PassManager.h
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:639
llvm::AMDGPUPropagateAttributesLatePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:422
llvm::AMDGPURewriteOutArgumentsID
char & AMDGPURewriteOutArgumentsID
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:340
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:362
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1142
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:363
llvm::AMDGPUAS::CONSTANT_BUFFER_15
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:396
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1465
llvm::createAMDGPUPromoteKernelArgumentsPass
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
Definition: AMDGPUPromoteKernelArguments.cpp:203
llvm::AMDGPUAS::PARAM_I_ADDRESS
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
Definition: AMDGPU.h:373
CodeGen.h
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
llvm::AMDGPULowerModuleLDSPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPULowerModuleLDSPass.cpp:474
llvm::AMDGPUAS::BUFFER_FAT_POINTER
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:368
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:105
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:298
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:342
llvm::AMDGPUPromoteAllocaToVectorID
char & AMDGPUPromoteAllocaToVectorID
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:79
llvm::AMDGPUAnnotateUniformValuesPassID
char & AMDGPUAnnotateUniformValuesPassID
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:389
llvm::initializeAMDGPUCtorDtorLoweringPass
void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &)
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::AMDGPUUseNativeCallsID
char & AMDGPUUseNativeCallsID
llvm::AMDGPUAS::CONSTANT_BUFFER_4
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:385
llvm::AMDGPUAnnotateKernelFeaturesID
char & AMDGPUAnnotateKernelFeaturesID
Definition: AMDGPUAnnotateKernelFeatures.cpp:57
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:135
llvm::AMDGPUAS::CONSTANT_BUFFER_12
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:393
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::AMDGPULateCodeGenPrepareID
char & AMDGPULateCodeGenPrepareID
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::initializeAMDGPUPerfHintAnalysisPass
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_6
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:387
llvm::AMDGPULowerKernelArgumentsID
char & AMDGPULowerKernelArgumentsID
llvm::AMDGPULowerIntrinsicsID
char & AMDGPULowerIntrinsicsID
Definition: AMDGPULowerIntrinsics.cpp:62
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1659