LLVM 18.0.0git
AMDGPU.h
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1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/IR/PassManager.h"
14#include "llvm/Pass.h"
16
17namespace llvm {
18
19class AMDGPUTargetMachine;
20class GCNTargetMachine;
21class TargetMachine;
22
23// GlobalISel passes
30
32
33// SI Passes
51
63
64struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
67};
68
70 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
73
74private:
75 TargetMachine &TM;
76};
77
78struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
80};
81
83
86
88
94
95// DPP/Iterative option enables the atomic optimizer with given strategy
96// whereas None disables the atomic optimizer.
97enum class ScanOptions { DPP, Iterative, None };
98FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
100extern char &AMDGPUAtomicOptimizerID;
101
105
109
113
115 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
117};
118
122
124 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
126};
127
130
131struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
134
136};
137
139extern char &AMDGPURewriteOutArgumentsID;
140
142extern char &GCNDPPCombineID;
143
145extern char &SIFoldOperandsID;
146
148extern char &SIPeepholeSDWAID;
149
151extern char &SIShrinkInstructionsID;
152
154extern char &SIFixSGPRCopiesID;
155
157extern char &SIFixVGPRCopiesID;
158
160extern char &SILowerWWMCopiesID;
161
163extern char &SILowerI1CopiesID;
164
166extern char &SILowerSGPRSpillsID;
167
169extern char &SILoadStoreOptimizerID;
170
172extern char &SIWholeQuadModeID;
173
175extern char &SILowerControlFlowID;
176
178extern char &SIPreEmitPeepholeID;
179
181extern char &SILateBranchLoweringPassID;
182
184extern char &SIOptimizeExecMaskingID;
185
187extern char &SIPreAllocateWWMRegsID;
188
191
193extern char &AMDGPUPerfHintAnalysisID;
194
196extern char &GCNRegPressurePrinterID;
197
198// Passes common to R600 and SI
201extern char &AMDGPUPromoteAllocaID;
202
206
207struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
210
211private:
212 TargetMachine &TM;
213};
214
216 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
219
220private:
221 TargetMachine &TM;
222};
223
224struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
226 : TM(TM), ScanImpl(ScanImpl) {}
228
229private:
230 TargetMachine &TM;
231 ScanOptions ScanImpl;
232};
233
236ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
237
238struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
239 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
241
242private:
243 bool GlobalOpt;
244};
245
247 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
248private:
249 TargetMachine &TM;
250
251public:
254};
255
257 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
258private:
259 TargetMachine &TM;
260
261public:
264};
265
266class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
267private:
268 TargetMachine &TM;
269
270public:
273};
274
276
280
283
285 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
287};
288
291extern char &AMDGPUUnifyMetadataID;
292
293struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
295};
296
299
301extern char &SIOptimizeVGPRLiveRangeID;
302
305
307extern char &AMDGPUCodeGenPrepareID;
308
311
313extern char &AMDGPULateCodeGenPrepareID;
314
318
320 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
321public:
324};
325
327extern char &SIAnnotateControlFlowPassID;
328
330extern char &SIMemoryLegalizerID;
331
333extern char &SIModeRegisterID;
334
336extern char &AMDGPUInsertDelayAluID;
337
339extern char &AMDGPUInsertSingleUseVDSTID;
340
342extern char &SIInsertHardClausesID;
343
345extern char &SIInsertWaitcntsID;
346
348extern char &SIFormMemoryClausesID;
349
351extern char &SIPostRABundlerID;
352
354extern char &GCNCreateVOPDID;
355
358
363
365
369
371extern char &GCNNSAReassignID;
372
374extern char &GCNPreRALongBranchRegID;
375
377extern char &GCNPreRAOptimizationsID;
378
381
383extern char &GCNRewritePartialRegUsesID;
384
385namespace AMDGPU {
393}
394
395/// OpenCL uses address spaces to differentiate between
396/// various memory regions on the hardware. On the CPU
397/// all of the address spaces point to the same memory,
398/// however on the GPU, each address space points to
399/// a separate piece of memory that is unique from other
400/// memory locations.
401namespace AMDGPUAS {
402enum : unsigned {
403 // The maximum value for flat, generic, local, private, constant and region.
405
406 FLAT_ADDRESS = 0, ///< Address space for flat memory.
407 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
408 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
409
410 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
411 LOCAL_ADDRESS = 3, ///< Address space for local memory.
412 PRIVATE_ADDRESS = 5, ///< Address space for private memory.
413
414 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
415
416 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
417 ///< Not used in backend.
418
419 BUFFER_RESOURCE = 8, ///< Address space for 128-bit buffer resources.
420
421 /// Internal address spaces. Can be freely renumbered.
422 STREAMOUT_REGISTER = 128, ///< Address space for GS NGG Streamout registers.
423 /// end Internal address spaces.
424
425 /// Address space for direct addressable parameter memory (CONST0).
427 /// Address space for indirect addressable parameter memory (VTX1).
429
430 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
431 // this order to be able to dynamically index a constant buffer, for
432 // example:
433 //
434 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
435
452
453 // Some places use this if the address space can't be determined.
455};
456}
457
458namespace AMDGPU {
459
460// FIXME: Missing constant_32bit
461inline bool isFlatGlobalAddrSpace(unsigned AS) {
462 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
466}
467
468inline bool isExtendedGlobalAddrSpace(unsigned AS) {
472}
473
474static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
475 static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 8, "Addr space out of range");
476
478 return true;
479
480 // This array is indexed by address space value enum elements 0 ... to 8
481 // clang-format off
482 static const bool ASAliasRules[9][9] = {
483 /* Flat Global Region Group Constant Private Const32 BufFatPtr BufRsrc */
484 /* Flat */ {true, true, false, true, true, true, true, true, true},
485 /* Global */ {true, true, false, false, true, false, true, true, true},
486 /* Region */ {false, false, true, false, false, false, false, false, false},
487 /* Group */ {true, false, false, true, false, false, false, false, false},
488 /* Constant */ {true, true, false, false, false, false, true, true, true},
489 /* Private */ {true, false, false, false, false, true, false, false, false},
490 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true},
491 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true},
492 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true},
493 };
494 // clang-format on
495
496 return ASAliasRules[AS1][AS2];
497}
498
499}
500
501} // End namespace llvm
502
503#endif
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef TM
This header defines various interfaces for pass management in LLVM.
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUAttributorPass(TargetMachine &TM)
Definition: AMDGPU.h:271
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
AMDGPUCodeGenPreparePass(TargetMachine &TM)
Definition: AMDGPU.h:252
AMDGPULowerKernelArgumentsPass(TargetMachine &TM)
Definition: AMDGPU.h:262
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:649
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:251
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:172
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:441
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:451
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:404
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:414
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:447
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:442
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:448
@ PARAM_D_ADDRESS
end Internal address spaces.
Definition: AMDGPU.h:426
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:408
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:438
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:437
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:436
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:411
@ STREAMOUT_REGISTER
Internal address spaces. Can be freely renumbered.
Definition: AMDGPU.h:422
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:444
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:440
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:439
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:446
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
Definition: AMDGPU.h:428
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:410
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:454
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:406
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:407
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:450
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:445
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:443
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:449
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:416
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:412
@ BUFFER_RESOURCE
Address space for 128-bit buffer resources.
Definition: AMDGPU.h:419
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:461
static bool addrspacesMayAlias(unsigned AS1, unsigned AS2)
Definition: AMDGPU.h:474
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:389
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:391
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:388
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:390
@ TI_CONSTDATA_START
Definition: AMDGPU.h:387
bool isExtendedGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:468
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFormMemoryClausesPass(PassRegistry &)
char & SIPreAllocateWWMRegsID
ScanOptions
Definition: AMDGPU.h:97
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createSIPreAllocateWWMRegsPass()
FunctionPass * createAMDGPUSetWavePriorityPass()
char & AMDGPUCtorDtorLoweringLegacyPassID
void initializeAMDGPUInsertSingleUseVDSTPass(PassRegistry &)
void initializeGCNCreateVOPDPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
char & AMDGPUAnnotateKernelFeaturesID
char & GCNPreRAOptimizationsID
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
char & SIMemoryLegalizerID
void initializeAMDGPUAttributorLegacyPass(PassRegistry &)
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIPostRABundlerID
FunctionPass * createSIModeRegisterPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeSIModeRegisterPass(PassRegistry &)
ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
char & AMDGPUImageIntrinsicOptimizerID
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &)
char & AMDGPUPromoteKernelArgumentsID
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
char & GCNRewritePartialRegUsesID
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
void initializeSIShrinkInstructionsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeGCNPreRALongBranchRegPass(PassRegistry &)
char & SILowerI1CopiesID
char & AMDGPUResourceUsageAnalysisID
char & SILoadStoreOptimizerID
FunctionPass * createSIWholeQuadModePass()
ModulePass * createAMDGPULowerKernelAttributesPass()
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
void initializeSIPreEmitPeepholePass(PassRegistry &)
FunctionPass * createSILoadStoreOptimizerPass()
char & SILowerWWMCopiesID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &)
void initializeSILowerWWMCopiesPass(PassRegistry &)
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPUInsertSingleUseVDSTID
char & SIFormMemoryClausesID
char & AMDGPURemoveIncompatibleFunctionsID
void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &)
void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSILateBranchLoweringPass(PassRegistry &)
void initializeSIPeepholeSDWAPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAllocaToVector()
char & AMDGPULateCodeGenPrepareID
char & AMDGPUUnifyDivergentExitNodesID
char & SIInsertWaitcntsID
FunctionPass * createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy)
char & AMDGPUPrintfRuntimeBindingID
char & GCNNSAReassignID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
char & AMDGPUPerfHintAnalysisID
char & SILowerSGPRSpillsID
char & SILateBranchLoweringPassID
char & SIModeRegisterID
FunctionPass * createGCNPreRAOptimizationsPass()
FunctionPass * createSIShrinkInstructionsPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeSIPostRABundlerPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
Pass * createAMDGPUAttributorLegacyPass()
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUInsertDelayAluID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
char & SIOptimizeVGPRLiveRangeID
char & SIOptimizeExecMaskingPreRAID
char & AMDGPULowerModuleLDSLegacyPassID
void initializeSIInsertHardClausesPass(PassRegistry &)
FunctionPass * createSIPostRABundlerPass()
FunctionPass * createSIFormMemoryClausesPass()
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
Pass * createAMDGPUStructurizeCFGPass()
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
void initializeSIAnnotateControlFlowPass(PassRegistry &)
ModulePass * createAMDGPUPrintfRuntimeBinding()
void initializeSIMemoryLegalizerPass(PassRegistry &)
char & AMDGPUUnifyMetadataID
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
ModulePass * createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM=nullptr)
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
char & SIPreEmitPeepholeID
ModulePass * createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *)
FunctionPass * createSILowerI1CopiesPass()
void initializeGCNRegPressurePrinterPass(PassRegistry &)
char & AMDGPURewriteOutArgumentsID
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
FunctionPass * createAMDGPUCodeGenPreparePass()
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & AMDGPUMachineCFGStructurizerID
char & AMDGPULowerKernelAttributesID
@ None
Not a recurrence.
char & GCNDPPCombineID
char & GCNRegPressurePrinterID
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
char & AMDGPUPromoteAllocaID
FunctionPass * createSIFoldOperandsPass()
char & SIWholeQuadModeID
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
ImmutablePass * createAMDGPUExternalAAWrapperPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
FunctionPass * createAMDGPURewriteUndefForPHILegacyPass()
void initializeSILowerSGPRSpillsPass(PassRegistry &)
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
char & SIInsertHardClausesID
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
char & GCNCreateVOPDID
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SILowerControlFlowID
char & AMDGPUAtomicOptimizerID
char & SIAnnotateControlFlowPassID
FunctionPass * createLowerWWMCopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIMemoryLegalizerPass()
void initializeSIFoldOperandsPass(PassRegistry &)
void initializeSILowerControlFlowPass(PassRegistry &)
char & SIPeepholeSDWAID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
char & SIFixVGPRCopiesID
void initializeAMDGPURegBankSelectPass(PassRegistry &)
char & AMDGPURewriteUndefForPHILegacyPassID
FunctionPass * createSIOptimizeVGPRLiveRangePass()
FunctionPass * createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *)
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
FunctionPass * createSIInsertWaitcntsPass()
void initializeGCNDPPCombinePass(PassRegistry &)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createGCNDPPCombinePass()
FunctionPass * createAMDGPULateCodeGenPreparePass()
FunctionPass * createSIFixSGPRCopiesPass()
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
char & AMDGPUPromoteAllocaToVectorID
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
char & SIOptimizeExecMaskingID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & SIFixSGPRCopiesID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUSetWavePriorityPass(PassRegistry &)
char & SIShrinkInstructionsID
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
char & GCNPreRALongBranchRegID
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:239
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
Definition: AMDGPU.h:225
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM)
Definition: AMDGPU.h:71
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_)
Definition: AMDGPU.h:133
const AMDGPUTargetMachine & TM
Definition: AMDGPU.h:132
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:208
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:217
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:391