LLVM 22.0.0git
Namespaces | Macros | Enumerations | Functions | Variables
ISDOpcodes.h File Reference
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Support/Compiler.h"
#include "llvm/IR/VPIntrinsics.def"

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
namespace  llvm::ISD
 ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types and value types.
namespace  llvm::ISD::GlobalISel

Macros

#define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...)

Enumerations

enum  llvm::ISD::NodeType {
  llvm::ISD::DELETED_NODE , llvm::ISD::EntryToken , llvm::ISD::TokenFactor , llvm::ISD::AssertSext ,
  llvm::ISD::AssertZext , llvm::ISD::AssertAlign , llvm::ISD::AssertNoFPClass , llvm::ISD::BasicBlock ,
  llvm::ISD::VALUETYPE , llvm::ISD::CONDCODE , llvm::ISD::Register , llvm::ISD::RegisterMask ,
  llvm::ISD::Constant , llvm::ISD::ConstantFP , llvm::ISD::GlobalAddress , llvm::ISD::GlobalTLSAddress ,
  llvm::ISD::FrameIndex , llvm::ISD::JumpTable , llvm::ISD::ConstantPool , llvm::ISD::ExternalSymbol ,
  llvm::ISD::BlockAddress , llvm::ISD::PtrAuthGlobalAddress , llvm::ISD::GLOBAL_OFFSET_TABLE , llvm::ISD::FRAMEADDR ,
  llvm::ISD::RETURNADDR , llvm::ISD::ADDROFRETURNADDR , llvm::ISD::SPONENTRY , llvm::ISD::LOCAL_RECOVER ,
  llvm::ISD::READ_REGISTER , llvm::ISD::WRITE_REGISTER , llvm::ISD::FRAME_TO_ARGS_OFFSET , llvm::ISD::EH_DWARF_CFA ,
  llvm::ISD::EH_RETURN , llvm::ISD::EH_SJLJ_SETJMP , llvm::ISD::EH_SJLJ_LONGJMP , llvm::ISD::EH_SJLJ_SETUP_DISPATCH ,
  llvm::ISD::TargetConstant , llvm::ISD::TargetConstantFP , llvm::ISD::TargetGlobalAddress , llvm::ISD::TargetGlobalTLSAddress ,
  llvm::ISD::TargetFrameIndex , llvm::ISD::TargetJumpTable , llvm::ISD::TargetConstantPool , llvm::ISD::TargetExternalSymbol ,
  llvm::ISD::TargetBlockAddress , llvm::ISD::MCSymbol , llvm::ISD::TargetIndex , llvm::ISD::INTRINSIC_WO_CHAIN ,
  llvm::ISD::INTRINSIC_W_CHAIN , llvm::ISD::INTRINSIC_VOID , llvm::ISD::CopyToReg , llvm::ISD::CopyFromReg ,
  llvm::ISD::UNDEF , llvm::ISD::POISON , llvm::ISD::FREEZE , llvm::ISD::EXTRACT_ELEMENT ,
  llvm::ISD::BUILD_PAIR , llvm::ISD::MERGE_VALUES , llvm::ISD::ADD , llvm::ISD::SUB ,
  llvm::ISD::MUL , llvm::ISD::SDIV , llvm::ISD::UDIV , llvm::ISD::SREM ,
  llvm::ISD::UREM , llvm::ISD::SMUL_LOHI , llvm::ISD::UMUL_LOHI , llvm::ISD::SDIVREM ,
  llvm::ISD::UDIVREM , llvm::ISD::CARRY_FALSE , llvm::ISD::ADDC , llvm::ISD::SUBC ,
  llvm::ISD::ADDE , llvm::ISD::SUBE , llvm::ISD::UADDO_CARRY , llvm::ISD::USUBO_CARRY ,
  llvm::ISD::SADDO_CARRY , llvm::ISD::SSUBO_CARRY , llvm::ISD::SADDO , llvm::ISD::UADDO ,
  llvm::ISD::SSUBO , llvm::ISD::USUBO , llvm::ISD::SMULO , llvm::ISD::UMULO ,
  llvm::ISD::SADDSAT , llvm::ISD::UADDSAT , llvm::ISD::SSUBSAT , llvm::ISD::USUBSAT ,
  llvm::ISD::SSHLSAT , llvm::ISD::USHLSAT , llvm::ISD::SMULFIX , llvm::ISD::UMULFIX ,
  llvm::ISD::SMULFIXSAT , llvm::ISD::UMULFIXSAT , llvm::ISD::SDIVFIX , llvm::ISD::UDIVFIX ,
  llvm::ISD::SDIVFIXSAT , llvm::ISD::UDIVFIXSAT , llvm::ISD::FADD , llvm::ISD::FSUB ,
  llvm::ISD::FMUL , llvm::ISD::FDIV , llvm::ISD::FREM , llvm::ISD::STRICT_FADD ,
  llvm::ISD::STRICT_FSUB , llvm::ISD::STRICT_FMUL , llvm::ISD::STRICT_FDIV , llvm::ISD::STRICT_FREM ,
  llvm::ISD::STRICT_FMA , llvm::ISD::STRICT_FSQRT , llvm::ISD::STRICT_FPOW , llvm::ISD::STRICT_FPOWI ,
  llvm::ISD::STRICT_FLDEXP , llvm::ISD::STRICT_FSIN , llvm::ISD::STRICT_FCOS , llvm::ISD::STRICT_FTAN ,
  llvm::ISD::STRICT_FASIN , llvm::ISD::STRICT_FACOS , llvm::ISD::STRICT_FATAN , llvm::ISD::STRICT_FATAN2 ,
  llvm::ISD::STRICT_FSINH , llvm::ISD::STRICT_FCOSH , llvm::ISD::STRICT_FTANH , llvm::ISD::STRICT_FEXP ,
  llvm::ISD::STRICT_FEXP2 , llvm::ISD::STRICT_FLOG , llvm::ISD::STRICT_FLOG10 , llvm::ISD::STRICT_FLOG2 ,
  llvm::ISD::STRICT_FRINT , llvm::ISD::STRICT_FNEARBYINT , llvm::ISD::STRICT_FMAXNUM , llvm::ISD::STRICT_FMINNUM ,
  llvm::ISD::STRICT_FCEIL , llvm::ISD::STRICT_FFLOOR , llvm::ISD::STRICT_FROUND , llvm::ISD::STRICT_FROUNDEVEN ,
  llvm::ISD::STRICT_FTRUNC , llvm::ISD::STRICT_LROUND , llvm::ISD::STRICT_LLROUND , llvm::ISD::STRICT_LRINT ,
  llvm::ISD::STRICT_LLRINT , llvm::ISD::STRICT_FMAXIMUM , llvm::ISD::STRICT_FMINIMUM , llvm::ISD::STRICT_FP_TO_SINT ,
  llvm::ISD::STRICT_FP_TO_UINT , llvm::ISD::STRICT_SINT_TO_FP , llvm::ISD::STRICT_UINT_TO_FP , llvm::ISD::STRICT_FP_ROUND ,
  llvm::ISD::STRICT_FP_EXTEND , llvm::ISD::STRICT_FSETCC , llvm::ISD::STRICT_FSETCCS , llvm::ISD::FPTRUNC_ROUND ,
  llvm::ISD::FMA , llvm::ISD::FMAD , llvm::ISD::FCOPYSIGN , llvm::ISD::FGETSIGN ,
  llvm::ISD::FCANONICALIZE , llvm::ISD::IS_FPCLASS , llvm::ISD::BUILD_VECTOR , llvm::ISD::INSERT_VECTOR_ELT ,
  llvm::ISD::EXTRACT_VECTOR_ELT , llvm::ISD::CONCAT_VECTORS , llvm::ISD::INSERT_SUBVECTOR , llvm::ISD::EXTRACT_SUBVECTOR ,
  llvm::ISD::VECTOR_DEINTERLEAVE , llvm::ISD::VECTOR_INTERLEAVE , llvm::ISD::VECTOR_REVERSE , llvm::ISD::VECTOR_SHUFFLE ,
  llvm::ISD::VECTOR_SPLICE , llvm::ISD::SCALAR_TO_VECTOR , llvm::ISD::SPLAT_VECTOR , llvm::ISD::SPLAT_VECTOR_PARTS ,
  llvm::ISD::STEP_VECTOR , llvm::ISD::VECTOR_COMPRESS , llvm::ISD::MULHU , llvm::ISD::MULHS ,
  llvm::ISD::AVGFLOORS , llvm::ISD::AVGFLOORU , llvm::ISD::AVGCEILS , llvm::ISD::AVGCEILU ,
  llvm::ISD::ABDS , llvm::ISD::ABDU , llvm::ISD::SMIN , llvm::ISD::SMAX ,
  llvm::ISD::UMIN , llvm::ISD::UMAX , llvm::ISD::SCMP , llvm::ISD::UCMP ,
  llvm::ISD::AND , llvm::ISD::OR , llvm::ISD::XOR , llvm::ISD::ABS ,
  llvm::ISD::SHL , llvm::ISD::SRA , llvm::ISD::SRL , llvm::ISD::ROTL ,
  llvm::ISD::ROTR , llvm::ISD::FSHL , llvm::ISD::FSHR , llvm::ISD::BSWAP ,
  llvm::ISD::CTTZ , llvm::ISD::CTLZ , llvm::ISD::CTPOP , llvm::ISD::BITREVERSE ,
  llvm::ISD::PARITY , llvm::ISD::CTTZ_ZERO_UNDEF , llvm::ISD::CTLZ_ZERO_UNDEF , llvm::ISD::SELECT ,
  llvm::ISD::VSELECT , llvm::ISD::SELECT_CC , llvm::ISD::SETCC , llvm::ISD::SETCCCARRY ,
  llvm::ISD::SHL_PARTS , llvm::ISD::SRA_PARTS , llvm::ISD::SRL_PARTS , llvm::ISD::SIGN_EXTEND ,
  llvm::ISD::ZERO_EXTEND , llvm::ISD::ANY_EXTEND , llvm::ISD::TRUNCATE , llvm::ISD::TRUNCATE_SSAT_S ,
  llvm::ISD::TRUNCATE_SSAT_U , llvm::ISD::TRUNCATE_USAT_U , llvm::ISD::SINT_TO_FP , llvm::ISD::UINT_TO_FP ,
  llvm::ISD::SIGN_EXTEND_INREG , llvm::ISD::ANY_EXTEND_VECTOR_INREG , llvm::ISD::SIGN_EXTEND_VECTOR_INREG , llvm::ISD::ZERO_EXTEND_VECTOR_INREG ,
  llvm::ISD::FP_TO_SINT , llvm::ISD::FP_TO_UINT , llvm::ISD::FP_TO_SINT_SAT , llvm::ISD::FP_TO_UINT_SAT ,
  llvm::ISD::FP_ROUND , llvm::ISD::GET_ROUNDING , llvm::ISD::LOOP_DEPENDENCE_WAR_MASK , llvm::ISD::LOOP_DEPENDENCE_RAW_MASK ,
  llvm::ISD::CLEAR_CACHE , llvm::ISD::BUILTIN_OP_END
}
 ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG. More...
enum  llvm::ISD::MemIndexedMode {
  llvm::ISD::UNINDEXED = 0 , llvm::ISD::PRE_INC , llvm::ISD::PRE_DEC , llvm::ISD::POST_INC ,
  llvm::ISD::POST_DEC
}
 MemIndexedMode enum - This enum defines the load / store indexed addressing modes. More...
enum  llvm::ISD::MemIndexType { llvm::ISD::SIGNED_SCALED = 0 , llvm::ISD::UNSIGNED_SCALED }
 MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calculating addresses. More...
enum  llvm::ISD::LoadExtType { llvm::ISD::NON_EXTLOAD = 0 , llvm::ISD::EXTLOAD , llvm::ISD::SEXTLOAD , llvm::ISD::ZEXTLOAD }
 LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension). More...
enum  llvm::ISD::CondCode {
  llvm::ISD::SETFALSE , llvm::ISD::SETOEQ , llvm::ISD::SETOGT , llvm::ISD::SETOGE ,
  llvm::ISD::SETOLT , llvm::ISD::SETOLE , llvm::ISD::SETONE , llvm::ISD::SETO ,
  llvm::ISD::SETUO , llvm::ISD::SETUEQ , llvm::ISD::SETUGT , llvm::ISD::SETUGE ,
  llvm::ISD::SETULT , llvm::ISD::SETULE , llvm::ISD::SETUNE , llvm::ISD::SETTRUE ,
  llvm::ISD::SETFALSE2 , llvm::ISD::SETEQ , llvm::ISD::SETGT , llvm::ISD::SETGE ,
  llvm::ISD::SETLT , llvm::ISD::SETLE , llvm::ISD::SETNE , llvm::ISD::SETTRUE2 ,
  llvm::ISD::SETCC_INVALID
}
 ISD::CondCode enum - These are ordered carefully to make the bitfields below work out, when considering SETFALSE (something that never exists dynamically) as 0. More...

Functions

bool llvm::ISD::isBitwiseLogicOp (unsigned Opcode)
 Whether this is bitwise logic opcode.
LLVM_ABI NodeType llvm::ISD::getInverseMinMaxOpcode (unsigned MinMaxOpc)
 Given a MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns ISD::(U|S)MAX and ISD::(U|S)MIN, respectively.
LLVM_ABI NodeType llvm::ISD::getVecReduceBaseOpcode (unsigned VecReduceOpcode)
 Get underlying scalar opcode for VECREDUCE opcode.
LLVM_ABI bool llvm::ISD::isVPOpcode (unsigned Opcode)
 Whether this is a vector-predicated Opcode.
LLVM_ABI bool llvm::ISD::isVPBinaryOp (unsigned Opcode)
 Whether this is a vector-predicated binary operation opcode.
LLVM_ABI bool llvm::ISD::isVPReduction (unsigned Opcode)
 Whether this is a vector-predicated reduction opcode.
LLVM_ABI std::optional< unsigned > llvm::ISD::getVPMaskIdx (unsigned Opcode)
 The operand position of the vector mask.
LLVM_ABI std::optional< unsigned > llvm::ISD::getVPExplicitVectorLengthIdx (unsigned Opcode)
 The operand position of the explicit vector length parameter.
LLVM_ABI std::optional< unsigned > llvm::ISD::getBaseOpcodeForVP (unsigned Opcode, bool hasFPExcept)
 Translate this VP Opcode to its corresponding non-VP Opcode.
LLVM_ABI std::optional< unsigned > llvm::ISD::getVPForBaseOpcode (unsigned Opcode)
 Translate this non-VP Opcode to its corresponding VP Opcode.
bool llvm::ISD::isIndexTypeSigned (MemIndexType IndexType)
LLVM_ABI NodeType llvm::ISD::getExtForLoadExtType (bool IsFP, LoadExtType)
bool llvm::ISD::isSignedIntSetCC (CondCode Code)
 Return true if this is a setcc instruction that performs a signed comparison when used with integer operands.
bool llvm::ISD::isUnsignedIntSetCC (CondCode Code)
 Return true if this is a setcc instruction that performs an unsigned comparison when used with integer operands.
bool llvm::ISD::isIntEqualitySetCC (CondCode Code)
 Return true if this is a setcc instruction that performs an equality comparison when used with integer operands.
bool llvm::ISD::isFPEqualitySetCC (CondCode Code)
 Return true if this is a setcc instruction that performs an equality comparison when used with floating point operands.
bool llvm::ISD::isTrueWhenEqual (CondCode Cond)
 Return true if the specified condition returns true if the two operands to the condition are equal.
unsigned llvm::ISD::getUnorderedFlavor (CondCode Cond)
 This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if the condition is undefined if the operand is a NaN.
LLVM_ABI CondCode llvm::ISD::getSetCCInverse (CondCode Operation, EVT Type)
 Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
bool llvm::ISD::isExtOpcode (unsigned Opcode)
bool llvm::ISD::isExtVecInRegOpcode (unsigned Opcode)
LLVM_ABI CondCode llvm::ISD::GlobalISel::getSetCCInverse (CondCode Operation, bool isIntegerLike)
 Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
LLVM_ABI CondCode llvm::ISD::getSetCCSwappedOperands (CondCode Operation)
 Return the operation corresponding to (Y op X) when given the operation for (X op Y).
LLVM_ABI CondCode llvm::ISD::getSetCCOrOperation (CondCode Op1, CondCode Op2, EVT Type)
 Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X op2 Y)).
LLVM_ABI CondCode llvm::ISD::getSetCCAndOperation (CondCode Op1, CondCode Op2, EVT Type)
 Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X op2 Y)).

Variables

static const int llvm::ISD::LAST_INDEXED_MODE = POST_DEC + 1
static const int llvm::ISD::LAST_MEM_INDEX_TYPE = UNSIGNED_SCALED + 1
static const int llvm::ISD::LAST_LOADEXT_TYPE = ZEXTLOAD + 1

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

#define BEGIN_REGISTER_VP_SDNODE ( VPSDID,
... )
Value:
VPSDID,
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