LLVM  15.0.0git
ISDOpcodes.h
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1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares codegen opcodes and related utilities.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_ISDOPCODES_H
14 #define LLVM_CODEGEN_ISDOPCODES_H
15 
17 
18 namespace llvm {
19 
20 /// ISD namespace - This namespace contains an enum which represents all of the
21 /// SelectionDAG node types and value types.
22 ///
23 namespace ISD {
24 
25 //===--------------------------------------------------------------------===//
26 /// ISD::NodeType enum - This enum defines the target-independent operators
27 /// for a SelectionDAG.
28 ///
29 /// Targets may also define target-dependent operator codes for SDNodes. For
30 /// example, on x86, these are the enum values in the X86ISD namespace.
31 /// Targets should aim to use target-independent operators to model their
32 /// instruction sets as much as possible, and only use target-dependent
33 /// operators when they have special requirements.
34 ///
35 /// Finally, during and after selection proper, SNodes may use special
36 /// operator codes that correspond directly with MachineInstr opcodes. These
37 /// are used to represent selected instructions. See the isMachineOpcode()
38 /// and getMachineOpcode() member functions of SDNode.
39 ///
40 enum NodeType {
41 
42  /// DELETED_NODE - This is an illegal value that is used to catch
43  /// errors. This opcode is not a legal opcode for any node.
45 
46  /// EntryToken - This is the marker used to indicate the start of a region.
48 
49  /// TokenFactor - This node takes multiple tokens as input and produces a
50  /// single token result. This is used to represent the fact that the operand
51  /// operators are independent of each other.
53 
54  /// AssertSext, AssertZext - These nodes record if a register contains a
55  /// value that has already been zero or sign extended from a narrower type.
56  /// These nodes take two operands. The first is the node that has already
57  /// been extended, and the second is a value type node indicating the width
58  /// of the extension.
59  /// NOTE: In case of the source value (or any vector element value) is
60  /// poisoned the assertion will not be true for that value.
63 
64  /// AssertAlign - These nodes record if a register contains a value that
65  /// has a known alignment and the trailing bits are known to be zero.
66  /// NOTE: In case of the source value (or any vector element value) is
67  /// poisoned the assertion will not be true for that value.
69 
70  /// Various leaf nodes.
85 
86  /// The address of the GOT
88 
89  /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
90  /// llvm.returnaddress on the DAG. These nodes take one operand, the index
91  /// of the frame or return address to return. An index of zero corresponds
92  /// to the current function's frame or return address, an index of one to
93  /// the parent's frame or return address, and so on.
96 
97  /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
98  /// This node takes no operand, returns a target-specific pointer to the
99  /// place in the stack frame where the return address of the current
100  /// function is stored.
102 
103  /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument
104  /// and returns the stack pointer value at the entry of the current
105  /// function calling this intrinsic.
107 
108  /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
109  /// Materializes the offset from the local object pointer of another
110  /// function to a particular local object passed to llvm.localescape. The
111  /// operand is the MCSymbol label used to represent this offset, since
112  /// typically the offset is not known until after code generation of the
113  /// parent.
115 
116  /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
117  /// the DAG, which implements the named register global variables extension.
120 
121  /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
122  /// first (possible) on-stack argument. This is needed for correct stack
123  /// adjustment during unwind.
125 
126  /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
127  /// Frame Address (CFA), generally the value of the stack pointer at the
128  /// call site in the previous frame.
130 
131  /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
132  /// 'eh_return' gcc dwarf builtin, which is used to return from
133  /// exception. The general meaning is: adjust stack by OFFSET and pass
134  /// execution to HANDLER. Many platform-related details also :)
136 
137  /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
138  /// This corresponds to the eh.sjlj.setjmp intrinsic.
139  /// It takes an input chain and a pointer to the jump buffer as inputs
140  /// and returns an outchain.
142 
143  /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
144  /// This corresponds to the eh.sjlj.longjmp intrinsic.
145  /// It takes an input chain and a pointer to the jump buffer as inputs
146  /// and returns an outchain.
148 
149  /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
150  /// The target initializes the dispatch table here.
152 
153  /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
154  /// simplification, or lowering of the constant. They are used for constants
155  /// which are known to fit in the immediate fields of their users, or for
156  /// carrying magic numbers which are not values which need to be
157  /// materialized in registers.
160 
161  /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
162  /// anything else with this node, and this is valid in the target-specific
163  /// dag, turning into a GlobalAddress operand.
171 
173 
174  /// TargetIndex - Like a constant pool entry, but with completely
175  /// target-dependent semantics. Holds target flags, a 32-bit index, and a
176  /// 64-bit index. Targets can use this however they like.
178 
179  /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
180  /// This node represents a target intrinsic function with no side effects.
181  /// The first operand is the ID number of the intrinsic from the
182  /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
183  /// node returns the result of the intrinsic.
185 
186  /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
187  /// This node represents a target intrinsic function with side effects that
188  /// returns a result. The first operand is a chain pointer. The second is
189  /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
190  /// operands to the intrinsic follow. The node has two results, the result
191  /// of the intrinsic and an output chain.
193 
194  /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
195  /// This node represents a target intrinsic function with side effects that
196  /// does not return a result. The first operand is a chain pointer. The
197  /// second is the ID number of the intrinsic from the llvm::Intrinsic
198  /// namespace. The operands to the intrinsic follow.
200 
201  /// CopyToReg - This node has three operands: a chain, a register number to
202  /// set to this value, and a value.
204 
205  /// CopyFromReg - This node indicates that the input value is a virtual or
206  /// physical register that is defined outside of the scope of this
207  /// SelectionDAG. The register is available from the RegisterSDNode object.
209 
210  /// UNDEF - An undefined node.
212 
213  // FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
214  // is evaluated to UNDEF), or returns VAL otherwise. Note that each
215  // read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.
217 
218  /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
219  /// a Constant, which is required to be operand #1) half of the integer or
220  /// float value specified as operand #0. This is only for use before
221  /// legalization, for values that will be broken into multiple registers.
223 
224  /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
225  /// Given two values of the same integer value type, this produces a value
226  /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
227  /// legalization. The lower part of the composite value should be in
228  /// element 0 and the upper part should be in element 1.
230 
231  /// MERGE_VALUES - This node takes multiple discrete operands and returns
232  /// them all as its individual results. This nodes has exactly the same
233  /// number of inputs and outputs. This node is useful for some pieces of the
234  /// code generator that want to think about a single node with multiple
235  /// results, not multiple nodes.
237 
238  /// Simple integer binary arithmetic operators.
246 
247  /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
248  /// a signed/unsigned value of type i[2*N], and return the full value as
249  /// two results, each of type iN.
252 
253  /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
254  /// remainder result.
257 
258  /// CARRY_FALSE - This node is used when folding other nodes,
259  /// like ADDC/SUBC, which indicate the carry result is always false.
261 
262  /// Carry-setting nodes for multiple precision addition and subtraction.
263  /// These nodes take two operands of the same value type, and produce two
264  /// results. The first result is the normal add or sub result, the second
265  /// result is the carry flag result.
266  /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
267  /// They are kept around for now to provide a smooth transition path
268  /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
271 
272  /// Carry-using nodes for multiple precision addition and subtraction. These
273  /// nodes take three operands: The first two are the normal lhs and rhs to
274  /// the add or sub, and the third is the input carry flag. These nodes
275  /// produce two results; the normal result of the add or sub, and the output
276  /// carry flag. These nodes both read and write a carry flag to allow them
277  /// to them to be chained together for add and sub of arbitrarily large
278  /// values.
281 
282  /// Carry-using nodes for multiple precision addition and subtraction.
283  /// These nodes take three operands: The first two are the normal lhs and
284  /// rhs to the add or sub, and the third is a boolean value that is 1 if and
285  /// only if there is an incoming carry/borrow. These nodes produce two
286  /// results: the normal result of the add or sub, and a boolean value that is
287  /// 1 if and only if there is an outgoing carry/borrow.
288  ///
289  /// Care must be taken if these opcodes are lowered to hardware instructions
290  /// that use the inverse logic -- 0 if and only if there is an
291  /// incoming/outgoing carry/borrow. In such cases, you must preserve the
292  /// semantics of these opcodes by inverting the incoming carry/borrow, feeding
293  /// it to the add/sub hardware instruction, and then inverting the outgoing
294  /// carry/borrow.
295  ///
296  /// The use of these opcodes is preferable to adde/sube if the target supports
297  /// it, as the carry is a regular value rather than a glue, which allows
298  /// further optimisation.
299  ///
300  /// These opcodes are different from [US]{ADD,SUB}O in that ADDCARRY/SUBCARRY
301  /// consume and produce a carry/borrow, whereas [US]{ADD,SUB}O produce an
302  /// overflow.
305 
306  /// Carry-using overflow-aware nodes for multiple precision addition and
307  /// subtraction. These nodes take three operands: The first two are normal lhs
308  /// and rhs to the add or sub, and the third is a boolean indicating if there
309  /// is an incoming carry. They produce two results: the normal result of the
310  /// add or sub, and a boolean that indicates if an overflow occurred (*not*
311  /// flag, because it may be a store to memory, etc.). If the type of the
312  /// boolean is not i1 then the high bits conform to getBooleanContents.
315 
316  /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
317  /// These nodes take two operands: the normal LHS and RHS to the add. They
318  /// produce two results: the normal result of the add, and a boolean that
319  /// indicates if an overflow occurred (*not* a flag, because it may be store
320  /// to memory, etc.). If the type of the boolean is not i1 then the high
321  /// bits conform to getBooleanContents.
322  /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
325 
326  /// Same for subtraction.
329 
330  /// Same for multiplication.
333 
334  /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
335  /// integers with the same bit width (W). If the true value of LHS + RHS
336  /// exceeds the largest value that can be represented by W bits, the
337  /// resulting value is this maximum value. Otherwise, if this value is less
338  /// than the smallest value that can be represented by W bits, the
339  /// resulting value is this minimum value.
342 
343  /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
344  /// integers with the same bit width (W). If the true value of LHS - RHS
345  /// exceeds the largest value that can be represented by W bits, the
346  /// resulting value is this maximum value. Otherwise, if this value is less
347  /// than the smallest value that can be represented by W bits, the
348  /// resulting value is this minimum value.
351 
352  /// RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift. The first
353  /// operand is the value to be shifted, and the second argument is the amount
354  /// to shift by. Both must be integers of the same bit width (W). If the true
355  /// value of LHS << RHS exceeds the largest value that can be represented by
356  /// W bits, the resulting value is this maximum value, Otherwise, if this
357  /// value is less than the smallest value that can be represented by W bits,
358  /// the resulting value is this minimum value.
361 
362  /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication
363  /// on 2 integers with the same width and scale. SCALE represents the scale
364  /// of both operands as fixed point numbers. This SCALE parameter must be a
365  /// constant integer. A scale of zero is effectively performing
366  /// multiplication on 2 integers.
369 
370  /// Same as the corresponding unsaturated fixed point instructions, but the
371  /// result is clamped between the min and max values representable by the
372  /// bits of the first 2 operands.
375 
376  /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on
377  /// 2 integers with the same width and scale. SCALE represents the scale
378  /// of both operands as fixed point numbers. This SCALE parameter must be a
379  /// constant integer.
382 
383  /// Same as the corresponding unsaturated fixed point instructions, but the
384  /// result is clamped between the min and max values representable by the
385  /// bits of the first 2 operands.
388 
389  /// Simple binary floating point operators.
395 
396  /// Constrained versions of the binary floating point operators.
397  /// These will be lowered to the simple operators before final selection.
398  /// They are used to limit optimizations while the DAG is being
399  /// optimized.
406 
407  /// Constrained versions of libm-equivalent floating point intrinsics.
408  /// These will be lowered to the equivalent non-constrained pseudo-op
409  /// (or expanded to the equivalent library call) before final selection.
410  /// They are used to limit optimizations while the DAG is being optimized.
436 
437  /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or
438  /// unsigned integer. These have the same semantics as fptosi and fptoui
439  /// in IR.
440  /// They are used to limit optimizations while the DAG is being optimized.
443 
444  /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to
445  /// a floating point value. These have the same semantics as sitofp and
446  /// uitofp in IR.
447  /// They are used to limit optimizations while the DAG is being optimized.
450 
451  /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
452  /// point type down to the precision of the destination VT. TRUNC is a
453  /// flag, which is always an integer that is zero or one. If TRUNC is 0,
454  /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
455  /// change the value of Y.
456  ///
457  /// The TRUNC = 1 case is used in cases where we know that the value will
458  /// not be modified by the node, because Y is not using any of the extra
459  /// precision of source type. This allows certain transformations like
460  /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for
461  /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't
462  /// removed.
463  /// It is used to limit optimizations while the DAG is being optimized.
465 
466  /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP
467  /// type.
468  /// It is used to limit optimizations while the DAG is being optimized.
470 
471  /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used
472  /// for floating-point operands only. STRICT_FSETCC performs a quiet
473  /// comparison operation, while STRICT_FSETCCS performs a signaling
474  /// comparison operation.
477 
478  // FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.
480 
481  /// FMA - Perform a * b + c with no intermediate rounding step.
483 
484  /// FMAD - Perform a * b + c, while getting the same result as the
485  /// separately rounded operations.
487 
488  /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
489  /// DAG node does not require that X and Y have the same type, just that
490  /// they are both floating point. X and the result must have the same type.
491  /// FCOPYSIGN(f32, f64) is allowed.
493 
494  /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
495  /// value as an integer 0/1 value.
497 
498  /// Returns platform specific canonical encoding of a floating point number.
500 
501  /// Performs a check of floating point class property, defined by IEEE-754.
502  /// The first operand is the floating point value to check. The second operand
503  /// specifies the checked property and is a TargetConstant which specifies
504  /// test in the same way as intrinsic 'is_fpclass'.
505  /// Returns boolean value.
507 
508  /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
509  /// with the specified, possibly variable, elements. The types of the
510  /// operands must match the vector element type, except that integer types
511  /// are allowed to be larger than the element type, in which case the
512  /// operands are implicitly truncated. The types of the operands must all
513  /// be the same.
515 
516  /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
517  /// at IDX replaced with VAL. If the type of VAL is larger than the vector
518  /// element type then VAL is truncated before replacement.
519  ///
520  /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
521  /// vector width. IDX is not first scaled by the runtime scaling factor of
522  /// VECTOR.
524 
525  /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
526  /// identified by the (potentially variable) element number IDX. If the return
527  /// type is an integer type larger than the element type of the vector, the
528  /// result is extended to the width of the return type. In that case, the high
529  /// bits are undefined.
530  ///
531  /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
532  /// vector width. IDX is not first scaled by the runtime scaling factor of
533  /// VECTOR.
535 
536  /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
537  /// vector type with the same length and element type, this produces a
538  /// concatenated vector result value, with length equal to the sum of the
539  /// lengths of the input vectors. If VECTOR0 is a fixed-width vector, then
540  /// VECTOR1..VECTORN must all be fixed-width vectors. Similarly, if VECTOR0
541  /// is a scalable vector, then VECTOR1..VECTORN must all be scalable vectors.
543 
544  /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2
545  /// inserted into VECTOR1. IDX represents the starting element number at which
546  /// VECTOR2 will be inserted. IDX must be a constant multiple of T's known
547  /// minimum vector length. Let the type of VECTOR2 be T, then if T is a
548  /// scalable vector, IDX is first scaled by the runtime scaling factor of T.
549  /// The elements of VECTOR1 starting at IDX are overwritten with VECTOR2.
550  /// Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR1
551  /// indices. If this condition cannot be determined statically but is false at
552  /// runtime, then the result vector is undefined. The IDX parameter must be a
553  /// vector index constant type, which for most targets will be an integer
554  /// pointer type.
555  ///
556  /// This operation supports inserting a fixed-width vector into a scalable
557  /// vector, but not the other way around.
559 
560  /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
561  /// Let the result type be T, then IDX represents the starting element number
562  /// from which a subvector of type T is extracted. IDX must be a constant
563  /// multiple of T's known minimum vector length. If T is a scalable vector,
564  /// IDX is first scaled by the runtime scaling factor of T. Elements IDX
565  /// through (IDX + num_elements(T) - 1) must be valid VECTOR indices. If this
566  /// condition cannot be determined statically but is false at runtime, then
567  /// the result vector is undefined. The IDX parameter must be a vector index
568  /// constant type, which for most targets will be an integer pointer type.
569  ///
570  /// This operation supports extracting a fixed-width vector from a scalable
571  /// vector, but not the other way around.
573 
574  /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
575  /// whose elements are shuffled using the following algorithm:
576  /// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
578 
579  /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
580  /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
581  /// values that indicate which value (or undef) each result element will
582  /// get. These constant ints are accessible through the
583  /// ShuffleVectorSDNode class. This is quite similar to the Altivec
584  /// 'vperm' instruction, except that the indices must be constants and are
585  /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
587 
588  /// VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as
589  /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways.
590  /// Let the result type be T, if IMM is positive it represents the starting
591  /// element number (an index) from which a subvector of type T is extracted
592  /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count
593  /// specifying the number of trailing elements to extract from VEC1, where the
594  /// elements of T are selected using the following algorithm:
595  /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i]
596  /// If IMM is not in the range [-VL, VL-1] the result vector is undefined. IMM
597  /// is a constant integer.
599 
600  /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
601  /// scalar value into element 0 of the resultant vector type. The top
602  /// elements 1 to N-1 of the N-element vector are undefined. The type
603  /// of the operand must match the vector element type, except when they
604  /// are integer types. In this case the operand is allowed to be wider
605  /// than the vector element type, and is implicitly truncated to it.
607 
608  /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL
609  /// duplicated in all lanes. The type of the operand must match the vector
610  /// element type, except when they are integer types. In this case the
611  /// operand is allowed to be wider than the vector element type, and is
612  /// implicitly truncated to it.
614 
615  /// SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the
616  /// scalar values joined together and then duplicated in all lanes. This
617  /// represents a SPLAT_VECTOR that has had its scalar operand expanded. This
618  /// allows representing a 64-bit splat on a target with 32-bit integers. The
619  /// total width of the scalars must cover the element width. SCALAR1 contains
620  /// the least significant bits of the value regardless of endianness and all
621  /// scalars should have the same type.
623 
624  /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
625  /// of a linear sequence of unsigned values starting from 0 with a step of
626  /// IMM, where IMM must be a TargetConstant with type equal to the vector
627  /// element type. The arithmetic is performed modulo the bitwidth of the
628  /// element.
629  ///
630  /// The operation does not support returning fixed-width vectors or
631  /// non-constant operands.
633 
634  /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
635  /// producing an unsigned/signed value of type i[2*N], then return the top
636  /// part.
639 
640  /// AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of
641  /// type i[N+1], halving the result by shifting it one bit right.
642  /// shr(add(ext(X), ext(Y)), 1)
645  /// AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an
646  /// integer of type i[N+2], add 1 and halve the result by shifting it one bit
647  /// right. shr(add(ext(X), ext(Y), 1), 1)
650 
651  // ABDS/ABDU - Absolute difference - Return the absolute difference between
652  // two numbers interpreted as signed/unsigned.
653  // i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1)
654  // or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1)
657 
658  /// [US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned
659  /// integers.
664 
665  /// Bitwise operators - logical and, logical or, logical xor.
667  OR,
669 
670  /// ABS - Determine the unsigned absolute value of a signed integer value of
671  /// the same bitwidth.
672  /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
673  /// is performed.
675 
676  /// Shift and rotation operations. After legalization, the type of the
677  /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
678  /// the shift amount can be any type, but care must be taken to ensure it is
679  /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
680  /// legalization, types like i1024 can occur and i8 doesn't have enough bits
681  /// to represent the shift amount.
682  /// When the 1st operand is a vector, the shift amount must be in the same
683  /// type. (TLI.getShiftAmountTy() will return the same type when the input
684  /// type is a vector.)
685  /// For rotates and funnel shifts, the shift amount is treated as an unsigned
686  /// amount modulo the element size of the first operand.
687  ///
688  /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
689  /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
690  /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
698 
699  /// Byte Swap and Counting operators.
706 
707  /// Bit counting operators with an undefined result for zero inputs.
710 
711  /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
712  /// i1 then the high bits must conform to getBooleanContents.
714 
715  /// Select with a vector condition (op #0) and two vector operands (ops #1
716  /// and #2), returning a vector result. All vectors have the same length.
717  /// Much like the scalar select and setcc, each bit in the condition selects
718  /// whether the corresponding result element is taken from op #1 or op #2.
719  /// At first, the VSELECT condition is of vXi1 type. Later, targets may
720  /// change the condition type in order to match the VSELECT node using a
721  /// pattern. The condition follows the BooleanContent format of the target.
723 
724  /// Select with condition operator - This selects between a true value and
725  /// a false value (ops #2 and #3) based on the boolean result of comparing
726  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
727  /// condition code in op #4, a CondCodeSDNode.
729 
730  /// SetCC operator - This evaluates to a true value iff the condition is
731  /// true. If the result value type is not i1 then the high bits conform
732  /// to getBooleanContents. The operands to this are the left and right
733  /// operands to compare (ops #0, and #1) and the condition code to compare
734  /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
735  /// then the result type must also be a vector type.
737 
738  /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
739  /// op #2 is a boolean indicating if there is an incoming carry. This
740  /// operator checks the result of "LHS - RHS - Carry", and can be used to
741  /// compare two wide integers:
742  /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
743  /// Only valid for integers.
745 
746  /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
747  /// integer shift operations. The operation ordering is:
748  /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
752 
753  /// Conversion operators. These are all single input single output
754  /// operations. For all of these, the result type must be strictly
755  /// wider or narrower (depending on the operation) than the source
756  /// type.
757 
758  /// SIGN_EXTEND - Used for integer types, replicating the sign bit
759  /// into new bits.
761 
762  /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
764 
765  /// ANY_EXTEND - Used for integer types. The high bits are undefined.
767 
768  /// TRUNCATE - Completely drop the high bits.
770 
771  /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
772  /// depends on the first letter) to floating point.
775 
776  /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
777  /// sign extend a small value in a large integer register (e.g. sign
778  /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
779  /// with the 7th bit). The size of the smaller type is indicated by the 1th
780  /// operand, a ValueType node.
782 
783  /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
784  /// in-register any-extension of the low lanes of an integer vector. The
785  /// result type must have fewer elements than the operand type, and those
786  /// elements must be larger integer types such that the total size of the
787  /// operand type is less than or equal to the size of the result type. Each
788  /// of the low operand elements is any-extended into the corresponding,
789  /// wider result elements with the high bits becoming undef.
790  /// NOTE: The type legalizer prefers to make the operand and result size
791  /// the same to allow expansion to shuffle vector during op legalization.
793 
794  /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
795  /// in-register sign-extension of the low lanes of an integer vector. The
796  /// result type must have fewer elements than the operand type, and those
797  /// elements must be larger integer types such that the total size of the
798  /// operand type is less than or equal to the size of the result type. Each
799  /// of the low operand elements is sign-extended into the corresponding,
800  /// wider result elements.
801  /// NOTE: The type legalizer prefers to make the operand and result size
802  /// the same to allow expansion to shuffle vector during op legalization.
804 
805  /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
806  /// in-register zero-extension of the low lanes of an integer vector. The
807  /// result type must have fewer elements than the operand type, and those
808  /// elements must be larger integer types such that the total size of the
809  /// operand type is less than or equal to the size of the result type. Each
810  /// of the low operand elements is zero-extended into the corresponding,
811  /// wider result elements.
812  /// NOTE: The type legalizer prefers to make the operand and result size
813  /// the same to allow expansion to shuffle vector during op legalization.
815 
816  /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
817  /// integer. These have the same semantics as fptosi and fptoui in IR. If
818  /// the FP value cannot fit in the integer type, the results are undefined.
821 
822  /// FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a
823  /// signed or unsigned scalar integer type given in operand 1 with the
824  /// following semantics:
825  ///
826  /// * If the value is NaN, zero is returned.
827  /// * If the value is larger/smaller than the largest/smallest integer,
828  /// the largest/smallest integer is returned (saturation).
829  /// * Otherwise the result of rounding the value towards zero is returned.
830  ///
831  /// The scalar width of the type given in operand 1 must be equal to, or
832  /// smaller than, the scalar result type width. It may end up being smaller
833  /// than the result width as a result of integer type legalization.
834  ///
835  /// After converting to the scalar integer type in operand 1, the value is
836  /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT
837  /// zero extends.
840 
841  /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
842  /// down to the precision of the destination VT. TRUNC is a flag, which is
843  /// always an integer that is zero or one. If TRUNC is 0, this is a
844  /// normal rounding, if it is 1, this FP_ROUND is known to not change the
845  /// value of Y.
846  ///
847  /// The TRUNC = 1 case is used in cases where we know that the value will
848  /// not be modified by the node, because Y is not using any of the extra
849  /// precision of source type. This allows certain transformations like
850  /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
851  /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
853 
854  /// Returns current rounding mode:
855  /// -1 Undefined
856  /// 0 Round to 0
857  /// 1 Round to nearest, ties to even
858  /// 2 Round to +inf
859  /// 3 Round to -inf
860  /// 4 Round to nearest, ties to zero
861  /// Result is rounding mode and chain. Input is a chain.
862  /// TODO: Rename this node to GET_ROUNDING.
864 
865  /// Set rounding mode.
866  /// The first operand is a chain pointer. The second specifies the required
867  /// rounding mode, encoded in the same way as used in '``FLT_ROUNDS_``'.
869 
870  /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
872 
873  /// BITCAST - This operator converts between integer, vector and FP
874  /// values, as if the value was stored to memory with one type and loaded
875  /// from the same address with the other type (or equivalently for vector
876  /// format conversions, etc). The source and result are required to have
877  /// the same bit size (e.g. f32 <-> i32). This can also be used for
878  /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
879  /// getNode().
880  ///
881  /// This operator is subtly different from the bitcast instruction from
882  /// LLVM-IR since this node may change the bits in the register. For
883  /// example, this occurs on big-endian NEON and big-endian MSA where the
884  /// layout of the bits in the register depends on the vector type and this
885  /// operator acts as a shuffle operation for some vector type combinations.
887 
888  /// ADDRSPACECAST - This operator converts between pointers of different
889  /// address spaces.
891 
892  /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
893  /// and truncation for half-precision (16 bit) floating numbers. These nodes
894  /// form a semi-softened interface for dealing with f16 (as an i16), which
895  /// is often a storage-only type but has native conversions.
900 
901  /// BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions
902  /// and truncation for bfloat16. These nodes form a semi-softened interface
903  /// for dealing with bf16 (as an i16), which is often a storage-only type but
904  /// has native conversions.
907 
908  /// Perform various unary floating-point operations inspired by libm. For
909  /// FPOWI, the result is undefined if if the integer operand doesn't fit into
910  /// sizeof(int).
935 
936  /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
937  /// values.
938  //
939  /// In the case where a single input is a NaN (either signaling or quiet),
940  /// the non-NaN input is returned.
941  ///
942  /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
945 
946  /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
947  /// two values, following the IEEE-754 2008 definition. This differs from
948  /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
949  /// signaling NaN, returns a quiet NaN.
952 
953  /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
954  /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
955  /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
958 
959  /// FSINCOS - Compute both fsin and fcos as a single operation.
961 
962  /// LOAD and STORE have token chains as their first operand, then the same
963  /// operands as an LLVM load/store instruction, then an offset node that
964  /// is added / subtracted from the base pointer to form the address (for
965  /// indexed memory ops).
968 
969  /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
970  /// to a specified boundary. This node always has two return values: a new
971  /// stack pointer value and a chain. The first operand is the token chain,
972  /// the second is the number of bytes to allocate, and the third is the
973  /// alignment boundary. The size is guaranteed to be a multiple of the
974  /// stack alignment, and the alignment is guaranteed to be bigger than the
975  /// stack alignment (if required) or 0 to get standard stack alignment.
977 
978  /// Control flow instructions. These all have token chains.
979 
980  /// BR - Unconditional branch. The first operand is the chain
981  /// operand, the second is the MBB to branch to.
982  BR,
983 
984  /// BRIND - Indirect branch. The first operand is the chain, the second
985  /// is the value to branch to, which must be of the same type as the
986  /// target's pointer type.
988 
989  /// BR_JT - Jumptable branch. The first operand is the chain, the second
990  /// is the jumptable index, the last one is the jumptable entry index.
992 
993  /// BRCOND - Conditional branch. The first operand is the chain, the
994  /// second is the condition, the third is the block to branch to if the
995  /// condition is true. If the type of the condition is not i1, then the
996  /// high bits must conform to getBooleanContents. If the condition is undef,
997  /// it nondeterministically jumps to the block.
998  /// TODO: Its semantics w.r.t undef requires further discussion; we need to
999  /// make it sure that it is consistent with optimizations in MIR & the
1000  /// meaning of IMPLICIT_DEF. See https://reviews.llvm.org/D92015
1002 
1003  /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
1004  /// that the condition is represented as condition code, and two nodes to
1005  /// compare, rather than as a combined SetCC node. The operands in order
1006  /// are chain, cc, lhs, rhs, block to branch to if condition is true. If
1007  /// condition is undef, it nondeterministically jumps to the block.
1009 
1010  /// INLINEASM - Represents an inline asm block. This node always has two
1011  /// return values: a chain and a flag result. The inputs are as follows:
1012  /// Operand #0 : Input chain.
1013  /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
1014  /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
1015  /// Operand #3 : HasSideEffect, IsAlignStack bits.
1016  /// After this, it is followed by a list of operands with this format:
1017  /// ConstantSDNode: Flags that encode whether it is a mem or not, the
1018  /// of operands that follow, etc. See InlineAsm.h.
1019  /// ... however many operands ...
1020  /// Operand #last: Optional, an incoming flag.
1021  ///
1022  /// The variable width operands are required to represent target addressing
1023  /// modes as a single "operand", even though they may have multiple
1024  /// SDOperands.
1026 
1027  /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
1029 
1030  /// EH_LABEL - Represents a label in mid basic block used to track
1031  /// locations needed for debug and exception handling tables. These nodes
1032  /// take a chain as input and return a chain.
1034 
1035  /// ANNOTATION_LABEL - Represents a mid basic block label used by
1036  /// annotations. This should remain within the basic block and be ordered
1037  /// with respect to other call instructions, but loads and stores may float
1038  /// past it.
1040 
1041  /// CATCHRET - Represents a return from a catch block funclet. Used for
1042  /// MSVC compatible exception handling. Takes a chain operand and a
1043  /// destination basic block operand.
1045 
1046  /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
1047  /// MSVC compatible exception handling. Takes only a chain operand.
1049 
1050  /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
1051  /// value, the same type as the pointer type for the system, and an output
1052  /// chain.
1054 
1055  /// STACKRESTORE has two operands, an input chain and a pointer to restore
1056  /// to it returns an output chain.
1058 
1059  /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
1060  /// of a call sequence, and carry arbitrary information that target might
1061  /// want to know. The first operand is a chain, the rest are specified by
1062  /// the target and not touched by the DAG optimizers.
1063  /// Targets that may use stack to pass call arguments define additional
1064  /// operands:
1065  /// - size of the call frame part that must be set up within the
1066  /// CALLSEQ_START..CALLSEQ_END pair,
1067  /// - part of the call frame prepared prior to CALLSEQ_START.
1068  /// Both these parameters must be constants, their sum is the total call
1069  /// frame size.
1070  /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
1071  CALLSEQ_START, // Beginning of a call sequence
1072  CALLSEQ_END, // End of a call sequence
1073 
1074  /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
1075  /// and the alignment. It returns a pair of values: the vaarg value and a
1076  /// new chain.
1078 
1079  /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
1080  /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
1081  /// source.
1083 
1084  /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
1085  /// pointer, and a SRCVALUE.
1088 
1089  // PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE
1090  // with the preallocated call Value.
1092  // PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE
1093  // with the preallocated call Value, and a constant int.
1095 
1096  /// SRCVALUE - This is a node type that holds a Value* that is used to
1097  /// make reference to a value in the LLVM IR.
1099 
1100  /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
1101  /// reference metadata in the IR.
1103 
1104  /// PCMARKER - This corresponds to the pcmarker intrinsic.
1106 
1107  /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
1108  /// It produces a chain and one i64 value. The only operand is a chain.
1109  /// If i64 is not legal, the result will be expanded into smaller values.
1110  /// Still, it returns an i64, so targets should set legality for i64.
1111  /// The result is the content of the architecture-specific cycle
1112  /// counter-like register (or other high accuracy low latency clock source).
1114 
1115  /// HANDLENODE node - Used as a handle for various purposes.
1117 
1118  /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
1119  /// takes as input a token chain, the pointer to the trampoline, the pointer
1120  /// to the nested function, the pointer to pass for the 'nest' parameter, a
1121  /// SRCVALUE for the trampoline and another for the nested function
1122  /// (allowing targets to access the original Function*).
1123  /// It produces a token chain as output.
1125 
1126  /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
1127  /// It takes a pointer to the trampoline and produces a (possibly) new
1128  /// pointer to the same trampoline with platform-specific adjustments
1129  /// applied. The pointer it returns points to an executable block of code.
1131 
1132  /// TRAP - Trapping instruction
1134 
1135  /// DEBUGTRAP - Trap intended to get the attention of a debugger.
1137 
1138  /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer
1139  /// failure.
1141 
1142  /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
1143  /// is the chain. The other operands are the address to prefetch,
1144  /// read / write specifier, locality specifier and instruction / data cache
1145  /// specifier.
1147 
1148  /// ARITH_FENCE - This corresponds to a arithmetic fence intrinsic. Both its
1149  /// operand and output are the same floating type.
1151 
1152  /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
1153  /// This corresponds to the fence instruction. It takes an input chain, and
1154  /// two integer constants: an AtomicOrdering and a SynchronizationScope.
1156 
1157  /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
1158  /// This corresponds to "load atomic" instruction.
1160 
1161  /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
1162  /// This corresponds to "store atomic" instruction.
1164 
1165  /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
1166  /// For double-word atomic operations:
1167  /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
1168  /// swapLo, swapHi)
1169  /// This corresponds to the cmpxchg instruction.
1171 
1172  /// Val, Success, OUTCHAIN
1173  /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
1174  /// N.b. this is still a strong cmpxchg operation, so
1175  /// Success == "Val == cmp".
1177 
1178  /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
1179  /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
1180  /// For double-word atomic operations:
1181  /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
1182  /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
1183  /// These correspond to the atomicrmw instruction.
1198 
1199  // Masked load and store - consecutive vector load and store operations
1200  // with additional mask operand that prevents memory accesses to the
1201  // masked-off lanes.
1202  //
1203  // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
1204  // OutChain = MSTORE(Value, BasePtr, Mask)
1207 
1208  // Masked gather and scatter - load and store operations for a vector of
1209  // random addresses with additional mask operand that prevents memory
1210  // accesses to the masked-off lanes.
1211  //
1212  // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
1213  // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
1214  //
1215  // The Index operand can have more vector elements than the other operands
1216  // due to type legalization. The extra elements are ignored.
1219 
1220  /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
1221  /// is the chain and the second operand is the alloca pointer.
1224 
1225  /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
1226  /// beginning and end of GC transition sequence, and carry arbitrary
1227  /// information that target might need for lowering. The first operand is
1228  /// a chain, the rest are specified by the target and not touched by the DAG
1229  /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
1230  /// nested.
1233 
1234  /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
1235  /// the most recent dynamic alloca. For most targets that would be 0, but
1236  /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
1237  /// known nonzero constant. The only operand here is the chain.
1239 
1240  /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve
1241  /// the sample counts quality.
1243 
1244  /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the
1245  /// number of elements within a scalable vector. IMM is a constant integer
1246  /// multiplier that is applied to the runtime value.
1248 
1249  /// Generic reduction nodes. These nodes represent horizontal vector
1250  /// reduction operations, producing a scalar result.
1251  /// The SEQ variants perform reductions in sequential order. The first
1252  /// operand is an initial scalar accumulator value, and the second operand
1253  /// is the vector to reduce.
1254  /// E.g. RES = VECREDUCE_SEQ_FADD f32 ACC, <4 x f32> SRC_VEC
1255  /// ... is equivalent to
1256  /// RES = (((ACC + SRC_VEC[0]) + SRC_VEC[1]) + SRC_VEC[2]) + SRC_VEC[3]
1259 
1260  /// These reductions have relaxed evaluation order semantics, and have a
1261  /// single vector operand. The order of evaluation is unspecified. For
1262  /// pow-of-2 vectors, one valid legalizer expansion is to use a tree
1263  /// reduction, i.e.:
1264  /// For RES = VECREDUCE_FADD <8 x f16> SRC_VEC
1265  /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7]
1266  /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3]
1267  /// RES = FADD PART_RDX2[0], PART_RDX2[1]
1268  /// For non-pow-2 vectors, this can be computed by extracting each element
1269  /// and performing the operation as if it were scalarized.
1272  /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
1275  /// Integer reductions may have a result type larger than the vector element
1276  /// type. However, the reduction is performed using the vector element type
1277  /// and the value in the top bits is unspecified.
1287 
1288 // Vector Predication
1289 #define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...) VPSDID,
1290 #include "llvm/IR/VPIntrinsics.def"
1291 
1292  /// BUILTIN_OP_END - This must be the last enum value in this list.
1293  /// The target-specific pre-isel opcode values start here.
1295 };
1296 
1297 /// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
1298 /// which cannot raise FP exceptions should be less than this value.
1299 /// Those that do must not be less than this value.
1301 
1302 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
1303 /// which do not reference a specific memory location should be less than
1304 /// this value. Those that do must not be less than this value, and can
1305 /// be used with SelectionDAG::getMemIntrinsicNode.
1307 
1308 /// Whether this is bitwise logic opcode.
1309 inline bool isBitwiseLogicOp(unsigned Opcode) {
1310  return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
1311 }
1312 
1313 /// Get underlying scalar opcode for VECREDUCE opcode.
1314 /// For example ISD::AND for ISD::VECREDUCE_AND.
1315 NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);
1316 
1317 /// Whether this is a vector-predicated Opcode.
1318 bool isVPOpcode(unsigned Opcode);
1319 
1320 /// Whether this is a vector-predicated binary operation opcode.
1321 bool isVPBinaryOp(unsigned Opcode);
1322 
1323 /// Whether this is a vector-predicated reduction opcode.
1324 bool isVPReduction(unsigned Opcode);
1325 
1326 /// The operand position of the vector mask.
1327 Optional<unsigned> getVPMaskIdx(unsigned Opcode);
1328 
1329 /// The operand position of the explicit vector length parameter.
1331 
1332 //===--------------------------------------------------------------------===//
1333 /// MemIndexedMode enum - This enum defines the load / store indexed
1334 /// addressing modes.
1335 ///
1336 /// UNINDEXED "Normal" load / store. The effective address is already
1337 /// computed and is available in the base pointer. The offset
1338 /// operand is always undefined. In addition to producing a
1339 /// chain, an unindexed load produces one value (result of the
1340 /// load); an unindexed store does not produce a value.
1341 ///
1342 /// PRE_INC Similar to the unindexed mode where the effective address is
1343 /// PRE_DEC the value of the base pointer add / subtract the offset.
1344 /// It considers the computation as being folded into the load /
1345 /// store operation (i.e. the load / store does the address
1346 /// computation as well as performing the memory transaction).
1347 /// The base operand is always undefined. In addition to
1348 /// producing a chain, pre-indexed load produces two values
1349 /// (result of the load and the result of the address
1350 /// computation); a pre-indexed store produces one value (result
1351 /// of the address computation).
1352 ///
1353 /// POST_INC The effective address is the value of the base pointer. The
1354 /// POST_DEC value of the offset operand is then added to / subtracted
1355 /// from the base after memory transaction. In addition to
1356 /// producing a chain, post-indexed load produces two values
1357 /// (the result of the load and the result of the base +/- offset
1358 /// computation); a post-indexed store produces one value (the
1359 /// the result of the base +/- offset computation).
1361 
1362 static const int LAST_INDEXED_MODE = POST_DEC + 1;
1363 
1364 //===--------------------------------------------------------------------===//
1365 /// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
1366 /// index parameter when calculating addresses.
1367 ///
1368 /// SIGNED_SCALED Addr = Base + ((signed)Index * Scale)
1369 /// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * Scale)
1370 ///
1371 /// NOTE: The value of Scale is typically only known to the node owning the
1372 /// IndexType, with a value of 1 the equivalent of being unscaled.
1374 
1375 static const int LAST_MEM_INDEX_TYPE = UNSIGNED_SCALED + 1;
1376 
1377 inline bool isIndexTypeSigned(MemIndexType IndexType) {
1378  return IndexType == SIGNED_SCALED;
1379 }
1380 
1381 //===--------------------------------------------------------------------===//
1382 /// LoadExtType enum - This enum defines the three variants of LOADEXT
1383 /// (load with extension).
1384 ///
1385 /// SEXTLOAD loads the integer operand and sign extends it to a larger
1386 /// integer result type.
1387 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
1388 /// integer result type.
1389 /// EXTLOAD is used for two things: floating point extending loads and
1390 /// integer extending loads [the top bits are undefined].
1392 
1393 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
1394 
1396 
1397 //===--------------------------------------------------------------------===//
1398 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1399 /// below work out, when considering SETFALSE (something that never exists
1400 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
1401 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
1402 /// to. If the "N" column is 1, the result of the comparison is undefined if
1403 /// the input is a NAN.
1404 ///
1405 /// All of these (except for the 'always folded ops') should be handled for
1406 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1407 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1408 ///
1409 /// Note that these are laid out in a specific order to allow bit-twiddling
1410 /// to transform conditions.
1411 enum CondCode {
1412  // Opcode N U L G E Intuitive operation
1413  SETFALSE, // 0 0 0 0 Always false (always folded)
1414  SETOEQ, // 0 0 0 1 True if ordered and equal
1415  SETOGT, // 0 0 1 0 True if ordered and greater than
1416  SETOGE, // 0 0 1 1 True if ordered and greater than or equal
1417  SETOLT, // 0 1 0 0 True if ordered and less than
1418  SETOLE, // 0 1 0 1 True if ordered and less than or equal
1419  SETONE, // 0 1 1 0 True if ordered and operands are unequal
1420  SETO, // 0 1 1 1 True if ordered (no nans)
1421  SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
1422  SETUEQ, // 1 0 0 1 True if unordered or equal
1423  SETUGT, // 1 0 1 0 True if unordered or greater than
1424  SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
1425  SETULT, // 1 1 0 0 True if unordered or less than
1426  SETULE, // 1 1 0 1 True if unordered, less than, or equal
1427  SETUNE, // 1 1 1 0 True if unordered or not equal
1428  SETTRUE, // 1 1 1 1 Always true (always folded)
1429  // Don't care operations: undefined if the input is a nan.
1430  SETFALSE2, // 1 X 0 0 0 Always false (always folded)
1431  SETEQ, // 1 X 0 0 1 True if equal
1432  SETGT, // 1 X 0 1 0 True if greater than
1433  SETGE, // 1 X 0 1 1 True if greater than or equal
1434  SETLT, // 1 X 1 0 0 True if less than
1435  SETLE, // 1 X 1 0 1 True if less than or equal
1436  SETNE, // 1 X 1 1 0 True if not equal
1437  SETTRUE2, // 1 X 1 1 1 Always true (always folded)
1438 
1439  SETCC_INVALID // Marker value.
1440 };
1441 
1442 /// Return true if this is a setcc instruction that performs a signed
1443 /// comparison when used with integer operands.
1444 inline bool isSignedIntSetCC(CondCode Code) {
1445  return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
1446 }
1447 
1448 /// Return true if this is a setcc instruction that performs an unsigned
1449 /// comparison when used with integer operands.
1450 inline bool isUnsignedIntSetCC(CondCode Code) {
1451  return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
1452 }
1453 
1454 /// Return true if this is a setcc instruction that performs an equality
1455 /// comparison when used with integer operands.
1456 inline bool isIntEqualitySetCC(CondCode Code) {
1457  return Code == SETEQ || Code == SETNE;
1458 }
1459 
1460 /// Return true if the specified condition returns true if the two operands to
1461 /// the condition are equal. Note that if one of the two operands is a NaN,
1462 /// this value is meaningless.
1463 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
1464 
1465 /// This function returns 0 if the condition is always false if an operand is
1466 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1467 /// the condition is undefined if the operand is a NaN.
1469  return ((int)Cond >> 3) & 3;
1470 }
1471 
1472 /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1473 /// SetCC operation.
1475 
1476 namespace GlobalISel {
1477 /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1478 /// SetCC operation. The U bit of the condition code has different meanings
1479 /// between floating point and integer comparisons and LLT's don't provide
1480 /// this distinction. As such we need to be told whether the comparison is
1481 /// floating point or integer-like. Pointers should use integer-like
1482 /// comparisons.
1483 CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike);
1484 } // end namespace GlobalISel
1485 
1486 /// Return the operation corresponding to (Y op X) when given the operation
1487 /// for (X op Y).
1489 
1490 /// Return the result of a logical OR between different comparisons of
1491 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1492 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1494 
1495 /// Return the result of a logical AND between different comparisons of
1496 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1497 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1499 
1500 } // namespace ISD
1501 
1502 } // namespace llvm
1503 
1504 #endif
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::ISD::LAST_LOADEXT_TYPE
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:1393
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:917
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:929
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::STRICT_FP_ROUND
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:464
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1424
ValueTypes.h
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::ISD::SETTRUE
@ SETTRUE
Definition: ISDOpcodes.h:1428
llvm::ISD::STRICT_FSETCC
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:475
llvm::ISD::getExtForLoadExtType
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
Definition: SelectionDAG.cpp:476
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:586
llvm::ISD::isSignedIntSetCC
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:1444
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1435
llvm::ISD::INTRINSIC_VOID
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:199
llvm::ISD::SETO
@ SETO
Definition: ISDOpcodes.h:1420
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1360
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
llvm::ISD::STRICT_FSQRT
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:411
llvm::ISD::isVPBinaryOp
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
Definition: SelectionDAG.cpp:428
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::ISD::VECTOR_REVERSE
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
Definition: ISDOpcodes.h:577
llvm::ISD::STRICT_FSIN
@ STRICT_FSIN
Definition: ISDOpcodes.h:414
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::ISD::FLT_ROUNDS_
@ FLT_ROUNDS_
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
Definition: ISDOpcodes.h:863
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1432
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1223
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1436
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1391
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:943
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:387
llvm::ISD::STRICT_FMAXNUM
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:423
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1195
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:542
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1222
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1360
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::STRICT_UINT_TO_FP
@ STRICT_UINT_TO_FP
Definition: ISDOpcodes.h:449
llvm::ISD::STRICT_FMINNUM
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:424
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1188
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:708
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::ISD::INIT_TRAMPOLINE
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:1124
llvm::ISD::MLOAD
@ MLOAD
Definition: ISDOpcodes.h:1205
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:696
llvm::ISD::getVPExplicitVectorLengthIdx
Optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
Definition: SelectionDAG.cpp:465
llvm::ISD::SIGNED_SCALED
@ SIGNED_SCALED
Definition: ISDOpcodes.h:1373
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:839
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1431
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::ISD::CONDCODE
@ CONDCODE
Definition: ISDOpcodes.h:73
llvm::ISD::GlobalISel::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:518
llvm::ISD::TargetIndex
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition: ISDOpcodes.h:177
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
llvm::ISD::MGATHER
@ MGATHER
Definition: ISDOpcodes.h:1217
llvm::ISD::STEP_VECTOR
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
Definition: ISDOpcodes.h:632
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::ISD::MemIndexType
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
Definition: ISDOpcodes.h:1373
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:920
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:350
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:482
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::ISD::STRICT_FMAXIMUM
@ STRICT_FMAXIMUM
Definition: ISDOpcodes.h:434
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:360
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1426
llvm::ISD::PREALLOCATED_SETUP
@ PREALLOCATED_SETUP
Definition: ISDOpcodes.h:1091
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::ISD::STRICT_FPOW
@ STRICT_FPOW
Definition: ISDOpcodes.h:412
llvm::ISD::CALLSEQ_START
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
Definition: ISDOpcodes.h:1071
llvm::Optional< unsigned >
llvm::ISD::SPLAT_VECTOR_PARTS
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
Definition: ISDOpcodes.h:622
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1273
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:951
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:803
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1391
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1257
llvm::ISD::FP_TO_BF16
@ FP_TO_BF16
Definition: ISDOpcodes.h:906
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1414
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:216
llvm::ISD::GC_TRANSITION_END
@ GC_TRANSITION_END
Definition: ISDOpcodes.h:1232
llvm::ISD::STRICT_FLOG
@ STRICT_FLOG
Definition: ISDOpcodes.h:418
llvm::ISD::CALLSEQ_END
@ CALLSEQ_END
Definition: ISDOpcodes.h:1072
llvm::ISD::STRICT_FP_TO_UINT
@ STRICT_FP_TO_UINT
Definition: ISDOpcodes.h:442
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1422
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1189
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:912
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:141
llvm::ISD::ARITH_FENCE
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
Definition: ISDOpcodes.h:1150
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1242
llvm::ISD::STRICT_FLOG2
@ STRICT_FLOG2
Definition: ISDOpcodes.h:420
llvm::ISD::STRICT_FROUND
@ STRICT_FROUND
Definition: ISDOpcodes.h:427
llvm::ISD::BRIND
@ BRIND
BRIND - Indirect branch.
Definition: ISDOpcodes.h:987
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
llvm::ISD::AVGFLOORU
@ AVGFLOORU
Definition: ISDOpcodes.h:644
llvm::ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:147
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1285
llvm::ISD::GC_TRANSITION_START
@ GC_TRANSITION_START
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
Definition: ISDOpcodes.h:1231
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:930
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1391
llvm::ISD::STRICT_FDIV
@ STRICT_FDIV
Definition: ISDOpcodes.h:403
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:697
llvm::ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:151
llvm::ISD::STRICT_FP_TO_SINT
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:441
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
llvm::ISD::STRICT_FRINT
@ STRICT_FRINT
Definition: ISDOpcodes.h:421
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::ISD::isVPReduction
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
Definition: SelectionDAG.cpp:440
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1433
Operation
PowerPC Reduce CR logical Operation
Definition: PPCReduceCRLogicals.cpp:734
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1044
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
llvm::ISD::STRICT_FNEARBYINT
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:422
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:792
llvm::ISD::getSetCCAndOperation
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
Definition: SelectionDAG.cpp:563
llvm::ISD::STRICT_FP16_TO_FP
@ STRICT_FP16_TO_FP
Definition: ISDOpcodes.h:898
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:928
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::STRICT_FLOG10
@ STRICT_FLOG10
Definition: ISDOpcodes.h:419
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:950
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:932
llvm::ISD::GLOBAL_OFFSET_TABLE
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:87
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::ISD::DELETED_NODE
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:890
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1187
llvm::ISD::MDNODE_SDNODE
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
Definition: ISDOpcodes.h:1102
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1194
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:927
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:926
llvm::ISD::FP16_TO_FP
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:896
llvm::ISD::ATOMIC_STORE
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:1163
llvm::ISD::AssertAlign
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
Definition: ISDOpcodes.h:68
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1439
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1417
llvm::ISD::UNSIGNED_SCALED
@ UNSIGNED_SCALED
Definition: ISDOpcodes.h:1373
llvm::ISD::ABDS
@ ABDS
Definition: ISDOpcodes.h:655
llvm::ISD::TargetGlobalAddress
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:164
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:613
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:960
llvm::ISD::UNINDEXED
@ UNINDEXED
Definition: ISDOpcodes.h:1360
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:914
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1418
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1423
llvm::ISD::VALUETYPE
@ VALUETYPE
Definition: ISDOpcodes.h:72
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1271
llvm::ISD::isBitwiseLogicOp
bool isBitwiseLogicOp(unsigned Opcode)
Whether this is bitwise logic opcode.
Definition: ISDOpcodes.h:1309
llvm::ISD::ATOMIC_LOAD_FADD
@ ATOMIC_LOAD_FADD
Definition: ISDOpcodes.h:1196
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1360
llvm::ISD::TargetConstantFP
@ TargetConstantFP
Definition: ISDOpcodes.h:159
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:918
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::ISD::AVGCEILU
@ AVGCEILU
Definition: ISDOpcodes.h:649
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1427
llvm::ISD::STRICT_FSETCCS
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:476
llvm::ISD::STRICT_FMINIMUM
@ STRICT_FMINIMUM
Definition: ISDOpcodes.h:435
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::ISD::WRITE_REGISTER
@ WRITE_REGISTER
Definition: ISDOpcodes.h:119
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:956
llvm::ISD::AVGCEILS
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:648
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::ISD::isVPOpcode
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
Definition: SelectionDAG.cpp:417
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1238
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:921
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1274
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:486
llvm::ISD::LOCAL_RECOVER
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition: ISDOpcodes.h:114
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1155
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1176
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1192
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1300
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1278
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:966
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1283
llvm::ISD::getUnorderedFlavor
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
Definition: ISDOpcodes.h:1468
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::ISD::SRCVALUE
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
Definition: ISDOpcodes.h:1098
llvm::ISD::STRICT_LRINT
@ STRICT_LRINT
Definition: ISDOpcodes.h:432
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::ISD::SPONENTRY
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
Definition: ISDOpcodes.h:106
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:314
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1270
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1048
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1191
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1258
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:933
llvm::ISD::FP_TO_FP16
@ FP_TO_FP16
Definition: ISDOpcodes.h:897
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1170
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:341
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1185
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::ISD::MSTORE
@ MSTORE
Definition: ISDOpcodes.h:1206
llvm::ISD::STRICT_LROUND
@ STRICT_LROUND
Definition: ISDOpcodes.h:430
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1391
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1415
llvm::ISD::ADJUST_TRAMPOLINE
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:1130
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1425
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1136
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1411
llvm::ISD::EH_DWARF_CFA
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:129
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
llvm::ISD::ATOMIC_LOAD_FSUB
@ ATOMIC_LOAD_FSUB
Definition: ISDOpcodes.h:1197
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1280
llvm::ISD::TargetGlobalTLSAddress
@ TargetGlobalTLSAddress
Definition: ISDOpcodes.h:165
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::ISD::POST_DEC
@ POST_DEC
Definition: ISDOpcodes.h:1360
llvm::ISD::STRICT_LLRINT
@ STRICT_LLRINT
Definition: ISDOpcodes.h:433
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::ISD::TargetBlockAddress
@ TargetBlockAddress
Definition: ISDOpcodes.h:170
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1039
llvm::ISD::VSCALE
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
Definition: ISDOpcodes.h:1247
llvm::ISD::STRICT_FROUNDEVEN
@ STRICT_FROUNDEVEN
Definition: ISDOpcodes.h:428
llvm::ISD::HANDLENODE
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
Definition: ISDOpcodes.h:1116
llvm::ISD::STRICT_FEXP
@ STRICT_FEXP
Definition: ISDOpcodes.h:416
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:957
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1140
llvm::ISD::TargetConstantPool
@ TargetConstantPool
Definition: ISDOpcodes.h:168
llvm::ISD::STRICT_FCOS
@ STRICT_FCOS
Definition: ISDOpcodes.h:415
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:663
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1360
llvm::ISD::SETTRUE2
@ SETTRUE2
Definition: ISDOpcodes.h:1437
llvm::ISD::getVPMaskIdx
Optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
Definition: SelectionDAG.cpp:453
llvm::ISD::STRICT_FTRUNC
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:429
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::ISD::ABDU
@ ABDU
Definition: ISDOpcodes.h:656
llvm::ISD::STRICT_SINT_TO_FP
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition: ISDOpcodes.h:448
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:934
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1186
llvm::ISD::STRICT_FSUB
@ STRICT_FSUB
Definition: ISDOpcodes.h:401
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:922
llvm::ISD::UNDEF
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:211
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1294
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:368
llvm::ISD::isIndexTypeSigned
bool isIndexTypeSigned(MemIndexType IndexType)
Definition: ISDOpcodes.h:1377
llvm::ISD::SETFALSE
@ SETFALSE
Definition: ISDOpcodes.h:1413
llvm::ISD::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:514
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:923
llvm::ISD::STRICT_FP_EXTEND
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:469
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1282
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:392
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1184
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:598
llvm::ISD::CARRY_FALSE
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition: ISDOpcodes.h:260
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1391
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
llvm::ISD::PCMARKER
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
Definition: ISDOpcodes.h:1105
llvm::ISD::INTRINSIC_WO_CHAIN
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:184
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::ISD::isIntEqualitySetCC
bool isIntEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with intege...
Definition: ISDOpcodes.h:1456
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:913
llvm::ISD::INSERT_SUBVECTOR
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition: ISDOpcodes.h:558
llvm::ISD::READ_REGISTER
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:118
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1434
llvm::ISD::STRICT_FMUL
@ STRICT_FMUL
Definition: ISDOpcodes.h:402
llvm::ISD::STRICT_FMA
@ STRICT_FMA
Definition: ISDOpcodes.h:405
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:944
llvm::ISD::EXTRACT_SUBVECTOR
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition: ISDOpcodes.h:572
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:838
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
llvm::ISD::LAST_MEM_INDEX_TYPE
static const int LAST_MEM_INDEX_TYPE
Definition: ISDOpcodes.h:1375
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1279
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:374
llvm::ISD::STRICT_FP_TO_FP16
@ STRICT_FP_TO_FP16
Definition: ISDOpcodes.h:899
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::ISD::TargetExternalSymbol
@ TargetExternalSymbol
Definition: ISDOpcodes.h:169
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:916
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:924
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
Definition: SelectionDAG.cpp:491
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:915
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::ISD::BUILD_VECTOR
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:514
llvm::ISD::STRICT_FCEIL
@ STRICT_FCEIL
Definition: ISDOpcodes.h:425
llvm::ISD::FRAME_TO_ARGS_OFFSET
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:124
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1281
llvm::ISD::SETUO
@ SETUO
Definition: ISDOpcodes.h:1421
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::ISD::TargetConstant
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:158
llvm::ISD::PREALLOCATED_ARG
@ PREALLOCATED_ARG
Definition: ISDOpcodes.h:1094
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
llvm::ISD::getSetCCOrOperation
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
Definition: SelectionDAG.cpp:542
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:967
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::ISD::STRICT_FFLOOR
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:426
llvm::ISD::IS_FPCLASS
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:506
llvm::ISD::isTrueWhenEqual
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
Definition: ISDOpcodes.h:1463
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1416
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:871
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:496
llvm::ISD::RegisterMask
@ RegisterMask
Definition: ISDOpcodes.h:75
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:391
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1146
llvm::ISD::BF16_TO_FP
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
Definition: ISDOpcodes.h:905
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1113
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::ISD::isUnsignedIntSetCC
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
Definition: ISDOpcodes.h:1450
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:814
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1306
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1362
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::ISD::ADDROFRETURNADDR
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
Definition: ISDOpcodes.h:101
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::ISD::TargetJumpTable
@ TargetJumpTable
Definition: ISDOpcodes.h:167
llvm::ISD::STRICT_FADD
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:400
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:705
llvm::ISD::STRICT_LLROUND
@ STRICT_LLROUND
Definition: ISDOpcodes.h:431
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:662
llvm::ISD::SETFALSE2
@ SETFALSE2
Definition: ISDOpcodes.h:1430
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:931
llvm::ISD::STRICT_FREM
@ STRICT_FREM
Definition: ISDOpcodes.h:404
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1419
llvm::ISD::INTRINSIC_W_CHAIN
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:192
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:911
llvm::ISD::STRICT_FEXP2
@ STRICT_FEXP2
Definition: ISDOpcodes.h:417
llvm::ISD::BUILD_PAIR
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:229
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:381
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::ISD::STRICT_FPOWI
@ STRICT_FPOWI
Definition: ISDOpcodes.h:413
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1190
llvm::ISD::TargetFrameIndex
@ TargetFrameIndex
Definition: ISDOpcodes.h:166
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1284
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::ISD::FPTRUNC_ROUND
@ FPTRUNC_ROUND
Definition: ISDOpcodes.h:479
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1286
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:925
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::ISD::FCANONICALIZE
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:499
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1053
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:919
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
llvm::ISD::AVGFLOORS
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:643
llvm::ISD::SET_ROUNDING
@ SET_ROUNDING
Set rounding mode.
Definition: ISDOpcodes.h:868
llvm::ISD::ATOMIC_LOAD
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:1159
llvm::ISD::SCALAR_TO_VECTOR
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:606
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::ISD::getVecReduceBaseOpcode
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
Definition: SelectionDAG.cpp:367
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1193
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
llvm::ISD::MSCATTER
@ MSCATTER
Definition: ISDOpcodes.h:1218
llvm::ISD::VSELECT
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:722
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393