LLVM 19.0.0git
ISDOpcodes.h
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1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares codegen opcodes and related utilities.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_ISDOPCODES_H
14#define LLVM_CODEGEN_ISDOPCODES_H
15
17
18namespace llvm {
19
20/// ISD namespace - This namespace contains an enum which represents all of the
21/// SelectionDAG node types and value types.
22///
23namespace ISD {
24
25//===--------------------------------------------------------------------===//
26/// ISD::NodeType enum - This enum defines the target-independent operators
27/// for a SelectionDAG.
28///
29/// Targets may also define target-dependent operator codes for SDNodes. For
30/// example, on x86, these are the enum values in the X86ISD namespace.
31/// Targets should aim to use target-independent operators to model their
32/// instruction sets as much as possible, and only use target-dependent
33/// operators when they have special requirements.
34///
35/// Finally, during and after selection proper, SNodes may use special
36/// operator codes that correspond directly with MachineInstr opcodes. These
37/// are used to represent selected instructions. See the isMachineOpcode()
38/// and getMachineOpcode() member functions of SDNode.
39///
41
42 /// DELETED_NODE - This is an illegal value that is used to catch
43 /// errors. This opcode is not a legal opcode for any node.
45
46 /// EntryToken - This is the marker used to indicate the start of a region.
48
49 /// TokenFactor - This node takes multiple tokens as input and produces a
50 /// single token result. This is used to represent the fact that the operand
51 /// operators are independent of each other.
53
54 /// AssertSext, AssertZext - These nodes record if a register contains a
55 /// value that has already been zero or sign extended from a narrower type.
56 /// These nodes take two operands. The first is the node that has already
57 /// been extended, and the second is a value type node indicating the width
58 /// of the extension.
59 /// NOTE: In case of the source value (or any vector element value) is
60 /// poisoned the assertion will not be true for that value.
63
64 /// AssertAlign - These nodes record if a register contains a value that
65 /// has a known alignment and the trailing bits are known to be zero.
66 /// NOTE: In case of the source value (or any vector element value) is
67 /// poisoned the assertion will not be true for that value.
69
70 /// Various leaf nodes.
85
86 /// The address of the GOT
88
89 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
90 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
91 /// of the frame or return address to return. An index of zero corresponds
92 /// to the current function's frame or return address, an index of one to
93 /// the parent's frame or return address, and so on.
96
97 /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
98 /// This node takes no operand, returns a target-specific pointer to the
99 /// place in the stack frame where the return address of the current
100 /// function is stored.
102
103 /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument
104 /// and returns the stack pointer value at the entry of the current
105 /// function calling this intrinsic.
107
108 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
109 /// Materializes the offset from the local object pointer of another
110 /// function to a particular local object passed to llvm.localescape. The
111 /// operand is the MCSymbol label used to represent this offset, since
112 /// typically the offset is not known until after code generation of the
113 /// parent.
115
116 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
117 /// the DAG, which implements the named register global variables extension.
120
121 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
122 /// first (possible) on-stack argument. This is needed for correct stack
123 /// adjustment during unwind.
125
126 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
127 /// Frame Address (CFA), generally the value of the stack pointer at the
128 /// call site in the previous frame.
130
131 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
132 /// 'eh_return' gcc dwarf builtin, which is used to return from
133 /// exception. The general meaning is: adjust stack by OFFSET and pass
134 /// execution to HANDLER. Many platform-related details also :)
136
137 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
138 /// This corresponds to the eh.sjlj.setjmp intrinsic.
139 /// It takes an input chain and a pointer to the jump buffer as inputs
140 /// and returns an outchain.
142
143 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
144 /// This corresponds to the eh.sjlj.longjmp intrinsic.
145 /// It takes an input chain and a pointer to the jump buffer as inputs
146 /// and returns an outchain.
148
149 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
150 /// The target initializes the dispatch table here.
152
153 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
154 /// simplification, or lowering of the constant. They are used for constants
155 /// which are known to fit in the immediate fields of their users, or for
156 /// carrying magic numbers which are not values which need to be
157 /// materialized in registers.
160
161 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
162 /// anything else with this node, and this is valid in the target-specific
163 /// dag, turning into a GlobalAddress operand.
171
173
174 /// TargetIndex - Like a constant pool entry, but with completely
175 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
176 /// 64-bit index. Targets can use this however they like.
178
179 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
180 /// This node represents a target intrinsic function with no side effects.
181 /// The first operand is the ID number of the intrinsic from the
182 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
183 /// node returns the result of the intrinsic.
185
186 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
187 /// This node represents a target intrinsic function with side effects that
188 /// returns a result. The first operand is a chain pointer. The second is
189 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
190 /// operands to the intrinsic follow. The node has two results, the result
191 /// of the intrinsic and an output chain.
193
194 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
195 /// This node represents a target intrinsic function with side effects that
196 /// does not return a result. The first operand is a chain pointer. The
197 /// second is the ID number of the intrinsic from the llvm::Intrinsic
198 /// namespace. The operands to the intrinsic follow.
200
201 /// CopyToReg - This node has three operands: a chain, a register number to
202 /// set to this value, and a value.
204
205 /// CopyFromReg - This node indicates that the input value is a virtual or
206 /// physical register that is defined outside of the scope of this
207 /// SelectionDAG. The register is available from the RegisterSDNode object.
208 /// Note that CopyFromReg is considered as also freezing the value.
210
211 /// UNDEF - An undefined node.
213
214 // FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
215 // is evaluated to UNDEF), or returns VAL otherwise. Note that each
216 // read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.
218
219 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
220 /// a Constant, which is required to be operand #1) half of the integer or
221 /// float value specified as operand #0. This is only for use before
222 /// legalization, for values that will be broken into multiple registers.
224
225 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
226 /// Given two values of the same integer value type, this produces a value
227 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
228 /// legalization. The lower part of the composite value should be in
229 /// element 0 and the upper part should be in element 1.
231
232 /// MERGE_VALUES - This node takes multiple discrete operands and returns
233 /// them all as its individual results. This nodes has exactly the same
234 /// number of inputs and outputs. This node is useful for some pieces of the
235 /// code generator that want to think about a single node with multiple
236 /// results, not multiple nodes.
238
239 /// Simple integer binary arithmetic operators.
247
248 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
249 /// a signed/unsigned value of type i[2*N], and return the full value as
250 /// two results, each of type iN.
253
254 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
255 /// remainder result.
258
259 /// CARRY_FALSE - This node is used when folding other nodes,
260 /// like ADDC/SUBC, which indicate the carry result is always false.
262
263 /// Carry-setting nodes for multiple precision addition and subtraction.
264 /// These nodes take two operands of the same value type, and produce two
265 /// results. The first result is the normal add or sub result, the second
266 /// result is the carry flag result.
267 /// FIXME: These nodes are deprecated in favor of UADDO_CARRY and USUBO_CARRY.
268 /// They are kept around for now to provide a smooth transition path
269 /// toward the use of UADDO_CARRY/USUBO_CARRY and will eventually be removed.
272
273 /// Carry-using nodes for multiple precision addition and subtraction. These
274 /// nodes take three operands: The first two are the normal lhs and rhs to
275 /// the add or sub, and the third is the input carry flag. These nodes
276 /// produce two results; the normal result of the add or sub, and the output
277 /// carry flag. These nodes both read and write a carry flag to allow them
278 /// to them to be chained together for add and sub of arbitrarily large
279 /// values.
282
283 /// Carry-using nodes for multiple precision addition and subtraction.
284 /// These nodes take three operands: The first two are the normal lhs and
285 /// rhs to the add or sub, and the third is a boolean value that is 1 if and
286 /// only if there is an incoming carry/borrow. These nodes produce two
287 /// results: the normal result of the add or sub, and a boolean value that is
288 /// 1 if and only if there is an outgoing carry/borrow.
289 ///
290 /// Care must be taken if these opcodes are lowered to hardware instructions
291 /// that use the inverse logic -- 0 if and only if there is an
292 /// incoming/outgoing carry/borrow. In such cases, you must preserve the
293 /// semantics of these opcodes by inverting the incoming carry/borrow, feeding
294 /// it to the add/sub hardware instruction, and then inverting the outgoing
295 /// carry/borrow.
296 ///
297 /// The use of these opcodes is preferable to adde/sube if the target supports
298 /// it, as the carry is a regular value rather than a glue, which allows
299 /// further optimisation.
300 ///
301 /// These opcodes are different from [US]{ADD,SUB}O in that
302 /// U{ADD,SUB}O_CARRY consume and produce a carry/borrow, whereas
303 /// [US]{ADD,SUB}O produce an overflow.
306
307 /// Carry-using overflow-aware nodes for multiple precision addition and
308 /// subtraction. These nodes take three operands: The first two are normal lhs
309 /// and rhs to the add or sub, and the third is a boolean indicating if there
310 /// is an incoming carry. They produce two results: the normal result of the
311 /// add or sub, and a boolean that indicates if an overflow occurred (*not*
312 /// flag, because it may be a store to memory, etc.). If the type of the
313 /// boolean is not i1 then the high bits conform to getBooleanContents.
316
317 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
318 /// These nodes take two operands: the normal LHS and RHS to the add. They
319 /// produce two results: the normal result of the add, and a boolean that
320 /// indicates if an overflow occurred (*not* a flag, because it may be store
321 /// to memory, etc.). If the type of the boolean is not i1 then the high
322 /// bits conform to getBooleanContents.
323 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
326
327 /// Same for subtraction.
330
331 /// Same for multiplication.
334
335 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
336 /// integers with the same bit width (W). If the true value of LHS + RHS
337 /// exceeds the largest value that can be represented by W bits, the
338 /// resulting value is this maximum value. Otherwise, if this value is less
339 /// than the smallest value that can be represented by W bits, the
340 /// resulting value is this minimum value.
343
344 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
345 /// integers with the same bit width (W). If the true value of LHS - RHS
346 /// exceeds the largest value that can be represented by W bits, the
347 /// resulting value is this maximum value. Otherwise, if this value is less
348 /// than the smallest value that can be represented by W bits, the
349 /// resulting value is this minimum value.
352
353 /// RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift. The first
354 /// operand is the value to be shifted, and the second argument is the amount
355 /// to shift by. Both must be integers of the same bit width (W). If the true
356 /// value of LHS << RHS exceeds the largest value that can be represented by
357 /// W bits, the resulting value is this maximum value, Otherwise, if this
358 /// value is less than the smallest value that can be represented by W bits,
359 /// the resulting value is this minimum value.
362
363 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication
364 /// on 2 integers with the same width and scale. SCALE represents the scale
365 /// of both operands as fixed point numbers. This SCALE parameter must be a
366 /// constant integer. A scale of zero is effectively performing
367 /// multiplication on 2 integers.
370
371 /// Same as the corresponding unsaturated fixed point instructions, but the
372 /// result is clamped between the min and max values representable by the
373 /// bits of the first 2 operands.
376
377 /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on
378 /// 2 integers with the same width and scale. SCALE represents the scale
379 /// of both operands as fixed point numbers. This SCALE parameter must be a
380 /// constant integer.
383
384 /// Same as the corresponding unsaturated fixed point instructions, but the
385 /// result is clamped between the min and max values representable by the
386 /// bits of the first 2 operands.
389
390 /// Simple binary floating point operators.
396
397 /// Constrained versions of the binary floating point operators.
398 /// These will be lowered to the simple operators before final selection.
399 /// They are used to limit optimizations while the DAG is being
400 /// optimized.
407
408 /// Constrained versions of libm-equivalent floating point intrinsics.
409 /// These will be lowered to the equivalent non-constrained pseudo-op
410 /// (or expanded to the equivalent library call) before final selection.
411 /// They are used to limit optimizations while the DAG is being optimized.
439
440 /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or
441 /// unsigned integer. These have the same semantics as fptosi and fptoui
442 /// in IR.
443 /// They are used to limit optimizations while the DAG is being optimized.
446
447 /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to
448 /// a floating point value. These have the same semantics as sitofp and
449 /// uitofp in IR.
450 /// They are used to limit optimizations while the DAG is being optimized.
453
454 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
455 /// point type down to the precision of the destination VT. TRUNC is a
456 /// flag, which is always an integer that is zero or one. If TRUNC is 0,
457 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
458 /// change the value of Y.
459 ///
460 /// The TRUNC = 1 case is used in cases where we know that the value will
461 /// not be modified by the node, because Y is not using any of the extra
462 /// precision of source type. This allows certain transformations like
463 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for
464 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't
465 /// removed.
466 /// It is used to limit optimizations while the DAG is being optimized.
468
469 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP
470 /// type.
471 /// It is used to limit optimizations while the DAG is being optimized.
473
474 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used
475 /// for floating-point operands only. STRICT_FSETCC performs a quiet
476 /// comparison operation, while STRICT_FSETCCS performs a signaling
477 /// comparison operation.
480
481 // FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.
483
484 /// FMA - Perform a * b + c with no intermediate rounding step.
486
487 /// FMAD - Perform a * b + c, while getting the same result as the
488 /// separately rounded operations.
490
491 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
492 /// DAG node does not require that X and Y have the same type, just that
493 /// they are both floating point. X and the result must have the same type.
494 /// FCOPYSIGN(f32, f64) is allowed.
496
497 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
498 /// value as an integer 0/1 value.
500
501 /// Returns platform specific canonical encoding of a floating point number.
503
504 /// Performs a check of floating point class property, defined by IEEE-754.
505 /// The first operand is the floating point value to check. The second operand
506 /// specifies the checked property and is a TargetConstant which specifies
507 /// test in the same way as intrinsic 'is_fpclass'.
508 /// Returns boolean value.
510
511 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
512 /// with the specified, possibly variable, elements. The types of the
513 /// operands must match the vector element type, except that integer types
514 /// are allowed to be larger than the element type, in which case the
515 /// operands are implicitly truncated. The types of the operands must all
516 /// be the same.
518
519 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
520 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
521 /// element type then VAL is truncated before replacement.
522 ///
523 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
524 /// vector width. IDX is not first scaled by the runtime scaling factor of
525 /// VECTOR.
527
528 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
529 /// identified by the (potentially variable) element number IDX. If the return
530 /// type is an integer type larger than the element type of the vector, the
531 /// result is extended to the width of the return type. In that case, the high
532 /// bits are undefined.
533 ///
534 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
535 /// vector width. IDX is not first scaled by the runtime scaling factor of
536 /// VECTOR.
538
539 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
540 /// vector type with the same length and element type, this produces a
541 /// concatenated vector result value, with length equal to the sum of the
542 /// lengths of the input vectors. If VECTOR0 is a fixed-width vector, then
543 /// VECTOR1..VECTORN must all be fixed-width vectors. Similarly, if VECTOR0
544 /// is a scalable vector, then VECTOR1..VECTORN must all be scalable vectors.
546
547 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2
548 /// inserted into VECTOR1. IDX represents the starting element number at which
549 /// VECTOR2 will be inserted. IDX must be a constant multiple of T's known
550 /// minimum vector length. Let the type of VECTOR2 be T, then if T is a
551 /// scalable vector, IDX is first scaled by the runtime scaling factor of T.
552 /// The elements of VECTOR1 starting at IDX are overwritten with VECTOR2.
553 /// Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR1
554 /// indices. If this condition cannot be determined statically but is false at
555 /// runtime, then the result vector is undefined. The IDX parameter must be a
556 /// vector index constant type, which for most targets will be an integer
557 /// pointer type.
558 ///
559 /// This operation supports inserting a fixed-width vector into a scalable
560 /// vector, but not the other way around.
562
563 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
564 /// Let the result type be T, then IDX represents the starting element number
565 /// from which a subvector of type T is extracted. IDX must be a constant
566 /// multiple of T's known minimum vector length. If T is a scalable vector,
567 /// IDX is first scaled by the runtime scaling factor of T. Elements IDX
568 /// through (IDX + num_elements(T) - 1) must be valid VECTOR indices. If this
569 /// condition cannot be determined statically but is false at runtime, then
570 /// the result vector is undefined. The IDX parameter must be a vector index
571 /// constant type, which for most targets will be an integer pointer type.
572 ///
573 /// This operation supports extracting a fixed-width vector from a scalable
574 /// vector, but not the other way around.
576
577 /// VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and
578 /// output vectors having the same type. The first output contains the even
579 /// indices from CONCAT_VECTORS(VEC1, VEC2), with the second output
580 /// containing the odd indices. The relative order of elements within an
581 /// output match that of the concatenated input.
583
584 /// VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and
585 /// output vectors having the same type. The first output contains the
586 /// result of interleaving the low half of CONCAT_VECTORS(VEC1, VEC2), with
587 /// the second output containing the result of interleaving the high half.
589
590 /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
591 /// whose elements are shuffled using the following algorithm:
592 /// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
594
595 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
596 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
597 /// values that indicate which value (or undef) each result element will
598 /// get. These constant ints are accessible through the
599 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
600 /// 'vperm' instruction, except that the indices must be constants and are
601 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
603
604 /// VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as
605 /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways.
606 /// Let the result type be T, if IMM is positive it represents the starting
607 /// element number (an index) from which a subvector of type T is extracted
608 /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count
609 /// specifying the number of trailing elements to extract from VEC1, where the
610 /// elements of T are selected using the following algorithm:
611 /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i]
612 /// If IMM is not in the range [-VL, VL-1] the result vector is undefined. IMM
613 /// is a constant integer.
615
616 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
617 /// scalar value into element 0 of the resultant vector type. The top
618 /// elements 1 to N-1 of the N-element vector are undefined. The type
619 /// of the operand must match the vector element type, except when they
620 /// are integer types. In this case the operand is allowed to be wider
621 /// than the vector element type, and is implicitly truncated to it.
623
624 /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL
625 /// duplicated in all lanes. The type of the operand must match the vector
626 /// element type, except when they are integer types. In this case the
627 /// operand is allowed to be wider than the vector element type, and is
628 /// implicitly truncated to it.
630
631 /// SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the
632 /// scalar values joined together and then duplicated in all lanes. This
633 /// represents a SPLAT_VECTOR that has had its scalar operand expanded. This
634 /// allows representing a 64-bit splat on a target with 32-bit integers. The
635 /// total width of the scalars must cover the element width. SCALAR1 contains
636 /// the least significant bits of the value regardless of endianness and all
637 /// scalars should have the same type.
639
640 /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
641 /// of a linear sequence of unsigned values starting from 0 with a step of
642 /// IMM, where IMM must be a TargetConstant with type equal to the vector
643 /// element type. The arithmetic is performed modulo the bitwidth of the
644 /// element.
645 ///
646 /// The operation does not support returning fixed-width vectors or
647 /// non-constant operands.
649
650 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
651 /// producing an unsigned/signed value of type i[2*N], then return the top
652 /// part.
655
656 /// AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of
657 /// type i[N+1], halving the result by shifting it one bit right.
658 /// shr(add(ext(X), ext(Y)), 1)
661 /// AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an
662 /// integer of type i[N+2], add 1 and halve the result by shifting it one bit
663 /// right. shr(add(ext(X), ext(Y), 1), 1)
666
667 // ABDS/ABDU - Absolute difference - Return the absolute difference between
668 // two numbers interpreted as signed/unsigned.
669 // i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1)
670 // or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1)
673
674 /// [US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned
675 /// integers.
680
681 /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
682 /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
683 /// different to the result.
686
687 /// Bitwise operators - logical and, logical or, logical xor.
691
692 /// ABS - Determine the unsigned absolute value of a signed integer value of
693 /// the same bitwidth.
694 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
695 /// is performed.
697
698 /// Shift and rotation operations. After legalization, the type of the
699 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
700 /// the shift amount can be any type, but care must be taken to ensure it is
701 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
702 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
703 /// to represent the shift amount.
704 /// When the 1st operand is a vector, the shift amount must be in the same
705 /// type. (TLI.getShiftAmountTy() will return the same type when the input
706 /// type is a vector.)
707 /// For rotates and funnel shifts, the shift amount is treated as an unsigned
708 /// amount modulo the element size of the first operand.
709 ///
710 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
711 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
712 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
720
721 /// Byte Swap and Counting operators.
728
729 /// Bit counting operators with an undefined result for zero inputs.
732
733 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
734 /// i1 then the high bits must conform to getBooleanContents.
736
737 /// Select with a vector condition (op #0) and two vector operands (ops #1
738 /// and #2), returning a vector result. All vectors have the same length.
739 /// Much like the scalar select and setcc, each bit in the condition selects
740 /// whether the corresponding result element is taken from op #1 or op #2.
741 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
742 /// change the condition type in order to match the VSELECT node using a
743 /// pattern. The condition follows the BooleanContent format of the target.
745
746 /// Select with condition operator - This selects between a true value and
747 /// a false value (ops #2 and #3) based on the boolean result of comparing
748 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
749 /// condition code in op #4, a CondCodeSDNode.
751
752 /// SetCC operator - This evaluates to a true value iff the condition is
753 /// true. If the result value type is not i1 then the high bits conform
754 /// to getBooleanContents. The operands to this are the left and right
755 /// operands to compare (ops #0, and #1) and the condition code to compare
756 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
757 /// then the result type must also be a vector type.
759
760 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
761 /// op #2 is a boolean indicating if there is an incoming carry. This
762 /// operator checks the result of "LHS - RHS - Carry", and can be used to
763 /// compare two wide integers:
764 /// (setcccarry lhshi rhshi (usubo_carry lhslo rhslo) cc).
765 /// Only valid for integers.
767
768 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
769 /// integer shift operations. The operation ordering is:
770 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
774
775 /// Conversion operators. These are all single input single output
776 /// operations. For all of these, the result type must be strictly
777 /// wider or narrower (depending on the operation) than the source
778 /// type.
779
780 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
781 /// into new bits.
783
784 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. Can carry
785 /// the NonNeg SDNodeFlag to indicate that the input is known to be
786 /// non-negative. If the flag is present and the input is negative, the result
787 /// is poison.
789
790 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
792
793 /// TRUNCATE - Completely drop the high bits.
795
796 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
797 /// depends on the first letter) to floating point.
800
801 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
802 /// sign extend a small value in a large integer register (e.g. sign
803 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
804 /// with the 7th bit). The size of the smaller type is indicated by the 1th
805 /// operand, a ValueType node.
807
808 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
809 /// in-register any-extension of the low lanes of an integer vector. The
810 /// result type must have fewer elements than the operand type, and those
811 /// elements must be larger integer types such that the total size of the
812 /// operand type is less than or equal to the size of the result type. Each
813 /// of the low operand elements is any-extended into the corresponding,
814 /// wider result elements with the high bits becoming undef.
815 /// NOTE: The type legalizer prefers to make the operand and result size
816 /// the same to allow expansion to shuffle vector during op legalization.
818
819 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
820 /// in-register sign-extension of the low lanes of an integer vector. The
821 /// result type must have fewer elements than the operand type, and those
822 /// elements must be larger integer types such that the total size of the
823 /// operand type is less than or equal to the size of the result type. Each
824 /// of the low operand elements is sign-extended into the corresponding,
825 /// wider result elements.
826 /// NOTE: The type legalizer prefers to make the operand and result size
827 /// the same to allow expansion to shuffle vector during op legalization.
829
830 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
831 /// in-register zero-extension of the low lanes of an integer vector. The
832 /// result type must have fewer elements than the operand type, and those
833 /// elements must be larger integer types such that the total size of the
834 /// operand type is less than or equal to the size of the result type. Each
835 /// of the low operand elements is zero-extended into the corresponding,
836 /// wider result elements.
837 /// NOTE: The type legalizer prefers to make the operand and result size
838 /// the same to allow expansion to shuffle vector during op legalization.
840
841 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
842 /// integer. These have the same semantics as fptosi and fptoui in IR. If
843 /// the FP value cannot fit in the integer type, the results are undefined.
846
847 /// FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a
848 /// signed or unsigned scalar integer type given in operand 1 with the
849 /// following semantics:
850 ///
851 /// * If the value is NaN, zero is returned.
852 /// * If the value is larger/smaller than the largest/smallest integer,
853 /// the largest/smallest integer is returned (saturation).
854 /// * Otherwise the result of rounding the value towards zero is returned.
855 ///
856 /// The scalar width of the type given in operand 1 must be equal to, or
857 /// smaller than, the scalar result type width. It may end up being smaller
858 /// than the result width as a result of integer type legalization.
859 ///
860 /// After converting to the scalar integer type in operand 1, the value is
861 /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT
862 /// zero extends.
865
866 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
867 /// down to the precision of the destination VT. TRUNC is a flag, which is
868 /// always an integer that is zero or one. If TRUNC is 0, this is a
869 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
870 /// value of Y.
871 ///
872 /// The TRUNC = 1 case is used in cases where we know that the value will
873 /// not be modified by the node, because Y is not using any of the extra
874 /// precision of source type. This allows certain transformations like
875 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
876 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
878
879 /// Returns current rounding mode:
880 /// -1 Undefined
881 /// 0 Round to 0
882 /// 1 Round to nearest, ties to even
883 /// 2 Round to +inf
884 /// 3 Round to -inf
885 /// 4 Round to nearest, ties to zero
886 /// Other values are target dependent.
887 /// Result is rounding mode and chain. Input is a chain.
889
890 /// Set rounding mode.
891 /// The first operand is a chain pointer. The second specifies the required
892 /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'.
894
895 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
897
898 /// BITCAST - This operator converts between integer, vector and FP
899 /// values, as if the value was stored to memory with one type and loaded
900 /// from the same address with the other type (or equivalently for vector
901 /// format conversions, etc). The source and result are required to have
902 /// the same bit size (e.g. f32 <-> i32). This can also be used for
903 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
904 /// getNode().
905 ///
906 /// This operator is subtly different from the bitcast instruction from
907 /// LLVM-IR since this node may change the bits in the register. For
908 /// example, this occurs on big-endian NEON and big-endian MSA where the
909 /// layout of the bits in the register depends on the vector type and this
910 /// operator acts as a shuffle operation for some vector type combinations.
912
913 /// ADDRSPACECAST - This operator converts between pointers of different
914 /// address spaces.
916
917 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
918 /// and truncation for half-precision (16 bit) floating numbers. These nodes
919 /// form a semi-softened interface for dealing with f16 (as an i16), which
920 /// is often a storage-only type but has native conversions.
925
926 /// BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions
927 /// and truncation for bfloat16. These nodes form a semi-softened interface
928 /// for dealing with bf16 (as an i16), which is often a storage-only type but
929 /// has native conversions.
934
935 /// Perform various unary floating-point operations inspired by libm. For
936 /// FPOWI, the result is undefined if the integer operand doesn't fit into
937 /// sizeof(int).
947 /// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
949
950 /// FFREXP - frexp, extract fractional and exponent component of a
951 /// floating-point value. Returns the two components as separate return
952 /// values.
954
972
973 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
974 /// values.
975 //
976 /// In the case where a single input is a NaN (either signaling or quiet),
977 /// the non-NaN input is returned.
978 ///
979 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
982
983 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or
984 /// maximumNumber on two values, following IEEE-754 definitions. This differs
985 /// from FMINNUM/FMAXNUM in the handling of signaling NaNs, and signed zero.
986 ///
987 /// If one input is a signaling NaN, returns a quiet NaN. This matches
988 /// IEEE-754 2008's minnum/maxnum behavior for signaling NaNs (which differs
989 /// from 2019).
990 ///
991 /// These treat -0 as ordered less than +0, matching the behavior of IEEE-754
992 /// 2019's minimumNumber/maximumNumber.
995
996 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
997 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
998 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2019 semantics.
1001
1002 /// FSINCOS - Compute both fsin and fcos as a single operation.
1004
1005 /// Gets the current floating-point environment. The first operand is a token
1006 /// chain. The results are FP environment, represented by an integer value,
1007 /// and a token chain.
1009
1010 /// Sets the current floating-point environment. The first operand is a token
1011 /// chain, the second is FP environment, represented by an integer value. The
1012 /// result is a token chain.
1014
1015 /// Set floating-point environment to default state. The first operand and the
1016 /// result are token chains.
1018
1019 /// Gets the current floating-point environment. The first operand is a token
1020 /// chain, the second is a pointer to memory, where FP environment is stored
1021 /// to. The result is a token chain.
1023
1024 /// Sets the current floating point environment. The first operand is a token
1025 /// chain, the second is a pointer to memory, where FP environment is loaded
1026 /// from. The result is a token chain.
1028
1029 /// Reads the current dynamic floating-point control modes. The operand is
1030 /// a token chain.
1032
1033 /// Sets the current dynamic floating-point control modes. The first operand
1034 /// is a token chain, the second is control modes set represented as integer
1035 /// value.
1037
1038 /// Sets default dynamic floating-point control modes. The operand is a
1039 /// token chain.
1041
1042 /// LOAD and STORE have token chains as their first operand, then the same
1043 /// operands as an LLVM load/store instruction, then an offset node that
1044 /// is added / subtracted from the base pointer to form the address (for
1045 /// indexed memory ops).
1048
1049 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
1050 /// to a specified boundary. This node always has two return values: a new
1051 /// stack pointer value and a chain. The first operand is the token chain,
1052 /// the second is the number of bytes to allocate, and the third is the
1053 /// alignment boundary. The size is guaranteed to be a multiple of the
1054 /// stack alignment, and the alignment is guaranteed to be bigger than the
1055 /// stack alignment (if required) or 0 to get standard stack alignment.
1057
1058 /// Control flow instructions. These all have token chains.
1059
1060 /// BR - Unconditional branch. The first operand is the chain
1061 /// operand, the second is the MBB to branch to.
1063
1064 /// BRIND - Indirect branch. The first operand is the chain, the second
1065 /// is the value to branch to, which must be of the same type as the
1066 /// target's pointer type.
1068
1069 /// BR_JT - Jumptable branch. The first operand is the chain, the second
1070 /// is the jumptable index, the last one is the jumptable entry index.
1072
1073 /// JUMP_TABLE_DEBUG_INFO - Jumptable debug info. The first operand is the
1074 /// chain, the second is the jumptable index.
1076
1077 /// BRCOND - Conditional branch. The first operand is the chain, the
1078 /// second is the condition, the third is the block to branch to if the
1079 /// condition is true. If the type of the condition is not i1, then the
1080 /// high bits must conform to getBooleanContents. If the condition is undef,
1081 /// it nondeterministically jumps to the block.
1082 /// TODO: Its semantics w.r.t undef requires further discussion; we need to
1083 /// make it sure that it is consistent with optimizations in MIR & the
1084 /// meaning of IMPLICIT_DEF. See https://reviews.llvm.org/D92015
1086
1087 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
1088 /// that the condition is represented as condition code, and two nodes to
1089 /// compare, rather than as a combined SetCC node. The operands in order
1090 /// are chain, cc, lhs, rhs, block to branch to if condition is true. If
1091 /// condition is undef, it nondeterministically jumps to the block.
1093
1094 /// INLINEASM - Represents an inline asm block. This node always has two
1095 /// return values: a chain and a flag result. The inputs are as follows:
1096 /// Operand #0 : Input chain.
1097 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
1098 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
1099 /// Operand #3 : HasSideEffect, IsAlignStack bits.
1100 /// After this, it is followed by a list of operands with this format:
1101 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
1102 /// of operands that follow, etc. See InlineAsm.h.
1103 /// ... however many operands ...
1104 /// Operand #last: Optional, an incoming flag.
1105 ///
1106 /// The variable width operands are required to represent target addressing
1107 /// modes as a single "operand", even though they may have multiple
1108 /// SDOperands.
1110
1111 /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
1113
1114 /// EH_LABEL - Represents a label in mid basic block used to track
1115 /// locations needed for debug and exception handling tables. These nodes
1116 /// take a chain as input and return a chain.
1118
1119 /// ANNOTATION_LABEL - Represents a mid basic block label used by
1120 /// annotations. This should remain within the basic block and be ordered
1121 /// with respect to other call instructions, but loads and stores may float
1122 /// past it.
1124
1125 /// CATCHRET - Represents a return from a catch block funclet. Used for
1126 /// MSVC compatible exception handling. Takes a chain operand and a
1127 /// destination basic block operand.
1129
1130 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
1131 /// MSVC compatible exception handling. Takes only a chain operand.
1133
1134 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
1135 /// value, the same type as the pointer type for the system, and an output
1136 /// chain.
1138
1139 /// STACKRESTORE has two operands, an input chain and a pointer to restore
1140 /// to it returns an output chain.
1142
1143 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
1144 /// of a call sequence, and carry arbitrary information that target might
1145 /// want to know. The first operand is a chain, the rest are specified by
1146 /// the target and not touched by the DAG optimizers.
1147 /// Targets that may use stack to pass call arguments define additional
1148 /// operands:
1149 /// - size of the call frame part that must be set up within the
1150 /// CALLSEQ_START..CALLSEQ_END pair,
1151 /// - part of the call frame prepared prior to CALLSEQ_START.
1152 /// Both these parameters must be constants, their sum is the total call
1153 /// frame size.
1154 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
1155 CALLSEQ_START, // Beginning of a call sequence
1156 CALLSEQ_END, // End of a call sequence
1157
1158 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
1159 /// and the alignment. It returns a pair of values: the vaarg value and a
1160 /// new chain.
1162
1163 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
1164 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
1165 /// source.
1167
1168 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
1169 /// pointer, and a SRCVALUE.
1172
1173 // PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE
1174 // with the preallocated call Value.
1176 // PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE
1177 // with the preallocated call Value, and a constant int.
1179
1180 /// SRCVALUE - This is a node type that holds a Value* that is used to
1181 /// make reference to a value in the LLVM IR.
1183
1184 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
1185 /// reference metadata in the IR.
1187
1188 /// PCMARKER - This corresponds to the pcmarker intrinsic.
1190
1191 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
1192 /// It produces a chain and one i64 value. The only operand is a chain.
1193 /// If i64 is not legal, the result will be expanded into smaller values.
1194 /// Still, it returns an i64, so targets should set legality for i64.
1195 /// The result is the content of the architecture-specific cycle
1196 /// counter-like register (or other high accuracy low latency clock source).
1198
1199 /// READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
1200 /// It has the same semantics as the READCYCLECOUNTER implementation except
1201 /// that the result is the content of the architecture-specific fixed
1202 /// frequency counter suitable for measuring elapsed time.
1204
1205 /// HANDLENODE node - Used as a handle for various purposes.
1207
1208 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
1209 /// takes as input a token chain, the pointer to the trampoline, the pointer
1210 /// to the nested function, the pointer to pass for the 'nest' parameter, a
1211 /// SRCVALUE for the trampoline and another for the nested function
1212 /// (allowing targets to access the original Function*).
1213 /// It produces a token chain as output.
1215
1216 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
1217 /// It takes a pointer to the trampoline and produces a (possibly) new
1218 /// pointer to the same trampoline with platform-specific adjustments
1219 /// applied. The pointer it returns points to an executable block of code.
1221
1222 /// TRAP - Trapping instruction
1224
1225 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
1227
1228 /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer
1229 /// failure.
1231
1232 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
1233 /// is the chain. The other operands are the address to prefetch,
1234 /// read / write specifier, locality specifier and instruction / data cache
1235 /// specifier.
1237
1238 /// ARITH_FENCE - This corresponds to a arithmetic fence intrinsic. Both its
1239 /// operand and output are the same floating type.
1241
1242 /// MEMBARRIER - Compiler barrier only; generate a no-op.
1244
1245 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
1246 /// This corresponds to the fence instruction. It takes an input chain, and
1247 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
1249
1250 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
1251 /// This corresponds to "load atomic" instruction.
1253
1254 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
1255 /// This corresponds to "store atomic" instruction.
1257
1258 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
1259 /// For double-word atomic operations:
1260 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
1261 /// swapLo, swapHi)
1262 /// This corresponds to the cmpxchg instruction.
1264
1265 /// Val, Success, OUTCHAIN
1266 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
1267 /// N.b. this is still a strong cmpxchg operation, so
1268 /// Success == "Val == cmp".
1270
1271 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
1272 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
1273 /// For double-word atomic operations:
1274 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
1275 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
1276 /// These correspond to the atomicrmw instruction.
1295
1296 // Masked load and store - consecutive vector load and store operations
1297 // with additional mask operand that prevents memory accesses to the
1298 // masked-off lanes.
1299 //
1300 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
1301 // OutChain = MSTORE(Value, BasePtr, Mask)
1304
1305 // Masked gather and scatter - load and store operations for a vector of
1306 // random addresses with additional mask operand that prevents memory
1307 // accesses to the masked-off lanes.
1308 //
1309 // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
1310 // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
1311 //
1312 // The Index operand can have more vector elements than the other operands
1313 // due to type legalization. The extra elements are ignored.
1316
1317 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
1318 /// is the chain and the second operand is the alloca pointer.
1321
1322 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
1323 /// beginning and end of GC transition sequence, and carry arbitrary
1324 /// information that target might need for lowering. The first operand is
1325 /// a chain, the rest are specified by the target and not touched by the DAG
1326 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
1327 /// nested.
1330
1331 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
1332 /// the most recent dynamic alloca. For most targets that would be 0, but
1333 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
1334 /// known nonzero constant. The only operand here is the chain.
1336
1337 /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve
1338 /// the sample counts quality.
1340
1341 /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the
1342 /// number of elements within a scalable vector. IMM is a constant integer
1343 /// multiplier that is applied to the runtime value.
1345
1346 /// Generic reduction nodes. These nodes represent horizontal vector
1347 /// reduction operations, producing a scalar result.
1348 /// The SEQ variants perform reductions in sequential order. The first
1349 /// operand is an initial scalar accumulator value, and the second operand
1350 /// is the vector to reduce.
1351 /// E.g. RES = VECREDUCE_SEQ_FADD f32 ACC, <4 x f32> SRC_VEC
1352 /// ... is equivalent to
1353 /// RES = (((ACC + SRC_VEC[0]) + SRC_VEC[1]) + SRC_VEC[2]) + SRC_VEC[3]
1356
1357 /// These reductions have relaxed evaluation order semantics, and have a
1358 /// single vector operand. The order of evaluation is unspecified. For
1359 /// pow-of-2 vectors, one valid legalizer expansion is to use a tree
1360 /// reduction, i.e.:
1361 /// For RES = VECREDUCE_FADD <8 x f16> SRC_VEC
1362 /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7]
1363 /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3]
1364 /// RES = FADD PART_RDX2[0], PART_RDX2[1]
1365 /// For non-pow-2 vectors, this can be computed by extracting each element
1366 /// and performing the operation as if it were scalarized.
1369 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
1372 /// FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the
1373 /// llvm.minimum and llvm.maximum semantics.
1376 /// Integer reductions may have a result type larger than the vector element
1377 /// type. However, the reduction is performed using the vector element type
1378 /// and the value in the top bits is unspecified.
1388
1389 // The `llvm.experimental.stackmap` intrinsic.
1390 // Operands: input chain, glue, <id>, <numShadowBytes>, [live0[, live1...]]
1391 // Outputs: output chain, glue
1393
1394 // The `llvm.experimental.patchpoint.*` intrinsic.
1395 // Operands: input chain, [glue], reg-mask, <id>, <numShadowBytes>, callee,
1396 // <numArgs>, cc, ...
1397 // Outputs: [rv], output chain, glue
1399
1400// Vector Predication
1401#define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...) VPSDID,
1402#include "llvm/IR/VPIntrinsics.def"
1403
1404 // The `llvm.experimental.convergence.*` intrinsics.
1408 // This does not correspond to any convergence control intrinsic. It is used
1409 // to glue a convergence control token to a convergent operation in the DAG,
1410 // which is later translated to an implicit use in the MIR.
1412
1413 // Experimental vector histogram intrinsic
1414 // Operands: Input Chain, Inc, Mask, Base, Index, Scale, ID
1415 // Output: Output Chain
1417
1418 // llvm.clear_cache intrinsic
1419 // Operands: Input Chain, Start Addres, End Address
1420 // Outputs: Output Chain
1422
1423 /// BUILTIN_OP_END - This must be the last enum value in this list.
1424 /// The target-specific pre-isel opcode values start here.
1427
1428/// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
1429/// which cannot raise FP exceptions should be less than this value.
1430/// Those that do must not be less than this value.
1432
1433/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
1434/// which do not reference a specific memory location should be less than
1435/// this value. Those that do must not be less than this value, and can
1436/// be used with SelectionDAG::getMemIntrinsicNode.
1438
1439/// Whether this is bitwise logic opcode.
1440inline bool isBitwiseLogicOp(unsigned Opcode) {
1441 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
1442}
1443
1444/// Get underlying scalar opcode for VECREDUCE opcode.
1445/// For example ISD::AND for ISD::VECREDUCE_AND.
1446NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);
1447
1448/// Whether this is a vector-predicated Opcode.
1449bool isVPOpcode(unsigned Opcode);
1450
1451/// Whether this is a vector-predicated binary operation opcode.
1452bool isVPBinaryOp(unsigned Opcode);
1453
1454/// Whether this is a vector-predicated reduction opcode.
1455bool isVPReduction(unsigned Opcode);
1456
1457/// The operand position of the vector mask.
1458std::optional<unsigned> getVPMaskIdx(unsigned Opcode);
1459
1460/// The operand position of the explicit vector length parameter.
1461std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
1462
1463/// Translate this VP Opcode to its corresponding non-VP Opcode.
1464std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept);
1465
1466/// Translate this non-VP Opcode to its corresponding VP Opcode.
1467unsigned getVPForBaseOpcode(unsigned Opcode);
1468
1469//===--------------------------------------------------------------------===//
1470/// MemIndexedMode enum - This enum defines the load / store indexed
1471/// addressing modes.
1472///
1473/// UNINDEXED "Normal" load / store. The effective address is already
1474/// computed and is available in the base pointer. The offset
1475/// operand is always undefined. In addition to producing a
1476/// chain, an unindexed load produces one value (result of the
1477/// load); an unindexed store does not produce a value.
1478///
1479/// PRE_INC Similar to the unindexed mode where the effective address is
1480/// PRE_DEC the value of the base pointer add / subtract the offset.
1481/// It considers the computation as being folded into the load /
1482/// store operation (i.e. the load / store does the address
1483/// computation as well as performing the memory transaction).
1484/// The base operand is always undefined. In addition to
1485/// producing a chain, pre-indexed load produces two values
1486/// (result of the load and the result of the address
1487/// computation); a pre-indexed store produces one value (result
1488/// of the address computation).
1489///
1490/// POST_INC The effective address is the value of the base pointer. The
1491/// POST_DEC value of the offset operand is then added to / subtracted
1492/// from the base after memory transaction. In addition to
1493/// producing a chain, post-indexed load produces two values
1494/// (the result of the load and the result of the base +/- offset
1495/// computation); a post-indexed store produces one value (the
1496/// the result of the base +/- offset computation).
1498
1499static const int LAST_INDEXED_MODE = POST_DEC + 1;
1500
1501//===--------------------------------------------------------------------===//
1502/// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
1503/// index parameter when calculating addresses.
1504///
1505/// SIGNED_SCALED Addr = Base + ((signed)Index * Scale)
1506/// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * Scale)
1507///
1508/// NOTE: The value of Scale is typically only known to the node owning the
1509/// IndexType, with a value of 1 the equivalent of being unscaled.
1511
1513
1514inline bool isIndexTypeSigned(MemIndexType IndexType) {
1515 return IndexType == SIGNED_SCALED;
1516}
1517
1518//===--------------------------------------------------------------------===//
1519/// LoadExtType enum - This enum defines the three variants of LOADEXT
1520/// (load with extension).
1521///
1522/// SEXTLOAD loads the integer operand and sign extends it to a larger
1523/// integer result type.
1524/// ZEXTLOAD loads the integer operand and zero extends it to a larger
1525/// integer result type.
1526/// EXTLOAD is used for two things: floating point extending loads and
1527/// integer extending loads [the top bits are undefined].
1529
1530static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
1531
1533
1534//===--------------------------------------------------------------------===//
1535/// ISD::CondCode enum - These are ordered carefully to make the bitfields
1536/// below work out, when considering SETFALSE (something that never exists
1537/// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
1538/// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
1539/// to. If the "N" column is 1, the result of the comparison is undefined if
1540/// the input is a NAN.
1541///
1542/// All of these (except for the 'always folded ops') should be handled for
1543/// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1544/// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1545///
1546/// Note that these are laid out in a specific order to allow bit-twiddling
1547/// to transform conditions.
1549 // Opcode N U L G E Intuitive operation
1550 SETFALSE, // 0 0 0 0 Always false (always folded)
1551 SETOEQ, // 0 0 0 1 True if ordered and equal
1552 SETOGT, // 0 0 1 0 True if ordered and greater than
1553 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
1554 SETOLT, // 0 1 0 0 True if ordered and less than
1555 SETOLE, // 0 1 0 1 True if ordered and less than or equal
1556 SETONE, // 0 1 1 0 True if ordered and operands are unequal
1557 SETO, // 0 1 1 1 True if ordered (no nans)
1558 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
1559 SETUEQ, // 1 0 0 1 True if unordered or equal
1560 SETUGT, // 1 0 1 0 True if unordered or greater than
1561 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
1562 SETULT, // 1 1 0 0 True if unordered or less than
1563 SETULE, // 1 1 0 1 True if unordered, less than, or equal
1564 SETUNE, // 1 1 1 0 True if unordered or not equal
1565 SETTRUE, // 1 1 1 1 Always true (always folded)
1566 // Don't care operations: undefined if the input is a nan.
1567 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
1568 SETEQ, // 1 X 0 0 1 True if equal
1569 SETGT, // 1 X 0 1 0 True if greater than
1570 SETGE, // 1 X 0 1 1 True if greater than or equal
1571 SETLT, // 1 X 1 0 0 True if less than
1572 SETLE, // 1 X 1 0 1 True if less than or equal
1573 SETNE, // 1 X 1 1 0 True if not equal
1574 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
1575
1576 SETCC_INVALID // Marker value.
1578
1579/// Return true if this is a setcc instruction that performs a signed
1580/// comparison when used with integer operands.
1581inline bool isSignedIntSetCC(CondCode Code) {
1582 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
1583}
1584
1585/// Return true if this is a setcc instruction that performs an unsigned
1586/// comparison when used with integer operands.
1587inline bool isUnsignedIntSetCC(CondCode Code) {
1588 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
1589}
1590
1591/// Return true if this is a setcc instruction that performs an equality
1592/// comparison when used with integer operands.
1593inline bool isIntEqualitySetCC(CondCode Code) {
1594 return Code == SETEQ || Code == SETNE;
1595}
1596
1597/// Return true if this is a setcc instruction that performs an equality
1598/// comparison when used with floating point operands.
1599inline bool isFPEqualitySetCC(CondCode Code) {
1600 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
1601}
1602
1603/// Return true if the specified condition returns true if the two operands to
1604/// the condition are equal. Note that if one of the two operands is a NaN,
1605/// this value is meaningless.
1606inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
1607
1608/// This function returns 0 if the condition is always false if an operand is
1609/// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1610/// the condition is undefined if the operand is a NaN.
1612 return ((int)Cond >> 3) & 3;
1613}
1614
1615/// Return the operation corresponding to !(X op Y), where 'op' is a valid
1616/// SetCC operation.
1618
1619inline bool isExtOpcode(unsigned Opcode) {
1620 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND ||
1621 Opcode == ISD::SIGN_EXTEND;
1622}
1623
1624inline bool isExtVecInRegOpcode(unsigned Opcode) {
1625 return Opcode == ISD::ANY_EXTEND_VECTOR_INREG ||
1628}
1629
1630namespace GlobalISel {
1631/// Return the operation corresponding to !(X op Y), where 'op' is a valid
1632/// SetCC operation. The U bit of the condition code has different meanings
1633/// between floating point and integer comparisons and LLT's don't provide
1634/// this distinction. As such we need to be told whether the comparison is
1635/// floating point or integer-like. Pointers should use integer-like
1636/// comparisons.
1637CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike);
1638} // end namespace GlobalISel
1639
1640/// Return the operation corresponding to (Y op X) when given the operation
1641/// for (X op Y).
1643
1644/// Return the result of a logical OR between different comparisons of
1645/// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1646/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1648
1649/// Return the result of a logical AND between different comparisons of
1650/// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1651/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1653
1654} // namespace ISD
1655
1656} // namespace llvm
1657
1658#endif
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:758
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:237
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1141
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1137
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:731
@ TargetConstantPool
Definition: ISDOpcodes.h:168
@ CONVERGENCECTRL_ANCHOR
Definition: ISDOpcodes.h:1405
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
Definition: ISDOpcodes.h:1186
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:478
@ ATOMIC_LOAD_FMAX
Definition: ISDOpcodes.h:1291
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
@ SET_FPENV
Sets the current floating-point environment.
Definition: ISDOpcodes.h:1013
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1354
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1385
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:147
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:499
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:251
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1284
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition: ISDOpcodes.h:561
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
Definition: ISDOpcodes.h:1075
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:722
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:368
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1170
@ TargetBlockAddress
Definition: ISDOpcodes.h:170
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1286
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:1256
@ STRICT_FCEIL
Definition: ISDOpcodes.h:428
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1287
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:270
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:124
@ RESET_FPENV
Set floating-point environment to default state.
Definition: ISDOpcodes.h:1017
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:489
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:994
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:240
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1046
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:374
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1036
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:791
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:485
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:199
@ RETURNADDR
Definition: ISDOpcodes.h:95
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:151
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1269
@ STRICT_FMINIMUM
Definition: ISDOpcodes.h:438
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:798
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:545
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1370
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:391
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
Definition: ISDOpcodes.h:1374
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:696
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
Definition: ISDOpcodes.h:1243
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1248
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
Definition: ISDOpcodes.h:1040
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:828
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:256
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1384
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:479
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:921
@ STRICT_FLOG2
Definition: ISDOpcodes.h:423
@ FPTRUNC_ROUND
Definition: ISDOpcodes.h:482
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1282
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:911
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:230
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1283
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:1214
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
Definition: ISDOpcodes.h:948
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:381
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:412
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1425
@ ATOMIC_LOAD_FADD
Definition: ISDOpcodes.h:1289
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
Definition: ISDOpcodes.h:1182
@ FrameIndex
Definition: ISDOpcodes.h:80
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1117
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1123
@ SET_ROUNDING
Set rounding mode.
Definition: ISDOpcodes.h:893
@ CONVERGENCECTRL_GLUE
Definition: ISDOpcodes.h:1411
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:782
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:664
@ STRICT_UINT_TO_FP
Definition: ISDOpcodes.h:452
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:622
@ PREALLOCATED_SETUP
Definition: ISDOpcodes.h:1175
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
Definition: ISDOpcodes.h:1203
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
Definition: ISDOpcodes.h:101
@ TargetExternalSymbol
Definition: ISDOpcodes.h:169
@ CONVERGENCECTRL_ENTRY
Definition: ISDOpcodes.h:1406
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:1062
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1367
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:730
@ TargetJumpTable
Definition: ISDOpcodes.h:167
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition: ISDOpcodes.h:177
@ WRITE_REGISTER
Definition: ISDOpcodes.h:119
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1236
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1371
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:1003
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:766
@ STRICT_LROUND
Definition: ISDOpcodes.h:433
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:938
@ ATOMIC_LOAD_FSUB
Definition: ISDOpcodes.h:1290
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1092
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:328
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1285
@ PREALLOCATED_ARG
Definition: ISDOpcodes.h:1178
@ BRIND
BRIND - Indirect branch.
Definition: ISDOpcodes.h:1067
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1071
@ GC_TRANSITION_START
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
Definition: ISDOpcodes.h:1328
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the same...
Definition: ISDOpcodes.h:588
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
Definition: ISDOpcodes.h:648
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:502
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:509
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:350
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:735
@ STRICT_FPOWI
Definition: ISDOpcodes.h:414
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:1252
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:212
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1386
@ RegisterMask
Definition: ISDOpcodes.h:75
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:223
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:629
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
Definition: ISDOpcodes.h:68
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1166
@ ATOMIC_LOAD_FMIN
Definition: ISDOpcodes.h:1292
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:209
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:324
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:164
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:432
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
Definition: ISDOpcodes.h:1240
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1379
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
Definition: ISDOpcodes.h:888
@ STRICT_FP_TO_FP16
Definition: ISDOpcodes.h:924
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:653
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1132
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1031
@ STRICT_FP16_TO_FP
Definition: ISDOpcodes.h:923
@ GET_FPENV
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1008
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:713
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1281
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:602
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1280
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition: ISDOpcodes.h:575
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
Definition: ISDOpcodes.h:993
@ STRICT_FMAXIMUM
Definition: ISDOpcodes.h:437
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:426
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:118
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:537
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:788
@ TargetConstantFP
Definition: ISDOpcodes.h:159
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1226
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:864
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:427
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:750
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
Definition: ISDOpcodes.h:1344
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1263
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1288
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition: ISDOpcodes.h:114
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:980
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1230
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:360
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:332
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1056
@ STRICT_LRINT
Definition: ISDOpcodes.h:435
@ TargetFrameIndex
Definition: ISDOpcodes.h:166
@ ConstantPool
Definition: ISDOpcodes.h:82
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:817
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:806
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:676
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
Definition: ISDOpcodes.h:593
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1319
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:387
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:896
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:87
@ STRICT_FROUND
Definition: ISDOpcodes.h:430
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:744
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:304
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition: ISDOpcodes.h:451
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
Definition: ISDOpcodes.h:1206
@ STRICT_BF16_TO_FP
Definition: ISDOpcodes.h:932
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1387
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
Definition: ISDOpcodes.h:1189
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:429
@ STRICT_FROUNDEVEN
Definition: ISDOpcodes.h:431
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1112
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:129
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
Definition: ISDOpcodes.h:930
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
@ ATOMIC_LOAD_UDEC_WRAP
Definition: ISDOpcodes.h:1294
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1278
@ STRICT_FP_TO_UINT
Definition: ISDOpcodes.h:445
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:467
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:444
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:999
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1279
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:844
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1197
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:158
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:472
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:688
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1223
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:184
@ GET_FPENV_MEM
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1022
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1339
@ STRICT_FP_TO_BF16
Definition: ISDOpcodes.h:933
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
Definition: ISDOpcodes.h:684
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition: ISDOpcodes.h:261
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:659
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1368
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:280
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:401
@ STRICT_FLOG10
Definition: ISDOpcodes.h:422
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
Definition: ISDOpcodes.h:638
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:526
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ STRICT_LLRINT
Definition: ISDOpcodes.h:436
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:614
@ STRICT_FEXP2
Definition: ISDOpcodes.h:420
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1277
@ ExternalSymbol
Definition: ISDOpcodes.h:83
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
Definition: ISDOpcodes.h:953
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:877
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
Definition: ISDOpcodes.h:106
@ STRICT_FLDEXP
Definition: ISDOpcodes.h:415
@ STRICT_LLROUND
Definition: ISDOpcodes.h:434
@ CONVERGENCECTRL_LOOP
Definition: ISDOpcodes.h:1407
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:839
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:915
@ EXPERIMENTAL_VECTOR_HISTOGRAM
Definition: ISDOpcodes.h:1416
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1109
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:425
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:863
@ VECREDUCE_FMINIMUM
Definition: ISDOpcodes.h:1375
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:141
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:794
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1161
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1085
@ BlockAddress
Definition: ISDOpcodes.h:84
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1355
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:771
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1128
@ GC_TRANSITION_END
Definition: ISDOpcodes.h:1329
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ ATOMIC_LOAD_UINC_WRAP
Definition: ISDOpcodes.h:1293
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:495
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:341
@ AssertZext
Definition: ISDOpcodes.h:62
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
Definition: ISDOpcodes.h:1155
@ STRICT_FRINT
Definition: ISDOpcodes.h:424
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the sa...
Definition: ISDOpcodes.h:582
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1335
@ SET_FPENV_MEM
Sets the current floating point environment.
Definition: ISDOpcodes.h:1027
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:1220
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:314
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:192
@ TargetGlobalTLSAddress
Definition: ISDOpcodes.h:165
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:517
bool isIndexTypeSigned(MemIndexType IndexType)
Definition: ISDOpcodes.h:1514
bool isExtVecInRegOpcode(unsigned Opcode)
Definition: ISDOpcodes.h:1624
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool isFPEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with floati...
Definition: ISDOpcodes.h:1599
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1437
bool isExtOpcode(unsigned Opcode)
Definition: ISDOpcodes.h:1619
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:1530
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isBitwiseLogicOp(unsigned Opcode)
Whether this is bitwise logic opcode.
Definition: ISDOpcodes.h:1440
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
Definition: ISDOpcodes.h:1606
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
static const int LAST_MEM_INDEX_TYPE
Definition: ISDOpcodes.h:1512
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
Definition: ISDOpcodes.h:1611
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
Definition: ISDOpcodes.h:1510
@ UNSIGNED_SCALED
Definition: ISDOpcodes.h:1510
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:1581
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1497
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1431
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1548
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1528
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
Definition: ISDOpcodes.h:1587
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1499
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
bool isIntEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with intege...
Definition: ISDOpcodes.h:1593
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Extended Value Type.
Definition: ValueTypes.h:34