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17 #ifndef LLVM_CODEGEN_MIRFSDISCRIMINATOR_H
18 #define LLVM_CODEGEN_MIRFSDISCRIMINATOR_H
29 class MachineFunction;
31 using namespace sampleprof;
44 assert(LowBit < HighBit &&
"HighBit needs to be greater than Lowbit");
48 return "Add FS discriminators in MIR";
52 unsigned getNumFSBBs();
67 #endif // LLVM_CODEGEN_MIRFSDISCRIMINATOR_H
MIRAddFSDiscriminators(FSDiscriminatorPass P=FSDiscriminatorPass::Pass1)
PassNum is the sequence number this pass is called, start from 1.
static unsigned getFSPassBitBegin(FSDiscriminatorPass P)
This is an optimization pass for GlobalISel generic memory operations.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
const MachineFunction * getMachineFunction() const
getMachineFunction - Return the current machine function.
static unsigned getFSPassBitEnd(FSDiscriminatorPass P)