LLVM  14.0.0git
Macros | Variables
RISCVSubtarget.cpp File Reference
#include "RISCVSubtarget.h"
#include "RISCV.h"
#include "RISCVCallLowering.h"
#include "RISCVFrameLowering.h"
#include "RISCVLegalizerInfo.h"
#include "RISCVRegisterBankInfo.h"
#include "RISCVTargetMachine.h"
#include "llvm/Support/TargetRegistry.h"
#include "RISCVGenSubtargetInfo.inc"
Include dependency graph for RISCVSubtarget.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-subtarget"
 
#define GET_SUBTARGETINFO_TARGET_DESC
 
#define GET_SUBTARGETINFO_CTOR
 

Variables

static cl::opt< unsigned > RVVVectorBitsMax ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
 
static cl::opt< unsigned > RVVVectorBitsMin ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
 
static cl::opt< unsigned > RVVVectorLMULMax ("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
 
static cl::opt< unsigned > RVVVectorELENMax ("riscv-v-fixed-length-vector-elen-max", cl::desc("The maximum ELEN value to use for fixed length vectors."), cl::init(64), cl::Hidden)
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-subtarget"

Definition at line 24 of file RISCVSubtarget.cpp.

◆ GET_SUBTARGETINFO_CTOR

#define GET_SUBTARGETINFO_CTOR

Definition at line 27 of file RISCVSubtarget.cpp.

◆ GET_SUBTARGETINFO_TARGET_DESC

#define GET_SUBTARGETINFO_TARGET_DESC

Definition at line 26 of file RISCVSubtarget.cpp.

Variable Documentation

◆ RVVVectorBitsMax

cl::opt<unsigned> RVVVectorBitsMax("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static

◆ RVVVectorBitsMin

cl::opt<unsigned> RVVVectorBitsMin("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
static

◆ RVVVectorELENMax

cl::opt<unsigned> RVVVectorELENMax("riscv-v-fixed-length-vector-elen-max", cl::desc("The maximum ELEN value to use for fixed length vectors."), cl::init(64), cl::Hidden)
static

◆ RVVVectorLMULMax

cl::opt<unsigned> RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
static