LLVM  15.0.0git
RISCVSubtarget.cpp
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1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/MC/TargetRegistry.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "riscv-subtarget"
26 
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "RISCVGenSubtargetInfo.inc"
30 
31 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
32  cl::init(false), cl::Hidden);
33 
35  "riscv-v-vector-bits-max",
36  cl::desc("Assume V extension vector registers are at most this big, "
37  "with zero meaning no maximum size is assumed."),
38  cl::init(0), cl::Hidden);
39 
41  "riscv-v-vector-bits-min",
42  cl::desc("Assume V extension vector registers are at least this big, "
43  "with zero meaning no minimum size is assumed. A value of -1 "
44  "means use Zvl*b extension. This is primarily used to enable "
45  "autovectorization with fixed width vectors."),
46  cl::init(0), cl::Hidden);
47 
49  "riscv-v-fixed-length-vector-lmul-max",
50  cl::desc("The maximum LMUL value to use for fixed length vectors. "
51  "Fractional LMUL values are not supported."),
52  cl::init(8), cl::Hidden);
53 
55  "riscv-disable-using-constant-pool-for-large-ints",
56  cl::desc("Disable using constant pool for large integers."),
57  cl::init(false), cl::Hidden);
58 
60  "riscv-max-build-ints-cost",
61  cl::desc("The maximum cost used for building integers."), cl::init(0),
62  cl::Hidden);
63 
64 void RISCVSubtarget::anchor() {}
65 
67 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
68  StringRef TuneCPU, StringRef FS,
69  StringRef ABIName) {
70  // Determine default and user-specified characteristics
71  bool Is64Bit = TT.isArch64Bit();
72  if (CPU.empty() || CPU == "generic")
73  CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
74 
75  if (TuneCPU.empty())
76  TuneCPU = CPU;
77 
78  ParseSubtargetFeatures(CPU, TuneCPU, FS);
79  if (Is64Bit) {
80  XLenVT = MVT::i64;
81  XLen = 64;
82  }
83 
84  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
85  RISCVFeatures::validate(TT, getFeatureBits());
86  return *this;
87 }
88 
90  StringRef TuneCPU, StringRef FS,
91  StringRef ABIName, const TargetMachine &TM)
92  : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
93  UserReservedRegister(RISCV::NUM_TARGET_REGS),
94  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
95  InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
97  Legalizer.reset(new RISCVLegalizerInfo(*this));
98 
99  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
100  RegBankInfo.reset(RBI);
102  *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
103 }
104 
106  return CallLoweringInfo.get();
107 }
108 
110  return InstSelector.get();
111 }
112 
114  return Legalizer.get();
115 }
116 
118  return RegBankInfo.get();
119 }
120 
123 }
124 
126  // Loading integer from constant pool needs two instructions (the reason why
127  // the minimum cost is 2): an address calculation instruction and a load
128  // instruction. Usually, address calculation and instructions used for
129  // building integers (addi, slli, etc.) can be done in one cycle, so here we
130  // set the default cost to (LoadLatency + 1) if no threshold is provided.
131  return RISCVMaxBuildIntsCost == 0
132  ? getSchedModel().LoadLatency + 1
133  : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
134 }
135 
138  "Tried to get vector length without Zve or V extension support!");
139  if (RVVVectorBitsMax == 0)
140  return 0;
141 
142  // ZvlLen specifies the minimum required vlen. The upper bound provided by
143  // riscv-v-vector-bits-max should be no less than it.
144  if (RVVVectorBitsMax < (int)ZvlLen)
145  report_fatal_error("riscv-v-vector-bits-max specified is lower "
146  "than the Zvl*b limitation");
147 
148  // FIXME: Change to >= 32 when VLEN = 32 is supported
149  assert(
150  RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
152  "V or Zve* extension requires vector length to be in the range of 64 to "
153  "65536 and a power of 2!");
155  "Minimum V extension vector length should not be larger than its "
156  "maximum!");
157  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
158  return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
159 }
160 
163  "Tried to get vector length without Zve or V extension support!");
164 
165  if (RVVVectorBitsMin == -1)
166  return ZvlLen;
167 
168  // ZvlLen specifies the minimum required vlen. The lower bound provided by
169  // riscv-v-vector-bits-min should be no less than it.
170  if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < (int)ZvlLen)
171  report_fatal_error("riscv-v-vector-bits-min specified is lower "
172  "than the Zvl*b limitation");
173 
174  // FIXME: Change to >= 32 when VLEN = 32 is supported
175  assert(
176  (RVVVectorBitsMin == 0 ||
177  (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
179  "V or Zve* extension requires vector length to be in the range of 64 to "
180  "65536 and a power of 2!");
182  "Minimum V extension vector length should not be larger than its "
183  "maximum!");
184  unsigned Min = RVVVectorBitsMin;
185  if (RVVVectorBitsMax != 0)
187  return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
188 }
189 
192  "Tried to get vector length without Zve or V extension support!");
194  "V extension requires a LMUL to be at most 8 and a power of 2!");
195  return PowerOf2Floor(
196  std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
197 }
198 
200  return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
201 }
202 
204  // TODO: Enable for for RVV to better handle LMUL>1 and segment load/store.
205  return EnableSubRegLiveness;
206 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARM::PredBlockMask::TT
@ TT
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:199
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:131
RISCVLegalizerInfo.h
llvm::RISCVRegisterBankInfo
This class provides the information for the target register banks.
Definition: RISCVRegisterBankInfo.h:32
RISCVDisableUsingConstantPoolForLargeInts
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:217
ErrorHandling.h
llvm::RISCVSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: RISCVSubtarget.cpp:203
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:105
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:232
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:89
llvm::RISCVCallLowering
Definition: RISCVCallLowering.h:25
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:722
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("riscv-enable-subreg-liveness", cl::init(false), cl::Hidden)
llvm::Legalizer
Definition: Legalizer.h:36
RVVVectorBitsMin
static cl::opt< int > RVVVectorBitsMin("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(0), cl::Hidden)
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::createRISCVInstructionSelector
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
Definition: RISCVInstructionSelector.cpp:98
llvm::cl::opt< bool >
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:136
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::RISCVSubtarget::getMaxBuildIntsCost
unsigned getMaxBuildIntsCost() const
Definition: RISCVSubtarget.cpp:125
RISCVCallLowering.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:190
RISCV.h
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:117
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:128
RVVVectorLMULMax
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
RVVVectorBitsMax
static cl::opt< int > RVVVectorBitsMax("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:233
llvm::RISCVLegalizerInfo
This class provides the information for the target register banks.
Definition: RISCVLegalizerInfo.h:23
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:37
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:113
RISCVSubtarget.h
RISCVFrameLowering.h
RISCVGenSubtargetInfo
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:235
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
RISCVMaxBuildIntsCost
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:161
llvm::cl::desc
Definition: CommandLine.h:405
llvm::X86AS::FS
@ FS
Definition: X86.h:188
TargetRegistry.h
llvm::CallLowering
Definition: CallLowering.h:44
llvm::RISCVSubtarget::useConstantPoolForLargeInts
bool useConstantPoolForLargeInts() const
Definition: RISCVSubtarget.cpp:121
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:109
RISCVRegisterBankInfo.h
RISCVTargetMachine.h