LLVM  14.0.0git
RISCVSubtarget.cpp
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1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "riscv-subtarget"
25 
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "RISCVGenSubtargetInfo.inc"
29 
31  "riscv-v-vector-bits-max",
32  cl::desc("Assume V extension vector registers are at most this big, "
33  "with zero meaning no maximum size is assumed."),
34  cl::init(0), cl::Hidden);
35 
37  "riscv-v-vector-bits-min",
38  cl::desc("Assume V extension vector registers are at least this big, "
39  "with zero meaning no minimum size is assumed."),
40  cl::init(0), cl::Hidden);
41 
43  "riscv-v-fixed-length-vector-lmul-max",
44  cl::desc("The maximum LMUL value to use for fixed length vectors. "
45  "Fractional LMUL values are not supported."),
46  cl::init(8), cl::Hidden);
47 
49  "riscv-v-fixed-length-vector-elen-max",
50  cl::desc("The maximum ELEN value to use for fixed length vectors."),
51  cl::init(64), cl::Hidden);
52 
53 void RISCVSubtarget::anchor() {}
54 
56 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
57  StringRef TuneCPU, StringRef FS,
58  StringRef ABIName) {
59  // Determine default and user-specified characteristics
60  bool Is64Bit = TT.isArch64Bit();
61  if (CPU.empty())
62  CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
63  if (CPU == "generic")
64  report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
65  (Is64Bit ? "generic-rv64" : "generic-rv32"));
66 
67  if (TuneCPU.empty())
68  TuneCPU = CPU;
69 
70  ParseSubtargetFeatures(CPU, TuneCPU, FS);
71  if (Is64Bit) {
72  XLenVT = MVT::i64;
73  XLen = 64;
74  }
75 
76  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
77  RISCVFeatures::validate(TT, getFeatureBits());
78  return *this;
79 }
80 
82  StringRef TuneCPU, StringRef FS,
83  StringRef ABIName, const TargetMachine &TM)
84  : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
85  UserReservedRegister(RISCV::NUM_TARGET_REGS),
86  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
87  InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
89  Legalizer.reset(new RISCVLegalizerInfo(*this));
90 
91  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
92  RegBankInfo.reset(RBI);
94  *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
95 }
96 
98  return CallLoweringInfo.get();
99 }
100 
102  return InstSelector.get();
103 }
104 
106  return Legalizer.get();
107 }
108 
110  return RegBankInfo.get();
111 }
112 
114  assert(hasStdExtV() && "Tried to get vector length without V support!");
115  if (RVVVectorBitsMax == 0)
116  return 0;
117  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
119  "V extension requires vector length to be in the range of 128 to "
120  "65536 and a power of 2!");
122  "Minimum V extension vector length should not be larger than its "
123  "maximum!");
124  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
125  return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
126 }
127 
129  assert(hasStdExtV() &&
130  "Tried to get vector length without V extension support!");
131  assert((RVVVectorBitsMin == 0 ||
132  (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
134  "V extension requires vector length to be in the range of 128 to "
135  "65536 and a power of 2!");
137  "Minimum V extension vector length should not be larger than its "
138  "maximum!");
139  unsigned Min = RVVVectorBitsMin;
140  if (RVVVectorBitsMax != 0)
142  return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
143 }
144 
146  assert(hasStdExtV() &&
147  "Tried to get maximum LMUL without V extension support!");
149  "V extension requires a LMUL to be at most 8 and a power of 2!");
150  return PowerOf2Floor(
151  std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
152 }
153 
155  assert(hasStdExtV() &&
156  "Tried to get maximum ELEN without V extension support!");
157  assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 &&
159  "V extension requires a ELEN to be a power of 2 between 8 and 64!");
160  return PowerOf2Floor(
161  std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, 64), 8));
162 }
163 
165  return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
166 }
RVVVectorBitsMax
static cl::opt< unsigned > RVVVectorBitsMax("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::ARM::PredBlockMask::TT
@ TT
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:164
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:98
RVVVectorBitsMin
static cl::opt< unsigned > RVVVectorBitsMin("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
RISCVLegalizerInfo.h
llvm::RISCVRegisterBankInfo
This class provides the information for the target register banks.
Definition: RISCVRegisterBankInfo.h:32
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:97
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:144
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:90
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:81
llvm::RISCVCallLowering
Definition: RISCVCallLowering.h:25
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:695
llvm::RISCVSubtarget::getMaxELENForFixedLengthVectors
unsigned getMaxELENForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:154
llvm::Legalizer
Definition: Legalizer.h:31
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::createRISCVInstructionSelector
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
Definition: RISCVInstructionSelector.cpp:99
llvm::cl::opt
Definition: CommandLine.h:1434
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:113
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
RISCVCallLowering.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:145
RISCV.h
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:109
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:95
RVVVectorELENMax
static cl::opt< unsigned > RVVVectorELENMax("riscv-v-fixed-length-vector-elen-max", cl::desc("The maximum ELEN value to use for fixed length vectors."), cl::init(64), cl::Hidden)
RVVVectorLMULMax
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:145
llvm::RISCVLegalizerInfo
This class provides the information for the target register banks.
Definition: RISCVLegalizerInfo.h:23
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:26
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:105
RISCVSubtarget.h
RISCVFrameLowering.h
RISCVGenSubtargetInfo
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:147
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1110
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:128
llvm::cl::desc
Definition: CommandLine.h:414
TargetRegistry.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:122
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:101
RISCVRegisterBankInfo.h
RISCVTargetMachine.h