LLVM 20.0.0git
RISCVSubtarget.h
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1//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15
18#include "RISCVFrameLowering.h"
19#include "RISCVISelLowering.h"
20#include "RISCVInstrInfo.h"
26#include "llvm/IR/DataLayout.h"
28#include <bitset>
29
30#define GET_RISCV_MACRO_FUSION_PRED_DECL
31#include "RISCVGenMacroFusion.inc"
32
33#define GET_SUBTARGETINFO_HEADER
34#include "RISCVGenSubtargetInfo.inc"
35
36namespace llvm {
37class StringRef;
38
39namespace RISCVTuneInfoTable {
40
42 const char *Name;
45
46 // Information needed by LoopDataPrefetch.
51
53
54 // Tail duplication threshold at -O3.
56};
57
58#define GET_RISCVTuneInfoTable_DECL
59#include "RISCVGenSearchableTables.inc"
60} // namespace RISCVTuneInfoTable
61
63public:
64 // clang-format off
65 enum RISCVProcFamilyEnum : uint8_t {
69 };
70 // clang-format on
71private:
72 virtual void anchor();
73
74 RISCVProcFamilyEnum RISCVProcFamily = Others;
75
76#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
77 bool ATTRIBUTE = DEFAULT;
78#include "RISCVGenSubtargetInfo.inc"
79
80 unsigned ZvlLen = 0;
81 unsigned RVVVectorBitsMin;
82 unsigned RVVVectorBitsMax;
83 uint8_t MaxInterleaveFactor = 2;
85 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
87
88 RISCVFrameLowering FrameLowering;
89 RISCVInstrInfo InstrInfo;
93
94 /// Initializes using the passed in CPU and feature strings so that we can
95 /// use initializer lists for subtarget initialization.
96 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
97 StringRef CPU,
98 StringRef TuneCPU,
99 StringRef FS,
100 StringRef ABIName);
101
102public:
103 // Initializes the data members to match that of the specified triple.
104 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
105 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
106 unsigned RVVVectorLMULMax, const TargetMachine &TM);
107
108 // Parses features string setting specified subtarget options. The
109 // definition of this function is auto-generated by tblgen.
111
112 const RISCVFrameLowering *getFrameLowering() const override {
113 return &FrameLowering;
114 }
115 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
116 const RISCVRegisterInfo *getRegisterInfo() const override {
117 return &RegInfo;
118 }
119 const RISCVTargetLowering *getTargetLowering() const override {
120 return &TLInfo;
121 }
123 return &TSInfo;
124 }
125 bool enableMachineScheduler() const override { return true; }
126
127 bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
128
130 return Align(TuneInfo->PrefFunctionAlignment);
131 }
133 return Align(TuneInfo->PrefLoopAlignment);
134 }
135
136 /// Returns RISC-V processor family.
137 /// Avoid this function! CPU specifics should be kept local to this class
138 /// and preferably modeled with SubtargetFeatures or properties in
139 /// initializeProperties().
140 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
141
142#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
143 bool GETTER() const { return ATTRIBUTE; }
144#include "RISCVGenSubtargetInfo.inc"
145
146 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
147 bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
148 bool hasStdExtCOrZcfOrZce() const {
149 return HasStdExtC || HasStdExtZcf || HasStdExtZce;
150 }
151 bool hasStdExtZvl() const { return ZvlLen != 0; }
152 bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
153 bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
154 bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
156 return HasStdExtZfhmin || HasStdExtZhinxmin;
157 }
159 return HasStdExtZfhmin || HasStdExtZfbfmin;
160 }
161
163 // Do we support fusing a branch+mv or branch+c.mv as a conditional move.
164 return (hasConditionalCompressedMoveFusion() && hasStdExtCOrZca()) ||
165 hasShortForwardBranchOpt();
166 }
167
168 bool is64Bit() const { return IsRV64; }
169 MVT getXLenVT() const {
170 return is64Bit() ? MVT::i64 : MVT::i32;
171 }
172 unsigned getXLen() const {
173 return is64Bit() ? 64 : 32;
174 }
175 unsigned getFLen() const {
176 if (HasStdExtD)
177 return 64;
178
179 if (HasStdExtF)
180 return 32;
181
182 return 0;
183 }
184 unsigned getELen() const {
185 assert(hasVInstructions() && "Expected V extension");
186 return hasVInstructionsI64() ? 64 : 32;
187 }
188 unsigned getRealMinVLen() const {
189 unsigned VLen = getMinRVVVectorSizeInBits();
190 return VLen == 0 ? ZvlLen : VLen;
191 }
192 unsigned getRealMaxVLen() const {
193 unsigned VLen = getMaxRVVVectorSizeInBits();
194 return VLen == 0 ? 65536 : VLen;
195 }
196 // If we know the exact VLEN, return it. Otherwise, return std::nullopt.
197 std::optional<unsigned> getRealVLen() const {
198 unsigned Min = getRealMinVLen();
199 if (Min != getRealMaxVLen())
200 return std::nullopt;
201 return Min;
202 }
203
204 /// If the ElementCount or TypeSize \p X is scalable and VScale (VLEN) is
205 /// exactly known, returns \p X converted to a fixed quantity. Otherwise
206 /// returns \p X unmodified.
207 template <typename Quantity> Quantity expandVScale(Quantity X) const {
208 if (auto VLen = getRealVLen(); VLen && X.isScalable()) {
209 const unsigned VScale = *VLen / RISCV::RVVBitsPerBlock;
210 X = Quantity::getFixed(X.getKnownMinValue() * VScale);
211 }
212 return X;
213 }
214
215 RISCVABI::ABI getTargetABI() const { return TargetABI; }
216 bool isSoftFPABI() const {
217 return TargetABI == RISCVABI::ABI_LP64 ||
218 TargetABI == RISCVABI::ABI_ILP32 ||
219 TargetABI == RISCVABI::ABI_ILP32E;
220 }
222 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
223 return UserReservedRegister[i];
224 }
225
226 // Vector codegen related methods.
227 bool hasVInstructions() const { return HasStdExtZve32x; }
228 bool hasVInstructionsI64() const { return HasStdExtZve64x; }
229 bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
230 bool hasVInstructionsF16() const { return HasStdExtZvfh; }
231 bool hasVInstructionsBF16Minimal() const { return HasStdExtZvfbfmin; }
232 bool hasVInstructionsF32() const { return HasStdExtZve32f; }
233 bool hasVInstructionsF64() const { return HasStdExtZve64d; }
234 // F16 and F64 both require F32.
235 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
236 bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
237 unsigned getMaxInterleaveFactor() const {
238 return hasVInstructions() ? MaxInterleaveFactor : 1;
239 }
240
241 // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
242 // vector hardware implementation which may be less than VLEN.
243 unsigned getDLenFactor() const {
244 if (DLenFactor2)
245 return 2;
246 return 1;
247 }
248
249protected:
250 // GlobalISel related APIs.
251 mutable std::unique_ptr<CallLowering> CallLoweringInfo;
252 mutable std::unique_ptr<InstructionSelector> InstSelector;
253 mutable std::unique_ptr<LegalizerInfo> Legalizer;
254 mutable std::unique_ptr<RISCVRegisterBankInfo> RegBankInfo;
255
256 // Return the known range for the bit length of RVV data registers as set
257 // at the command line. A value of 0 means nothing is known about that particular
258 // limit beyond what's implied by the architecture.
259 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
260 unsigned getMaxRVVVectorSizeInBits() const;
261 unsigned getMinRVVVectorSizeInBits() const;
262
263public:
264 const CallLowering *getCallLowering() const override;
266 const LegalizerInfo *getLegalizerInfo() const override;
267 const RISCVRegisterBankInfo *getRegBankInfo() const override;
268
269 bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }
270 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
271
272 bool useConstantPoolForLargeInts() const;
273
274 // Maximum cost used for building integers, integers will be put into constant
275 // pool if exceeded.
276 unsigned getMaxBuildIntsCost() const;
277
278 unsigned getMaxLMULForFixedLengthVectors() const;
279 bool useRVVForFixedLengthVectors() const;
280
281 bool enableSubRegLiveness() const override;
282
283 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
284 &Mutations) const override;
285
286 bool useAA() const override;
287
288 unsigned getCacheLineSize() const override {
289 return TuneInfo->CacheLineSize;
290 };
291 unsigned getPrefetchDistance() const override {
292 return TuneInfo->PrefetchDistance;
293 };
294 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
295 unsigned NumStridedMemAccesses,
296 unsigned NumPrefetches,
297 bool HasCall) const override {
298 return TuneInfo->MinPrefetchStride;
299 };
300 unsigned getMaxPrefetchIterationsAhead() const override {
301 return TuneInfo->MaxPrefetchIterationsAhead;
302 };
303
304 unsigned getMinimumJumpTableEntries() const;
305
307 return TuneInfo->TailDupAggressiveThreshold;
308 }
309
310 bool supportsInitUndef() const override { return hasVInstructions(); }
311};
312} // End llvm namespace
313
314#endif
This file describes how to lower LLVM calls to machine code calls.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
This file declares the targeting of the RegisterBankInfo class for RISC-V.
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Machine Value Type.
This class provides the information for the target register banks.
RISCVABI::ABI getTargetABI() const
unsigned getMinimumJumpTableEntries() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
unsigned getMaxPrefetchIterationsAhead() const override
bool hasVInstructionsF64() const
bool hasStdExtDOrZdinx() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasStdExtZfhOrZhinx() const
unsigned getTailDupAggressiveThreshold() const
unsigned getRealMinVLen() const
Quantity expandVScale(Quantity X) const
If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted...
bool useRVVForFixedLengthVectors() const
bool isTargetFuchsia() const
bool hasVInstructionsBF16Minimal() const
unsigned getDLenFactor() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasVInstructionsF16Minimal() const
unsigned getXLen() const
bool hasConditionalMoveFusion() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
const RISCVRegisterBankInfo * getRegBankInfo() const override
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool hasVInstructionsAnyF() const
std::optional< unsigned > getRealVLen() const
bool useConstantPoolForLargeInts() const
bool hasStdExtCOrZcfOrZce() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISC-V processor family.
unsigned getMaxRVVVectorSizeInBits() const
bool hasStdExtZfhminOrZhinxmin() const
unsigned getRealMaxVLen() const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVRegisterInfo * getRegisterInfo() const override
std::unique_ptr< RISCVRegisterBankInfo > RegBankInfo
const RISCVInstrInfo * getInstrInfo() const override
unsigned getCacheLineSize() const override
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasStdExtCOrZcd() const
bool hasVInstructionsFullMultiply() const
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool supportsInitUndef() const override
bool enableSubRegLiveness() const override
unsigned getELen() const
bool isTargetAndroid() const
bool hasStdExtFOrZfinx() const
bool enablePostRAScheduler() const override
bool hasStdExtZvl() const
bool isSoftFPABI() const
bool hasHalfFPLoadStoreMove() const
const RISCVFrameLowering * getFrameLowering() const override
unsigned getFLen() const
unsigned getPrefetchDistance() const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static constexpr unsigned RVVBitsPerBlock
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39