LLVM 18.0.0git
RISCVSubtarget.h
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1//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15
17#include "RISCVFrameLowering.h"
18#include "RISCVISelLowering.h"
19#include "RISCVInstrInfo.h"
26#include "llvm/IR/DataLayout.h"
28
29#define GET_SUBTARGETINFO_HEADER
30#include "RISCVGenSubtargetInfo.inc"
31
32namespace llvm {
33class StringRef;
34
35namespace RISCVTuneInfoTable {
36
38 const char *Name;
41
42 // Information needed by LoopDataPrefetch.
47
49};
50
51#define GET_RISCVTuneInfoTable_DECL
52#include "RISCVGenSearchableTables.inc"
53} // namespace RISCVTuneInfoTable
54
56public:
57 // clang-format off
58 enum RISCVProcFamilyEnum : uint8_t {
62 };
63 // clang-format on
64private:
65 virtual void anchor();
66
67 RISCVProcFamilyEnum RISCVProcFamily = Others;
68
69#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
70 bool ATTRIBUTE = DEFAULT;
71#include "RISCVGenSubtargetInfo.inc"
72
73 unsigned ZvlLen = 0;
74 unsigned RVVVectorBitsMin;
75 unsigned RVVVectorBitsMax;
76 uint8_t MaxInterleaveFactor = 2;
78 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
80
81 RISCVFrameLowering FrameLowering;
82 RISCVInstrInfo InstrInfo;
86
87 /// Initializes using the passed in CPU and feature strings so that we can
88 /// use initializer lists for subtarget initialization.
89 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
90 StringRef CPU,
91 StringRef TuneCPU,
92 StringRef FS,
93 StringRef ABIName);
94
95public:
96 // Initializes the data members to match that of the specified triple.
97 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
98 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
99 unsigned RVVVectorLMULMax, const TargetMachine &TM);
100
101 // Parses features string setting specified subtarget options. The
102 // definition of this function is auto-generated by tblgen.
104
105 const RISCVFrameLowering *getFrameLowering() const override {
106 return &FrameLowering;
107 }
108 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
109 const RISCVRegisterInfo *getRegisterInfo() const override {
110 return &RegInfo;
111 }
112 const RISCVTargetLowering *getTargetLowering() const override {
113 return &TLInfo;
114 }
116 return &TSInfo;
117 }
118 bool enableMachineScheduler() const override { return true; }
119
120 bool enablePostRAScheduler() const override {
121 return getSchedModel().PostRAScheduler || UsePostRAScheduler;
122 }
123
125 return Align(TuneInfo->PrefFunctionAlignment);
126 }
128 return Align(TuneInfo->PrefLoopAlignment);
129 }
130
131 /// Returns RISC-V processor family.
132 /// Avoid this function! CPU specifics should be kept local to this class
133 /// and preferably modeled with SubtargetFeatures or properties in
134 /// initializeProperties().
135 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
136
137#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
138 bool GETTER() const { return ATTRIBUTE; }
139#include "RISCVGenSubtargetInfo.inc"
140
141 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
142 bool hasStdExtZvl() const { return ZvlLen != 0; }
143 bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
144 bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
145 bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
146 bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
148 return HasStdExtZhinx || HasStdExtZhinxmin;
149 }
152 }
154 return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
155 }
156 bool is64Bit() const { return IsRV64; }
157 MVT getXLenVT() const {
158 return is64Bit() ? MVT::i64 : MVT::i32;
159 }
160 unsigned getXLen() const {
161 return is64Bit() ? 64 : 32;
162 }
163 unsigned getFLen() const {
164 if (HasStdExtD)
165 return 64;
166
167 if (HasStdExtF)
168 return 32;
169
170 return 0;
171 }
172 unsigned getELen() const {
173 assert(hasVInstructions() && "Expected V extension");
174 return hasVInstructionsI64() ? 64 : 32;
175 }
176 unsigned getRealMinVLen() const {
177 unsigned VLen = getMinRVVVectorSizeInBits();
178 return VLen == 0 ? ZvlLen : VLen;
179 }
180 unsigned getRealMaxVLen() const {
181 unsigned VLen = getMaxRVVVectorSizeInBits();
182 return VLen == 0 ? 65536 : VLen;
183 }
184 RISCVABI::ABI getTargetABI() const { return TargetABI; }
185 bool isSoftFPABI() const {
186 return TargetABI == RISCVABI::ABI_LP64 ||
187 TargetABI == RISCVABI::ABI_ILP32 ||
188 TargetABI == RISCVABI::ABI_ILP32E;
189 }
191 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
192 return UserReservedRegister[i];
193 }
194
195 bool hasMacroFusion() const { return hasLUIADDIFusion(); }
196
197 // Vector codegen related methods.
198 bool hasVInstructions() const { return HasStdExtZve32x; }
199 bool hasVInstructionsI64() const { return HasStdExtZve64x; }
201 return HasStdExtZvfhmin || HasStdExtZvfh;
202 }
203 bool hasVInstructionsF16() const { return HasStdExtZvfh; }
204 bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
205 bool hasVInstructionsF32() const { return HasStdExtZve32f; }
206 bool hasVInstructionsF64() const { return HasStdExtZve64d; }
207 // F16 and F64 both require F32.
208 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
209 bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
210 unsigned getMaxInterleaveFactor() const {
211 return hasVInstructions() ? MaxInterleaveFactor : 1;
212 }
213
214 // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
215 // vector hardware implementation which may be less than VLEN.
216 unsigned getDLenFactor() const {
217 if (DLenFactor2)
218 return 2;
219 return 1;
220 }
221
222protected:
223 // GlobalISel related APIs.
224 std::unique_ptr<CallLowering> CallLoweringInfo;
225 std::unique_ptr<InstructionSelector> InstSelector;
226 std::unique_ptr<LegalizerInfo> Legalizer;
227 std::unique_ptr<RegisterBankInfo> RegBankInfo;
228
229 // Return the known range for the bit length of RVV data registers as set
230 // at the command line. A value of 0 means nothing is known about that particular
231 // limit beyond what's implied by the architecture.
232 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
233 unsigned getMaxRVVVectorSizeInBits() const;
234 unsigned getMinRVVVectorSizeInBits() const;
235
236public:
237 const CallLowering *getCallLowering() const override;
239 const LegalizerInfo *getLegalizerInfo() const override;
240 const RegisterBankInfo *getRegBankInfo() const override;
241
242 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
243
244 bool useConstantPoolForLargeInts() const;
245
246 // Maximum cost used for building integers, integers will be put into constant
247 // pool if exceeded.
248 unsigned getMaxBuildIntsCost() const;
249
250 unsigned getMaxLMULForFixedLengthVectors() const;
251 bool useRVVForFixedLengthVectors() const;
252
253 bool enableSubRegLiveness() const override;
254
255 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
256 &Mutations) const override;
257
258 bool useAA() const override;
259
260 unsigned getCacheLineSize() const override {
261 return TuneInfo->CacheLineSize;
262 };
263 unsigned getPrefetchDistance() const override {
264 return TuneInfo->PrefetchDistance;
265 };
266 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
267 unsigned NumStridedMemAccesses,
268 unsigned NumPrefetches,
269 bool HasCall) const override {
270 return TuneInfo->MinPrefetchStride;
271 };
272 unsigned getMaxPrefetchIterationsAhead() const override {
273 return TuneInfo->MaxPrefetchIterationsAhead;
274 };
275
276 unsigned getMinimumJumpTableEntries() const;
277};
278} // End llvm namespace
279
280#endif
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Machine Value Type.
RISCVABI::ABI getTargetABI() const
unsigned getMinimumJumpTableEntries() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
unsigned getMaxPrefetchIterationsAhead() const override
bool hasVInstructionsF64() const
bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const
bool hasStdExtDOrZdinx() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasStdExtZfhOrZhinx() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool isTargetFuchsia() const
unsigned getDLenFactor() const
bool hasMacroFusion() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasStdExtZfhOrZfhmin() const
bool hasVInstructionsF16Minimal() const
unsigned getXLen() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
bool hasVInstructionsBF16() const
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool hasVInstructionsAnyF() const
bool useConstantPoolForLargeInts() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISC-V processor family.
unsigned getMaxRVVVectorSizeInBits() const
unsigned getRealMaxVLen() const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
bool hasStdExtZhinxOrZhinxmin() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
unsigned getCacheLineSize() const override
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasVInstructionsFullMultiply() const
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool enableSubRegLiveness() const override
unsigned getELen() const
bool hasStdExtFOrZfinx() const
bool enablePostRAScheduler() const override
bool hasStdExtZvl() const
bool isSoftFPABI() const
bool hasHalfFPLoadStoreMove() const
const RISCVFrameLowering * getFrameLowering() const override
unsigned getFLen() const
unsigned getPrefetchDistance() const override
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39