LLVM  16.0.0git
RISCVSubtarget.h
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1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
17 #include "RISCVFrameLowering.h"
18 #include "RISCVISelLowering.h"
19 #include "RISCVInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
36 public:
37  enum RISCVProcFamilyEnum : uint8_t {
40  };
41 
42 private:
43  virtual void anchor();
44 
45  RISCVProcFamilyEnum RISCVProcFamily = Others;
46 
47  bool HasStdExtM = false;
48  bool HasStdExtA = false;
49  bool HasStdExtF = false;
50  bool HasStdExtD = false;
51  bool HasStdExtC = false;
52  bool HasStdExtZihintpause = false;
53  bool HasStdExtZihintntl = false;
54  bool HasStdExtZba = false;
55  bool HasStdExtZbb = false;
56  bool HasStdExtZbc = false;
57  bool HasStdExtZbs = false;
58  bool HasStdExtZca = false;
59  bool HasStdExtZcd = false;
60  bool HasStdExtZcf = false;
61  bool HasStdExtV = false;
62  bool HasStdExtZve32x = false;
63  bool HasStdExtZve32f = false;
64  bool HasStdExtZve64x = false;
65  bool HasStdExtZve64f = false;
66  bool HasStdExtZve64d = false;
67  bool HasStdExtZvfh = false;
68  bool HasStdExtZfhmin = false;
69  bool HasStdExtZfh = false;
70  bool HasStdExtZfinx = false;
71  bool HasStdExtZdinx = false;
72  bool HasStdExtZhinxmin = false;
73  bool HasStdExtZhinx = false;
74  bool HasStdExtZbkb = false;
75  bool HasStdExtZbkc = false;
76  bool HasStdExtZbkx = false;
77  bool HasStdExtZknd = false;
78  bool HasStdExtZkne = false;
79  bool HasStdExtZknh = false;
80  bool HasStdExtZksed = false;
81  bool HasStdExtZksh = false;
82  bool HasStdExtZkr = false;
83  bool HasStdExtZkn = false;
84  bool HasStdExtZks = false;
85  bool HasStdExtZkt = false;
86  bool HasStdExtZk = false;
87  bool HasStdExtZicbom = false;
88  bool HasStdExtZicboz = false;
89  bool HasStdExtZicbop = false;
90  bool HasStdExtSvnapot = false;
91  bool HasStdExtSvinval = false;
92  bool HasStdExtZmmul = false;
93  bool HasStdExtZawrs = false;
94  bool HasStdExtZtso = false;
95  bool HasVendorXVentanaCondOps = false;
96  bool HasRV32 = false;
97  bool HasRV64 = false;
98  bool IsRV32E = false;
99  bool EnableLinkerRelax = false;
100  bool EnableRVCHintInstrs = true;
101  bool EnableDefaultUnroll = true;
102  bool EnableSaveRestore = false;
103  bool EnableUnalignedScalarMem = false;
104  bool HasShortForwardBranchOpt = false;
105  bool HasLUIADDIFusion = false;
106  bool HasForcedAtomics = false;
107  bool HasOptimizedZeroStrideLoad = true;
108  unsigned XLen = 32;
109  unsigned ZvlLen = 0;
110  MVT XLenVT = MVT::i32;
111  uint8_t MaxInterleaveFactor = 2;
113  std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
114  RISCVFrameLowering FrameLowering;
115  RISCVInstrInfo InstrInfo;
117  RISCVTargetLowering TLInfo;
118  SelectionDAGTargetInfo TSInfo;
119 
120  /// Initializes using the passed in CPU and feature strings so that we can
121  /// use initializer lists for subtarget initialization.
122  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
123  StringRef CPU,
124  StringRef TuneCPU,
125  StringRef FS,
126  StringRef ABIName);
127 
128 public:
129  // Initializes the data members to match that of the specified triple.
130  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
131  StringRef FS, StringRef ABIName, const TargetMachine &TM);
132 
133  // Parses features string setting specified subtarget options. The
134  // definition of this function is auto-generated by tblgen.
136 
137  const RISCVFrameLowering *getFrameLowering() const override {
138  return &FrameLowering;
139  }
140  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
141  const RISCVRegisterInfo *getRegisterInfo() const override {
142  return &RegInfo;
143  }
144  const RISCVTargetLowering *getTargetLowering() const override {
145  return &TLInfo;
146  }
147  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
148  return &TSInfo;
149  }
150  bool enableMachineScheduler() const override { return true; }
151 
152  /// Returns RISCV processor family.
153  /// Avoid this function! CPU specifics should be kept local to this class
154  /// and preferably modeled with SubtargetFeatures or properties in
155  /// initializeProperties().
156  RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
157 
158  bool hasStdExtM() const { return HasStdExtM; }
159  bool hasStdExtA() const { return HasStdExtA; }
160  bool hasStdExtF() const { return HasStdExtF; }
161  bool hasStdExtD() const { return HasStdExtD; }
162  bool hasStdExtC() const { return HasStdExtC; }
163  bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
164  bool hasStdExtV() const { return HasStdExtV; }
165  bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
166  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
167  bool hasStdExtZba() const { return HasStdExtZba; }
168  bool hasStdExtZbb() const { return HasStdExtZbb; }
169  bool hasStdExtZbc() const { return HasStdExtZbc; }
170  bool hasStdExtZbs() const { return HasStdExtZbs; }
171  bool hasStdExtZca() const { return HasStdExtZca; }
172  bool hasStdExtZcd() const { return HasStdExtZcd; }
173  bool hasStdExtZcf() const { return HasStdExtZcf; }
174  bool hasStdExtZvl() const { return ZvlLen != 0; }
175  bool hasStdExtZvfh() const { return HasStdExtZvfh; }
176  bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
177  bool hasStdExtZfh() const { return HasStdExtZfh; }
178  bool hasStdExtZfinx() const { return HasStdExtZfinx; }
179  bool hasStdExtZdinx() const { return HasStdExtZdinx; }
180  bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
181  bool hasStdExtZhinx() const { return HasStdExtZhinx; }
182  bool hasStdExtZbkb() const { return HasStdExtZbkb; }
183  bool hasStdExtZbkc() const { return HasStdExtZbkc; }
184  bool hasStdExtZbkx() const { return HasStdExtZbkx; }
185  bool hasStdExtZknd() const { return HasStdExtZknd; }
186  bool hasStdExtZkne() const { return HasStdExtZkne; }
187  bool hasStdExtZknh() const { return HasStdExtZknh; }
188  bool hasStdExtZksed() const { return HasStdExtZksed; }
189  bool hasStdExtZksh() const { return HasStdExtZksh; }
190  bool hasStdExtZkr() const { return HasStdExtZkr; }
191  bool hasStdExtZicbom() const { return HasStdExtZicbom; }
192  bool hasStdExtZicboz() const { return HasStdExtZicboz; }
193  bool hasStdExtZicbop() const { return HasStdExtZicbop; }
194  bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
195  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
196  bool hasStdExtZawrs() const { return HasStdExtZawrs; }
197  bool hasStdExtZmmul() const { return HasStdExtZmmul; }
198  bool hasStdExtZtso() const { return HasStdExtZtso; }
199  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
200  bool is64Bit() const { return HasRV64; }
201  bool isRV32E() const { return IsRV32E; }
202  bool enableLinkerRelax() const { return EnableLinkerRelax; }
203  bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
204  bool enableDefaultUnroll() const { return EnableDefaultUnroll; }
205  bool enableSaveRestore() const { return EnableSaveRestore; }
206  bool hasShortForwardBranchOpt() const { return HasShortForwardBranchOpt; }
207  bool enableUnalignedScalarMem() const { return EnableUnalignedScalarMem; }
208  bool hasLUIADDIFusion() const { return HasLUIADDIFusion; }
209  bool hasForcedAtomics() const { return HasForcedAtomics; }
210  bool hasOptimizedZeroStrideLoad() const { return HasOptimizedZeroStrideLoad; }
211  MVT getXLenVT() const { return XLenVT; }
212  unsigned getXLen() const { return XLen; }
213  unsigned getFLen() const {
214  if (HasStdExtD)
215  return 64;
216 
217  if (HasStdExtF)
218  return 32;
219 
220  return 0;
221  }
222  unsigned getELEN() const {
223  assert(hasVInstructions() && "Expected V extension");
224  return hasVInstructionsI64() ? 64 : 32;
225  }
226  unsigned getRealMinVLen() const {
227  unsigned VLen = getMinRVVVectorSizeInBits();
228  return VLen == 0 ? getArchMinVLen() : VLen;
229  }
230  unsigned getRealMaxVLen() const {
231  unsigned VLen = getMaxRVVVectorSizeInBits();
232  return VLen == 0 ? getArchMaxVLen() : VLen;
233  }
234  RISCVABI::ABI getTargetABI() const { return TargetABI; }
236  assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
237  return UserReservedRegister[i];
238  }
239 
240  bool hasMacroFusion() const { return hasLUIADDIFusion(); }
241 
242  // Vector codegen related methods.
243  bool hasVInstructions() const { return HasStdExtZve32x; }
244  bool hasVInstructionsI64() const { return HasStdExtZve64x; }
245  bool hasVInstructionsF16() const { return HasStdExtZvfh && HasStdExtZfh; }
246  // FIXME: Consider Zfinx in the future
247  bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
248  // FIXME: Consider Zdinx in the future
249  bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
250  // F16 and F64 both require F32.
251  bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
252  unsigned getMaxInterleaveFactor() const {
253  return hasVInstructions() ? MaxInterleaveFactor : 1;
254  }
255 
256 protected:
257  // GlobalISel related APIs.
258  std::unique_ptr<CallLowering> CallLoweringInfo;
259  std::unique_ptr<InstructionSelector> InstSelector;
260  std::unique_ptr<LegalizerInfo> Legalizer;
261  std::unique_ptr<RegisterBankInfo> RegBankInfo;
262 
263  // Return the known range for the bit length of RVV data registers as set
264  // at the command line. A value of 0 means nothing is known about that particular
265  // limit beyond what's implied by the architecture.
266  // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
267  unsigned getMaxRVVVectorSizeInBits() const;
268  unsigned getMinRVVVectorSizeInBits() const;
269 
270  // Return the known range for the bit length of RVV data registers as indicated
271  // by -march and -mattr.
272  unsigned getArchMinVLen() const { return ZvlLen; }
273  unsigned getArchMaxVLen() const { return 65536; }
274 
275 public:
276  const CallLowering *getCallLowering() const override;
278  const LegalizerInfo *getLegalizerInfo() const override;
279  const RegisterBankInfo *getRegBankInfo() const override;
280 
281  bool useConstantPoolForLargeInts() const;
282 
283  // Maximum cost used for building integers, integers will be put into constant
284  // pool if exceeded.
285  unsigned getMaxBuildIntsCost() const;
286 
287  unsigned getMaxLMULForFixedLengthVectors() const;
288  bool useRVVForFixedLengthVectors() const;
289 
290  bool enableSubRegLiveness() const override;
291 
292  void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
293  &Mutations) const override;
294 };
295 } // End llvm namespace
296 
297 #endif
llvm::RISCVSubtarget::hasStdExtZihintntl
bool hasStdExtZihintntl() const
Definition: RISCVSubtarget.h:166
i
i
Definition: README.txt:29
llvm::RISCVSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: RISCVSubtarget.cpp:210
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVSubtarget::hasStdExtSvinval
bool hasStdExtSvinval() const
Definition: RISCVSubtarget.h:195
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:200
llvm::RISCVSubtarget::hasVInstructionsF16
bool hasVInstructionsF16() const
Definition: RISCVSubtarget.h:245
llvm::RISCVSubtarget::hasShortForwardBranchOpt
bool hasShortForwardBranchOpt() const
Definition: RISCVSubtarget.h:206
CallLowering.h
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:144
llvm::RISCVSubtarget::hasStdExtZca
bool hasStdExtZca() const
Definition: RISCVSubtarget.h:171
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVSubtarget::hasOptimizedZeroStrideLoad
bool hasOptimizedZeroStrideLoad() const
Definition: RISCVSubtarget.h:210
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:235
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:243
llvm::RISCVSubtarget::getRealMaxVLen
unsigned getRealMaxVLen() const
Definition: RISCVSubtarget.h:230
llvm::RISCVSubtarget::hasStdExtZksed
bool hasStdExtZksed() const
Definition: RISCVSubtarget.h:188
RegisterBankInfo.h
llvm::RISCVSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: RISCVSubtarget.cpp:204
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:106
llvm::RISCVSubtarget::Others
@ Others
Definition: RISCVSubtarget.h:38
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::RISCVSubtarget::hasStdExtZbs
bool hasStdExtZbs() const
Definition: RISCVSubtarget.h:170
llvm::RISCVSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: RISCVSubtarget.h:260
llvm::RISCVSubtarget::hasStdExtZhinx
bool hasStdExtZhinx() const
Definition: RISCVSubtarget.h:181
llvm::RISCVSubtarget::hasStdExtD
bool hasStdExtD() const
Definition: RISCVSubtarget.h:161
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:258
llvm::RISCVSubtarget::hasVInstructionsI64
bool hasVInstructionsI64() const
Definition: RISCVSubtarget.h:244
LegalizerInfo.h
llvm::RISCVSubtarget::hasStdExtZihintpause
bool hasStdExtZihintpause() const
Definition: RISCVSubtarget.h:165
llvm::RISCVSubtarget::hasMacroFusion
bool hasMacroFusion() const
Definition: RISCVSubtarget.h:240
llvm::RISCVSubtarget::getFrameLowering
const RISCVFrameLowering * getFrameLowering() const override
Definition: RISCVSubtarget.h:137
llvm::RISCVSubtarget::getFLen
unsigned getFLen() const
Definition: RISCVSubtarget.h:213
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:90
llvm::RISCVSubtarget::hasStdExtZbkx
bool hasStdExtZbkx() const
Definition: RISCVSubtarget.h:184
llvm::RISCVSubtarget::is64Bit
bool is64Bit() const
Definition: RISCVSubtarget.h:200
llvm::RISCVSubtarget::hasStdExtZbc
bool hasStdExtZbc() const
Definition: RISCVSubtarget.h:169
llvm::RISCVSubtarget::hasVInstructionsF64
bool hasVInstructionsF64() const
Definition: RISCVSubtarget.h:249
llvm::RISCVSubtarget::hasStdExtZtso
bool hasStdExtZtso() const
Definition: RISCVSubtarget.h:198
InstrInfo
return InstrInfo
Definition: RISCVInsertVSETVLI.cpp:668
llvm::RISCVSubtarget::hasStdExtZfhmin
bool hasStdExtZfhmin() const
Definition: RISCVSubtarget.h:176
TargetMachine.h
llvm::RISCVSubtarget::hasStdExtZmmul
bool hasStdExtZmmul() const
Definition: RISCVSubtarget.h:197
llvm::RISCVSubtarget::hasLUIADDIFusion
bool hasLUIADDIFusion() const
Definition: RISCVSubtarget.h:208
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
llvm::RISCVSubtarget::getXLenVT
MVT getXLenVT() const
Definition: RISCVSubtarget.h:211
llvm::RISCVSubtarget::getELEN
unsigned getELEN() const
Definition: RISCVSubtarget.h:222
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::RISCVSubtarget::hasStdExtZfinx
bool hasStdExtZfinx() const
Definition: RISCVSubtarget.h:178
llvm::RISCVSubtarget::hasForcedAtomics
bool hasForcedAtomics() const
Definition: RISCVSubtarget.h:209
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:168
llvm::RISCVSubtarget::enableDefaultUnroll
bool enableDefaultUnroll() const
Definition: RISCVSubtarget.h:204
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:140
llvm::RISCVSubtarget::hasStdExtZdinx
bool hasStdExtZdinx() const
Definition: RISCVSubtarget.h:179
llvm::RISCVSubtarget::getRealMinVLen
unsigned getRealMinVLen() const
Definition: RISCVSubtarget.h:226
llvm::RISCVSubtarget::getTargetABI
RISCVABI::ABI getTargetABI() const
Definition: RISCVSubtarget.h:234
llvm::RISCVSubtarget::hasStdExtC
bool hasStdExtC() const
Definition: RISCVSubtarget.h:162
llvm::RISCVSubtarget::enableRVCHintInstrs
bool enableRVCHintInstrs() const
Definition: RISCVSubtarget.h:203
InstructionSelector.h
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:137
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::RISCVSubtarget::hasStdExtZknh
bool hasStdExtZknh() const
Definition: RISCVSubtarget.h:187
llvm::RISCVSubtarget::getProcFamily
RISCVProcFamilyEnum getProcFamily() const
Returns RISCV processor family.
Definition: RISCVSubtarget.h:156
llvm::RISCVSubtarget::getMaxBuildIntsCost
unsigned getMaxBuildIntsCost() const
Definition: RISCVSubtarget.cpp:126
llvm::RISCVSubtarget::hasStdExtCOrZca
bool hasStdExtCOrZca() const
Definition: RISCVSubtarget.h:163
llvm::RISCVSubtarget::getArchMaxVLen
unsigned getArchMaxVLen() const
Definition: RISCVSubtarget.h:273
llvm::RISCVSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: RISCVSubtarget.h:252
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::RISCVSubtarget::enableSaveRestore
bool enableSaveRestore() const
Definition: RISCVSubtarget.h:205
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:191
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: RISCVSubtarget.h:147
llvm::RISCVSubtarget::hasStdExtZba
bool hasStdExtZba() const
Definition: RISCVSubtarget.h:167
llvm::RISCVSubtarget::hasStdExtZkne
bool hasStdExtZkne() const
Definition: RISCVSubtarget.h:186
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:118
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
RegInfo
Definition: AMDGPUAsmParser.cpp:2578
llvm::RISCVSubtarget::hasStdExtZbkc
bool hasStdExtZbkc() const
Definition: RISCVSubtarget.h:183
DataLayout.h
llvm::RISCVSubtarget::hasStdExtZicboz
bool hasStdExtZicboz() const
Definition: RISCVSubtarget.h:192
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:141
llvm::RISCVSubtarget::hasStdExtZkr
bool hasStdExtZkr() const
Definition: RISCVSubtarget.h:190
TargetSubtargetInfo.h
llvm::RISCVSubtarget::hasStdExtZicbop
bool hasStdExtZicbop() const
Definition: RISCVSubtarget.h:193
llvm::RISCVSubtarget::enableUnalignedScalarMem
bool enableUnalignedScalarMem() const
Definition: RISCVSubtarget.h:207
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVSubtarget::getArchMinVLen
unsigned getArchMinVLen() const
Definition: RISCVSubtarget.h:272
llvm::RISCVSubtarget::hasStdExtZknd
bool hasStdExtZknd() const
Definition: RISCVSubtarget.h:185
llvm::RISCVSubtarget::hasVInstructionsAnyF
bool hasVInstructionsAnyF() const
Definition: RISCVSubtarget.h:251
llvm::RISCVSubtarget::hasStdExtZfh
bool hasStdExtZfh() const
Definition: RISCVSubtarget.h:177
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:259
llvm::RISCVSubtarget::hasStdExtZicbom
bool hasStdExtZicbom() const
Definition: RISCVSubtarget.h:191
RISCVISelLowering.h
llvm::RISCVSubtarget::hasVInstructionsF32
bool hasVInstructionsF32() const
Definition: RISCVSubtarget.h:247
llvm::RISCVSubtarget::isRV32E
bool isRV32E() const
Definition: RISCVSubtarget.h:201
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::RISCVSubtarget::hasStdExtZbkb
bool hasStdExtZbkb() const
Definition: RISCVSubtarget.h:182
llvm::RISCVSubtarget::hasStdExtZhinxmin
bool hasStdExtZhinxmin() const
Definition: RISCVSubtarget.h:180
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:212
RISCVInstrInfo.h
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:335
RISCVBaseInfo.h
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:114
llvm::RISCVSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: RISCVSubtarget.h:150
llvm::RISCVSubtarget::hasVendorXVentanaCondOps
bool hasVendorXVentanaCondOps() const
Definition: RISCVSubtarget.h:199
SelectionDAGTargetInfo.h
llvm::RISCVSubtarget::hasStdExtA
bool hasStdExtA() const
Definition: RISCVSubtarget.h:159
llvm::RISCVSubtarget::hasStdExtZawrs
bool hasStdExtZawrs() const
Definition: RISCVSubtarget.h:196
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:380
llvm::RISCVSubtarget::hasStdExtZvl
bool hasStdExtZvl() const
Definition: RISCVSubtarget.h:174
RISCVFrameLowering.h
llvm::RISCVSubtarget::RISCVProcFamilyEnum
RISCVProcFamilyEnum
Definition: RISCVSubtarget.h:37
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Definition: RISCVSubtarget.h:261
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Definition: RISCVSubtarget.h:172
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Definition: RISCVSubtarget.h:173
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Definition: RISCVSubtarget.cpp:162
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Definition: RISCVSubtarget.h:39
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Definition: RISCVSubtarget.h:189
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Definition: RISCVSubtarget.h:175
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Definition: RISCVSubtarget.h:158
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Definition: RISCVSubtarget.h:160
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Definition: CallLowering.h:44
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Definition: RISCVSubtarget.h:202
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Definition: RISCVSubtarget.h:194
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Definition: RISCVSubtarget.h:164
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Definition: RISCVSubtarget.cpp:110