LLVM  16.0.0git
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RISCV.h File Reference
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "llvm/Target/TargetMachine.h"
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Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Functions

FunctionPassllvm::createRISCVCodeGenPreparePass ()
 
void llvm::initializeRISCVCodeGenPreparePass (PassRegistry &)
 
bool llvm::lowerRISCVMachineInstrToMCInst (const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
 
bool llvm::lowerRISCVMachineOperandToMCOperand (const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
 
FunctionPassllvm::createRISCVISelDag (RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
 
FunctionPassllvm::createRISCVMakeCompressibleOptPass ()
 Returns an instance of the Make Compressible Optimization pass. More...
 
void llvm::initializeRISCVMakeCompressibleOptPass (PassRegistry &)
 
FunctionPass * llvm::createRISCVGatherScatterLoweringPass ()
 
void llvm::initializeRISCVGatherScatterLoweringPass (PassRegistry &)
 
FunctionPass * llvm::createRISCVSExtWRemovalPass ()
 
void llvm::initializeRISCVSExtWRemovalPass (PassRegistry &)
 
FunctionPassllvm::createRISCVMergeBaseOffsetOptPass ()
 Returns an instance of the Merge Base Offset Optimization pass. More...
 
void llvm::initializeRISCVMergeBaseOffsetOptPass (PassRegistry &)
 
FunctionPassllvm::createRISCVExpandPseudoPass ()
 
void llvm::initializeRISCVExpandPseudoPass (PassRegistry &)
 
FunctionPassllvm::createRISCVPreRAExpandPseudoPass ()
 
void llvm::initializeRISCVPreRAExpandPseudoPass (PassRegistry &)
 
FunctionPass * llvm::createRISCVExpandAtomicPseudoPass ()
 
void llvm::initializeRISCVExpandAtomicPseudoPass (PassRegistry &)
 
FunctionPassllvm::createRISCVInsertVSETVLIPass ()
 Returns an instance of the Insert VSETVLI pass. More...
 
void llvm::initializeRISCVInsertVSETVLIPass (PassRegistry &)
 
FunctionPassllvm::createRISCVRedundantCopyEliminationPass ()
 
void llvm::initializeRISCVRedundantCopyEliminationPass (PassRegistry &)
 
InstructionSelectorllvm::createRISCVInstructionSelector (const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)