llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others , SiFive7 , VentanaVeyron }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
bool	hasStdExtCOrZca () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZfhmin () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZhinxOrZhinxmin () const
bool	hasStdExtZfhOrZfhminOrZhinxOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	is64Bit () const
MVT	getXLenVT () const
unsigned	getXLen () const
unsigned	getFLen () const
unsigned	getELen () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
bool	isRegisterReservedByUser (Register i) const
bool	hasMacroFusion () const
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16Minimal () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsBF16 () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
unsigned	getDLenFactor () const
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RegisterBankInfo *	getRegBankInfo () const override
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMaxLMULForFixedLengthVectors () const
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
void	getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
unsigned	getCacheLineSize () const override
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
unsigned	getMinimumJumpTableEntries () const

Protected Member Functions
unsigned	getMaxRVVVectorSizeInBits () const
unsigned	getMinRVVVectorSizeInBits () const

Protected Attributes
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RegisterBankInfo >	RegBankInfo

Detailed Description

Definition at line 55 of file RISCVSubtarget.h.

Member Enumeration Documentation

RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t

Enumerator
Others
SiFive7
VentanaVeyron

Definition at line 58 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringRef	ABIName,
		unsigned	RVVVectorBitsMin,
		unsigned	RVVVectorLMULMax,
		const TargetMachine &	TM
	)

Definition at line 90 of file RISCVSubtarget.cpp.

References CallLoweringInfo, llvm::createRISCVInstructionSelector(), getTargetLowering(), InstrInfo, InstSelector, RegBankInfo, and TM.

Member Function Documentation

enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const

inlineoverride

Definition at line 118 of file RISCVSubtarget.h.

enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const

inlineoverride

Definition at line 120 of file RISCVSubtarget.h.

enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const

override

Definition at line 182 of file RISCVSubtarget.cpp.

References EnableSubRegLiveness.

getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const

inlineoverride

Definition at line 260 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::CacheLineSize.

getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const

override

Definition at line 109 of file RISCVSubtarget.cpp.

References CallLoweringInfo.

getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const

inline

Definition at line 216 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getLMULCost().

getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const

inline

Definition at line 172 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by combineBinOpOfExtractToReduceTree(), llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTTIImpl::getShuffleCost(), getWideningInterleave(), isDeinterleaveShuffle(), isInterleaveShuffle(), lowerBuildVectorOfConstants(), lowerGetVectorLength(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const

inline

Definition at line 163 of file RISCVSubtarget.h.

Referenced by lowerBUILD_VECTOR().

getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 105 of file RISCVSubtarget.h.

getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 108 of file RISCVSubtarget.h.

References InstrInfo.

Referenced by emitFROUND(), EmitLoweredCascadedSelect(), llvm::RISCVFrameLowering::emitPrologue(), emitSelectPseudo(), llvm::RISCVCallLowering::lowerCall(), and lowerRISCVVMachineInstrToMCInst().

getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const

override

Definition at line 113 of file RISCVSubtarget.cpp.

References InstSelector.

getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const

override

Definition at line 117 of file RISCVSubtarget.cpp.

getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost

(

)

const

Definition at line 129 of file RISCVSubtarget.cpp.

References RISCVMaxBuildIntsCost.

Referenced by lowerConstant(), and llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm().

getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 210 of file RISCVSubtarget.h.

References hasVInstructions().

getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors

(

)

const

Definition at line 169 of file RISCVSubtarget.cpp.

References assert(), llvm::bit_floor(), hasVInstructions(), and RVVVectorLMULMax.

Referenced by useRVVForFixedLengthVectorVT().

getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const

inlineoverride

Definition at line 272 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxPrefetchIterationsAhead.

getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const

protected

Definition at line 140 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries

(

)

const

Definition at line 197 of file RISCVSubtarget.cpp.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MinimumJumpTableEntries, and RISCVMinimumJumpTableEntries.

getMinPrefetchStride()

unsigned llvm::RISCVSubtarget::getMinPrefetchStride ( unsigned  NumMemAccesses, unsigned  NumStridedMemAccesses, unsigned  NumPrefetches, bool  HasCall  ) const

inlineoverride

Definition at line 266 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MinPrefetchStride.

getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const

protected

Definition at line 153 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

getPostRAMutations()

void RISCVSubtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > &  Mutations ) const

override

Definition at line 188 of file RISCVSubtarget.cpp.

References llvm::createRISCVMacroFusionDAGMutation().

getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const

inlineoverride

Definition at line 263 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefetchDistance.

getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const

inline

Definition at line 124 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefFunctionAlignment.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 127 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefLoopAlignment.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const

inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 135 of file RISCVSubtarget.h.

getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const

inline

Definition at line 180 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTTIImpl::getMaxVScale(), lowerBUILD_VECTOR(), lowerVectorIntrinsicScalars(), and llvm::RISCVDAGToDAGISel::selectVSETVLI().

getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const

inline

Definition at line 176 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), getContainerForFixedLengthVector(), llvm::RISCVTargetLowering::getLMULCost(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), getSmallestVTForIndex(), llvm::RISCVTTIImpl::getVScaleForTuning(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), and useRVVForFixedLengthVectorVT().

getRegBankInfo()

const RegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const

override

Definition at line 121 of file RISCVSubtarget.cpp.

References RegBankInfo.

Referenced by llvm::RISCVCallLowering::lowerCall().

getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 109 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr(), llvm::RISCVFrameLowering::emitEpilogue(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVFrameLowering::hasBP(), isConvertibleToVMV_V_V(), llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

getSelectionDAGInfo()

const SelectionDAGTargetInfo * llvm::RISCVSubtarget::getSelectionDAGInfo ( ) const

inlineoverride

Definition at line 115 of file RISCVSubtarget.h.

getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const

inline

Definition at line 184 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 112 of file RISCVSubtarget.h.

Referenced by lowerBitreverseShuffle(), lowerVECTOR_SHUFFLEAsRotate(), RISCVSubtarget(), and llvm::RISCVDAGToDAGISel::Select().

getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const

inline

Definition at line 160 of file RISCVSubtarget.h.

References is64Bit().

Referenced by combineSelectAndUse(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(), llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVTTIImpl::getIntImmCostInst(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getVectorInstrCost(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), llvm::RISCVInstrInfo::isBranchOffsetInRange(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSupportedArgumentType(), isSupportedReturnType(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), llvm::RISCVTargetLowering::lowerInterleavedStore(), llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore(), performBITREVERSECombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectShiftMaskXLen(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm(), llvm::RISCVTargetLowering::shouldExtendTypeInLibCall(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), transformAddImmMulImm(), and transformAddShlImm().

getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const

inline

Definition at line 157 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), llvm::RISCV::CC_RISCV_FastCC(), combine_CC(), combineBinOpToReduce(), llvm::RISCVTargetLowering::computeVLMax(), convertFromScalableVector(), convertToScalableVector(), getDefaultScalableVLOps(), getDeinterleaveViaVNSRL(), getRVVFPReductionOpAndOperands(), getVLOp(), getVSlidedown(), getVSlideup(), getWideningInterleave(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), llvm::RISCVTargetLowering::LowerCall(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), selectVSplatImmHelper(), and tryMemPairCombine().

hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const

inline

Definition at line 153 of file RISCVSubtarget.h.

References hasStdExtZfhOrZfhmin().

hasMacroFusion()

bool llvm::RISCVSubtarget::hasMacroFusion ( ) const

inline

Definition at line 195 of file RISCVSubtarget.h.

hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const

inline

Definition at line 141 of file RISCVSubtarget.h.

Referenced by llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVInstrInfo::getNop(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const

inline

Definition at line 144 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const

inline

Definition at line 143 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhOrZfhmin()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZfhmin ( ) const

inline

Definition at line 145 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), hasHalfFPLoadStoreMove(), hasStdExtZfhOrZfhminOrZhinxOrZhinxmin(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldConvertFpToSat().

hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZfhminOrZhinxOrZhinxmin ( ) const

inline

Definition at line 150 of file RISCVSubtarget.h.

References hasStdExtZfhOrZfhmin(), and hasStdExtZhinxOrZhinxmin().

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const

inline

Definition at line 146 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZhinxOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZhinxOrZhinxmin ( ) const

inline

Definition at line 147 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), hasStdExtZfhOrZfhminOrZhinxOrZhinxmin(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const

inline

Definition at line 142 of file RISCVSubtarget.h.

hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const

inline

Definition at line 198 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::canSplatOperand(), llvm::RISCV::CC_RISCV(), combineBinOpOfExtractToReduceTree(), getELen(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), llvm::RISCVTTIImpl::getMaxVScale(), getMinRVVVectorSizeInBits(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), getScavSlotsNumForRVV(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), isSupportedArgumentType(), isSupportedReturnType(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::RISCVTargetLowering::shouldSinkOperands(), and useRVVForFixedLengthVectors().

hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const

inline

Definition at line 208 of file RISCVSubtarget.h.

References hasVInstructionsF32().

hasVInstructionsBF16()

bool llvm::RISCVSubtarget::hasVInstructionsBF16 ( ) const

inline

Definition at line 204 of file RISCVSubtarget.h.

Referenced by isLegalElementTypeForRVV(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const

inline

Definition at line 203 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::LowerOperation(), performFADDSUB_VLCombine(), performVFMADD_VLCombine(), performVFMUL_VLCombine(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const

inline

Definition at line 200 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), performFADDSUB_VLCombine(), performVFMADD_VLCombine(), performVFMUL_VLCombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const

inline

Definition at line 205 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), hasVInstructionsAnyF(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const

inline

Definition at line 206 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const

inline

Definition at line 209 of file RISCVSubtarget.h.

hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const

inline

Definition at line 199 of file RISCVSubtarget.h.

Referenced by getELen(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const

inline

Definition at line 156 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::canFoldIntoAddrMode(), llvm::RISCV::CC_RISCV_FastCC(), llvm::RISCV::CC_RISCV_GHC(), emitFROUND(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(), getXLen(), getXLenVT(), isCompressibleLoad(), isCompressibleStore(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isSExtCheaperThanZExt(), llvm::RISCVTargetLowering::isTruncateFree(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVInstrInfo::movImm(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSRACombine(), performTRUNCATECombine(), performXORCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::signExtendConstant(), and llvm::RISCVInstrInfo::verifyInstruction().

isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register  i ) const

inline

Definition at line 190 of file RISCVSubtarget.h.

References assert().

Referenced by llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().

isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const

inline

Definition at line 185 of file RISCVSubtarget.h.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldExtendTypeInLibCall().

isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const

inline

Definition at line 242 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS
	)

useAA()

bool RISCVSubtarget::useAA ( ) const

override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 195 of file RISCVSubtarget.cpp.

References UseAA.

useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts

(

)

const

Definition at line 125 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors

(

)

const

Definition at line 178 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), and hasVInstructions().

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

Member Data Documentation

CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo

protected

Definition at line 224 of file RISCVSubtarget.h.

Referenced by getCallLowering(), and RISCVSubtarget().

InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector

protected

Definition at line 225 of file RISCVSubtarget.h.

Referenced by getInstructionSelector(), and RISCVSubtarget().

Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer

protected

Definition at line 226 of file RISCVSubtarget.h.

RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo

protected

Definition at line 227 of file RISCVSubtarget.h.

Referenced by getRegBankInfo(), and RISCVSubtarget().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVSubtarget.h
• lib/Target/RISCV/RISCVSubtarget.cpp