LLVM  15.0.0git
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 
23 namespace llvm {
24 
25 // RISCVII - This namespace holds all of the target specific flags that
26 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
27 namespace RISCVII {
28 enum {
47 
50 
53 
55  VLMulMask = 0b111 << VLMulShift,
56 
57  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
60 
61  // Force a tail agnostic policy even this instruction has a tied destination.
64 
65  // Does this instruction have a merge operand that must be removed when
66  // converting to MCInst. It will be the first explicit use operand. Used by
67  // RVV Pseudos.
70 
71  // Does this instruction have a SEW operand. It will be the last explicit
72  // operand unless there is a vector policy operand. Used by RVV Pseudos.
75 
76  // Does this instruction have a VL operand. It will be the second to last
77  // explicit operand unless there is a vector policy operand. Used by RVV
78  // Pseudos.
81 
82  // Does this instruction have a vector policy operand. It will be the last
83  // explicit operand. Used by RVV Pseudos.
86 
87  // Is this instruction a vector widening reduction instruction. Used by RVV
88  // Pseudos.
91 
92  // Does this instruction care about mask policy. If it is not, the mask policy
93  // could be either agnostic or undisturbed. For example, unmasked, store, and
94  // reduction operations result would not be affected by mask policy, so
95  // compiler has free to select either one.
98 };
99 
100 // Match with the definitions in RISCVInstrFormats.td
103  VS2Constraint = 0b001,
104  VS1Constraint = 0b010,
105  VMConstraint = 0b100,
106 };
107 
108 enum VLMUL : uint8_t {
109  LMUL_1 = 0,
117 };
118 
119 enum {
122 };
123 
124 // Helper functions to read TSFlags.
125 /// \returns the format of the instruction.
126 static inline unsigned getFormat(uint64_t TSFlags) {
127  return (TSFlags & InstFormatMask) >> InstFormatShift;
128 }
129 /// \returns the constraint for the instruction.
130 static inline VConstraintType getConstraint(uint64_t TSFlags) {
131  return static_cast<VConstraintType>((TSFlags & ConstraintMask) >>
133 }
134 /// \returns the LMUL for the instruction.
135 static inline VLMUL getLMul(uint64_t TSFlags) {
136  return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
137 }
138 /// \returns true if there is a dummy mask operand for the instruction.
139 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
140  return TSFlags & HasDummyMaskOpMask;
141 }
142 /// \returns true if tail agnostic is enforced for the instruction.
143 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
144  return TSFlags & ForceTailAgnosticMask;
145 }
146 /// \returns true if there is a merge operand for the instruction.
147 static inline bool hasMergeOp(uint64_t TSFlags) {
148  return TSFlags & HasMergeOpMask;
149 }
150 /// \returns true if there is a SEW operand for the instruction.
151 static inline bool hasSEWOp(uint64_t TSFlags) {
152  return TSFlags & HasSEWOpMask;
153 }
154 /// \returns true if there is a VL operand for the instruction.
155 static inline bool hasVLOp(uint64_t TSFlags) {
156  return TSFlags & HasVLOpMask;
157 }
158 /// \returns true if there is a vector policy operand for this instruction.
159 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
160  return TSFlags & HasVecPolicyOpMask;
161 }
162 /// \returns true if it is a vector widening reduction instruction.
163 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
164  return TSFlags & IsRVVWideningReductionMask;
165 }
166 /// \returns true if mask policy is valid for the instruction.
167 static inline bool usesMaskPolicy(uint64_t TSFlags) {
168  return TSFlags & UsesMaskPolicyMask;
169 }
170 
171 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
172  const uint64_t TSFlags = Desc.TSFlags;
173  // This method is only called if we expect to have a VL operand, and all
174  // instructions with VL also have SEW.
175  assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
176  unsigned Offset = 2;
177  if (hasVecPolicyOp(TSFlags))
178  Offset = 3;
179  return Desc.getNumOperands() - Offset;
180 }
181 
182 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
183  const uint64_t TSFlags = Desc.TSFlags;
184  assert(hasSEWOp(TSFlags));
185  unsigned Offset = 1;
186  if (hasVecPolicyOp(TSFlags))
187  Offset = 2;
188  return Desc.getNumOperands() - Offset;
189 }
190 
191 // RISC-V Specific Machine Operand Flags
192 enum {
193  MO_None = 0,
194  MO_CALL = 1,
195  MO_PLT = 2,
196  MO_LO = 3,
197  MO_HI = 4,
206 
207  // Used to differentiate between target-specific "direct" flags and "bitmask"
208  // flags. A machine operand can only have one "direct" flag, but can have
209  // multiple "bitmask" flags.
211 };
212 } // namespace RISCVII
213 
214 namespace RISCVOp {
215 enum OperandType : unsigned {
228  // Operand is either a register or uimm5, this is used by V extension pseudo
229  // instructions to represent a value that be passed as AVL to either vsetvli
230  // or vsetivli.
232 };
233 } // namespace RISCVOp
234 
235 // Describes the predecessor/successor bits used in the FENCE instruction.
236 namespace RISCVFenceField {
238  I = 8,
239  O = 4,
240  R = 2,
241  W = 1
242 };
243 }
244 
245 // Describes the supported floating point rounding mode encodings.
246 namespace RISCVFPRndMode {
248  RNE = 0,
249  RTZ = 1,
250  RDN = 2,
251  RUP = 3,
252  RMM = 4,
253  DYN = 7,
255 };
256 
258  switch (RndMode) {
259  default:
260  llvm_unreachable("Unknown floating point rounding mode");
261  case RISCVFPRndMode::RNE:
262  return "rne";
263  case RISCVFPRndMode::RTZ:
264  return "rtz";
265  case RISCVFPRndMode::RDN:
266  return "rdn";
267  case RISCVFPRndMode::RUP:
268  return "rup";
269  case RISCVFPRndMode::RMM:
270  return "rmm";
271  case RISCVFPRndMode::DYN:
272  return "dyn";
273  }
274 }
275 
277  return StringSwitch<RoundingMode>(Str)
278  .Case("rne", RISCVFPRndMode::RNE)
279  .Case("rtz", RISCVFPRndMode::RTZ)
280  .Case("rdn", RISCVFPRndMode::RDN)
281  .Case("rup", RISCVFPRndMode::RUP)
282  .Case("rmm", RISCVFPRndMode::RMM)
283  .Case("dyn", RISCVFPRndMode::DYN)
285 }
286 
287 inline static bool isValidRoundingMode(unsigned Mode) {
288  switch (Mode) {
289  default:
290  return false;
291  case RISCVFPRndMode::RNE:
292  case RISCVFPRndMode::RTZ:
293  case RISCVFPRndMode::RDN:
294  case RISCVFPRndMode::RUP:
295  case RISCVFPRndMode::RMM:
296  case RISCVFPRndMode::DYN:
297  return true;
298  }
299 }
300 } // namespace RISCVFPRndMode
301 
302 namespace RISCVSysReg {
303 struct SysReg {
304  const char *Name;
305  const char *AltName;
306  const char *DeprecatedName;
307  unsigned Encoding;
308  // FIXME: add these additional fields when needed.
309  // Privilege Access: Read, Write, Read-Only.
310  // unsigned ReadWrite;
311  // Privilege Mode: User, System or Machine.
312  // unsigned Mode;
313  // Check field name.
314  // unsigned Extra;
315  // Register number without the privilege bits.
316  // unsigned Number;
319 
320  bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
321  // Not in 32-bit mode.
322  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
323  return false;
324  // No required feature associated with the system register.
325  if (FeaturesRequired.none())
326  return true;
327  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
328  }
329 };
330 
331 #define GET_SysRegsList_DECL
332 #include "RISCVGenSearchableTables.inc"
333 } // end namespace RISCVSysReg
334 
335 namespace RISCVInsnOpcode {
336 struct RISCVOpcode {
337  const char *Name;
338  unsigned Value;
339 };
340 
341 #define GET_RISCVOpcodesList_DECL
342 #include "RISCVGenSearchableTables.inc"
343 } // end namespace RISCVInsnOpcode
344 
345 namespace RISCVABI {
346 
347 enum ABI {
356 };
357 
358 // Returns the target ABI, or else a StringError if the requested ABIName is
359 // not supported for the given TT and FeatureBits combination.
360 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
361  StringRef ABIName);
362 
363 ABI getTargetABI(StringRef ABIName);
364 
365 // Returns the register used to hold the stack pointer after realignment.
367 
368 // Returns the register holding shadow call stack pointer.
370 
371 } // namespace RISCVABI
372 
373 namespace RISCVFeatures {
374 
375 // Validates if the given combination of features are valid for the target
376 // triple. Exits with report_fatal_error if not.
377 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
378 
380 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
381 
382 } // namespace RISCVFeatures
383 
384 namespace RISCVVType {
385 // Is this a SEW value that can be encoded into the VTYPE format.
386 inline static bool isValidSEW(unsigned SEW) {
387  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
388 }
389 
390 // Is this a LMUL value that can be encoded into the VTYPE format.
391 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
392  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
393 }
394 
395 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
396  bool MaskAgnostic);
397 
398 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
399  unsigned VLMUL = VType & 0x7;
400  return static_cast<RISCVII::VLMUL>(VLMUL);
401 }
402 
403 // Decode VLMUL into 1,2,4,8 and fractional indicator.
404 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
405 
406 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
407  assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
408  unsigned LmulLog2 = Log2_32(LMUL);
409  return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
410 }
411 
412 inline static unsigned decodeVSEW(unsigned VSEW) {
413  assert(VSEW < 8 && "Unexpected VSEW value");
414  return 1 << (VSEW + 3);
415 }
416 
417 inline static unsigned encodeSEW(unsigned SEW) {
418  assert(isValidSEW(SEW) && "Unexpected SEW value");
419  return Log2_32(SEW) - 3;
420 }
421 
422 inline static unsigned getSEW(unsigned VType) {
423  unsigned VSEW = (VType >> 3) & 0x7;
424  return decodeVSEW(VSEW);
425 }
426 
427 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
428 
429 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
430 
431 void printVType(unsigned VType, raw_ostream &OS);
432 
433 } // namespace RISCVVType
434 
435 } // namespace llvm
436 
437 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:109
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:353
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:80
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:248
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:205
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:73
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:238
llvm::RISCVII::getSEWOpNum
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:182
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:29
llvm::RISCVII::isRVVWideningReduction
static bool isRVVWideningReduction(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:163
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:252
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:391
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:44
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:201
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:36
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:223
llvm::RISCVII::usesMaskPolicy
static bool usesMaskPolicy(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:167
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:104
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:72
MCInstrDesc.h
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:40
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:68
StringRef.h
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:37
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:74
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:227
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:241
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:225
llvm::RISCVInsnOpcode::RISCVOpcode
Definition: RISCVBaseInfo.h:336
llvm::RISCVII::LMUL_RESERVED
@ LMUL_RESERVED
Definition: RISCVBaseInfo.h:113
llvm::RISCVInsnOpcode::RISCVOpcode::Value
unsigned Value
Definition: RISCVBaseInfo.h:338
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:250
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:112
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:386
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:151
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:195
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:62
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:103
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:427
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:237
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:43
llvm::RISCVII::HasVecPolicyOpMask
@ HasVecPolicyOpMask
Definition: RISCVBaseInfo.h:85
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:59
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:42
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:97
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVII::UsesMaskPolicyMask
@ UsesMaskPolicyMask
Definition: RISCVBaseInfo.h:97
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:304
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:193
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:276
llvm::RISCVII::HasVecPolicyOpShift
@ HasVecPolicyOpShift
Definition: RISCVBaseInfo.h:84
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:159
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:422
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:63
llvm::RISCVOp::OPERAND_AVL
@ OPERAND_AVL
Definition: RISCVBaseInfo.h:231
llvm::RISCVOp::OPERAND_UIMM7
@ OPERAND_UIMM7
Definition: RISCVBaseInfo.h:221
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:240
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:204
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:348
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:111
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:102
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:352
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:48
SubtargetFeature.h
llvm::RISCVVType::encodeSEW
static unsigned encodeSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:417
llvm::RISCVOp::OPERAND_RVKRNUM
@ OPERAND_RVKRNUM
Definition: RISCVBaseInfo.h:226
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:46
llvm::RISCVII::InstFormatShift
@ InstFormatShift
Definition: RISCVBaseInfo.h:49
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:55
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:623
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:155
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:350
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:220
llvm::RISCVVType::decodeVSEW
static unsigned decodeVSEW(unsigned VSEW)
Definition: RISCVBaseInfo.h:412
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:351
RISCVMCTargetDesc.h
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:303
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:222
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:91
llvm::RISCVOp::OPERAND_UIMM2
@ OPERAND_UIMM2
Definition: RISCVBaseInfo.h:217
llvm::RISCVII::VConstraintType
VConstraintType
Definition: RISCVBaseInfo.h:101
llvm::RISCVFeatures::parseFeatureBits
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:107
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:35
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:196
llvm::RISCVII::getConstraint
static VConstraintType getConstraint(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:130
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:202
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:126
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:34
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::RISCVOp::OPERAND_UIMM3
@ OPERAND_UIMM3
Definition: RISCVBaseInfo.h:218
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:144
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:51
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:197
uint64_t
llvm::RISCVII::getVLOpNum
static unsigned getVLOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:171
llvm::RISCVII::IsRVVWideningReductionMask
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:90
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:224
RISCVISAInfo.h
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:58
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:79
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:249
llvm::RISCVII::UsesMaskPolicyShift
@ UsesMaskPolicyShift
Definition: RISCVBaseInfo.h:96
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:198
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:251
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::RISCVII::IsRVVWideningReductionShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:89
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:254
llvm::RISCVII::hasMergeOp
static bool hasMergeOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:147
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:105
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:52
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:110
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:203
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:219
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:69
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:210
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:143
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:54
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:257
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:160
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:398
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:354
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:287
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:307
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:429
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:130
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:135
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:38
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:31
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:305
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:41
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:37
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:39
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:199
StringSwitch.h
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:317
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:215
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::RISCVSysReg::SysReg::DeprecatedName
const char * DeprecatedName
Definition: RISCVBaseInfo.h:306
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:32
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:247
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:114
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:200
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:355
llvm::RISCVVType::encodeLMUL
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:406
llvm::RISCVII::TAIL_AGNOSTIC
@ TAIL_AGNOSTIC
Definition: RISCVBaseInfo.h:120
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:115
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:45
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:349
llvm::RISCVII::hasDummyMaskOp
static bool hasDummyMaskOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:139
llvm::RISCVInsnOpcode::RISCVOpcode::Name
const char * Name
Definition: RISCVBaseInfo.h:337
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:253
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:33
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:318
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:30
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:216
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:194
llvm::RISCVII::MASK_AGNOSTIC
@ MASK_AGNOSTIC
Definition: RISCVBaseInfo.h:121
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:347
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:116
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Definition: RISCVBaseInfo.h:320
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24