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RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
24
25namespace llvm {
26
27// RISCVII - This namespace holds all of the target specific flags that
28// instruction info tracks. All definitions must match RISCVInstrFormats.td.
29namespace RISCVII {
30enum {
54
57
63
66
67 // Force a tail agnostic policy even this instruction has a tied destination.
70
71 // Is this a _TIED vector pseudo instruction. For these instructions we
72 // shouldn't skip the tied operand when converting to MC instructions.
75
76 // Does this instruction have a SEW operand. It will be the last explicit
77 // operand unless there is a vector policy operand. Used by RVV Pseudos.
80
81 // Does this instruction have a VL operand. It will be the second to last
82 // explicit operand unless there is a vector policy operand. Used by RVV
83 // Pseudos.
86
87 // Does this instruction have a vector policy operand. It will be the last
88 // explicit operand. Used by RVV Pseudos.
91
92 // Is this instruction a vector widening reduction instruction. Used by RVV
93 // Pseudos.
96
97 // Does this instruction care about mask policy. If it is not, the mask policy
98 // could be either agnostic or undisturbed. For example, unmasked, store, and
99 // reduction operations result would not be affected by mask policy, so
100 // compiler has free to select either one.
103
104 // Indicates that the result can be considered sign extended from bit 31. Some
105 // instructions with this flag aren't W instructions, but are either sign
106 // extended from a smaller size, always outputs a small integer, or put zeros
107 // in bits 63:31. Used by the SExtWRemoval pass.
110
113
116
117 // Indicates whether these instructions can partially overlap between source
118 // registers and destination registers according to the vector spec.
119 // 0 -> not a vector pseudo
120 // 1 -> default value for vector pseudos. not widening or narrowing.
121 // 2 -> narrowing case
122 // 3 -> widening case
125};
126
127enum VLMUL : uint8_t {
135 LMUL_F2
137
138enum {
142};
143
144// Helper functions to read TSFlags.
145/// \returns the format of the instruction.
146static inline unsigned getFormat(uint64_t TSFlags) {
147 return (TSFlags & InstFormatMask) >> InstFormatShift;
148}
149/// \returns the LMUL for the instruction.
150static inline VLMUL getLMul(uint64_t TSFlags) {
151 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
152}
153/// \returns true if tail agnostic is enforced for the instruction.
154static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
155 return TSFlags & ForceTailAgnosticMask;
156}
157/// \returns true if this a _TIED pseudo.
158static inline bool isTiedPseudo(uint64_t TSFlags) {
159 return TSFlags & IsTiedPseudoMask;
160}
161/// \returns true if there is a SEW operand for the instruction.
162static inline bool hasSEWOp(uint64_t TSFlags) {
163 return TSFlags & HasSEWOpMask;
164}
165/// \returns true if there is a VL operand for the instruction.
166static inline bool hasVLOp(uint64_t TSFlags) {
167 return TSFlags & HasVLOpMask;
168}
169/// \returns true if there is a vector policy operand for this instruction.
170static inline bool hasVecPolicyOp(uint64_t TSFlags) {
171 return TSFlags & HasVecPolicyOpMask;
172}
173/// \returns true if it is a vector widening reduction instruction.
174static inline bool isRVVWideningReduction(uint64_t TSFlags) {
175 return TSFlags & IsRVVWideningReductionMask;
176}
177/// \returns true if mask policy is valid for the instruction.
178static inline bool usesMaskPolicy(uint64_t TSFlags) {
179 return TSFlags & UsesMaskPolicyMask;
180}
181
182/// \returns true if there is a rounding mode operand for this instruction
183static inline bool hasRoundModeOp(uint64_t TSFlags) {
184 return TSFlags & HasRoundModeOpMask;
185}
186
187/// \returns true if this instruction uses vxrm
188static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
189
190static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
191 const uint64_t TSFlags = Desc.TSFlags;
192 // This method is only called if we expect to have a VL operand, and all
193 // instructions with VL also have SEW.
194 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
195 unsigned Offset = 2;
196 if (hasVecPolicyOp(TSFlags))
197 Offset = 3;
198 return Desc.getNumOperands() - Offset;
199}
200
201static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
202 const uint64_t TSFlags = Desc.TSFlags;
203 assert(hasSEWOp(TSFlags));
204 unsigned Offset = 1;
205 if (hasVecPolicyOp(TSFlags))
206 Offset = 2;
207 return Desc.getNumOperands() - Offset;
208}
209
210static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
211 assert(hasVecPolicyOp(Desc.TSFlags));
212 return Desc.getNumOperands() - 1;
213}
214
215/// \returns the index to the rounding mode immediate value if any, otherwise
216/// returns -1.
217static inline int getFRMOpNum(const MCInstrDesc &Desc) {
218 const uint64_t TSFlags = Desc.TSFlags;
219 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
220 return -1;
221
222 // The operand order
223 // --------------------------------------
224 // | n-1 (if any) | n-2 | n-3 | n-4 |
225 // | policy | sew | vl | frm |
226 // --------------------------------------
227 return getVLOpNum(Desc) - 1;
228}
229
230/// \returns the index to the rounding mode immediate value if any, otherwise
231/// returns -1.
232static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
233 const uint64_t TSFlags = Desc.TSFlags;
234 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
235 return -1;
236 // The operand order
237 // --------------------------------------
238 // | n-1 (if any) | n-2 | n-3 | n-4 |
239 // | policy | sew | vl | vxrm |
240 // --------------------------------------
241 return getVLOpNum(Desc) - 1;
242}
243
244// Is the first def operand tied to the first use operand. This is true for
245// vector pseudo instructions that have a merge operand for tail/mask
246// undisturbed. It's also true for vector FMA instructions where one of the
247// operands is also the destination register.
248static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
249 return Desc.getNumDefs() < Desc.getNumOperands() &&
250 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
251}
252
253// RISC-V Specific Machine Operand Flags
254enum {
257 MO_LO = 3,
258 MO_HI = 4,
271
272 // Used to differentiate between target-specific "direct" flags and "bitmask"
273 // flags. A machine operand can only have one "direct" flag, but can have
274 // multiple "bitmask" flags.
277} // namespace RISCVII
278
279namespace RISCVOp {
280enum OperandType : unsigned {
317 // Operand is either a register or uimm5, this is used by V extension pseudo
318 // instructions to represent a value that be passed as AVL to either vsetvli
319 // or vsetivli.
321};
322} // namespace RISCVOp
323
324// Describes the predecessor/successor bits used in the FENCE instruction.
325namespace RISCVFenceField {
327 I = 8,
328 O = 4,
329 R = 2,
330 W = 1
332}
333
334// Describes the supported floating point rounding mode encodings.
335namespace RISCVFPRndMode {
337 RNE = 0,
338 RTZ = 1,
339 RDN = 2,
340 RUP = 3,
341 RMM = 4,
342 DYN = 7,
343 Invalid
345
347 switch (RndMode) {
348 default:
349 llvm_unreachable("Unknown floating point rounding mode");
351 return "rne";
353 return "rtz";
355 return "rdn";
357 return "rup";
359 return "rmm";
361 return "dyn";
362 }
363}
364
374}
375
376inline static bool isValidRoundingMode(unsigned Mode) {
377 switch (Mode) {
378 default:
379 return false;
386 return true;
387 }
388}
389} // namespace RISCVFPRndMode
390
391//===----------------------------------------------------------------------===//
392// Floating-point Immediates
393//
394
395namespace RISCVLoadFPImm {
396float getFPImm(unsigned Imm);
397
398/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
399/// immediate value. If the value cannot be represented as a 5-bit binary
400/// encoding, then return -1.
401int getLoadFPImm(APFloat FPImm);
402} // namespace RISCVLoadFPImm
403
404namespace RISCVSysReg {
405struct SysReg {
406 const char *Name;
407 const char *AltName;
408 const char *DeprecatedName;
409 unsigned Encoding;
410 // FIXME: add these additional fields when needed.
411 // Privilege Access: Read, Write, Read-Only.
412 // unsigned ReadWrite;
413 // Privilege Mode: User, System or Machine.
414 // unsigned Mode;
415 // Check field name.
416 // unsigned Extra;
417 // Register number without the privilege bits.
418 // unsigned Number;
421
422 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
423 // Not in 32-bit mode.
424 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
425 return false;
426 // No required feature associated with the system register.
428 return true;
429 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
430 }
431};
432
433#define GET_SysRegsList_DECL
434#include "RISCVGenSearchableTables.inc"
435} // end namespace RISCVSysReg
436
437namespace RISCVInsnOpcode {
439 const char *Name;
440 unsigned Value;
441};
442
443#define GET_RISCVOpcodesList_DECL
444#include "RISCVGenSearchableTables.inc"
445} // end namespace RISCVInsnOpcode
446
447namespace RISCVABI {
448
449enum ABI {
460
461// Returns the target ABI, or else a StringError if the requested ABIName is
462// not supported for the given TT and FeatureBits combination.
463ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
464 StringRef ABIName);
465
466ABI getTargetABI(StringRef ABIName);
467
468// Returns the register used to hold the stack pointer after realignment.
470
471// Returns the register holding shadow call stack pointer.
473
474} // namespace RISCVABI
475
476namespace RISCVFeatures {
477
478// Validates if the given combination of features are valid for the target
479// triple. Exits with report_fatal_error if not.
480void validate(const Triple &TT, const FeatureBitset &FeatureBits);
481
483parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
484
485} // namespace RISCVFeatures
486
487namespace RISCVVType {
488// Is this a SEW value that can be encoded into the VTYPE format.
489inline static bool isValidSEW(unsigned SEW) {
490 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
491}
492
493// Is this a LMUL value that can be encoded into the VTYPE format.
494inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
495 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
496}
497
498unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
499 bool MaskAgnostic);
500
501inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
502 unsigned VLMUL = VType & 0x7;
503 return static_cast<RISCVII::VLMUL>(VLMUL);
504}
505
506// Decode VLMUL into 1,2,4,8 and fractional indicator.
507std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
508
509inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
510 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
511 unsigned LmulLog2 = Log2_32(LMUL);
512 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
513}
514
515inline static unsigned decodeVSEW(unsigned VSEW) {
516 assert(VSEW < 8 && "Unexpected VSEW value");
517 return 1 << (VSEW + 3);
518}
519
520inline static unsigned encodeSEW(unsigned SEW) {
521 assert(isValidSEW(SEW) && "Unexpected SEW value");
522 return Log2_32(SEW) - 3;
523}
524
525inline static unsigned getSEW(unsigned VType) {
526 unsigned VSEW = (VType >> 3) & 0x7;
527 return decodeVSEW(VSEW);
528}
529
530inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
531
532inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
533
534void printVType(unsigned VType, raw_ostream &OS);
535
536unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537
538std::optional<RISCVII::VLMUL>
539getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
540} // namespace RISCVVType
541
542namespace RISCVRVC {
543bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
544bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
545} // namespace RISCVRVC
546
547namespace RISCVZC {
549 RA = 4,
560 // note - to include s10, s11 must also be included
563};
564
565inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
566 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
567 switch (EndReg) {
568 case RISCV::X1:
569 return RLISTENCODE::RA;
570 case RISCV::X8:
571 return RLISTENCODE::RA_S0;
572 case RISCV::X9:
574 case RISCV::X18:
576 case RISCV::X19:
578 case RISCV::X20:
580 case RISCV::X21:
582 case RISCV::X22:
584 case RISCV::X23:
586 case RISCV::X24:
588 case RISCV::X25:
590 case RISCV::X26:
592 case RISCV::X27:
594 default:
595 llvm_unreachable("Undefined input.");
596 }
597}
598
599inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
600 bool IsEABI) {
602 "{ra, s0-s10} is not supported, s11 must be included.");
603 if (IsEABI)
604 return 16;
605 if (!IsRV64) {
606 switch (RlistVal) {
607 case RLISTENCODE::RA:
611 return 16;
616 return 32;
620 return 48;
622 return 64;
623 }
624 } else {
625 switch (RlistVal) {
626 case RLISTENCODE::RA:
628 return 16;
631 return 32;
634 return 48;
637 return 64;
640 return 80;
642 return 96;
644 return 112;
645 }
646 }
647 llvm_unreachable("Unexpected RlistVal");
648}
649
650inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
651 int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
652 if (RlistVal == RLISTENCODE::INVALID_RLIST)
653 return false;
654 unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
655 SpimmVal = (StackAdjustment - stackAdj) / 16;
656 if (SpimmVal > 3)
657 return false;
658 return true;
659}
660
661void printRlist(unsigned SlistEncode, raw_ostream &OS);
662void printSpimm(int64_t Spimm, raw_ostream &OS);
663} // namespace RISCVZC
664
665} // namespace llvm
666
667#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:474
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static int getFRMOpNum(const MCInstrDesc &Desc)
static int getVXRMOpNum(const MCInstrDesc &Desc)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool usesVXRM(uint64_t TSFlags)
static bool isRVVWideningReduction(uint64_t TSFlags)
@ TargetOverlapConstraintTypeMask
@ TargetOverlapConstraintTypeShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:94
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:95
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static unsigned decodeVSEW(unsigned VSEW)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, bool IsEABI)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64, bool IsEABI)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:313
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
Description of the encoding of one expression Op.
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const