LLVM  16.0.0git
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 
23 namespace llvm {
24 
25 // RISCVII - This namespace holds all of the target specific flags that
26 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
27 namespace RISCVII {
28 enum {
47 
50 
53 
55  VLMulMask = 0b111 << VLMulShift,
56 
57  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
60 
61  // Force a tail agnostic policy even this instruction has a tied destination.
64 
65  // Does this instruction have a merge operand that must be removed when
66  // converting to MCInst. It will be the first explicit use operand. Used by
67  // RVV Pseudos.
70 
71  // Does this instruction have a SEW operand. It will be the last explicit
72  // operand unless there is a vector policy operand. Used by RVV Pseudos.
75 
76  // Does this instruction have a VL operand. It will be the second to last
77  // explicit operand unless there is a vector policy operand. Used by RVV
78  // Pseudos.
81 
82  // Does this instruction have a vector policy operand. It will be the last
83  // explicit operand. Used by RVV Pseudos.
86 
87  // Is this instruction a vector widening reduction instruction. Used by RVV
88  // Pseudos.
91 
92  // Does this instruction care about mask policy. If it is not, the mask policy
93  // could be either agnostic or undisturbed. For example, unmasked, store, and
94  // reduction operations result would not be affected by mask policy, so
95  // compiler has free to select either one.
98 };
99 
100 // Match with the definitions in RISCVInstrFormats.td
103  VS2Constraint = 0b001,
104  VS1Constraint = 0b010,
105  VMConstraint = 0b100,
106 };
107 
108 enum VLMUL : uint8_t {
109  LMUL_1 = 0,
117 };
118 
119 enum {
122 };
123 
124 // Helper functions to read TSFlags.
125 /// \returns the format of the instruction.
126 static inline unsigned getFormat(uint64_t TSFlags) {
127  return (TSFlags & InstFormatMask) >> InstFormatShift;
128 }
129 /// \returns the constraint for the instruction.
131  return static_cast<VConstraintType>((TSFlags & ConstraintMask) >>
133 }
134 /// \returns the LMUL for the instruction.
135 static inline VLMUL getLMul(uint64_t TSFlags) {
136  return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
137 }
138 /// \returns true if there is a dummy mask operand for the instruction.
139 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
140  return TSFlags & HasDummyMaskOpMask;
141 }
142 /// \returns true if tail agnostic is enforced for the instruction.
145 }
146 /// \returns true if there is a merge operand for the instruction.
147 static inline bool hasMergeOp(uint64_t TSFlags) {
148  return TSFlags & HasMergeOpMask;
149 }
150 /// \returns true if there is a SEW operand for the instruction.
151 static inline bool hasSEWOp(uint64_t TSFlags) {
152  return TSFlags & HasSEWOpMask;
153 }
154 /// \returns true if there is a VL operand for the instruction.
155 static inline bool hasVLOp(uint64_t TSFlags) {
156  return TSFlags & HasVLOpMask;
157 }
158 /// \returns true if there is a vector policy operand for this instruction.
159 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
160  return TSFlags & HasVecPolicyOpMask;
161 }
162 /// \returns true if it is a vector widening reduction instruction.
165 }
166 /// \returns true if mask policy is valid for the instruction.
167 static inline bool usesMaskPolicy(uint64_t TSFlags) {
168  return TSFlags & UsesMaskPolicyMask;
169 }
170 
171 static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
172  assert(hasMergeOp(Desc.TSFlags));
173  assert(!Desc.isVariadic());
174  return Desc.getNumDefs();
175 }
176 
177 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
178  const uint64_t TSFlags = Desc.TSFlags;
179  // This method is only called if we expect to have a VL operand, and all
180  // instructions with VL also have SEW.
182  unsigned Offset = 2;
183  if (hasVecPolicyOp(TSFlags))
184  Offset = 3;
185  return Desc.getNumOperands() - Offset;
186 }
187 
188 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
189  const uint64_t TSFlags = Desc.TSFlags;
191  unsigned Offset = 1;
192  if (hasVecPolicyOp(TSFlags))
193  Offset = 2;
194  return Desc.getNumOperands() - Offset;
195 }
196 
197 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
199  return Desc.getNumOperands() - 1;
200 }
201 
202 // RISC-V Specific Machine Operand Flags
203 enum {
204  MO_None = 0,
205  MO_CALL = 1,
206  MO_PLT = 2,
207  MO_LO = 3,
208  MO_HI = 4,
217 
218  // Used to differentiate between target-specific "direct" flags and "bitmask"
219  // flags. A machine operand can only have one "direct" flag, but can have
220  // multiple "bitmask" flags.
222 };
223 } // namespace RISCVII
224 
225 namespace RISCVOp {
226 enum OperandType : unsigned {
253  // Operand is either a register or uimm5, this is used by V extension pseudo
254  // instructions to represent a value that be passed as AVL to either vsetvli
255  // or vsetivli.
257 };
258 } // namespace RISCVOp
259 
260 // Describes the predecessor/successor bits used in the FENCE instruction.
261 namespace RISCVFenceField {
263  I = 8,
264  O = 4,
265  R = 2,
266  W = 1
267 };
268 }
269 
270 // Describes the supported floating point rounding mode encodings.
271 namespace RISCVFPRndMode {
273  RNE = 0,
274  RTZ = 1,
275  RDN = 2,
276  RUP = 3,
277  RMM = 4,
278  DYN = 7,
280 };
281 
283  switch (RndMode) {
284  default:
285  llvm_unreachable("Unknown floating point rounding mode");
286  case RISCVFPRndMode::RNE:
287  return "rne";
288  case RISCVFPRndMode::RTZ:
289  return "rtz";
290  case RISCVFPRndMode::RDN:
291  return "rdn";
292  case RISCVFPRndMode::RUP:
293  return "rup";
294  case RISCVFPRndMode::RMM:
295  return "rmm";
296  case RISCVFPRndMode::DYN:
297  return "dyn";
298  }
299 }
300 
302  return StringSwitch<RoundingMode>(Str)
303  .Case("rne", RISCVFPRndMode::RNE)
304  .Case("rtz", RISCVFPRndMode::RTZ)
305  .Case("rdn", RISCVFPRndMode::RDN)
306  .Case("rup", RISCVFPRndMode::RUP)
307  .Case("rmm", RISCVFPRndMode::RMM)
308  .Case("dyn", RISCVFPRndMode::DYN)
310 }
311 
312 inline static bool isValidRoundingMode(unsigned Mode) {
313  switch (Mode) {
314  default:
315  return false;
316  case RISCVFPRndMode::RNE:
317  case RISCVFPRndMode::RTZ:
318  case RISCVFPRndMode::RDN:
319  case RISCVFPRndMode::RUP:
320  case RISCVFPRndMode::RMM:
321  case RISCVFPRndMode::DYN:
322  return true;
323  }
324 }
325 } // namespace RISCVFPRndMode
326 
327 namespace RISCVSysReg {
328 struct SysReg {
329  const char *Name;
330  const char *AltName;
331  const char *DeprecatedName;
332  unsigned Encoding;
333  // FIXME: add these additional fields when needed.
334  // Privilege Access: Read, Write, Read-Only.
335  // unsigned ReadWrite;
336  // Privilege Mode: User, System or Machine.
337  // unsigned Mode;
338  // Check field name.
339  // unsigned Extra;
340  // Register number without the privilege bits.
341  // unsigned Number;
344 
345  bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
346  // Not in 32-bit mode.
347  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
348  return false;
349  // No required feature associated with the system register.
350  if (FeaturesRequired.none())
351  return true;
352  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
353  }
354 };
355 
356 #define GET_SysRegsList_DECL
357 #include "RISCVGenSearchableTables.inc"
358 } // end namespace RISCVSysReg
359 
360 namespace RISCVInsnOpcode {
361 struct RISCVOpcode {
362  const char *Name;
363  unsigned Value;
364 };
365 
366 #define GET_RISCVOpcodesList_DECL
367 #include "RISCVGenSearchableTables.inc"
368 } // end namespace RISCVInsnOpcode
369 
370 namespace RISCVABI {
371 
372 enum ABI {
381 };
382 
383 // Returns the target ABI, or else a StringError if the requested ABIName is
384 // not supported for the given TT and FeatureBits combination.
385 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
386  StringRef ABIName);
387 
388 ABI getTargetABI(StringRef ABIName);
389 
390 // Returns the register used to hold the stack pointer after realignment.
392 
393 // Returns the register holding shadow call stack pointer.
395 
396 } // namespace RISCVABI
397 
398 namespace RISCVFeatures {
399 
400 // Validates if the given combination of features are valid for the target
401 // triple. Exits with report_fatal_error if not.
402 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
403 
405 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
406 
407 } // namespace RISCVFeatures
408 
409 namespace RISCVVType {
410 // Is this a SEW value that can be encoded into the VTYPE format.
411 inline static bool isValidSEW(unsigned SEW) {
412  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
413 }
414 
415 // Is this a LMUL value that can be encoded into the VTYPE format.
416 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
417  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
418 }
419 
420 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
421  bool MaskAgnostic);
422 
423 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
424  unsigned VLMUL = VType & 0x7;
425  return static_cast<RISCVII::VLMUL>(VLMUL);
426 }
427 
428 // Decode VLMUL into 1,2,4,8 and fractional indicator.
429 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
430 
431 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
432  assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
433  unsigned LmulLog2 = Log2_32(LMUL);
434  return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
435 }
436 
437 inline static unsigned decodeVSEW(unsigned VSEW) {
438  assert(VSEW < 8 && "Unexpected VSEW value");
439  return 1 << (VSEW + 3);
440 }
441 
442 inline static unsigned encodeSEW(unsigned SEW) {
443  assert(isValidSEW(SEW) && "Unexpected SEW value");
444  return Log2_32(SEW) - 3;
445 }
446 
447 inline static unsigned getSEW(unsigned VType) {
448  unsigned VSEW = (VType >> 3) & 0x7;
449  return decodeVSEW(VSEW);
450 }
451 
452 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
453 
454 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
455 
456 void printVType(unsigned VType, raw_ostream &OS);
457 
458 } // namespace RISCVVType
459 
460 } // namespace llvm
461 
462 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:109
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:378
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:273
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:44
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:263
llvm::RISCVII::getSEWOpNum
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:188
llvm::RISCVII::isRVVWideningReduction
static bool isRVVWideningReduction(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:163
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:277
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:58
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:416
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:214
llvm::RISCVOp::OPERAND_SIMM6
@ OPERAND_SIMM6
Definition: RISCVBaseInfo.h:240
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:243
llvm::RISCVII::usesMaskPolicy
static bool usesMaskPolicy(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:167
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:104
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:72
llvm::RISCVOp::OPERAND_SIMM5_PLUS1
@ OPERAND_SIMM5_PLUS1
Definition: RISCVBaseInfo.h:239
MCInstrDesc.h
StringRef.h
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:59
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:252
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:211
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:221
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:266
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:246
llvm::RISCVInsnOpcode::RISCVOpcode
Definition: RISCVBaseInfo.h:361
llvm::RISCVII::TAIL_AGNOSTIC
@ TAIL_AGNOSTIC
Definition: RISCVBaseInfo.h:120
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:38
llvm::RISCVII::LMUL_RESERVED
@ LMUL_RESERVED
Definition: RISCVBaseInfo.h:113
llvm::RISCVInsnOpcode::RISCVOpcode::Value
unsigned Value
Definition: RISCVBaseInfo.h:363
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:208
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:275
llvm::RISCVII::getVecPolicyOpNum
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:197
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:112
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:411
llvm::RISCVII::HasVecPolicyOpShift
@ HasVecPolicyOpShift
Definition: RISCVBaseInfo.h:84
llvm::RISCVII::MASK_AGNOSTIC
@ MASK_AGNOSTIC
Definition: RISCVBaseInfo.h:121
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:151
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:80
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:103
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:452
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:262
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:42
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:215
llvm::RISCVII::UsesMaskPolicyShift
@ UsesMaskPolicyShift
Definition: RISCVBaseInfo.h:96
llvm::RISCVOp::OPERAND_UIMM8_LSB000
@ OPERAND_UIMM8_LSB000
Definition: RISCVBaseInfo.h:235
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:205
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:94
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:48
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:329
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:301
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:159
llvm::RISCVOp::OPERAND_SIMM6_NONZERO
@ OPERAND_SIMM6_NONZERO
Definition: RISCVBaseInfo.h:241
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:447
llvm::RISCVII::HasVecPolicyOpMask
@ HasVecPolicyOpMask
Definition: RISCVBaseInfo.h:85
llvm::RISCVOp::OPERAND_AVL
@ OPERAND_AVL
Definition: RISCVBaseInfo.h:256
llvm::RISCVOp::OPERAND_UIMM7
@ OPERAND_UIMM7
Definition: RISCVBaseInfo.h:232
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:373
TailAgnostic
bool TailAgnostic
Definition: RISCVInsertVSETVLI.cpp:783
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:111
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:102
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:377
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:30
SubtargetFeature.h
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:216
llvm::RISCVVType::encodeSEW
static unsigned encodeSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:442
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:45
llvm::RISCVOp::OPERAND_RVKRNUM
@ OPERAND_RVKRNUM
Definition: RISCVBaseInfo.h:251
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:46
llvm::RISCVII::UsesMaskPolicyMask
@ UsesMaskPolicyMask
Definition: RISCVBaseInfo.h:97
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:207
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:547
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:155
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:375
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:231
llvm::RISCVVType::decodeVSEW
static unsigned decodeVSEW(unsigned VSEW)
Definition: RISCVBaseInfo.h:437
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:376
RISCVMCTargetDesc.h
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:328
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:236
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:91
llvm::RISCVOp::OPERAND_UIMM2
@ OPERAND_UIMM2
Definition: RISCVBaseInfo.h:228
llvm::RISCVII::VConstraintType
VConstraintType
Definition: RISCVBaseInfo.h:101
llvm::RISCVFeatures::parseFeatureBits
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:110
llvm::RISCVII::IsRVVWideningReductionMask
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:90
llvm::RISCVOp::OPERAND_VTYPEI11
@ OPERAND_VTYPEI11
Definition: RISCVBaseInfo.h:250
llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
Definition: RISCVBaseInfo.h:242
llvm::RISCVII::getConstraint
static VConstraintType getConstraint(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:130
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:73
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:126
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:37
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:52
llvm::RISCVOp::OPERAND_UIMM_SHFL
@ OPERAND_UIMM_SHFL
Definition: RISCVBaseInfo.h:248
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:775
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:29
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:54
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:39
llvm::RISCVOp::OPERAND_UIMM3
@ OPERAND_UIMM3
Definition: RISCVBaseInfo.h:229
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:147
uint64_t
llvm::RISCVII::getVLOpNum
static unsigned getVLOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:177
llvm::RISCVII::getMergeOpNum
static unsigned getMergeOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:171
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:209
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:245
RISCVISAInfo.h
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:274
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:276
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:210
llvm::RISCVII::IsRVVWideningReductionShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:89
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:279
MaskAgnostic
bool MaskAgnostic
Definition: RISCVInsertVSETVLI.cpp:790
llvm::RISCVII::hasMergeOp
static bool hasMergeOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:147
llvm::RISCVOp::OPERAND_SIMM5
@ OPERAND_SIMM5
Definition: RISCVBaseInfo.h:238
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:105
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:110
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:35
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:31
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:230
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:213
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:32
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:143
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:282
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:163
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:55
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:423
llvm::RISCVOp::OPERAND_UIMM8_LSB00
@ OPERAND_UIMM8_LSB00
Definition: RISCVBaseInfo.h:234
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:379
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:74
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:312
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:332
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:454
llvm::RISCVOp::OPERAND_VTYPEI10
@ OPERAND_VTYPEI10
Definition: RISCVBaseInfo.h:249
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMMLOG2XLEN_NONZERO
Definition: RISCVBaseInfo.h:247
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:133
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:135
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:79
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:330
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:37
StringSwitch.h
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:342
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:206
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:226
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:34
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::RISCVSysReg::SysReg::DeprecatedName
const char * DeprecatedName
Definition: RISCVBaseInfo.h:331
SEW
unsigned SEW
Definition: RISCVInsertVSETVLI.cpp:825
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:272
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:36
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:114
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:204
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:40
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:380
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:51
llvm::RISCVOp::OPERAND_ZERO
@ OPERAND_ZERO
Definition: RISCVBaseInfo.h:237
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:63
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:212
llvm::RISCVVType::encodeLMUL
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:431
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:115
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:33
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:68
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::StringSwitch::Default
R Default(T Value)
Definition: StringSwitch.h:182
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:374
llvm::RISCVII::hasDummyMaskOp
static bool hasDummyMaskOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:139
llvm::RISCVOp::OPERAND_SIMM12_LSB00000
@ OPERAND_SIMM12_LSB00000
Definition: RISCVBaseInfo.h:244
llvm::RISCVOp::OPERAND_UIMM7_LSB00
@ OPERAND_UIMM7_LSB00
Definition: RISCVBaseInfo.h:233
llvm::RISCVInsnOpcode::RISCVOpcode::Name
const char * Name
Definition: RISCVBaseInfo.h:362
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:41
llvm::RISCVII::InstFormatShift
@ InstFormatShift
Definition: RISCVBaseInfo.h:49
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:278
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:343
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:227
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:69
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:62
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:372
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:116
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Definition: RISCVBaseInfo.h:345
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:43