LLVM 19.0.0git
RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
25
26namespace llvm {
27
28// RISCVII - This namespace holds all of the target specific flags that
29// instruction info tracks. All definitions must match RISCVInstrFormats.td.
30namespace RISCVII {
31enum {
55
58
64
67
68 // Force a tail agnostic policy even this instruction has a tied destination.
71
72 // Is this a _TIED vector pseudo instruction. For these instructions we
73 // shouldn't skip the tied operand when converting to MC instructions.
76
77 // Does this instruction have a SEW operand. It will be the last explicit
78 // operand unless there is a vector policy operand. Used by RVV Pseudos.
81
82 // Does this instruction have a VL operand. It will be the second to last
83 // explicit operand unless there is a vector policy operand. Used by RVV
84 // Pseudos.
87
88 // Does this instruction have a vector policy operand. It will be the last
89 // explicit operand. Used by RVV Pseudos.
92
93 // Is this instruction a vector widening reduction instruction. Used by RVV
94 // Pseudos.
97
98 // Does this instruction care about mask policy. If it is not, the mask policy
99 // could be either agnostic or undisturbed. For example, unmasked, store, and
100 // reduction operations result would not be affected by mask policy, so
101 // compiler has free to select either one.
104
105 // Indicates that the result can be considered sign extended from bit 31. Some
106 // instructions with this flag aren't W instructions, but are either sign
107 // extended from a smaller size, always outputs a small integer, or put zeros
108 // in bits 63:31. Used by the SExtWRemoval pass.
111
114
117
118 // Indicates whether these instructions can partially overlap between source
119 // registers and destination registers according to the vector spec.
120 // 0 -> not a vector pseudo
121 // 1 -> default value for vector pseudos. not widening or narrowing.
122 // 2 -> narrowing case
123 // 3 -> widening case
126};
127
128// Helper functions to read TSFlags.
129/// \returns the format of the instruction.
130static inline unsigned getFormat(uint64_t TSFlags) {
131 return (TSFlags & InstFormatMask) >> InstFormatShift;
132}
133/// \returns the LMUL for the instruction.
134static inline VLMUL getLMul(uint64_t TSFlags) {
135 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
136}
137/// \returns true if tail agnostic is enforced for the instruction.
138static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
139 return TSFlags & ForceTailAgnosticMask;
140}
141/// \returns true if this a _TIED pseudo.
142static inline bool isTiedPseudo(uint64_t TSFlags) {
143 return TSFlags & IsTiedPseudoMask;
144}
145/// \returns true if there is a SEW operand for the instruction.
146static inline bool hasSEWOp(uint64_t TSFlags) {
147 return TSFlags & HasSEWOpMask;
148}
149/// \returns true if there is a VL operand for the instruction.
150static inline bool hasVLOp(uint64_t TSFlags) {
151 return TSFlags & HasVLOpMask;
152}
153/// \returns true if there is a vector policy operand for this instruction.
154static inline bool hasVecPolicyOp(uint64_t TSFlags) {
155 return TSFlags & HasVecPolicyOpMask;
156}
157/// \returns true if it is a vector widening reduction instruction.
158static inline bool isRVVWideningReduction(uint64_t TSFlags) {
159 return TSFlags & IsRVVWideningReductionMask;
160}
161/// \returns true if mask policy is valid for the instruction.
162static inline bool usesMaskPolicy(uint64_t TSFlags) {
163 return TSFlags & UsesMaskPolicyMask;
164}
165
166/// \returns true if there is a rounding mode operand for this instruction
167static inline bool hasRoundModeOp(uint64_t TSFlags) {
168 return TSFlags & HasRoundModeOpMask;
169}
170
171/// \returns true if this instruction uses vxrm
172static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
173
174static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
175 const uint64_t TSFlags = Desc.TSFlags;
176 // This method is only called if we expect to have a VL operand, and all
177 // instructions with VL also have SEW.
178 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
179 unsigned Offset = 2;
180 if (hasVecPolicyOp(TSFlags))
181 Offset = 3;
182 return Desc.getNumOperands() - Offset;
183}
184
185static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
186 const uint64_t TSFlags = Desc.TSFlags;
187 assert(hasSEWOp(TSFlags));
188 unsigned Offset = 1;
189 if (hasVecPolicyOp(TSFlags))
190 Offset = 2;
191 return Desc.getNumOperands() - Offset;
192}
193
194static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
195 assert(hasVecPolicyOp(Desc.TSFlags));
196 return Desc.getNumOperands() - 1;
197}
198
199/// \returns the index to the rounding mode immediate value if any, otherwise
200/// returns -1.
201static inline int getFRMOpNum(const MCInstrDesc &Desc) {
202 const uint64_t TSFlags = Desc.TSFlags;
203 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
204 return -1;
205
206 // The operand order
207 // --------------------------------------
208 // | n-1 (if any) | n-2 | n-3 | n-4 |
209 // | policy | sew | vl | frm |
210 // --------------------------------------
211 return getVLOpNum(Desc) - 1;
212}
213
214/// \returns the index to the rounding mode immediate value if any, otherwise
215/// returns -1.
216static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
217 const uint64_t TSFlags = Desc.TSFlags;
218 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
219 return -1;
220 // The operand order
221 // --------------------------------------
222 // | n-1 (if any) | n-2 | n-3 | n-4 |
223 // | policy | sew | vl | vxrm |
224 // --------------------------------------
225 return getVLOpNum(Desc) - 1;
226}
227
228// Is the first def operand tied to the first use operand. This is true for
229// vector pseudo instructions that have a merge operand for tail/mask
230// undisturbed. It's also true for vector FMA instructions where one of the
231// operands is also the destination register.
232static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
233 return Desc.getNumDefs() < Desc.getNumOperands() &&
234 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
235}
236
237// RISC-V Specific Machine Operand Flags
238enum {
241 MO_LO = 3,
242 MO_HI = 4,
255
256 // Used to differentiate between target-specific "direct" flags and "bitmask"
257 // flags. A machine operand can only have one "direct" flag, but can have
258 // multiple "bitmask" flags.
261} // namespace RISCVII
262
263namespace RISCVOp {
264enum OperandType : unsigned {
302 // Operand is either a register or uimm5, this is used by V extension pseudo
303 // instructions to represent a value that be passed as AVL to either vsetvli
304 // or vsetivli.
306};
307} // namespace RISCVOp
308
309// Describes the predecessor/successor bits used in the FENCE instruction.
310namespace RISCVFenceField {
312 I = 8,
313 O = 4,
314 R = 2,
315 W = 1
317}
318
319// Describes the supported floating point rounding mode encodings.
320namespace RISCVFPRndMode {
322 RNE = 0,
323 RTZ = 1,
324 RDN = 2,
325 RUP = 3,
326 RMM = 4,
327 DYN = 7,
328 Invalid
330
332 switch (RndMode) {
333 default:
334 llvm_unreachable("Unknown floating point rounding mode");
336 return "rne";
338 return "rtz";
340 return "rdn";
342 return "rup";
344 return "rmm";
346 return "dyn";
347 }
348}
349
359}
360
361inline static bool isValidRoundingMode(unsigned Mode) {
362 switch (Mode) {
363 default:
364 return false;
371 return true;
372 }
373}
374} // namespace RISCVFPRndMode
375
376namespace RISCVVXRndMode {
378 RNU = 0,
379 RNE = 1,
380 RDN = 2,
381 ROD = 3,
382};
383} // namespace RISCVVXRndMode
384
385//===----------------------------------------------------------------------===//
386// Floating-point Immediates
387//
388
389namespace RISCVLoadFPImm {
390float getFPImm(unsigned Imm);
391
392/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
393/// immediate value. If the value cannot be represented as a 5-bit binary
394/// encoding, then return -1.
395int getLoadFPImm(APFloat FPImm);
396} // namespace RISCVLoadFPImm
397
398namespace RISCVSysReg {
399struct SysReg {
400 const char *Name;
401 const char *AltName;
402 const char *DeprecatedName;
403 unsigned Encoding;
404 // FIXME: add these additional fields when needed.
405 // Privilege Access: Read, Write, Read-Only.
406 // unsigned ReadWrite;
407 // Privilege Mode: User, System or Machine.
408 // unsigned Mode;
409 // Check field name.
410 // unsigned Extra;
411 // Register number without the privilege bits.
412 // unsigned Number;
415
416 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
417 // Not in 32-bit mode.
418 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
419 return false;
420 // No required feature associated with the system register.
422 return true;
423 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
424 }
425};
426
427#define GET_SysRegsList_DECL
428#include "RISCVGenSearchableTables.inc"
429} // end namespace RISCVSysReg
430
431namespace RISCVInsnOpcode {
433 const char *Name;
434 unsigned Value;
435};
436
437#define GET_RISCVOpcodesList_DECL
438#include "RISCVGenSearchableTables.inc"
439} // end namespace RISCVInsnOpcode
440
441namespace RISCVABI {
442
443enum ABI {
454
455// Returns the target ABI, or else a StringError if the requested ABIName is
456// not supported for the given TT and FeatureBits combination.
457ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
458 StringRef ABIName);
459
460ABI getTargetABI(StringRef ABIName);
461
462// Returns the register used to hold the stack pointer after realignment.
464
465// Returns the register holding shadow call stack pointer.
467
468} // namespace RISCVABI
469
470namespace RISCVFeatures {
471
472// Validates if the given combination of features are valid for the target
473// triple. Exits with report_fatal_error if not.
474void validate(const Triple &TT, const FeatureBitset &FeatureBits);
475
477parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
478
479} // namespace RISCVFeatures
480
481namespace RISCVRVC {
482bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
483bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
484} // namespace RISCVRVC
485
486namespace RISCVZC {
488 RA = 4,
499 // note - to include s10, s11 must also be included
502};
503
504inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
505 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
506 switch (EndReg) {
507 case RISCV::X1:
508 return RLISTENCODE::RA;
509 case RISCV::X8:
510 return RLISTENCODE::RA_S0;
511 case RISCV::X9:
513 case RISCV::X18:
515 case RISCV::X19:
517 case RISCV::X20:
519 case RISCV::X21:
521 case RISCV::X22:
523 case RISCV::X23:
525 case RISCV::X24:
527 case RISCV::X25:
529 case RISCV::X26:
531 case RISCV::X27:
533 default:
534 llvm_unreachable("Undefined input.");
535 }
536}
537
538inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
540 "{ra, s0-s10} is not supported, s11 must be included.");
541 if (!IsRV64) {
542 switch (RlistVal) {
543 case RLISTENCODE::RA:
547 return 16;
552 return 32;
556 return 48;
558 return 64;
559 }
560 } else {
561 switch (RlistVal) {
562 case RLISTENCODE::RA:
564 return 16;
567 return 32;
570 return 48;
573 return 64;
576 return 80;
578 return 96;
580 return 112;
581 }
582 }
583 llvm_unreachable("Unexpected RlistVal");
584}
585
586inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
587 int64_t StackAdjustment, bool IsRV64) {
588 if (RlistVal == RLISTENCODE::INVALID_RLIST)
589 return false;
590 unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64);
591 StackAdjustment -= StackAdjBase;
592 if (StackAdjustment % 16 != 0)
593 return false;
594 SpimmVal = StackAdjustment / 16;
595 if (SpimmVal > 3)
596 return false;
597 return true;
598}
599
600void printRlist(unsigned SlistEncode, raw_ostream &OS);
601} // namespace RISCVZC
602
603} // namespace llvm
604
605#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:481
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasRoundModeOp(uint64_t TSFlags)
@ TargetOverlapConstraintTypeMask
@ TargetOverlapConstraintTypeShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:95
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:96
static bool isTiedPseudo(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static int getFRMOpNum(const MCInstrDesc &Desc)
static int getVXRMOpNum(const MCInstrDesc &Desc)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool usesVXRM(uint64_t TSFlags)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Description of the encoding of one expression Op.
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const