LLVM 17.0.0git
RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISCV target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/StringRef.h"
19#include "llvm/MC/MCInstrDesc.h"
22
23namespace llvm {
24
25// RISCVII - This namespace holds all of the target specific flags that
26// instruction info tracks. All definitions must match RISCVInstrFormats.td.
27namespace RISCVII {
28enum {
48
51
54
57
58 // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
61
62 // Force a tail agnostic policy even this instruction has a tied destination.
65
66 // Does this instruction have a merge operand that must be removed when
67 // converting to MCInst. It will be the first explicit use operand. Used by
68 // RVV Pseudos.
71
72 // Does this instruction have a SEW operand. It will be the last explicit
73 // operand unless there is a vector policy operand. Used by RVV Pseudos.
76
77 // Does this instruction have a VL operand. It will be the second to last
78 // explicit operand unless there is a vector policy operand. Used by RVV
79 // Pseudos.
82
83 // Does this instruction have a vector policy operand. It will be the last
84 // explicit operand. Used by RVV Pseudos.
87
88 // Is this instruction a vector widening reduction instruction. Used by RVV
89 // Pseudos.
92
93 // Does this instruction care about mask policy. If it is not, the mask policy
94 // could be either agnostic or undisturbed. For example, unmasked, store, and
95 // reduction operations result would not be affected by mask policy, so
96 // compiler has free to select either one.
99
100 // Indicates that the result can be considered sign extended from bit 31. Some
101 // instructions with this flag aren't W instructions, but are either sign
102 // extended from a smaller size, always outputs a small integer, or put zeros
103 // in bits 63:31. Used by the SExtWRemoval pass.
106};
107
108// Match with the definitions in RISCVInstrFormats.td
114};
115
116enum VLMUL : uint8_t {
124 LMUL_F2
126
127enum {
131};
132
133// Helper functions to read TSFlags.
134/// \returns the format of the instruction.
135static inline unsigned getFormat(uint64_t TSFlags) {
137}
138/// \returns the constraint for the instruction.
140 return static_cast<VConstraintType>((TSFlags & ConstraintMask) >>
142}
143/// \returns the LMUL for the instruction.
145 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
146}
147/// \returns true if there is a dummy mask operand for the instruction.
148static inline bool hasDummyMaskOp(uint64_t TSFlags) {
150}
151/// \returns true if tail agnostic is enforced for the instruction.
154}
155/// \returns true if there is a merge operand for the instruction.
156static inline bool hasMergeOp(uint64_t TSFlags) {
157 return TSFlags & HasMergeOpMask;
158}
159/// \returns true if there is a SEW operand for the instruction.
160static inline bool hasSEWOp(uint64_t TSFlags) {
161 return TSFlags & HasSEWOpMask;
162}
163/// \returns true if there is a VL operand for the instruction.
164static inline bool hasVLOp(uint64_t TSFlags) {
165 return TSFlags & HasVLOpMask;
166}
167/// \returns true if there is a vector policy operand for this instruction.
168static inline bool hasVecPolicyOp(uint64_t TSFlags) {
170}
171/// \returns true if it is a vector widening reduction instruction.
174}
175/// \returns true if mask policy is valid for the instruction.
176static inline bool usesMaskPolicy(uint64_t TSFlags) {
178}
179
180static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
182 assert(!Desc.isVariadic());
183 return Desc.getNumDefs();
184}
185
186static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
187 const uint64_t TSFlags = Desc.TSFlags;
188 // This method is only called if we expect to have a VL operand, and all
189 // instructions with VL also have SEW.
191 unsigned Offset = 2;
193 Offset = 3;
194 return Desc.getNumOperands() - Offset;
195}
196
197static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
198 const uint64_t TSFlags = Desc.TSFlags;
200 unsigned Offset = 1;
202 Offset = 2;
203 return Desc.getNumOperands() - Offset;
204}
205
206static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
208 return Desc.getNumOperands() - 1;
209}
210
211// RISC-V Specific Machine Operand Flags
212enum {
216 MO_LO = 3,
217 MO_HI = 4,
226
227 // Used to differentiate between target-specific "direct" flags and "bitmask"
228 // flags. A machine operand can only have one "direct" flag, but can have
229 // multiple "bitmask" flags.
232} // namespace RISCVII
233
234namespace RISCVOp {
235enum OperandType : unsigned {
263 // Operand is either a register or uimm5, this is used by V extension pseudo
264 // instructions to represent a value that be passed as AVL to either vsetvli
265 // or vsetivli.
267};
268} // namespace RISCVOp
269
270// Describes the predecessor/successor bits used in the FENCE instruction.
271namespace RISCVFenceField {
273 I = 8,
274 O = 4,
275 R = 2,
276 W = 1
278}
279
280// Describes the supported floating point rounding mode encodings.
281namespace RISCVFPRndMode {
283 RNE = 0,
284 RTZ = 1,
285 RDN = 2,
286 RUP = 3,
287 RMM = 4,
288 DYN = 7,
289 Invalid
291
293 switch (RndMode) {
294 default:
295 llvm_unreachable("Unknown floating point rounding mode");
297 return "rne";
299 return "rtz";
301 return "rdn";
303 return "rup";
305 return "rmm";
307 return "dyn";
308 }
309}
310
320}
321
322inline static bool isValidRoundingMode(unsigned Mode) {
323 switch (Mode) {
324 default:
325 return false;
332 return true;
333 }
334}
335} // namespace RISCVFPRndMode
336
337namespace RISCVSysReg {
338struct SysReg {
339 const char *Name;
340 const char *AltName;
341 const char *DeprecatedName;
342 unsigned Encoding;
343 // FIXME: add these additional fields when needed.
344 // Privilege Access: Read, Write, Read-Only.
345 // unsigned ReadWrite;
346 // Privilege Mode: User, System or Machine.
347 // unsigned Mode;
348 // Check field name.
349 // unsigned Extra;
350 // Register number without the privilege bits.
351 // unsigned Number;
354
355 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
356 // Not in 32-bit mode.
357 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
358 return false;
359 // No required feature associated with the system register.
361 return true;
362 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
363 }
364};
365
366#define GET_SysRegsList_DECL
367#include "RISCVGenSearchableTables.inc"
368} // end namespace RISCVSysReg
369
370namespace RISCVInsnOpcode {
372 const char *Name;
373 unsigned Value;
374};
375
376#define GET_RISCVOpcodesList_DECL
377#include "RISCVGenSearchableTables.inc"
378} // end namespace RISCVInsnOpcode
379
380namespace RISCVABI {
381
382enum ABI {
392
393// Returns the target ABI, or else a StringError if the requested ABIName is
394// not supported for the given TT and FeatureBits combination.
395ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
396 StringRef ABIName);
397
398ABI getTargetABI(StringRef ABIName);
399
400// Returns the register used to hold the stack pointer after realignment.
402
403// Returns the register holding shadow call stack pointer.
405
406} // namespace RISCVABI
407
408namespace RISCVFeatures {
409
410// Validates if the given combination of features are valid for the target
411// triple. Exits with report_fatal_error if not.
412void validate(const Triple &TT, const FeatureBitset &FeatureBits);
413
415parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
416
417} // namespace RISCVFeatures
418
419namespace RISCVVType {
420// Is this a SEW value that can be encoded into the VTYPE format.
421inline static bool isValidSEW(unsigned SEW) {
422 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
423}
424
425// Is this a LMUL value that can be encoded into the VTYPE format.
426inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
427 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
428}
429
430unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
431 bool MaskAgnostic);
432
433inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
434 unsigned VLMUL = VType & 0x7;
435 return static_cast<RISCVII::VLMUL>(VLMUL);
436}
437
438// Decode VLMUL into 1,2,4,8 and fractional indicator.
439std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
440
441inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
442 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
443 unsigned LmulLog2 = Log2_32(LMUL);
444 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
445}
446
447inline static unsigned decodeVSEW(unsigned VSEW) {
448 assert(VSEW < 8 && "Unexpected VSEW value");
449 return 1 << (VSEW + 3);
450}
451
452inline static unsigned encodeSEW(unsigned SEW) {
453 assert(isValidSEW(SEW) && "Unexpected SEW value");
454 return Log2_32(SEW) - 3;
455}
456
457inline static unsigned getSEW(unsigned VType) {
458 unsigned VSEW = (VType >> 3) & 0x7;
459 return decodeVSEW(VSEW);
460}
461
462inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
463
464inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
465
466void printVType(unsigned VType, raw_ostream &OS);
467
468unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
469
470} // namespace RISCVVType
471
472namespace RISCVRVC {
473bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
474bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
475} // namespace RISCVRVC
476
477} // namespace llvm
478
479#endif
IRTranslator LLVM IR MI
RISCVII::VLMUL VLMul
unsigned SEW
bool MaskAgnostic
bool TailAgnostic
uint64_t TSFlags
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:470
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:247
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:260
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:90
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:91
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasDummyMaskOp(uint64_t TSFlags)
static bool hasMergeOp(uint64_t TSFlags)
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static VConstraintType getConstraint(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getMergeOpNum(const MCInstrDesc &Desc)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static unsigned decodeVSEW(unsigned VSEW)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:373
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:288
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const