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13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
236 namespace RISCVFenceField {
246 namespace RISCVFPRndMode {
302 namespace RISCVSysReg {
322 if (
isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
331 #define GET_SysRegsList_DECL
332 #include "RISCVGenSearchableTables.inc"
335 namespace RISCVInsnOpcode {
341 #define GET_RISCVOpcodesList_DECL
342 #include "RISCVGenSearchableTables.inc"
373 namespace RISCVFeatures {
377 void validate(
const Triple &TT,
const FeatureBitset &FeatureBits);
384 namespace RISCVVType {
399 unsigned VLMUL = VType & 0x7;
409 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
413 assert(VSEW < 8 &&
"Unexpected VSEW value");
414 return 1 << (VSEW + 3);
422 inline static unsigned getSEW(
unsigned VType) {
423 unsigned VSEW = (VType >> 3) & 0x7;
StringSwitch & Case(StringLiteral S, T Value)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool isRVVWideningReduction(uint64_t TSFlags)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
This is an optimization pass for GlobalISel generic memory operations.
static bool usesMaskPolicy(uint64_t TSFlags)
ABI getTargetABI(StringRef ABIName)
LLVM_NODISCARD R Default(T Value)
Triple - Helper class for working with autoconf configuration names.
static bool isValidSEW(unsigned SEW)
static bool hasSEWOp(uint64_t TSFlags)
static bool isTailAgnostic(unsigned VType)
Container class for subtarget features.
Tagged union holding either a T or a Error.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
static RoundingMode stringToRoundingMode(StringRef Str)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getSEW(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Describe properties that are true of each instruction in the target description file.
static bool hasVLOp(uint64_t TSFlags)
static unsigned decodeVSEW(unsigned VSEW)
This class implements an extremely fast bulk output stream that can only output to a stream.
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static VConstraintType getConstraint(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
@ IsRVVWideningReductionMask
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ IsRVVWideningReductionShift
static bool hasMergeOp(uint64_t TSFlags)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool doesForceTailAgnostic(uint64_t TSFlags)
static StringRef roundingModeToString(RoundingMode RndMode)
void printVType(unsigned VType, raw_ostream &OS)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static bool isValidRoundingMode(unsigned Mode)
static bool isMaskAgnostic(unsigned VType)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static VLMUL getLMul(uint64_t TSFlags)
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
FeatureBitset FeaturesRequired
const char * DeprecatedName
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
A switch()-like statement whose cases are string literals.
static bool hasDummyMaskOp(uint64_t TSFlags)
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
@ OPERAND_FIRST_RISCV_IMM
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Wrapper class representing physical registers. Should be passed by value.