LLVM  14.0.0git
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
21 
22 namespace llvm {
23 
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
26 namespace RISCVII {
27 enum {
46 
49 
52 
54  VLMulMask = 0b111 << VLMulShift,
55 
56  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
59 
60  // Force a tail agnostic policy even this instruction has a tied destination.
63 
64  // Does this instruction have a merge operand that must be removed when
65  // converting to MCInst. It will be the first explicit use operand. Used by
66  // RVV Pseudos.
69 
70  // Does this instruction have a SEW operand. It will be the last explicit
71  // operand. Used by RVV Pseudos.
74 
75  // Does this instruction have a VL operand. It will be the second to last
76  // explicit operand. Used by RVV Pseudos.
79 };
80 
81 // Match with the definitions in RISCVInstrFormatsV.td
84  VS2Constraint = 0b001,
85  VS1Constraint = 0b010,
86  VMConstraint = 0b100,
87 };
88 
89 enum VLMUL : uint8_t {
90  LMUL_1 = 0,
98 };
99 
100 // Helper functions to read TSFlags.
101 /// \returns the format of the instruction.
102 static inline unsigned getFormat(uint64_t TSFlags) {
103  return (TSFlags & InstFormatMask) >> InstFormatShift;
104 }
105 /// \returns the constraint for the instruction.
106 static inline VConstraintType getConstraint(uint64_t TSFlags) {
107  return static_cast<VConstraintType>
108  ((TSFlags & ConstraintMask) >> ConstraintShift);
109 }
110 /// \returns the LMUL for the instruction.
111 static inline VLMUL getLMul(uint64_t TSFlags) {
112  return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
113 }
114 /// \returns true if there is a dummy mask operand for the instruction.
115 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
116  return TSFlags & HasDummyMaskOpMask;
117 }
118 /// \returns true if tail agnostic is enforced for the instruction.
119 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
120  return TSFlags & ForceTailAgnosticMask;
121 }
122 /// \returns true if there is a merge operand for the instruction.
123 static inline bool hasMergeOp(uint64_t TSFlags) {
124  return TSFlags & HasMergeOpMask;
125 }
126 /// \returns true if there is a SEW operand for the instruction.
127 static inline bool hasSEWOp(uint64_t TSFlags) {
128  return TSFlags & HasSEWOpMask;
129 }
130 /// \returns true if there is a VL operand for the instruction.
131 static inline bool hasVLOp(uint64_t TSFlags) {
132  return TSFlags & HasVLOpMask;
133 }
134 
135 // RISC-V Specific Machine Operand Flags
136 enum {
137  MO_None = 0,
138  MO_CALL = 1,
139  MO_PLT = 2,
140  MO_LO = 3,
141  MO_HI = 4,
150 
151  // Used to differentiate between target-specific "direct" flags and "bitmask"
152  // flags. A machine operand can only have one "direct" flag, but can have
153  // multiple "bitmask" flags.
155 };
156 } // namespace RISCVII
157 
158 namespace RISCVOp {
159 enum OperandType : unsigned {
168  // Operand is either a register or uimm5, this is used by V extension pseudo
169  // instructions to represent a value that be passed as AVL to either vsetvli
170  // or vsetivli.
172 };
173 } // namespace RISCVOp
174 
175 // Describes the predecessor/successor bits used in the FENCE instruction.
176 namespace RISCVFenceField {
178  I = 8,
179  O = 4,
180  R = 2,
181  W = 1
182 };
183 }
184 
185 // Describes the supported floating point rounding mode encodings.
186 namespace RISCVFPRndMode {
188  RNE = 0,
189  RTZ = 1,
190  RDN = 2,
191  RUP = 3,
192  RMM = 4,
193  DYN = 7,
195 };
196 
198  switch (RndMode) {
199  default:
200  llvm_unreachable("Unknown floating point rounding mode");
201  case RISCVFPRndMode::RNE:
202  return "rne";
203  case RISCVFPRndMode::RTZ:
204  return "rtz";
205  case RISCVFPRndMode::RDN:
206  return "rdn";
207  case RISCVFPRndMode::RUP:
208  return "rup";
209  case RISCVFPRndMode::RMM:
210  return "rmm";
211  case RISCVFPRndMode::DYN:
212  return "dyn";
213  }
214 }
215 
217  return StringSwitch<RoundingMode>(Str)
218  .Case("rne", RISCVFPRndMode::RNE)
219  .Case("rtz", RISCVFPRndMode::RTZ)
220  .Case("rdn", RISCVFPRndMode::RDN)
221  .Case("rup", RISCVFPRndMode::RUP)
222  .Case("rmm", RISCVFPRndMode::RMM)
223  .Case("dyn", RISCVFPRndMode::DYN)
225 }
226 
227 inline static bool isValidRoundingMode(unsigned Mode) {
228  switch (Mode) {
229  default:
230  return false;
231  case RISCVFPRndMode::RNE:
232  case RISCVFPRndMode::RTZ:
233  case RISCVFPRndMode::RDN:
234  case RISCVFPRndMode::RUP:
235  case RISCVFPRndMode::RMM:
236  case RISCVFPRndMode::DYN:
237  return true;
238  }
239 }
240 } // namespace RISCVFPRndMode
241 
242 namespace RISCVSysReg {
243 struct SysReg {
244  const char *Name;
245  const char *AltName;
246  const char *DeprecatedName;
247  unsigned Encoding;
248  // FIXME: add these additional fields when needed.
249  // Privilege Access: Read, Write, Read-Only.
250  // unsigned ReadWrite;
251  // Privilege Mode: User, System or Machine.
252  // unsigned Mode;
253  // Check field name.
254  // unsigned Extra;
255  // Register number without the privilege bits.
256  // unsigned Number;
259 
260  bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
261  // Not in 32-bit mode.
262  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
263  return false;
264  // No required feature associated with the system register.
265  if (FeaturesRequired.none())
266  return true;
267  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
268  }
269 };
270 
271 #define GET_SysRegsList_DECL
272 #include "RISCVGenSearchableTables.inc"
273 } // end namespace RISCVSysReg
274 
275 namespace RISCVABI {
276 
277 enum ABI {
286 };
287 
288 // Returns the target ABI, or else a StringError if the requested ABIName is
289 // not supported for the given TT and FeatureBits combination.
290 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
291  StringRef ABIName);
292 
293 ABI getTargetABI(StringRef ABIName);
294 
295 // Returns the register used to hold the stack pointer after realignment.
297 
298 // Returns the register holding shadow call stack pointer.
300 
301 } // namespace RISCVABI
302 
303 namespace RISCVFeatures {
304 
305 // Validates if the given combination of features are valid for the target
306 // triple. Exits with report_fatal_error if not.
307 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
308 
309 } // namespace RISCVFeatures
310 
311 namespace RISCVVType {
312 // Is this a SEW value that can be encoded into the VTYPE format.
313 inline static bool isValidSEW(unsigned SEW) {
314  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
315 }
316 
317 // Is this a LMUL value that can be encoded into the VTYPE format.
318 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
319  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
320 }
321 
322 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
323  bool MaskAgnostic);
324 
325 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
326  unsigned VLMUL = VType & 0x7;
327  return static_cast<RISCVII::VLMUL>(VLMUL);
328 }
329 
330 // Decode VLMUL into 1,2,4,8 and fractional indicator.
331 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
332 
333 inline static unsigned decodeVSEW(unsigned VSEW) {
334  assert(VSEW < 8 && "Unexpected VSEW value");
335  return 1 << (VSEW + 3);
336 }
337 
338 inline static unsigned getSEW(unsigned VType) {
339  unsigned VSEW = (VType >> 3) & 0x7;
340  return decodeVSEW(VSEW);
341 }
342 
343 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
344 
345 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
346 
347 void printVType(unsigned VType, raw_ostream &OS);
348 
349 } // namespace RISCVVType
350 
351 } // namespace llvm
352 
353 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:90
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:283
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:145
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:188
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:178
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:192
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:318
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:28
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:164
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:85
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:65
MCInstrDesc.h
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:53
StringRef.h
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:45
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:167
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:35
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:181
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:166
llvm::RISCVII::LMUL_RESERVED
@ LMUL_RESERVED
Definition: RISCVBaseInfo.h:94
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:41
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:190
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:51
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:93
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:313
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:127
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:84
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:343
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:177
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:40
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:47
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:97
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:244
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:90
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:216
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:143
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:81
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:338
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:33
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:146
llvm::RISCVOp::OPERAND_AVL
@ OPERAND_AVL
Definition: RISCVBaseInfo.h:171
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:180
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:44
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:278
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:92
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:83
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:282
SubtargetFeature.h
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:72
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:148
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:32
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:141
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:144
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:58
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:131
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:280
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:162
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:77
llvm::RISCVVType::decodeVSEW
static unsigned decodeVSEW(unsigned VSEW)
Definition: RISCVBaseInfo.h:333
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:281
RISCVMCTargetDesc.h
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:243
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:163
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:36
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:84
llvm::RISCVII::VConstraintType
VConstraintType
Definition: RISCVBaseInfo.h:82
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:50
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:34
llvm::RISCVII::getConstraint
static VConstraintType getConstraint(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:106
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:102
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:29
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:37
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:137
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:138
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:179
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:124
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:165
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:42
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:189
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:191
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:38
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:194
llvm::RISCVII::hasMergeOp
static bool hasMergeOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:123
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:86
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:68
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:149
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:91
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:31
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:161
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:142
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:119
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:197
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:140
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:325
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:284
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:30
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:227
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:247
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:345
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:110
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:111
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:57
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:245
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:61
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:26
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:67
StringSwitch.h
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:257
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:159
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::RISCVSysReg::SysReg::DeprecatedName
const char * DeprecatedName
Definition: RISCVBaseInfo.h:246
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:62
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:140
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:187
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:95
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:285
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:54
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:96
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:89
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:73
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:154
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:279
llvm::RISCVII::hasDummyMaskOp
static bool hasDummyMaskOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:115
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:139
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:147
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:193
llvm::RISCVII::InstFormatShift
@ InstFormatShift
Definition: RISCVBaseInfo.h:48
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:258
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:39
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:160
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:43
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:78
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:277
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:97
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Definition: RISCVBaseInfo.h:260
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23