LLVM  13.0.0git
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
21 
22 namespace llvm {
23 
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
26 namespace RISCVII {
27 enum {
46 
48 
51 
53  VLMulMask = 0b111 << VLMulShift,
54 
55  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
58 
59  // Force a tail agnostic policy even this instruction has a tied destination.
62 
63  // Does this instruction have a merge operand that must be removed when
64  // converting to MCInst. It will be the first explicit use operand. Used by
65  // RVV Pseudos.
68 
69  // Does this instruction have a SEW operand. It will be the last explicit
70  // operand. Used by RVV Pseudos.
73 
74  // Does this instruction have a VL operand. It will be the second to last
75  // explicit operand. Used by RVV Pseudos.
78 };
79 
80 // Match with the definitions in RISCVInstrFormatsV.td
83  VS2Constraint = 0b001,
84  VS1Constraint = 0b010,
85  VMConstraint = 0b100,
86 };
87 
88 // RISC-V Specific Machine Operand Flags
89 enum {
90  MO_None = 0,
91  MO_CALL = 1,
92  MO_PLT = 2,
93  MO_LO = 3,
94  MO_HI = 4,
97  MO_GOT_HI = 7,
103 
104  // Used to differentiate between target-specific "direct" flags and "bitmask"
105  // flags. A machine operand can only have one "direct" flag, but can have
106  // multiple "bitmask" flags.
108 };
109 } // namespace RISCVII
110 
111 namespace RISCVOp {
112 enum OperandType : unsigned {
121  // Operand is either a register or uimm5, this is used by V extension pseudo
122  // instructions to represent a value that be passed as AVL to either vsetvli
123  // or vsetivli.
125 };
126 } // namespace RISCVOp
127 
128 // Describes the predecessor/successor bits used in the FENCE instruction.
129 namespace RISCVFenceField {
131  I = 8,
132  O = 4,
133  R = 2,
134  W = 1
135 };
136 }
137 
138 // Describes the supported floating point rounding mode encodings.
139 namespace RISCVFPRndMode {
141  RNE = 0,
142  RTZ = 1,
143  RDN = 2,
144  RUP = 3,
145  RMM = 4,
146  DYN = 7,
148 };
149 
151  switch (RndMode) {
152  default:
153  llvm_unreachable("Unknown floating point rounding mode");
154  case RISCVFPRndMode::RNE:
155  return "rne";
156  case RISCVFPRndMode::RTZ:
157  return "rtz";
158  case RISCVFPRndMode::RDN:
159  return "rdn";
160  case RISCVFPRndMode::RUP:
161  return "rup";
162  case RISCVFPRndMode::RMM:
163  return "rmm";
164  case RISCVFPRndMode::DYN:
165  return "dyn";
166  }
167 }
168 
170  return StringSwitch<RoundingMode>(Str)
171  .Case("rne", RISCVFPRndMode::RNE)
172  .Case("rtz", RISCVFPRndMode::RTZ)
173  .Case("rdn", RISCVFPRndMode::RDN)
174  .Case("rup", RISCVFPRndMode::RUP)
175  .Case("rmm", RISCVFPRndMode::RMM)
176  .Case("dyn", RISCVFPRndMode::DYN)
178 }
179 
180 inline static bool isValidRoundingMode(unsigned Mode) {
181  switch (Mode) {
182  default:
183  return false;
184  case RISCVFPRndMode::RNE:
185  case RISCVFPRndMode::RTZ:
186  case RISCVFPRndMode::RDN:
187  case RISCVFPRndMode::RUP:
188  case RISCVFPRndMode::RMM:
189  case RISCVFPRndMode::DYN:
190  return true;
191  }
192 }
193 } // namespace RISCVFPRndMode
194 
195 namespace RISCVSysReg {
196 struct SysReg {
197  const char *Name;
198  unsigned Encoding;
199  const char *AltName;
200  // FIXME: add these additional fields when needed.
201  // Privilege Access: Read, Write, Read-Only.
202  // unsigned ReadWrite;
203  // Privilege Mode: User, System or Machine.
204  // unsigned Mode;
205  // Check field name.
206  // unsigned Extra;
207  // Register number without the privilege bits.
208  // unsigned Number;
211 
212  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
213  // Not in 32-bit mode.
214  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
215  return false;
216  // No required feature associated with the system register.
217  if (FeaturesRequired.none())
218  return true;
219  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
220  }
221 };
222 
223 #define GET_SysRegsList_DECL
224 #include "RISCVGenSearchableTables.inc"
225 } // end namespace RISCVSysReg
226 
227 namespace RISCVABI {
228 
229 enum ABI {
238 };
239 
240 // Returns the target ABI, or else a StringError if the requested ABIName is
241 // not supported for the given TT and FeatureBits combination.
242 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
243  StringRef ABIName);
244 
245 ABI getTargetABI(StringRef ABIName);
246 
247 // Returns the register used to hold the stack pointer after realignment.
249 
250 // Returns the register holding shadow call stack pointer.
252 
253 } // namespace RISCVABI
254 
255 namespace RISCVFeatures {
256 
257 // Validates if the given combination of features are valid for the target
258 // triple. Exits with report_fatal_error if not.
259 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
260 
261 } // namespace RISCVFeatures
262 
263 enum class RISCVVSEW {
264  SEW_8 = 0,
265  SEW_16,
266  SEW_32,
267  SEW_64,
268  SEW_128,
269  SEW_256,
270  SEW_512,
271  SEW_1024,
272 };
273 
274 enum class RISCVVLMUL {
275  LMUL_1 = 0,
276  LMUL_2,
277  LMUL_4,
278  LMUL_8,
280  LMUL_F8,
281  LMUL_F4,
282  LMUL_F2
283 };
284 
285 namespace RISCVVType {
286 // Is this a SEW value that can be encoded into the VTYPE format.
287 inline static bool isValidSEW(unsigned SEW) {
288  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
289 }
290 
291 // Is this a LMUL value that can be encoded into the VTYPE format.
292 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
293  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
294 }
295 
296 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
297 // is used by our MC layer representation.
298 //
299 // Bits | Name | Description
300 // -----+------------+------------------------------------------------
301 // 7 | vma | Vector mask agnostic
302 // 6 | vta | Vector tail agnostic
303 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
304 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
305 inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
306  bool TailAgnostic, bool MaskAgnostic) {
307  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
308  unsigned VSEWBits = static_cast<unsigned>(VSEW);
309  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
310  if (TailAgnostic)
311  VTypeI |= 0x40;
312  if (MaskAgnostic)
313  VTypeI |= 0x80;
314 
315  return VTypeI;
316 }
317 
318 inline static RISCVVLMUL getVLMUL(unsigned VType) {
319  unsigned VLMUL = VType & 0x7;
320  return static_cast<RISCVVLMUL>(VLMUL);
321 }
322 
323 inline static RISCVVSEW getVSEW(unsigned VType) {
324  unsigned VSEW = (VType >> 3) & 0x7;
325  return static_cast<RISCVVSEW>(VSEW);
326 }
327 
328 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
329 
330 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
331 
332 void printVType(unsigned VType, raw_ostream &OS);
333 
334 } // namespace RISCVVType
335 
336 } // namespace llvm
337 
338 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:235
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:141
llvm::RISCVVSEW::SEW_256
@ SEW_256
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:131
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:99
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:145
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:40
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:292
llvm
Definition: AllocatorList.h:23
llvm::RISCVVLMUL::LMUL_1
@ LMUL_1
llvm::RISCVVType::getVSEW
static RISCVVSEW getVSEW(unsigned VType)
Definition: RISCVBaseInfo.h:323
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:117
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:65
MCInstrDesc.h
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:57
StringRef.h
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:120
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:66
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:32
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:134
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:119
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:101
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:29
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:96
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:143
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:287
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:102
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:328
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:130
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:97
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:35
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:197
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:56
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:37
llvm::RISCVVLMUL::LMUL_F8
@ LMUL_F8
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:71
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:41
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:90
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:169
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:81
llvm::RISCVVType::getVLMUL
static RISCVVLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:318
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:39
llvm::RISCVOp::OPERAND_AVL
@ OPERAND_AVL
Definition: RISCVBaseInfo.h:124
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:133
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:91
llvm::RISCVVSEW::SEW_512
@ SEW_512
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:52
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:230
llvm::RISCVVSEW::SEW_1024
@ SEW_1024
llvm::RISCVVLMUL::LMUL_2
@ LMUL_2
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:234
SubtargetFeature.h
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:47
llvm::RISCVVSEW::SEW_16
@ SEW_16
llvm::RISCVVSEW
RISCVVSEW
Definition: RISCVBaseInfo.h:263
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:43
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:90
llvm::RISCVVSEW::SEW_128
@ SEW_128
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:72
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:45
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:97
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:232
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:115
llvm::RISCVVLMUL::LMUL_F2
@ LMUL_F2
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:233
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:94
RISCVMCTargetDesc.h
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:196
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:116
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:84
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:92
llvm::RISCVVLMUL::LMUL_4
@ LMUL_4
llvm::RISCVVLMUL::LMUL_F4
@ LMUL_F4
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:44
llvm::RISCVII::RVVConstraintType
RVVConstraintType
Definition: RISCVBaseInfo.h:81
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:95
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:83
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:67
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:28
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:50
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:132
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:85
llvm::RISCVVSEW::SEW_32
@ SEW_32
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:82
llvm::RISCVVType::encodeVTYPE
static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.h:305
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:118
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:100
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:142
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:144
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:93
llvm::RISCVVLMUL::LMUL_8
@ LMUL_8
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:147
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:77
llvm::RISCVVSEW::SEW_64
@ SEW_64
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:33
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:76
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:114
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:150
llvm::RISCVVSEW::SEW_8
@ SEW_8
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:101
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:236
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:84
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:180
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:198
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:330
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:30
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:199
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:26
StringSwitch.h
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:209
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:112
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const
Definition: RISCVBaseInfo.h:212
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:140
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:237
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:60
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:38
llvm::RISCVVLMUL
RISCVVLMUL
Definition: RISCVBaseInfo.h:274
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:231
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:49
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:36
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:53
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:42
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:31
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:146
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:107
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:34
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:210
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:113
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:98
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:61
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:229
llvm::RISCVVLMUL::LMUL_RESERVED
@ LMUL_RESERVED
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22