LLVM  13.0.0git
RISCVBaseInfo.h
Go to the documentation of this file.
1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
21 
22 namespace llvm {
23 
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
26 namespace RISCVII {
27 enum {
46 
48 
51 
53  VLMulMask = 0b111 << VLMulShift,
54 
55  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
58 
59  // Force a tail agnostic policy even this instruction has a tied destination.
62 
63  // Does this instruction have a merge operand that must be removed when
64  // converting to MCInst. It will be the first explicit use operand. Used by
65  // RVV Pseudos.
68 
69  // Does this instruction have a SEW operand. It will be the last explicit
70  // operand. Used by RVV Pseudos.
73 
74  // Does this instruction have a VL operand. It will be the second to last
75  // explicit operand. Used by RVV Pseudos.
78 };
79 
80 // Match with the definitions in RISCVInstrFormatsV.td
83  VS2Constraint = 0b001,
84  VS1Constraint = 0b010,
85  VMConstraint = 0b100,
86 };
87 
88 // RISC-V Specific Machine Operand Flags
89 enum {
90  MO_None = 0,
91  MO_CALL = 1,
92  MO_PLT = 2,
93  MO_LO = 3,
94  MO_HI = 4,
97  MO_GOT_HI = 7,
103 
104  // Used to differentiate between target-specific "direct" flags and "bitmask"
105  // flags. A machine operand can only have one "direct" flag, but can have
106  // multiple "bitmask" flags.
108 };
109 } // namespace RISCVII
110 
111 namespace RISCVOp {
112 enum OperandType : unsigned {
121 };
122 } // namespace RISCVOp
123 
124 // Describes the predecessor/successor bits used in the FENCE instruction.
125 namespace RISCVFenceField {
127  I = 8,
128  O = 4,
129  R = 2,
130  W = 1
131 };
132 }
133 
134 // Describes the supported floating point rounding mode encodings.
135 namespace RISCVFPRndMode {
137  RNE = 0,
138  RTZ = 1,
139  RDN = 2,
140  RUP = 3,
141  RMM = 4,
142  DYN = 7,
144 };
145 
147  switch (RndMode) {
148  default:
149  llvm_unreachable("Unknown floating point rounding mode");
150  case RISCVFPRndMode::RNE:
151  return "rne";
152  case RISCVFPRndMode::RTZ:
153  return "rtz";
154  case RISCVFPRndMode::RDN:
155  return "rdn";
156  case RISCVFPRndMode::RUP:
157  return "rup";
158  case RISCVFPRndMode::RMM:
159  return "rmm";
160  case RISCVFPRndMode::DYN:
161  return "dyn";
162  }
163 }
164 
166  return StringSwitch<RoundingMode>(Str)
167  .Case("rne", RISCVFPRndMode::RNE)
168  .Case("rtz", RISCVFPRndMode::RTZ)
169  .Case("rdn", RISCVFPRndMode::RDN)
170  .Case("rup", RISCVFPRndMode::RUP)
171  .Case("rmm", RISCVFPRndMode::RMM)
172  .Case("dyn", RISCVFPRndMode::DYN)
174 }
175 
176 inline static bool isValidRoundingMode(unsigned Mode) {
177  switch (Mode) {
178  default:
179  return false;
180  case RISCVFPRndMode::RNE:
181  case RISCVFPRndMode::RTZ:
182  case RISCVFPRndMode::RDN:
183  case RISCVFPRndMode::RUP:
184  case RISCVFPRndMode::RMM:
185  case RISCVFPRndMode::DYN:
186  return true;
187  }
188 }
189 } // namespace RISCVFPRndMode
190 
191 namespace RISCVSysReg {
192 struct SysReg {
193  const char *Name;
194  unsigned Encoding;
195  const char *AltName;
196  // FIXME: add these additional fields when needed.
197  // Privilege Access: Read, Write, Read-Only.
198  // unsigned ReadWrite;
199  // Privilege Mode: User, System or Machine.
200  // unsigned Mode;
201  // Check field name.
202  // unsigned Extra;
203  // Register number without the privilege bits.
204  // unsigned Number;
207 
208  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
209  // Not in 32-bit mode.
210  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
211  return false;
212  // No required feature associated with the system register.
213  if (FeaturesRequired.none())
214  return true;
215  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
216  }
217 };
218 
219 #define GET_SysRegsList_DECL
220 #include "RISCVGenSearchableTables.inc"
221 } // end namespace RISCVSysReg
222 
223 namespace RISCVABI {
224 
225 enum ABI {
234 };
235 
236 // Returns the target ABI, or else a StringError if the requested ABIName is
237 // not supported for the given TT and FeatureBits combination.
238 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
239  StringRef ABIName);
240 
241 ABI getTargetABI(StringRef ABIName);
242 
243 // Returns the register used to hold the stack pointer after realignment.
245 
246 // Returns the register holding shadow call stack pointer.
248 
249 } // namespace RISCVABI
250 
251 namespace RISCVFeatures {
252 
253 // Validates if the given combination of features are valid for the target
254 // triple. Exits with report_fatal_error if not.
255 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
256 
257 } // namespace RISCVFeatures
258 
259 enum class RISCVVSEW {
260  SEW_8 = 0,
261  SEW_16,
262  SEW_32,
263  SEW_64,
264  SEW_128,
265  SEW_256,
266  SEW_512,
267  SEW_1024,
268 };
269 
270 enum class RISCVVLMUL {
271  LMUL_1 = 0,
272  LMUL_2,
273  LMUL_4,
274  LMUL_8,
276  LMUL_F8,
277  LMUL_F4,
278  LMUL_F2
279 };
280 
281 namespace RISCVVType {
282 // Is this a SEW value that can be encoded into the VTYPE format.
283 inline static bool isValidSEW(unsigned SEW) {
284  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
285 }
286 
287 // Is this a LMUL value that can be encoded into the VTYPE format.
288 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
289  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
290 }
291 
292 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
293 // is used by our MC layer representation.
294 //
295 // Bits | Name | Description
296 // -----+------------+------------------------------------------------
297 // 7 | vma | Vector mask agnostic
298 // 6 | vta | Vector tail agnostic
299 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
300 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
301 inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
302  bool TailAgnostic, bool MaskAgnostic) {
303  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
304  unsigned VSEWBits = static_cast<unsigned>(VSEW);
305  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
306  if (TailAgnostic)
307  VTypeI |= 0x40;
308  if (MaskAgnostic)
309  VTypeI |= 0x80;
310 
311  return VTypeI;
312 }
313 
314 inline static RISCVVLMUL getVLMUL(unsigned VType) {
315  unsigned VLMUL = VType & 0x7;
316  return static_cast<RISCVVLMUL>(VLMUL);
317 }
318 
319 inline static RISCVVSEW getVSEW(unsigned VType) {
320  unsigned VSEW = (VType >> 3) & 0x7;
321  return static_cast<RISCVVSEW>(VSEW);
322 }
323 
324 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
325 
326 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
327 
328 void printVType(unsigned VType, raw_ostream &OS);
329 
330 } // namespace RISCVVType
331 
332 } // namespace llvm
333 
334 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:231
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:137
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:34
llvm::RISCVVSEW::SEW_256
@ SEW_256
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:127
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:141
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:288
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::RISCVVLMUL::LMUL_1
@ LMUL_1
llvm::RISCVVType::getVSEW
static RISCVVSEW getVSEW(unsigned VType)
Definition: RISCVBaseInfo.h:319
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:117
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:65
MCInstrDesc.h
StringRef.h
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:120
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:130
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:119
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:90
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:30
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:52
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:28
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:139
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:283
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:324
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:126
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:101
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:97
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:40
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:57
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:29
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:193
llvm::RISCVVLMUL::LMUL_F8
@ LMUL_F8
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:492
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:90
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:165
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:81
llvm::RISCVVType::getVLMUL
static RISCVVLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:314
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:77
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:129
llvm::RISCVVSEW::SEW_512
@ SEW_512
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:92
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:226
llvm::RISCVVSEW::SEW_1024
@ SEW_1024
llvm::RISCVVLMUL::LMUL_2
@ LMUL_2
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:230
SubtargetFeature.h
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:95
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:100
llvm::RISCVVSEW::SEW_16
@ SEW_16
llvm::RISCVVSEW
RISCVVSEW
Definition: RISCVBaseInfo.h:259
llvm::RISCVVSEW::SEW_128
@ SEW_128
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:228
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:115
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:93
llvm::RISCVVLMUL::LMUL_F2
@ LMUL_F2
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:229
RISCVMCTargetDesc.h
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:192
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:116
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:84
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:53
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:44
llvm::RISCVVLMUL::LMUL_4
@ LMUL_4
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:37
llvm::RISCVVLMUL::LMUL_F4
@ LMUL_F4
llvm::RISCVII::RVVConstraintType
RVVConstraintType
Definition: RISCVBaseInfo.h:81
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:98
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:83
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:71
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:97
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:56
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:128
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:85
llvm::RISCVVSEW::SEW_32
@ SEW_32
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:82
llvm::RISCVVType::encodeVTYPE
static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.h:301
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:91
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:118
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:138
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:39
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:38
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:140
llvm::RISCVVLMUL::LMUL_8
@ LMUL_8
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:47
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:107
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:76
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:241
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:143
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:50
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:61
llvm::RISCVVSEW::SEW_64
@ SEW_64
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:33
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:114
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:94
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:146
llvm::RISCVVSEW::SEW_8
@ SEW_8
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:232
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:84
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:96
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:176
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:194
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:66
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:326
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:60
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:195
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:36
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:102
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:26
StringSwitch.h
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:205
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:112
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const
Definition: RISCVBaseInfo.h:208
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:136
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:49
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:233
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:41
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:99
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:32
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:35
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:45
llvm::RISCVVLMUL
RISCVVLMUL
Definition: RISCVBaseInfo.h:270
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:227
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:72
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:142
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:206
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:31
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:113
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:42
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:225
llvm::RISCVVLMUL::LMUL_RESERVED
@ LMUL_RESERVED
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:67
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:43