LLVM  14.0.0git
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
21 
22 namespace llvm {
23 
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
26 namespace RISCVII {
27 enum {
46 
49 
52 
54  VLMulMask = 0b111 << VLMulShift,
55 
56  // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
59 
60  // Force a tail agnostic policy even this instruction has a tied destination.
63 
64  // Does this instruction have a merge operand that must be removed when
65  // converting to MCInst. It will be the first explicit use operand. Used by
66  // RVV Pseudos.
69 
70  // Does this instruction have a SEW operand. It will be the last explicit
71  // operand unless there is a vector policy operand. Used by RVV Pseudos.
74 
75  // Does this instruction have a VL operand. It will be the second to last
76  // explicit operand unless there is a vector policy operand. Used by RVV
77  // Pseudos.
80 
81  // Does this instruction have a vector policy operand. It will be the last
82  // explicit operand. Used by RVV Pseudos.
85 };
86 
87 // Match with the definitions in RISCVInstrFormatsV.td
90  VS2Constraint = 0b001,
91  VS1Constraint = 0b010,
92  VMConstraint = 0b100,
93 };
94 
95 enum VLMUL : uint8_t {
96  LMUL_1 = 0,
104 };
105 
106 enum {
109 };
110 
111 // Helper functions to read TSFlags.
112 /// \returns the format of the instruction.
113 static inline unsigned getFormat(uint64_t TSFlags) {
114  return (TSFlags & InstFormatMask) >> InstFormatShift;
115 }
116 /// \returns the constraint for the instruction.
117 static inline VConstraintType getConstraint(uint64_t TSFlags) {
118  return static_cast<VConstraintType>
119  ((TSFlags & ConstraintMask) >> ConstraintShift);
120 }
121 /// \returns the LMUL for the instruction.
122 static inline VLMUL getLMul(uint64_t TSFlags) {
123  return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
124 }
125 /// \returns true if there is a dummy mask operand for the instruction.
126 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
127  return TSFlags & HasDummyMaskOpMask;
128 }
129 /// \returns true if tail agnostic is enforced for the instruction.
130 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
131  return TSFlags & ForceTailAgnosticMask;
132 }
133 /// \returns true if there is a merge operand for the instruction.
134 static inline bool hasMergeOp(uint64_t TSFlags) {
135  return TSFlags & HasMergeOpMask;
136 }
137 /// \returns true if there is a SEW operand for the instruction.
138 static inline bool hasSEWOp(uint64_t TSFlags) {
139  return TSFlags & HasSEWOpMask;
140 }
141 /// \returns true if there is a VL operand for the instruction.
142 static inline bool hasVLOp(uint64_t TSFlags) {
143  return TSFlags & HasVLOpMask;
144 }
145 /// \returns true if there is a vector policy operand for this instruction.
146 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
147  return TSFlags & HasVecPolicyOpMask;
148 }
149 
150 // RISC-V Specific Machine Operand Flags
151 enum {
152  MO_None = 0,
153  MO_CALL = 1,
154  MO_PLT = 2,
155  MO_LO = 3,
156  MO_HI = 4,
165 
166  // Used to differentiate between target-specific "direct" flags and "bitmask"
167  // flags. A machine operand can only have one "direct" flag, but can have
168  // multiple "bitmask" flags.
170 };
171 } // namespace RISCVII
172 
173 namespace RISCVOp {
174 enum OperandType : unsigned {
186  // Operand is either a register or uimm5, this is used by V extension pseudo
187  // instructions to represent a value that be passed as AVL to either vsetvli
188  // or vsetivli.
190 };
191 } // namespace RISCVOp
192 
193 // Describes the predecessor/successor bits used in the FENCE instruction.
194 namespace RISCVFenceField {
196  I = 8,
197  O = 4,
198  R = 2,
199  W = 1
200 };
201 }
202 
203 // Describes the supported floating point rounding mode encodings.
204 namespace RISCVFPRndMode {
206  RNE = 0,
207  RTZ = 1,
208  RDN = 2,
209  RUP = 3,
210  RMM = 4,
211  DYN = 7,
213 };
214 
216  switch (RndMode) {
217  default:
218  llvm_unreachable("Unknown floating point rounding mode");
219  case RISCVFPRndMode::RNE:
220  return "rne";
221  case RISCVFPRndMode::RTZ:
222  return "rtz";
223  case RISCVFPRndMode::RDN:
224  return "rdn";
225  case RISCVFPRndMode::RUP:
226  return "rup";
227  case RISCVFPRndMode::RMM:
228  return "rmm";
229  case RISCVFPRndMode::DYN:
230  return "dyn";
231  }
232 }
233 
235  return StringSwitch<RoundingMode>(Str)
236  .Case("rne", RISCVFPRndMode::RNE)
237  .Case("rtz", RISCVFPRndMode::RTZ)
238  .Case("rdn", RISCVFPRndMode::RDN)
239  .Case("rup", RISCVFPRndMode::RUP)
240  .Case("rmm", RISCVFPRndMode::RMM)
241  .Case("dyn", RISCVFPRndMode::DYN)
243 }
244 
245 inline static bool isValidRoundingMode(unsigned Mode) {
246  switch (Mode) {
247  default:
248  return false;
249  case RISCVFPRndMode::RNE:
250  case RISCVFPRndMode::RTZ:
251  case RISCVFPRndMode::RDN:
252  case RISCVFPRndMode::RUP:
253  case RISCVFPRndMode::RMM:
254  case RISCVFPRndMode::DYN:
255  return true;
256  }
257 }
258 } // namespace RISCVFPRndMode
259 
260 namespace RISCVSysReg {
261 struct SysReg {
262  const char *Name;
263  const char *AltName;
264  const char *DeprecatedName;
265  unsigned Encoding;
266  // FIXME: add these additional fields when needed.
267  // Privilege Access: Read, Write, Read-Only.
268  // unsigned ReadWrite;
269  // Privilege Mode: User, System or Machine.
270  // unsigned Mode;
271  // Check field name.
272  // unsigned Extra;
273  // Register number without the privilege bits.
274  // unsigned Number;
277 
278  bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
279  // Not in 32-bit mode.
280  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
281  return false;
282  // No required feature associated with the system register.
283  if (FeaturesRequired.none())
284  return true;
285  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
286  }
287 };
288 
289 #define GET_SysRegsList_DECL
290 #include "RISCVGenSearchableTables.inc"
291 } // end namespace RISCVSysReg
292 
293 namespace RISCVABI {
294 
295 enum ABI {
304 };
305 
306 // Returns the target ABI, or else a StringError if the requested ABIName is
307 // not supported for the given TT and FeatureBits combination.
308 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
309  StringRef ABIName);
310 
311 ABI getTargetABI(StringRef ABIName);
312 
313 // Returns the register used to hold the stack pointer after realignment.
315 
316 // Returns the register holding shadow call stack pointer.
318 
319 } // namespace RISCVABI
320 
321 namespace RISCVFeatures {
322 
323 // Validates if the given combination of features are valid for the target
324 // triple. Exits with report_fatal_error if not.
325 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
326 
327 // Convert FeatureBitset to FeatureVector.
328 void toFeatureVector(std::vector<std::string> &FeatureVector,
329  const FeatureBitset &FeatureBits);
330 
331 } // namespace RISCVFeatures
332 
333 namespace RISCVVType {
334 // Is this a SEW value that can be encoded into the VTYPE format.
335 inline static bool isValidSEW(unsigned SEW) {
336  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
337 }
338 
339 // Is this a LMUL value that can be encoded into the VTYPE format.
340 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
341  return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
342 }
343 
344 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
345  bool MaskAgnostic);
346 
347 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
348  unsigned VLMUL = VType & 0x7;
349  return static_cast<RISCVII::VLMUL>(VLMUL);
350 }
351 
352 // Decode VLMUL into 1,2,4,8 and fractional indicator.
353 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
354 
355 inline static unsigned decodeVSEW(unsigned VSEW) {
356  assert(VSEW < 8 && "Unexpected VSEW value");
357  return 1 << (VSEW + 3);
358 }
359 
360 inline static unsigned getSEW(unsigned VType) {
361  unsigned VSEW = (VType >> 3) & 0x7;
362  return decodeVSEW(VSEW);
363 }
364 
365 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
366 
367 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
368 
369 void printVType(unsigned VType, raw_ostream &OS);
370 
371 } // namespace RISCVVType
372 
373 } // namespace llvm
374 
375 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:96
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:301
llvm::RISCVFPRndMode::RNE
@ RNE
Definition: RISCVBaseInfo.h:206
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:159
llvm::RISCVFenceField::I
@ I
Definition: RISCVBaseInfo.h:196
llvm::RISCVFPRndMode::RMM
@ RMM
Definition: RISCVBaseInfo.h:210
llvm::RISCVII::HasDummyMaskOpShift
@ HasDummyMaskOpShift
Definition: RISCVBaseInfo.h:57
llvm::RISCVVType::isValidLMUL
static bool isValidLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVBaseInfo.h:340
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:155
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:31
llvm::RISCVOp::OPERAND_SIMM12
@ OPERAND_SIMM12
Definition: RISCVBaseInfo.h:182
llvm::RISCVII::VS1Constraint
@ VS1Constraint
Definition: RISCVBaseInfo.h:91
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:158
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:70
MCInstrDesc.h
StringRef.h
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::RISCVOp::OPERAND_LAST_RISCV_IMM
@ OPERAND_LAST_RISCV_IMM
Definition: RISCVBaseInfo.h:185
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:199
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:156
llvm::RISCVOp::OPERAND_UIMMLOG2XLEN
@ OPERAND_UIMMLOG2XLEN
Definition: RISCVBaseInfo.h:184
llvm::RISCVII::LMUL_RESERVED
@ LMUL_RESERVED
Definition: RISCVBaseInfo.h:100
llvm::RISCVII::InstFormatCA
@ InstFormatCA
Definition: RISCVBaseInfo.h:42
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVFPRndMode::RDN
@ RDN
Definition: RISCVBaseInfo.h:208
llvm::RISCVII::MO_DIRECT_FLAG_MASK
@ MO_DIRECT_FLAG_MASK
Definition: RISCVBaseInfo.h:169
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:99
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:335
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:138
llvm::RISCVII::VS2Constraint
@ VS2Constraint
Definition: RISCVBaseInfo.h:90
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:58
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:365
llvm::RISCVFenceField::FenceField
FenceField
Definition: RISCVBaseInfo.h:195
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:32
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:160
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:152
llvm::RISCVII::HasMergeOpShift
@ HasMergeOpShift
Definition: RISCVBaseInfo.h:67
llvm::RISCVII::InstFormatCS
@ InstFormatCS
Definition: RISCVBaseInfo.h:41
llvm::FeatureBitset::none
bool none() const
Definition: SubtargetFeature.h:97
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVSysReg::SysReg::Name
const char * Name
Definition: RISCVBaseInfo.h:262
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:95
llvm::RISCVFPRndMode::stringToRoundingMode
static RoundingMode stringToRoundingMode(StringRef Str)
Definition: RISCVBaseInfo.h:234
llvm::RISCVII::InstFormatShift
@ InstFormatShift
Definition: RISCVBaseInfo.h:48
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:146
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:86
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:360
llvm::RISCVII::ConstraintShift
@ ConstraintShift
Definition: RISCVBaseInfo.h:50
llvm::RISCVOp::OPERAND_AVL
@ OPERAND_AVL
Definition: RISCVBaseInfo.h:189
llvm::RISCVOp::OPERAND_UIMM7
@ OPERAND_UIMM7
Definition: RISCVBaseInfo.h:180
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:198
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:296
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:98
llvm::RISCVII::NoConstraint
@ NoConstraint
Definition: RISCVBaseInfo.h:89
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:300
SubtargetFeature.h
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:163
llvm::RISCVII::TAIL_UNDISTURBED
@ TAIL_UNDISTURBED
Definition: RISCVBaseInfo.h:107
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:43
llvm::RISCVII::ForceTailAgnosticMask
@ ForceTailAgnosticMask
Definition: RISCVBaseInfo.h:62
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:142
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:298
llvm::RISCVOp::OPERAND_UIMM5
@ OPERAND_UIMM5
Definition: RISCVBaseInfo.h:179
llvm::RISCVVType::decodeVSEW
static unsigned decodeVSEW(unsigned VSEW)
Definition: RISCVBaseInfo.h:355
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:299
RISCVMCTargetDesc.h
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:35
llvm::RISCVSysReg::SysReg
Definition: RISCVBaseInfo.h:261
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::RISCVOp::OPERAND_UIMM12
@ OPERAND_UIMM12
Definition: RISCVBaseInfo.h:181
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:89
llvm::RISCVOp::OPERAND_UIMM2
@ OPERAND_UIMM2
Definition: RISCVBaseInfo.h:176
llvm::RISCVII::VConstraintType
VConstraintType
Definition: RISCVBaseInfo.h:88
llvm::RISCVII::getConstraint
static VConstraintType getConstraint(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:117
llvm::RISCVII::HasVecPolicyOpMask
@ HasVecPolicyOpMask
Definition: RISCVBaseInfo.h:84
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:113
llvm::RISCVII::InstFormatOther
@ InstFormatOther
Definition: RISCVBaseInfo.h:45
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:162
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:197
llvm::RISCVII::InstFormatCSS
@ InstFormatCSS
Definition: RISCVBaseInfo.h:38
llvm::RISCVOp::OPERAND_UIMM3
@ OPERAND_UIMM3
Definition: RISCVBaseInfo.h:177
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:138
llvm::RISCVII::ForceTailAgnosticShift
@ ForceTailAgnosticShift
Definition: RISCVBaseInfo.h:61
uint64_t
llvm::RISCVOp::OPERAND_UIMM20
@ OPERAND_UIMM20
Definition: RISCVBaseInfo.h:183
llvm::RISCVFPRndMode::RTZ
@ RTZ
Definition: RISCVBaseInfo.h:207
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:209
llvm::RISCVII::TAIL_AGNOSTIC
@ TAIL_AGNOSTIC
Definition: RISCVBaseInfo.h:108
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:33
llvm::RISCVFeatures::toFeatureVector
void toFeatureVector(std::vector< std::string > &FeatureVector, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:104
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::RISCVFPRndMode::Invalid
@ Invalid
Definition: RISCVBaseInfo.h:212
llvm::RISCVII::hasMergeOp
static bool hasMergeOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:134
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:154
llvm::RISCVII::VMConstraint
@ VMConstraint
Definition: RISCVBaseInfo.h:92
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVII::InstFormatR4
@ InstFormatR4
Definition: RISCVBaseInfo.h:30
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:97
llvm::RISCVII::VLMulMask
@ VLMulMask
Definition: RISCVBaseInfo.h:54
llvm::RISCVII::HasSEWOpShift
@ HasSEWOpShift
Definition: RISCVBaseInfo.h:72
llvm::RISCVII::InstFormatCIW
@ InstFormatCIW
Definition: RISCVBaseInfo.h:39
llvm::RISCVII::HasVecPolicyOpShift
@ HasVecPolicyOpShift
Definition: RISCVBaseInfo.h:83
llvm::RISCVOp::OPERAND_UIMM4
@ OPERAND_UIMM4
Definition: RISCVBaseInfo.h:178
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:44
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:130
llvm::RISCVII::InstFormatU
@ InstFormatU
Definition: RISCVBaseInfo.h:34
llvm::RISCVFPRndMode::roundingModeToString
static StringRef roundingModeToString(RoundingMode RndMode)
Definition: RISCVBaseInfo.h:215
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:154
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:347
llvm::RISCVII::InstFormatPseudo
@ InstFormatPseudo
Definition: RISCVBaseInfo.h:28
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:302
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:245
llvm::RISCVSysReg::SysReg::Encoding
unsigned Encoding
Definition: RISCVBaseInfo.h:265
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:367
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:124
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:122
llvm::RISCVII::InstFormatCR
@ InstFormatCR
Definition: RISCVBaseInfo.h:36
llvm::RISCVSysReg::SysReg::AltName
const char * AltName
Definition: RISCVBaseInfo.h:263
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:31
StringSwitch.h
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:68
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::RISCVSysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: RISCVBaseInfo.h:275
llvm::RISCVII::InstFormatR
@ InstFormatR
Definition: RISCVBaseInfo.h:29
llvm::RISCVII::HasVLOpShift
@ HasVLOpShift
Definition: RISCVBaseInfo.h:78
llvm::RISCVII::InstFormatCI
@ InstFormatCI
Definition: RISCVBaseInfo.h:37
llvm::RISCVII::VLMulShift
@ VLMulShift
Definition: RISCVBaseInfo.h:53
llvm::RISCVOp::OperandType
OperandType
Definition: RISCVBaseInfo.h:174
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::RISCVSysReg::SysReg::DeprecatedName
const char * DeprecatedName
Definition: RISCVBaseInfo.h:264
llvm::RISCVFPRndMode::RoundingMode
RoundingMode
Definition: RISCVBaseInfo.h:205
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:101
llvm::RISCVII::InstFormatCL
@ InstFormatCL
Definition: RISCVBaseInfo.h:40
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:303
llvm::RISCVII::InstFormatMask
@ InstFormatMask
Definition: RISCVBaseInfo.h:47
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:157
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:153
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:79
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:102
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:95
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:297
llvm::RISCVII::ConstraintMask
@ ConstraintMask
Definition: RISCVBaseInfo.h:51
llvm::RISCVII::hasDummyMaskOp
static bool hasDummyMaskOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:126
llvm::RISCVFPRndMode::DYN
@ DYN
Definition: RISCVBaseInfo.h:211
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:164
llvm::RISCVSysReg::SysReg::isRV32Only
bool isRV32Only
Definition: RISCVBaseInfo.h:276
llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM
@ OPERAND_FIRST_RISCV_IMM
Definition: RISCVBaseInfo.h:175
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:161
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:73
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:295
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:103
llvm::RISCVSysReg::SysReg::haveRequiredFeatures
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Definition: RISCVBaseInfo.h:278
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24