LLVM 18.0.0git
Public Member Functions | List of all members
llvm::RISCVRegisterBankInfo Class Referencefinal

This class provides the information for the target register banks. More...

#include "Target/RISCV/GISel/RISCVRegisterBankInfo.h"

Inheritance diagram for llvm::RISCVRegisterBankInfo:
Inheritance graph
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Public Member Functions

 RISCVRegisterBankInfo (unsigned HwMode)
 
const RegisterBank & getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const override
 Get a register bank that covers RC.
 
const InstructionMapping & getInstrMapping (const MachineInstr &MI) const override
 Get the mapping of the different operands of MI on the register bank.
 
- Public Member Functions inherited from llvm::RegisterBankInfo
const RegisterBank * getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
 
virtual void applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
 See applyMapping.
 
virtual ~RegisterBankInfo ()=default
 
const RegisterBank & getRegBank (unsigned ID) const
 Get the register bank identified by ID.
 
unsigned getMaximumSize (unsigned RegBankID) const
 Get the maximum size in bits that fits in the given register bank.
 
const RegisterBank * getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg.
 
unsigned getNumRegBanks () const
 Get the total number of register banks.
 
virtual bool isDivergentRegBank (const RegisterBank *RB) const
 Returns true if the register bank is considered divergent.
 
virtual const RegisterBank & getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const
 Get a register bank that covers RC.
 
virtual unsigned copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
 
bool cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
 
virtual unsigned getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
 Get the cost of using ValMapping to decompose a register.
 
virtual const InstructionMapping & getInstrMapping (const MachineInstr &MI) const
 Get the mapping of the different operands of MI on the register bank.
 
virtual InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const
 Get the alternative mappings for MI.
 
InstructionMappings getInstrPossibleMappings (const MachineInstr &MI) const
 Get the possible mapping for MI.
 
void applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
 Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
 
unsigned getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the size in bits of Reg.
 
bool verify (const TargetRegisterInfo &TRI) const
 Check that information hold by this instance make sense for the given TRI.
 
const InstructionMapping & getInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping.
 
const InstructionMapping & getInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping.
 

Additional Inherited Members

- Public Types inherited from llvm::RegisterBankInfo
using InstructionMappings = SmallVector< const InstructionMapping *, 4 >
 Convenient type to represent the alternatives for mapping an instruction.
 
- Static Public Member Functions inherited from llvm::RegisterBankInfo
static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping.
 
static const TargetRegisterClass * constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC.
 
- Static Public Attributes inherited from llvm::RegisterBankInfo
static const unsigned DefaultMappingID = UINT_MAX
 Identifier used when the related instruction mapping instance is generated by target independent code.
 
static const unsigned InvalidMappingID = UINT_MAX - 1
 Identifier used when the related instruction mapping instance is generated by the default constructor.
 
- Protected Member Functions inherited from llvm::RegisterBankInfo
 RegisterBankInfo (const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
 
 RegisterBankInfo ()
 This constructor is meaningless.
 
const RegisterBank & getRegBank (unsigned ID)
 Get the register bank identified by ID.
 
const TargetRegisterClass * getMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg.
 
const InstructionMapping & getInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI.
 
const PartialMapping & getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments.
 
const ValueMapping & getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping.
 
const ValueMapping & getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments.
 
template<typename Iterator >
const ValueMapping * getOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
 
const ValueMapping * getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.
 
const ValueMapping * getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments.
 
- Protected Attributes inherited from llvm::RegisterBankInfo
const RegisterBank ** RegBanks
 Hold the set of supported register banks.
 
unsigned NumRegBanks
 Total number of register banks.
 
const unsigned * Sizes
 Hold the sizes of the register banks for all HwModes.
 
unsigned HwMode
 Current HwMode for the target.
 
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map.
 
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map.
 
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map.
 
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map.
 
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive.
 

Detailed Description

This class provides the information for the target register banks.

Definition at line 32 of file RISCVRegisterBankInfo.h.

Constructor & Destructor Documentation

◆ RISCVRegisterBankInfo()

RISCVRegisterBankInfo::RISCVRegisterBankInfo ( unsigned  HwMode)

Definition at line 60 of file RISCVRegisterBankInfo.cpp.

Member Function Documentation

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & RISCVRegisterBankInfo::getInstrMapping ( const MachineInstr &  MI) const
overridevirtual

Get the mapping of the different operands of MI on the register bank.

This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, if MI is a vector add, the mapping should not be a scalarization of the add.

Postcondition
returnedVal.verify(MI).
Note
If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 85 of file RISCVRegisterBankInfo.cpp.

References assert(), llvm::RegisterBankInfo::DefaultMappingID, llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), llvm::RegisterBankInfo::getMaximumSize(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RISCV::GPR32Idx, llvm::RISCV::GPR64Idx, llvm::isPreISelGenericOpcode(), llvm::RegisterBankInfo::InstructionMapping::isValid(), MI, and llvm::RISCV::ValueMappings.

◆ getRegBankFromRegClass()

const RegisterBank & RISCVRegisterBankInfo::getRegBankFromRegClass ( const TargetRegisterClass &  RC,
LLT  Ty 
) const
overridevirtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo:
This should be TableGen'ed.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 64 of file RISCVRegisterBankInfo.cpp.

References llvm::TargetRegisterClass::getID(), llvm::RegisterBankInfo::getRegBank(), and llvm_unreachable.

The documentation for this class was generated from the following files:
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