LLVM  9.0.0svn
ARMAsmParser.cpp
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1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMFeatures.h"
10 #include "Utils/ARMBaseInfo.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringMap.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Triple.h"
27 #include "llvm/ADT/Twine.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
40 #include "llvm/MC/MCRegisterInfo.h"
41 #include "llvm/MC/MCSection.h"
42 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMEHABI.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/SMLoc.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstddef>
60 #include <cstdint>
61 #include <iterator>
62 #include <limits>
63 #include <memory>
64 #include <string>
65 #include <utility>
66 #include <vector>
67 
68 #define DEBUG_TYPE "asm-parser"
69 
70 using namespace llvm;
71 
72 namespace {
73 
74 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
75 
76 static cl::opt<ImplicitItModeTy> ImplicitItMode(
77  "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
78  cl::desc("Allow conditional instructions outdside of an IT block"),
79  cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
80  "Accept in both ISAs, emit implicit ITs in Thumb"),
81  clEnumValN(ImplicitItModeTy::Never, "never",
82  "Warn in ARM, reject in Thumb"),
83  clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
84  "Accept in ARM, reject in Thumb"),
85  clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
86  "Warn in ARM, emit implicit ITs in Thumb")));
87 
88 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
89  cl::init(false));
90 
91 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
92 
93 class UnwindContext {
94  using Locs = SmallVector<SMLoc, 4>;
95 
96  MCAsmParser &Parser;
97  Locs FnStartLocs;
98  Locs CantUnwindLocs;
99  Locs PersonalityLocs;
100  Locs PersonalityIndexLocs;
101  Locs HandlerDataLocs;
102  int FPReg;
103 
104 public:
105  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
106 
107  bool hasFnStart() const { return !FnStartLocs.empty(); }
108  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
109  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
110 
111  bool hasPersonality() const {
112  return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
113  }
114 
115  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
116  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
117  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
118  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
119  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
120 
121  void saveFPReg(int Reg) { FPReg = Reg; }
122  int getFPReg() const { return FPReg; }
123 
124  void emitFnStartLocNotes() const {
125  for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
126  FI != FE; ++FI)
127  Parser.Note(*FI, ".fnstart was specified here");
128  }
129 
130  void emitCantUnwindLocNotes() const {
131  for (Locs::const_iterator UI = CantUnwindLocs.begin(),
132  UE = CantUnwindLocs.end(); UI != UE; ++UI)
133  Parser.Note(*UI, ".cantunwind was specified here");
134  }
135 
136  void emitHandlerDataLocNotes() const {
137  for (Locs::const_iterator HI = HandlerDataLocs.begin(),
138  HE = HandlerDataLocs.end(); HI != HE; ++HI)
139  Parser.Note(*HI, ".handlerdata was specified here");
140  }
141 
142  void emitPersonalityLocNotes() const {
143  for (Locs::const_iterator PI = PersonalityLocs.begin(),
144  PE = PersonalityLocs.end(),
145  PII = PersonalityIndexLocs.begin(),
146  PIE = PersonalityIndexLocs.end();
147  PI != PE || PII != PIE;) {
148  if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
149  Parser.Note(*PI++, ".personality was specified here");
150  else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
151  Parser.Note(*PII++, ".personalityindex was specified here");
152  else
153  llvm_unreachable(".personality and .personalityindex cannot be "
154  "at the same location");
155  }
156  }
157 
158  void reset() {
159  FnStartLocs = Locs();
160  CantUnwindLocs = Locs();
161  PersonalityLocs = Locs();
162  HandlerDataLocs = Locs();
163  PersonalityIndexLocs = Locs();
164  FPReg = ARM::SP;
165  }
166 };
167 
168 
169 class ARMAsmParser : public MCTargetAsmParser {
170  const MCRegisterInfo *MRI;
171  UnwindContext UC;
172 
173  ARMTargetStreamer &getTargetStreamer() {
174  assert(getParser().getStreamer().getTargetStreamer() &&
175  "do not have a target streamer");
176  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
177  return static_cast<ARMTargetStreamer &>(TS);
178  }
179 
180  // Map of register aliases registers via the .req directive.
181  StringMap<unsigned> RegisterReqs;
182 
183  bool NextSymbolIsThumb;
184 
185  bool useImplicitITThumb() const {
186  return ImplicitItMode == ImplicitItModeTy::Always ||
187  ImplicitItMode == ImplicitItModeTy::ThumbOnly;
188  }
189 
190  bool useImplicitITARM() const {
191  return ImplicitItMode == ImplicitItModeTy::Always ||
192  ImplicitItMode == ImplicitItModeTy::ARMOnly;
193  }
194 
195  struct {
196  ARMCC::CondCodes Cond; // Condition for IT block.
197  unsigned Mask:4; // Condition mask for instructions.
198  // Starting at first 1 (from lsb).
199  // '1' condition as indicated in IT.
200  // '0' inverse of condition (else).
201  // Count of instructions in IT block is
202  // 4 - trailingzeroes(mask)
203  // Note that this does not have the same encoding
204  // as in the IT instruction, which also depends
205  // on the low bit of the condition code.
206 
207  unsigned CurPosition; // Current position in parsing of IT
208  // block. In range [0,4], with 0 being the IT
209  // instruction itself. Initialized according to
210  // count of instructions in block. ~0U if no
211  // active IT block.
212 
213  bool IsExplicit; // true - The IT instruction was present in the
214  // input, we should not modify it.
215  // false - The IT instruction was added
216  // implicitly, we can extend it if that
217  // would be legal.
218  } ITState;
219 
220  SmallVector<MCInst, 4> PendingConditionalInsts;
221 
222  void flushPendingInstructions(MCStreamer &Out) override {
223  if (!inImplicitITBlock()) {
224  assert(PendingConditionalInsts.size() == 0);
225  return;
226  }
227 
228  // Emit the IT instruction
229  unsigned Mask = getITMaskEncoding();
230  MCInst ITInst;
231  ITInst.setOpcode(ARM::t2IT);
232  ITInst.addOperand(MCOperand::createImm(ITState.Cond));
233  ITInst.addOperand(MCOperand::createImm(Mask));
234  Out.EmitInstruction(ITInst, getSTI());
235 
236  // Emit the conditonal instructions
237  assert(PendingConditionalInsts.size() <= 4);
238  for (const MCInst &Inst : PendingConditionalInsts) {
239  Out.EmitInstruction(Inst, getSTI());
240  }
241  PendingConditionalInsts.clear();
242 
243  // Clear the IT state
244  ITState.Mask = 0;
245  ITState.CurPosition = ~0U;
246  }
247 
248  bool inITBlock() { return ITState.CurPosition != ~0U; }
249  bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
250  bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
251 
252  bool lastInITBlock() {
253  return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
254  }
255 
256  void forwardITPosition() {
257  if (!inITBlock()) return;
258  // Move to the next instruction in the IT block, if there is one. If not,
259  // mark the block as done, except for implicit IT blocks, which we leave
260  // open until we find an instruction that can't be added to it.
261  unsigned TZ = countTrailingZeros(ITState.Mask);
262  if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
263  ITState.CurPosition = ~0U; // Done with the IT block after this.
264  }
265 
266  // Rewind the state of the current IT block, removing the last slot from it.
267  void rewindImplicitITPosition() {
268  assert(inImplicitITBlock());
269  assert(ITState.CurPosition > 1);
270  ITState.CurPosition--;
271  unsigned TZ = countTrailingZeros(ITState.Mask);
272  unsigned NewMask = 0;
273  NewMask |= ITState.Mask & (0xC << TZ);
274  NewMask |= 0x2 << TZ;
275  ITState.Mask = NewMask;
276  }
277 
278  // Rewind the state of the current IT block, removing the last slot from it.
279  // If we were at the first slot, this closes the IT block.
280  void discardImplicitITBlock() {
281  assert(inImplicitITBlock());
282  assert(ITState.CurPosition == 1);
283  ITState.CurPosition = ~0U;
284  }
285 
286  // Return the low-subreg of a given Q register.
287  unsigned getDRegFromQReg(unsigned QReg) const {
288  return MRI->getSubReg(QReg, ARM::dsub_0);
289  }
290 
291  // Get the encoding of the IT mask, as it will appear in an IT instruction.
292  unsigned getITMaskEncoding() {
293  assert(inITBlock());
294  unsigned Mask = ITState.Mask;
295  unsigned TZ = countTrailingZeros(Mask);
296  if ((ITState.Cond & 1) == 0) {
297  assert(Mask && TZ <= 3 && "illegal IT mask value!");
298  Mask ^= (0xE << TZ) & 0xF;
299  }
300  return Mask;
301  }
302 
303  // Get the condition code corresponding to the current IT block slot.
304  ARMCC::CondCodes currentITCond() {
305  unsigned MaskBit;
306  if (ITState.CurPosition == 1)
307  MaskBit = 1;
308  else
309  MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
310 
311  return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
312  }
313 
314  // Invert the condition of the current IT block slot without changing any
315  // other slots in the same block.
316  void invertCurrentITCondition() {
317  if (ITState.CurPosition == 1) {
318  ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
319  } else {
320  ITState.Mask ^= 1 << (5 - ITState.CurPosition);
321  }
322  }
323 
324  // Returns true if the current IT block is full (all 4 slots used).
325  bool isITBlockFull() {
326  return inITBlock() && (ITState.Mask & 1);
327  }
328 
329  // Extend the current implicit IT block to have one more slot with the given
330  // condition code.
331  void extendImplicitITBlock(ARMCC::CondCodes Cond) {
332  assert(inImplicitITBlock());
333  assert(!isITBlockFull());
334  assert(Cond == ITState.Cond ||
335  Cond == ARMCC::getOppositeCondition(ITState.Cond));
336  unsigned TZ = countTrailingZeros(ITState.Mask);
337  unsigned NewMask = 0;
338  // Keep any existing condition bits.
339  NewMask |= ITState.Mask & (0xE << TZ);
340  // Insert the new condition bit.
341  NewMask |= (Cond == ITState.Cond) << TZ;
342  // Move the trailing 1 down one bit.
343  NewMask |= 1 << (TZ - 1);
344  ITState.Mask = NewMask;
345  }
346 
347  // Create a new implicit IT block with a dummy condition code.
348  void startImplicitITBlock() {
349  assert(!inITBlock());
350  ITState.Cond = ARMCC::AL;
351  ITState.Mask = 8;
352  ITState.CurPosition = 1;
353  ITState.IsExplicit = false;
354  }
355 
356  // Create a new explicit IT block with the given condition and mask. The mask
357  // should be in the parsed format, with a 1 implying 't', regardless of the
358  // low bit of the condition.
359  void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
360  assert(!inITBlock());
361  ITState.Cond = Cond;
362  ITState.Mask = Mask;
363  ITState.CurPosition = 0;
364  ITState.IsExplicit = true;
365  }
366 
367  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
368  return getParser().Note(L, Msg, Range);
369  }
370 
371  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
372  return getParser().Warning(L, Msg, Range);
373  }
374 
375  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
376  return getParser().Error(L, Msg, Range);
377  }
378 
379  bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
380  unsigned ListNo, bool IsARPop = false);
381  bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
382  unsigned ListNo);
383 
384  int tryParseRegister();
385  bool tryParseRegisterWithWriteBack(OperandVector &);
386  int tryParseShiftRegister(OperandVector &);
387  bool parseRegisterList(OperandVector &);
388  bool parseMemory(OperandVector &);
389  bool parseOperand(OperandVector &, StringRef Mnemonic);
390  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
391  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
392  unsigned &ShiftAmount);
393  bool parseLiteralValues(unsigned Size, SMLoc L);
394  bool parseDirectiveThumb(SMLoc L);
395  bool parseDirectiveARM(SMLoc L);
396  bool parseDirectiveThumbFunc(SMLoc L);
397  bool parseDirectiveCode(SMLoc L);
398  bool parseDirectiveSyntax(SMLoc L);
399  bool parseDirectiveReq(StringRef Name, SMLoc L);
400  bool parseDirectiveUnreq(SMLoc L);
401  bool parseDirectiveArch(SMLoc L);
402  bool parseDirectiveEabiAttr(SMLoc L);
403  bool parseDirectiveCPU(SMLoc L);
404  bool parseDirectiveFPU(SMLoc L);
405  bool parseDirectiveFnStart(SMLoc L);
406  bool parseDirectiveFnEnd(SMLoc L);
407  bool parseDirectiveCantUnwind(SMLoc L);
408  bool parseDirectivePersonality(SMLoc L);
409  bool parseDirectiveHandlerData(SMLoc L);
410  bool parseDirectiveSetFP(SMLoc L);
411  bool parseDirectivePad(SMLoc L);
412  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
413  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
414  bool parseDirectiveLtorg(SMLoc L);
415  bool parseDirectiveEven(SMLoc L);
416  bool parseDirectivePersonalityIndex(SMLoc L);
417  bool parseDirectiveUnwindRaw(SMLoc L);
418  bool parseDirectiveTLSDescSeq(SMLoc L);
419  bool parseDirectiveMovSP(SMLoc L);
420  bool parseDirectiveObjectArch(SMLoc L);
421  bool parseDirectiveArchExtension(SMLoc L);
422  bool parseDirectiveAlign(SMLoc L);
423  bool parseDirectiveThumbSet(SMLoc L);
424 
425  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
426  bool &CarrySetting, unsigned &ProcessorIMod,
427  StringRef &ITMask);
428  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
429  bool &CanAcceptCarrySet,
430  bool &CanAcceptPredicationCode);
431 
432  void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
433  OperandVector &Operands);
434  bool isThumb() const {
435  // FIXME: Can tablegen auto-generate this?
436  return getSTI().getFeatureBits()[ARM::ModeThumb];
437  }
438 
439  bool isThumbOne() const {
440  return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
441  }
442 
443  bool isThumbTwo() const {
444  return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
445  }
446 
447  bool hasThumb() const {
448  return getSTI().getFeatureBits()[ARM::HasV4TOps];
449  }
450 
451  bool hasThumb2() const {
452  return getSTI().getFeatureBits()[ARM::FeatureThumb2];
453  }
454 
455  bool hasV6Ops() const {
456  return getSTI().getFeatureBits()[ARM::HasV6Ops];
457  }
458 
459  bool hasV6T2Ops() const {
460  return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
461  }
462 
463  bool hasV6MOps() const {
464  return getSTI().getFeatureBits()[ARM::HasV6MOps];
465  }
466 
467  bool hasV7Ops() const {
468  return getSTI().getFeatureBits()[ARM::HasV7Ops];
469  }
470 
471  bool hasV8Ops() const {
472  return getSTI().getFeatureBits()[ARM::HasV8Ops];
473  }
474 
475  bool hasV8MBaseline() const {
476  return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
477  }
478 
479  bool hasV8MMainline() const {
480  return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
481  }
482 
483  bool has8MSecExt() const {
484  return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
485  }
486 
487  bool hasARM() const {
488  return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
489  }
490 
491  bool hasDSP() const {
492  return getSTI().getFeatureBits()[ARM::FeatureDSP];
493  }
494 
495  bool hasD16() const {
496  return getSTI().getFeatureBits()[ARM::FeatureD16];
497  }
498 
499  bool hasV8_1aOps() const {
500  return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
501  }
502 
503  bool hasRAS() const {
504  return getSTI().getFeatureBits()[ARM::FeatureRAS];
505  }
506 
507  void SwitchMode() {
508  MCSubtargetInfo &STI = copySTI();
509  auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
510  setAvailableFeatures(FB);
511  }
512 
513  void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
514 
515  bool isMClass() const {
516  return getSTI().getFeatureBits()[ARM::FeatureMClass];
517  }
518 
519  /// @name Auto-generated Match Functions
520  /// {
521 
522 #define GET_ASSEMBLER_HEADER
523 #include "ARMGenAsmMatcher.inc"
524 
525  /// }
526 
527  OperandMatchResultTy parseITCondCode(OperandVector &);
528  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
529  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
530  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
531  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
532  OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
533  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
534  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
535  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
536  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
537  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
538  int High);
539  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
540  return parsePKHImm(O, "lsl", 0, 31);
541  }
542  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
543  return parsePKHImm(O, "asr", 1, 32);
544  }
545  OperandMatchResultTy parseSetEndImm(OperandVector &);
546  OperandMatchResultTy parseShifterImm(OperandVector &);
547  OperandMatchResultTy parseRotImm(OperandVector &);
548  OperandMatchResultTy parseModImm(OperandVector &);
549  OperandMatchResultTy parseBitfield(OperandVector &);
550  OperandMatchResultTy parsePostIdxReg(OperandVector &);
551  OperandMatchResultTy parseAM3Offset(OperandVector &);
552  OperandMatchResultTy parseFPImm(OperandVector &);
553  OperandMatchResultTy parseVectorList(OperandVector &);
554  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
555  SMLoc &EndLoc);
556 
557  // Asm Match Converter Methods
558  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
559  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
560 
561  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
562  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
563  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
564  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
565  bool isITBlockTerminator(MCInst &Inst) const;
566  void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
567  bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
568  bool Load, bool ARMMode, bool Writeback);
569 
570 public:
571  enum ARMMatchResultTy {
572  Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
573  Match_RequiresNotITBlock,
574  Match_RequiresV6,
575  Match_RequiresThumb2,
576  Match_RequiresV8,
577  Match_RequiresFlagSetting,
578 #define GET_OPERAND_DIAGNOSTIC_TYPES
579 #include "ARMGenAsmMatcher.inc"
580 
581  };
582 
583  ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
584  const MCInstrInfo &MII, const MCTargetOptions &Options)
585  : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
587 
588  // Cache the MCRegisterInfo.
589  MRI = getContext().getRegisterInfo();
590 
591  // Initialize the set of available features.
592  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
593 
594  // Add build attributes based on the selected target.
595  if (AddBuildAttributes)
596  getTargetStreamer().emitTargetAttributes(STI);
597 
598  // Not in an ITBlock to start with.
599  ITState.CurPosition = ~0U;
600 
601  NextSymbolIsThumb = false;
602  }
603 
604  // Implementation of the MCTargetAsmParser interface:
605  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
606  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
607  SMLoc NameLoc, OperandVector &Operands) override;
608  bool ParseDirective(AsmToken DirectiveID) override;
609 
610  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
611  unsigned Kind) override;
612  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
613 
614  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
615  OperandVector &Operands, MCStreamer &Out,
616  uint64_t &ErrorInfo,
617  bool MatchingInlineAsm) override;
618  unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
619  SmallVectorImpl<NearMissInfo> &NearMisses,
620  bool MatchingInlineAsm, bool &EmitInITBlock,
621  MCStreamer &Out);
622 
623  struct NearMissMessage {
624  SMLoc Loc;
625  SmallString<128> Message;
626  };
627 
628  const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
629 
630  void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
631  SmallVectorImpl<NearMissMessage> &NearMissesOut,
632  SMLoc IDLoc, OperandVector &Operands);
633  void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
634  OperandVector &Operands);
635 
636  void doBeforeLabelEmit(MCSymbol *Symbol) override;
637 
638  void onLabelParsed(MCSymbol *Symbol) override;
639 };
640 
641 /// ARMOperand - Instances of this class represent a parsed ARM machine
642 /// operand.
643 class ARMOperand : public MCParsedAsmOperand {
644  enum KindTy {
645  k_CondCode,
646  k_CCOut,
647  k_ITCondMask,
648  k_CoprocNum,
649  k_CoprocReg,
650  k_CoprocOption,
651  k_Immediate,
652  k_MemBarrierOpt,
653  k_InstSyncBarrierOpt,
654  k_TraceSyncBarrierOpt,
655  k_Memory,
656  k_PostIndexRegister,
657  k_MSRMask,
658  k_BankedReg,
659  k_ProcIFlags,
660  k_VectorIndex,
661  k_Register,
662  k_RegisterList,
663  k_DPRRegisterList,
664  k_SPRRegisterList,
665  k_VectorList,
666  k_VectorListAllLanes,
667  k_VectorListIndexed,
668  k_ShiftedRegister,
669  k_ShiftedImmediate,
670  k_ShifterImmediate,
671  k_RotateImmediate,
672  k_ModifiedImmediate,
673  k_ConstantPoolImmediate,
674  k_BitfieldDescriptor,
675  k_Token,
676  } Kind;
677 
678  SMLoc StartLoc, EndLoc, AlignmentLoc;
680 
681  struct CCOp {
682  ARMCC::CondCodes Val;
683  };
684 
685  struct CopOp {
686  unsigned Val;
687  };
688 
689  struct CoprocOptionOp {
690  unsigned Val;
691  };
692 
693  struct ITMaskOp {
694  unsigned Mask:4;
695  };
696 
697  struct MBOptOp {
698  ARM_MB::MemBOpt Val;
699  };
700 
701  struct ISBOptOp {
703  };
704 
705  struct TSBOptOp {
707  };
708 
709  struct IFlagsOp {
710  ARM_PROC::IFlags Val;
711  };
712 
713  struct MMaskOp {
714  unsigned Val;
715  };
716 
717  struct BankedRegOp {
718  unsigned Val;
719  };
720 
721  struct TokOp {
722  const char *Data;
723  unsigned Length;
724  };
725 
726  struct RegOp {
727  unsigned RegNum;
728  };
729 
730  // A vector register list is a sequential list of 1 to 4 registers.
731  struct VectorListOp {
732  unsigned RegNum;
733  unsigned Count;
734  unsigned LaneIndex;
735  bool isDoubleSpaced;
736  };
737 
738  struct VectorIndexOp {
739  unsigned Val;
740  };
741 
742  struct ImmOp {
743  const MCExpr *Val;
744  };
745 
746  /// Combined record for all forms of ARM address expressions.
747  struct MemoryOp {
748  unsigned BaseRegNum;
749  // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
750  // was specified.
751  const MCConstantExpr *OffsetImm; // Offset immediate value
752  unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
753  ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
754  unsigned ShiftImm; // shift for OffsetReg.
755  unsigned Alignment; // 0 = no alignment specified
756  // n = alignment in bytes (2, 4, 8, 16, or 32)
757  unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
758  };
759 
760  struct PostIdxRegOp {
761  unsigned RegNum;
762  bool isAdd;
763  ARM_AM::ShiftOpc ShiftTy;
764  unsigned ShiftImm;
765  };
766 
767  struct ShifterImmOp {
768  bool isASR;
769  unsigned Imm;
770  };
771 
772  struct RegShiftedRegOp {
773  ARM_AM::ShiftOpc ShiftTy;
774  unsigned SrcReg;
775  unsigned ShiftReg;
776  unsigned ShiftImm;
777  };
778 
779  struct RegShiftedImmOp {
780  ARM_AM::ShiftOpc ShiftTy;
781  unsigned SrcReg;
782  unsigned ShiftImm;
783  };
784 
785  struct RotImmOp {
786  unsigned Imm;
787  };
788 
789  struct ModImmOp {
790  unsigned Bits;
791  unsigned Rot;
792  };
793 
794  struct BitfieldOp {
795  unsigned LSB;
796  unsigned Width;
797  };
798 
799  union {
800  struct CCOp CC;
801  struct CopOp Cop;
802  struct CoprocOptionOp CoprocOption;
803  struct MBOptOp MBOpt;
804  struct ISBOptOp ISBOpt;
805  struct TSBOptOp TSBOpt;
806  struct ITMaskOp ITMask;
807  struct IFlagsOp IFlags;
808  struct MMaskOp MMask;
809  struct BankedRegOp BankedReg;
810  struct TokOp Tok;
811  struct RegOp Reg;
812  struct VectorListOp VectorList;
813  struct VectorIndexOp VectorIndex;
814  struct ImmOp Imm;
815  struct MemoryOp Memory;
816  struct PostIdxRegOp PostIdxReg;
817  struct ShifterImmOp ShifterImm;
818  struct RegShiftedRegOp RegShiftedReg;
819  struct RegShiftedImmOp RegShiftedImm;
820  struct RotImmOp RotImm;
821  struct ModImmOp ModImm;
822  struct BitfieldOp Bitfield;
823  };
824 
825 public:
826  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
827 
828  /// getStartLoc - Get the location of the first token of this operand.
829  SMLoc getStartLoc() const override { return StartLoc; }
830 
831  /// getEndLoc - Get the location of the last token of this operand.
832  SMLoc getEndLoc() const override { return EndLoc; }
833 
834  /// getLocRange - Get the range between the first and last token of this
835  /// operand.
836  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
837 
838  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
839  SMLoc getAlignmentLoc() const {
840  assert(Kind == k_Memory && "Invalid access!");
841  return AlignmentLoc;
842  }
843 
844  ARMCC::CondCodes getCondCode() const {
845  assert(Kind == k_CondCode && "Invalid access!");
846  return CC.Val;
847  }
848 
849  unsigned getCoproc() const {
850  assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
851  return Cop.Val;
852  }
853 
854  StringRef getToken() const {
855  assert(Kind == k_Token && "Invalid access!");
856  return StringRef(Tok.Data, Tok.Length);
857  }
858 
859  unsigned getReg() const override {
860  assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
861  return Reg.RegNum;
862  }
863 
864  const SmallVectorImpl<unsigned> &getRegList() const {
865  assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
866  Kind == k_SPRRegisterList) && "Invalid access!");
867  return Registers;
868  }
869 
870  const MCExpr *getImm() const {
871  assert(isImm() && "Invalid access!");
872  return Imm.Val;
873  }
874 
875  const MCExpr *getConstantPoolImm() const {
876  assert(isConstantPoolImm() && "Invalid access!");
877  return Imm.Val;
878  }
879 
880  unsigned getVectorIndex() const {
881  assert(Kind == k_VectorIndex && "Invalid access!");
882  return VectorIndex.Val;
883  }
884 
885  ARM_MB::MemBOpt getMemBarrierOpt() const {
886  assert(Kind == k_MemBarrierOpt && "Invalid access!");
887  return MBOpt.Val;
888  }
889 
890  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
891  assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
892  return ISBOpt.Val;
893  }
894 
895  ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
896  assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
897  return TSBOpt.Val;
898  }
899 
900  ARM_PROC::IFlags getProcIFlags() const {
901  assert(Kind == k_ProcIFlags && "Invalid access!");
902  return IFlags.Val;
903  }
904 
905  unsigned getMSRMask() const {
906  assert(Kind == k_MSRMask && "Invalid access!");
907  return MMask.Val;
908  }
909 
910  unsigned getBankedReg() const {
911  assert(Kind == k_BankedReg && "Invalid access!");
912  return BankedReg.Val;
913  }
914 
915  bool isCoprocNum() const { return Kind == k_CoprocNum; }
916  bool isCoprocReg() const { return Kind == k_CoprocReg; }
917  bool isCoprocOption() const { return Kind == k_CoprocOption; }
918  bool isCondCode() const { return Kind == k_CondCode; }
919  bool isCCOut() const { return Kind == k_CCOut; }
920  bool isITMask() const { return Kind == k_ITCondMask; }
921  bool isITCondCode() const { return Kind == k_CondCode; }
922  bool isImm() const override {
923  return Kind == k_Immediate;
924  }
925 
926  bool isARMBranchTarget() const {
927  if (!isImm()) return false;
928 
929  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
930  return CE->getValue() % 4 == 0;
931  return true;
932  }
933 
934 
935  bool isThumbBranchTarget() const {
936  if (!isImm()) return false;
937 
938  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
939  return CE->getValue() % 2 == 0;
940  return true;
941  }
942 
943  // checks whether this operand is an unsigned offset which fits is a field
944  // of specified width and scaled by a specific number of bits
945  template<unsigned width, unsigned scale>
946  bool isUnsignedOffset() const {
947  if (!isImm()) return false;
948  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
949  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
950  int64_t Val = CE->getValue();
951  int64_t Align = 1LL << scale;
952  int64_t Max = Align * ((1LL << width) - 1);
953  return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
954  }
955  return false;
956  }
957 
958  // checks whether this operand is an signed offset which fits is a field
959  // of specified width and scaled by a specific number of bits
960  template<unsigned width, unsigned scale>
961  bool isSignedOffset() const {
962  if (!isImm()) return false;
963  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
964  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
965  int64_t Val = CE->getValue();
966  int64_t Align = 1LL << scale;
967  int64_t Max = Align * ((1LL << (width-1)) - 1);
968  int64_t Min = -Align * (1LL << (width-1));
969  return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
970  }
971  return false;
972  }
973 
974  // checks whether this operand is a memory operand computed as an offset
975  // applied to PC. the offset may have 8 bits of magnitude and is represented
976  // with two bits of shift. textually it may be either [pc, #imm], #imm or
977  // relocable expression...
978  bool isThumbMemPC() const {
979  int64_t Val = 0;
980  if (isImm()) {
981  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
982  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
983  if (!CE) return false;
984  Val = CE->getValue();
985  }
986  else if (isMem()) {
987  if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
988  if(Memory.BaseRegNum != ARM::PC) return false;
989  Val = Memory.OffsetImm->getValue();
990  }
991  else return false;
992  return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
993  }
994 
995  bool isFPImm() const {
996  if (!isImm()) return false;
997  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998  if (!CE) return false;
999  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1000  return Val != -1;
1001  }
1002 
1003  template<int64_t N, int64_t M>
1004  bool isImmediate() const {
1005  if (!isImm()) return false;
1006  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007  if (!CE) return false;
1008  int64_t Value = CE->getValue();
1009  return Value >= N && Value <= M;
1010  }
1011 
1012  template<int64_t N, int64_t M>
1013  bool isImmediateS4() const {
1014  if (!isImm()) return false;
1015  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1016  if (!CE) return false;
1017  int64_t Value = CE->getValue();
1018  return ((Value & 3) == 0) && Value >= N && Value <= M;
1019  }
1020 
1021  bool isFBits16() const {
1022  return isImmediate<0, 17>();
1023  }
1024  bool isFBits32() const {
1025  return isImmediate<1, 33>();
1026  }
1027  bool isImm8s4() const {
1028  return isImmediateS4<-1020, 1020>();
1029  }
1030  bool isImm0_1020s4() const {
1031  return isImmediateS4<0, 1020>();
1032  }
1033  bool isImm0_508s4() const {
1034  return isImmediateS4<0, 508>();
1035  }
1036  bool isImm0_508s4Neg() const {
1037  if (!isImm()) return false;
1038  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1039  if (!CE) return false;
1040  int64_t Value = -CE->getValue();
1041  // explicitly exclude zero. we want that to use the normal 0_508 version.
1042  return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1043  }
1044 
1045  bool isImm0_4095Neg() const {
1046  if (!isImm()) return false;
1047  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048  if (!CE) return false;
1049  // isImm0_4095Neg is used with 32-bit immediates only.
1050  // 32-bit immediates are zero extended to 64-bit when parsed,
1051  // thus simple -CE->getValue() results in a big negative number,
1052  // not a small positive number as intended
1053  if ((CE->getValue() >> 32) > 0) return false;
1054  uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1055  return Value > 0 && Value < 4096;
1056  }
1057 
1058  bool isImm0_7() const {
1059  return isImmediate<0, 7>();
1060  }
1061 
1062  bool isImm1_16() const {
1063  return isImmediate<1, 16>();
1064  }
1065 
1066  bool isImm1_32() const {
1067  return isImmediate<1, 32>();
1068  }
1069 
1070  bool isImm8_255() const {
1071  return isImmediate<8, 255>();
1072  }
1073 
1074  bool isImm256_65535Expr() const {
1075  if (!isImm()) return false;
1076  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1077  // If it's not a constant expression, it'll generate a fixup and be
1078  // handled later.
1079  if (!CE) return true;
1080  int64_t Value = CE->getValue();
1081  return Value >= 256 && Value < 65536;
1082  }
1083 
1084  bool isImm0_65535Expr() const {
1085  if (!isImm()) return false;
1086  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1087  // If it's not a constant expression, it'll generate a fixup and be
1088  // handled later.
1089  if (!CE) return true;
1090  int64_t Value = CE->getValue();
1091  return Value >= 0 && Value < 65536;
1092  }
1093 
1094  bool isImm24bit() const {
1095  return isImmediate<0, 0xffffff + 1>();
1096  }
1097 
1098  bool isImmThumbSR() const {
1099  return isImmediate<1, 33>();
1100  }
1101 
1102  bool isPKHLSLImm() const {
1103  return isImmediate<0, 32>();
1104  }
1105 
1106  bool isPKHASRImm() const {
1107  return isImmediate<0, 33>();
1108  }
1109 
1110  bool isAdrLabel() const {
1111  // If we have an immediate that's not a constant, treat it as a label
1112  // reference needing a fixup.
1113  if (isImm() && !isa<MCConstantExpr>(getImm()))
1114  return true;
1115 
1116  // If it is a constant, it must fit into a modified immediate encoding.
1117  if (!isImm()) return false;
1118  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1119  if (!CE) return false;
1120  int64_t Value = CE->getValue();
1121  return (ARM_AM::getSOImmVal(Value) != -1 ||
1122  ARM_AM::getSOImmVal(-Value) != -1);
1123  }
1124 
1125  bool isT2SOImm() const {
1126  // If we have an immediate that's not a constant, treat it as an expression
1127  // needing a fixup.
1128  if (isImm() && !isa<MCConstantExpr>(getImm())) {
1129  // We want to avoid matching :upper16: and :lower16: as we want these
1130  // expressions to match in isImm0_65535Expr()
1131  const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1132  return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1133  ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1134  }
1135  if (!isImm()) return false;
1136  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137  if (!CE) return false;
1138  int64_t Value = CE->getValue();
1139  return ARM_AM::getT2SOImmVal(Value) != -1;
1140  }
1141 
1142  bool isT2SOImmNot() const {
1143  if (!isImm()) return false;
1144  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1145  if (!CE) return false;
1146  int64_t Value = CE->getValue();
1147  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1148  ARM_AM::getT2SOImmVal(~Value) != -1;
1149  }
1150 
1151  bool isT2SOImmNeg() const {
1152  if (!isImm()) return false;
1153  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1154  if (!CE) return false;
1155  int64_t Value = CE->getValue();
1156  // Only use this when not representable as a plain so_imm.
1157  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1158  ARM_AM::getT2SOImmVal(-Value) != -1;
1159  }
1160 
1161  bool isSetEndImm() const {
1162  if (!isImm()) return false;
1163  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1164  if (!CE) return false;
1165  int64_t Value = CE->getValue();
1166  return Value == 1 || Value == 0;
1167  }
1168 
1169  bool isReg() const override { return Kind == k_Register; }
1170  bool isRegList() const { return Kind == k_RegisterList; }
1171  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1172  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1173  bool isToken() const override { return Kind == k_Token; }
1174  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1175  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1176  bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1177  bool isMem() const override {
1178  if (Kind != k_Memory)
1179  return false;
1180  if (Memory.BaseRegNum &&
1181  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1182  return false;
1183  if (Memory.OffsetRegNum &&
1184  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1185  return false;
1186  return true;
1187  }
1188  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1189  bool isRegShiftedReg() const {
1190  return Kind == k_ShiftedRegister &&
1191  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1192  RegShiftedReg.SrcReg) &&
1193  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1194  RegShiftedReg.ShiftReg);
1195  }
1196  bool isRegShiftedImm() const {
1197  return Kind == k_ShiftedImmediate &&
1198  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1199  RegShiftedImm.SrcReg);
1200  }
1201  bool isRotImm() const { return Kind == k_RotateImmediate; }
1202  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1203 
1204  bool isModImmNot() const {
1205  if (!isImm()) return false;
1206  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1207  if (!CE) return false;
1208  int64_t Value = CE->getValue();
1209  return ARM_AM::getSOImmVal(~Value) != -1;
1210  }
1211 
1212  bool isModImmNeg() const {
1213  if (!isImm()) return false;
1214  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1215  if (!CE) return false;
1216  int64_t Value = CE->getValue();
1217  return ARM_AM::getSOImmVal(Value) == -1 &&
1218  ARM_AM::getSOImmVal(-Value) != -1;
1219  }
1220 
1221  bool isThumbModImmNeg1_7() const {
1222  if (!isImm()) return false;
1223  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224  if (!CE) return false;
1225  int32_t Value = -(int32_t)CE->getValue();
1226  return 0 < Value && Value < 8;
1227  }
1228 
1229  bool isThumbModImmNeg8_255() const {
1230  if (!isImm()) return false;
1231  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1232  if (!CE) return false;
1233  int32_t Value = -(int32_t)CE->getValue();
1234  return 7 < Value && Value < 256;
1235  }
1236 
1237  bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1238  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1239  bool isPostIdxRegShifted() const {
1240  return Kind == k_PostIndexRegister &&
1241  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1242  }
1243  bool isPostIdxReg() const {
1244  return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1245  }
1246  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1247  if (!isMem())
1248  return false;
1249  // No offset of any kind.
1250  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1251  (alignOK || Memory.Alignment == Alignment);
1252  }
1253  bool isMemPCRelImm12() const {
1254  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1255  return false;
1256  // Base register must be PC.
1257  if (Memory.BaseRegNum != ARM::PC)
1258  return false;
1259  // Immediate offset in range [-4095, 4095].
1260  if (!Memory.OffsetImm) return true;
1261  int64_t Val = Memory.OffsetImm->getValue();
1262  return (Val > -4096 && Val < 4096) ||
1263  (Val == std::numeric_limits<int32_t>::min());
1264  }
1265 
1266  bool isAlignedMemory() const {
1267  return isMemNoOffset(true);
1268  }
1269 
1270  bool isAlignedMemoryNone() const {
1271  return isMemNoOffset(false, 0);
1272  }
1273 
1274  bool isDupAlignedMemoryNone() const {
1275  return isMemNoOffset(false, 0);
1276  }
1277 
1278  bool isAlignedMemory16() const {
1279  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1280  return true;
1281  return isMemNoOffset(false, 0);
1282  }
1283 
1284  bool isDupAlignedMemory16() const {
1285  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1286  return true;
1287  return isMemNoOffset(false, 0);
1288  }
1289 
1290  bool isAlignedMemory32() const {
1291  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1292  return true;
1293  return isMemNoOffset(false, 0);
1294  }
1295 
1296  bool isDupAlignedMemory32() const {
1297  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1298  return true;
1299  return isMemNoOffset(false, 0);
1300  }
1301 
1302  bool isAlignedMemory64() const {
1303  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1304  return true;
1305  return isMemNoOffset(false, 0);
1306  }
1307 
1308  bool isDupAlignedMemory64() const {
1309  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1310  return true;
1311  return isMemNoOffset(false, 0);
1312  }
1313 
1314  bool isAlignedMemory64or128() const {
1315  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1316  return true;
1317  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1318  return true;
1319  return isMemNoOffset(false, 0);
1320  }
1321 
1322  bool isDupAlignedMemory64or128() const {
1323  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1324  return true;
1325  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1326  return true;
1327  return isMemNoOffset(false, 0);
1328  }
1329 
1330  bool isAlignedMemory64or128or256() const {
1331  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1332  return true;
1333  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1334  return true;
1335  if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1336  return true;
1337  return isMemNoOffset(false, 0);
1338  }
1339 
1340  bool isAddrMode2() const {
1341  if (!isMem() || Memory.Alignment != 0) return false;
1342  // Check for register offset.
1343  if (Memory.OffsetRegNum) return true;
1344  // Immediate offset in range [-4095, 4095].
1345  if (!Memory.OffsetImm) return true;
1346  int64_t Val = Memory.OffsetImm->getValue();
1347  return Val > -4096 && Val < 4096;
1348  }
1349 
1350  bool isAM2OffsetImm() const {
1351  if (!isImm()) return false;
1352  // Immediate offset in range [-4095, 4095].
1353  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1354  if (!CE) return false;
1355  int64_t Val = CE->getValue();
1356  return (Val == std::numeric_limits<int32_t>::min()) ||
1357  (Val > -4096 && Val < 4096);
1358  }
1359 
1360  bool isAddrMode3() const {
1361  // If we have an immediate that's not a constant, treat it as a label
1362  // reference needing a fixup. If it is a constant, it's something else
1363  // and we reject it.
1364  if (isImm() && !isa<MCConstantExpr>(getImm()))
1365  return true;
1366  if (!isMem() || Memory.Alignment != 0) return false;
1367  // No shifts are legal for AM3.
1368  if (Memory.ShiftType != ARM_AM::no_shift) return false;
1369  // Check for register offset.
1370  if (Memory.OffsetRegNum) return true;
1371  // Immediate offset in range [-255, 255].
1372  if (!Memory.OffsetImm) return true;
1373  int64_t Val = Memory.OffsetImm->getValue();
1374  // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1375  // have to check for this too.
1376  return (Val > -256 && Val < 256) ||
1377  Val == std::numeric_limits<int32_t>::min();
1378  }
1379 
1380  bool isAM3Offset() const {
1381  if (isPostIdxReg())
1382  return true;
1383  if (!isImm())
1384  return false;
1385  // Immediate offset in range [-255, 255].
1386  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1387  if (!CE) return false;
1388  int64_t Val = CE->getValue();
1389  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1390  return (Val > -256 && Val < 256) ||
1391  Val == std::numeric_limits<int32_t>::min();
1392  }
1393 
1394  bool isAddrMode5() const {
1395  // If we have an immediate that's not a constant, treat it as a label
1396  // reference needing a fixup. If it is a constant, it's something else
1397  // and we reject it.
1398  if (isImm() && !isa<MCConstantExpr>(getImm()))
1399  return true;
1400  if (!isMem() || Memory.Alignment != 0) return false;
1401  // Check for register offset.
1402  if (Memory.OffsetRegNum) return false;
1403  // Immediate offset in range [-1020, 1020] and a multiple of 4.
1404  if (!Memory.OffsetImm) return true;
1405  int64_t Val = Memory.OffsetImm->getValue();
1406  return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1407  Val == std::numeric_limits<int32_t>::min();
1408  }
1409 
1410  bool isAddrMode5FP16() const {
1411  // If we have an immediate that's not a constant, treat it as a label
1412  // reference needing a fixup. If it is a constant, it's something else
1413  // and we reject it.
1414  if (isImm() && !isa<MCConstantExpr>(getImm()))
1415  return true;
1416  if (!isMem() || Memory.Alignment != 0) return false;
1417  // Check for register offset.
1418  if (Memory.OffsetRegNum) return false;
1419  // Immediate offset in range [-510, 510] and a multiple of 2.
1420  if (!Memory.OffsetImm) return true;
1421  int64_t Val = Memory.OffsetImm->getValue();
1422  return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1423  Val == std::numeric_limits<int32_t>::min();
1424  }
1425 
1426  bool isMemTBB() const {
1427  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1428  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1429  return false;
1430  return true;
1431  }
1432 
1433  bool isMemTBH() const {
1434  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1435  Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1436  Memory.Alignment != 0 )
1437  return false;
1438  return true;
1439  }
1440 
1441  bool isMemRegOffset() const {
1442  if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1443  return false;
1444  return true;
1445  }
1446 
1447  bool isT2MemRegOffset() const {
1448  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1449  Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1450  return false;
1451  // Only lsl #{0, 1, 2, 3} allowed.
1452  if (Memory.ShiftType == ARM_AM::no_shift)
1453  return true;
1454  if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1455  return false;
1456  return true;
1457  }
1458 
1459  bool isMemThumbRR() const {
1460  // Thumb reg+reg addressing is simple. Just two registers, a base and
1461  // an offset. No shifts, negations or any other complicating factors.
1462  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1463  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1464  return false;
1465  return isARMLowRegister(Memory.BaseRegNum) &&
1466  (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1467  }
1468 
1469  bool isMemThumbRIs4() const {
1470  if (!isMem() || Memory.OffsetRegNum != 0 ||
1471  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1472  return false;
1473  // Immediate offset, multiple of 4 in range [0, 124].
1474  if (!Memory.OffsetImm) return true;
1475  int64_t Val = Memory.OffsetImm->getValue();
1476  return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1477  }
1478 
1479  bool isMemThumbRIs2() const {
1480  if (!isMem() || Memory.OffsetRegNum != 0 ||
1481  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1482  return false;
1483  // Immediate offset, multiple of 4 in range [0, 62].
1484  if (!Memory.OffsetImm) return true;
1485  int64_t Val = Memory.OffsetImm->getValue();
1486  return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1487  }
1488 
1489  bool isMemThumbRIs1() const {
1490  if (!isMem() || Memory.OffsetRegNum != 0 ||
1491  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1492  return false;
1493  // Immediate offset in range [0, 31].
1494  if (!Memory.OffsetImm) return true;
1495  int64_t Val = Memory.OffsetImm->getValue();
1496  return Val >= 0 && Val <= 31;
1497  }
1498 
1499  bool isMemThumbSPI() const {
1500  if (!isMem() || Memory.OffsetRegNum != 0 ||
1501  Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1502  return false;
1503  // Immediate offset, multiple of 4 in range [0, 1020].
1504  if (!Memory.OffsetImm) return true;
1505  int64_t Val = Memory.OffsetImm->getValue();
1506  return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1507  }
1508 
1509  bool isMemImm8s4Offset() const {
1510  // If we have an immediate that's not a constant, treat it as a label
1511  // reference needing a fixup. If it is a constant, it's something else
1512  // and we reject it.
1513  if (isImm() && !isa<MCConstantExpr>(getImm()))
1514  return true;
1515  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1516  return false;
1517  // Immediate offset a multiple of 4 in range [-1020, 1020].
1518  if (!Memory.OffsetImm) return true;
1519  int64_t Val = Memory.OffsetImm->getValue();
1520  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1521  return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1522  Val == std::numeric_limits<int32_t>::min();
1523  }
1524 
1525  bool isMemImm0_1020s4Offset() const {
1526  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1527  return false;
1528  // Immediate offset a multiple of 4 in range [0, 1020].
1529  if (!Memory.OffsetImm) return true;
1530  int64_t Val = Memory.OffsetImm->getValue();
1531  return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1532  }
1533 
1534  bool isMemImm8Offset() const {
1535  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1536  return false;
1537  // Base reg of PC isn't allowed for these encodings.
1538  if (Memory.BaseRegNum == ARM::PC) return false;
1539  // Immediate offset in range [-255, 255].
1540  if (!Memory.OffsetImm) return true;
1541  int64_t Val = Memory.OffsetImm->getValue();
1542  return (Val == std::numeric_limits<int32_t>::min()) ||
1543  (Val > -256 && Val < 256);
1544  }
1545 
1546  bool isMemPosImm8Offset() const {
1547  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1548  return false;
1549  // Immediate offset in range [0, 255].
1550  if (!Memory.OffsetImm) return true;
1551  int64_t Val = Memory.OffsetImm->getValue();
1552  return Val >= 0 && Val < 256;
1553  }
1554 
1555  bool isMemNegImm8Offset() const {
1556  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1557  return false;
1558  // Base reg of PC isn't allowed for these encodings.
1559  if (Memory.BaseRegNum == ARM::PC) return false;
1560  // Immediate offset in range [-255, -1].
1561  if (!Memory.OffsetImm) return false;
1562  int64_t Val = Memory.OffsetImm->getValue();
1563  return (Val == std::numeric_limits<int32_t>::min()) ||
1564  (Val > -256 && Val < 0);
1565  }
1566 
1567  bool isMemUImm12Offset() const {
1568  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1569  return false;
1570  // Immediate offset in range [0, 4095].
1571  if (!Memory.OffsetImm) return true;
1572  int64_t Val = Memory.OffsetImm->getValue();
1573  return (Val >= 0 && Val < 4096);
1574  }
1575 
1576  bool isMemImm12Offset() const {
1577  // If we have an immediate that's not a constant, treat it as a label
1578  // reference needing a fixup. If it is a constant, it's something else
1579  // and we reject it.
1580 
1581  if (isImm() && !isa<MCConstantExpr>(getImm()))
1582  return true;
1583 
1584  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1585  return false;
1586  // Immediate offset in range [-4095, 4095].
1587  if (!Memory.OffsetImm) return true;
1588  int64_t Val = Memory.OffsetImm->getValue();
1589  return (Val > -4096 && Val < 4096) ||
1590  (Val == std::numeric_limits<int32_t>::min());
1591  }
1592 
1593  bool isConstPoolAsmImm() const {
1594  // Delay processing of Constant Pool Immediate, this will turn into
1595  // a constant. Match no other operand
1596  return (isConstantPoolImm());
1597  }
1598 
1599  bool isPostIdxImm8() const {
1600  if (!isImm()) return false;
1601  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602  if (!CE) return false;
1603  int64_t Val = CE->getValue();
1604  return (Val > -256 && Val < 256) ||
1605  (Val == std::numeric_limits<int32_t>::min());
1606  }
1607 
1608  bool isPostIdxImm8s4() const {
1609  if (!isImm()) return false;
1610  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1611  if (!CE) return false;
1612  int64_t Val = CE->getValue();
1613  return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1614  (Val == std::numeric_limits<int32_t>::min());
1615  }
1616 
1617  bool isMSRMask() const { return Kind == k_MSRMask; }
1618  bool isBankedReg() const { return Kind == k_BankedReg; }
1619  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1620 
1621  // NEON operands.
1622  bool isSingleSpacedVectorList() const {
1623  return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1624  }
1625 
1626  bool isDoubleSpacedVectorList() const {
1627  return Kind == k_VectorList && VectorList.isDoubleSpaced;
1628  }
1629 
1630  bool isVecListOneD() const {
1631  if (!isSingleSpacedVectorList()) return false;
1632  return VectorList.Count == 1;
1633  }
1634 
1635  bool isVecListDPair() const {
1636  if (!isSingleSpacedVectorList()) return false;
1637  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1638  .contains(VectorList.RegNum));
1639  }
1640 
1641  bool isVecListThreeD() const {
1642  if (!isSingleSpacedVectorList()) return false;
1643  return VectorList.Count == 3;
1644  }
1645 
1646  bool isVecListFourD() const {
1647  if (!isSingleSpacedVectorList()) return false;
1648  return VectorList.Count == 4;
1649  }
1650 
1651  bool isVecListDPairSpaced() const {
1652  if (Kind != k_VectorList) return false;
1653  if (isSingleSpacedVectorList()) return false;
1654  return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1655  .contains(VectorList.RegNum));
1656  }
1657 
1658  bool isVecListThreeQ() const {
1659  if (!isDoubleSpacedVectorList()) return false;
1660  return VectorList.Count == 3;
1661  }
1662 
1663  bool isVecListFourQ() const {
1664  if (!isDoubleSpacedVectorList()) return false;
1665  return VectorList.Count == 4;
1666  }
1667 
1668  bool isSingleSpacedVectorAllLanes() const {
1669  return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1670  }
1671 
1672  bool isDoubleSpacedVectorAllLanes() const {
1673  return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1674  }
1675 
1676  bool isVecListOneDAllLanes() const {
1677  if (!isSingleSpacedVectorAllLanes()) return false;
1678  return VectorList.Count == 1;
1679  }
1680 
1681  bool isVecListDPairAllLanes() const {
1682  if (!isSingleSpacedVectorAllLanes()) return false;
1683  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1684  .contains(VectorList.RegNum));
1685  }
1686 
1687  bool isVecListDPairSpacedAllLanes() const {
1688  if (!isDoubleSpacedVectorAllLanes()) return false;
1689  return VectorList.Count == 2;
1690  }
1691 
1692  bool isVecListThreeDAllLanes() const {
1693  if (!isSingleSpacedVectorAllLanes()) return false;
1694  return VectorList.Count == 3;
1695  }
1696 
1697  bool isVecListThreeQAllLanes() const {
1698  if (!isDoubleSpacedVectorAllLanes()) return false;
1699  return VectorList.Count == 3;
1700  }
1701 
1702  bool isVecListFourDAllLanes() const {
1703  if (!isSingleSpacedVectorAllLanes()) return false;
1704  return VectorList.Count == 4;
1705  }
1706 
1707  bool isVecListFourQAllLanes() const {
1708  if (!isDoubleSpacedVectorAllLanes()) return false;
1709  return VectorList.Count == 4;
1710  }
1711 
1712  bool isSingleSpacedVectorIndexed() const {
1713  return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1714  }
1715 
1716  bool isDoubleSpacedVectorIndexed() const {
1717  return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1718  }
1719 
1720  bool isVecListOneDByteIndexed() const {
1721  if (!isSingleSpacedVectorIndexed()) return false;
1722  return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1723  }
1724 
1725  bool isVecListOneDHWordIndexed() const {
1726  if (!isSingleSpacedVectorIndexed()) return false;
1727  return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1728  }
1729 
1730  bool isVecListOneDWordIndexed() const {
1731  if (!isSingleSpacedVectorIndexed()) return false;
1732  return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1733  }
1734 
1735  bool isVecListTwoDByteIndexed() const {
1736  if (!isSingleSpacedVectorIndexed()) return false;
1737  return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1738  }
1739 
1740  bool isVecListTwoDHWordIndexed() const {
1741  if (!isSingleSpacedVectorIndexed()) return false;
1742  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1743  }
1744 
1745  bool isVecListTwoQWordIndexed() const {
1746  if (!isDoubleSpacedVectorIndexed()) return false;
1747  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1748  }
1749 
1750  bool isVecListTwoQHWordIndexed() const {
1751  if (!isDoubleSpacedVectorIndexed()) return false;
1752  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1753  }
1754 
1755  bool isVecListTwoDWordIndexed() const {
1756  if (!isSingleSpacedVectorIndexed()) return false;
1757  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1758  }
1759 
1760  bool isVecListThreeDByteIndexed() const {
1761  if (!isSingleSpacedVectorIndexed()) return false;
1762  return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1763  }
1764 
1765  bool isVecListThreeDHWordIndexed() const {
1766  if (!isSingleSpacedVectorIndexed()) return false;
1767  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1768  }
1769 
1770  bool isVecListThreeQWordIndexed() const {
1771  if (!isDoubleSpacedVectorIndexed()) return false;
1772  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1773  }
1774 
1775  bool isVecListThreeQHWordIndexed() const {
1776  if (!isDoubleSpacedVectorIndexed()) return false;
1777  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1778  }
1779 
1780  bool isVecListThreeDWordIndexed() const {
1781  if (!isSingleSpacedVectorIndexed()) return false;
1782  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1783  }
1784 
1785  bool isVecListFourDByteIndexed() const {
1786  if (!isSingleSpacedVectorIndexed()) return false;
1787  return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1788  }
1789 
1790  bool isVecListFourDHWordIndexed() const {
1791  if (!isSingleSpacedVectorIndexed()) return false;
1792  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1793  }
1794 
1795  bool isVecListFourQWordIndexed() const {
1796  if (!isDoubleSpacedVectorIndexed()) return false;
1797  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1798  }
1799 
1800  bool isVecListFourQHWordIndexed() const {
1801  if (!isDoubleSpacedVectorIndexed()) return false;
1802  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1803  }
1804 
1805  bool isVecListFourDWordIndexed() const {
1806  if (!isSingleSpacedVectorIndexed()) return false;
1807  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1808  }
1809 
1810  bool isVectorIndex8() const {
1811  if (Kind != k_VectorIndex) return false;
1812  return VectorIndex.Val < 8;
1813  }
1814 
1815  bool isVectorIndex16() const {
1816  if (Kind != k_VectorIndex) return false;
1817  return VectorIndex.Val < 4;
1818  }
1819 
1820  bool isVectorIndex32() const {
1821  if (Kind != k_VectorIndex) return false;
1822  return VectorIndex.Val < 2;
1823  }
1824  bool isVectorIndex64() const {
1825  if (Kind != k_VectorIndex) return false;
1826  return VectorIndex.Val < 1;
1827  }
1828 
1829  bool isNEONi8splat() const {
1830  if (!isImm()) return false;
1831  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1832  // Must be a constant.
1833  if (!CE) return false;
1834  int64_t Value = CE->getValue();
1835  // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1836  // value.
1837  return Value >= 0 && Value < 256;
1838  }
1839 
1840  bool isNEONi16splat() const {
1841  if (isNEONByteReplicate(2))
1842  return false; // Leave that for bytes replication and forbid by default.
1843  if (!isImm())
1844  return false;
1845  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1846  // Must be a constant.
1847  if (!CE) return false;
1848  unsigned Value = CE->getValue();
1849  return ARM_AM::isNEONi16splat(Value);
1850  }
1851 
1852  bool isNEONi16splatNot() const {
1853  if (!isImm())
1854  return false;
1855  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1856  // Must be a constant.
1857  if (!CE) return false;
1858  unsigned Value = CE->getValue();
1859  return ARM_AM::isNEONi16splat(~Value & 0xffff);
1860  }
1861 
1862  bool isNEONi32splat() const {
1863  if (isNEONByteReplicate(4))
1864  return false; // Leave that for bytes replication and forbid by default.
1865  if (!isImm())
1866  return false;
1867  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868  // Must be a constant.
1869  if (!CE) return false;
1870  unsigned Value = CE->getValue();
1871  return ARM_AM::isNEONi32splat(Value);
1872  }
1873 
1874  bool isNEONi32splatNot() const {
1875  if (!isImm())
1876  return false;
1877  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1878  // Must be a constant.
1879  if (!CE) return false;
1880  unsigned Value = CE->getValue();
1881  return ARM_AM::isNEONi32splat(~Value);
1882  }
1883 
1884  static bool isValidNEONi32vmovImm(int64_t Value) {
1885  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1886  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1887  return ((Value & 0xffffffffffffff00) == 0) ||
1888  ((Value & 0xffffffffffff00ff) == 0) ||
1889  ((Value & 0xffffffffff00ffff) == 0) ||
1890  ((Value & 0xffffffff00ffffff) == 0) ||
1891  ((Value & 0xffffffffffff00ff) == 0xff) ||
1892  ((Value & 0xffffffffff00ffff) == 0xffff);
1893  }
1894 
1895  bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
1896  assert((Width == 8 || Width == 16 || Width == 32) &&
1897  "Invalid element width");
1898  assert(NumElems * Width <= 64 && "Invalid result width");
1899 
1900  if (!isImm())
1901  return false;
1902  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1903  // Must be a constant.
1904  if (!CE)
1905  return false;
1906  int64_t Value = CE->getValue();
1907  if (!Value)
1908  return false; // Don't bother with zero.
1909  if (Inv)
1910  Value = ~Value;
1911 
1912  uint64_t Mask = (1ull << Width) - 1;
1913  uint64_t Elem = Value & Mask;
1914  if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
1915  return false;
1916  if (Width == 32 && !isValidNEONi32vmovImm(Elem))
1917  return false;
1918 
1919  for (unsigned i = 1; i < NumElems; ++i) {
1920  Value >>= Width;
1921  if ((Value & Mask) != Elem)
1922  return false;
1923  }
1924  return true;
1925  }
1926 
1927  bool isNEONByteReplicate(unsigned NumBytes) const {
1928  return isNEONReplicate(8, NumBytes, false);
1929  }
1930 
1931  static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
1932  assert((FromW == 8 || FromW == 16 || FromW == 32) &&
1933  "Invalid source width");
1934  assert((ToW == 16 || ToW == 32 || ToW == 64) &&
1935  "Invalid destination width");
1936  assert(FromW < ToW && "ToW is not less than FromW");
1937  }
1938 
1939  template<unsigned FromW, unsigned ToW>
1940  bool isNEONmovReplicate() const {
1941  checkNeonReplicateArgs(FromW, ToW);
1942  if (ToW == 64 && isNEONi64splat())
1943  return false;
1944  return isNEONReplicate(FromW, ToW / FromW, false);
1945  }
1946 
1947  template<unsigned FromW, unsigned ToW>
1948  bool isNEONinvReplicate() const {
1949  checkNeonReplicateArgs(FromW, ToW);
1950  return isNEONReplicate(FromW, ToW / FromW, true);
1951  }
1952 
1953  bool isNEONi32vmov() const {
1954  if (isNEONByteReplicate(4))
1955  return false; // Let it to be classified as byte-replicate case.
1956  if (!isImm())
1957  return false;
1958  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1959  // Must be a constant.
1960  if (!CE)
1961  return false;
1962  return isValidNEONi32vmovImm(CE->getValue());
1963  }
1964 
1965  bool isNEONi32vmovNeg() const {
1966  if (!isImm()) return false;
1967  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1968  // Must be a constant.
1969  if (!CE) return false;
1970  return isValidNEONi32vmovImm(~CE->getValue());
1971  }
1972 
1973  bool isNEONi64splat() const {
1974  if (!isImm()) return false;
1975  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1976  // Must be a constant.
1977  if (!CE) return false;
1978  uint64_t Value = CE->getValue();
1979  // i64 value with each byte being either 0 or 0xff.
1980  for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1981  if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1982  return true;
1983  }
1984 
1985  template<int64_t Angle, int64_t Remainder>
1986  bool isComplexRotation() const {
1987  if (!isImm()) return false;
1988 
1989  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1990  if (!CE) return false;
1991  uint64_t Value = CE->getValue();
1992 
1993  return (Value % Angle == Remainder && Value <= 270);
1994  }
1995 
1996  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1997  // Add as immediates when possible. Null MCExpr = 0.
1998  if (!Expr)
2000  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2001  Inst.addOperand(MCOperand::createImm(CE->getValue()));
2002  else
2003  Inst.addOperand(MCOperand::createExpr(Expr));
2004  }
2005 
2006  void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2007  assert(N == 1 && "Invalid number of operands!");
2008  addExpr(Inst, getImm());
2009  }
2010 
2011  void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2012  assert(N == 1 && "Invalid number of operands!");
2013  addExpr(Inst, getImm());
2014  }
2015 
2016  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2017  assert(N == 2 && "Invalid number of operands!");
2018  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2019  unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2020  Inst.addOperand(MCOperand::createReg(RegNum));
2021  }
2022 
2023  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2024  assert(N == 1 && "Invalid number of operands!");
2025  Inst.addOperand(MCOperand::createImm(getCoproc()));
2026  }
2027 
2028  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2029  assert(N == 1 && "Invalid number of operands!");
2030  Inst.addOperand(MCOperand::createImm(getCoproc()));
2031  }
2032 
2033  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2034  assert(N == 1 && "Invalid number of operands!");
2035  Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2036  }
2037 
2038  void addITMaskOperands(MCInst &Inst, unsigned N) const {
2039  assert(N == 1 && "Invalid number of operands!");
2040  Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2041  }
2042 
2043  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2044  assert(N == 1 && "Invalid number of operands!");
2045  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2046  }
2047 
2048  void addCCOutOperands(MCInst &Inst, unsigned N) const {
2049  assert(N == 1 && "Invalid number of operands!");
2051  }
2052 
2053  void addRegOperands(MCInst &Inst, unsigned N) const {
2054  assert(N == 1 && "Invalid number of operands!");
2056  }
2057 
2058  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2059  assert(N == 3 && "Invalid number of operands!");
2060  assert(isRegShiftedReg() &&
2061  "addRegShiftedRegOperands() on non-RegShiftedReg!");
2062  Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2063  Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2065  ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2066  }
2067 
2068  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2069  assert(N == 2 && "Invalid number of operands!");
2070  assert(isRegShiftedImm() &&
2071  "addRegShiftedImmOperands() on non-RegShiftedImm!");
2072  Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2073  // Shift of #32 is encoded as 0 where permitted
2074  unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2076  ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2077  }
2078 
2079  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2080  assert(N == 1 && "Invalid number of operands!");
2081  Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2082  ShifterImm.Imm));
2083  }
2084 
2085  void addRegListOperands(MCInst &Inst, unsigned N) const {
2086  assert(N == 1 && "Invalid number of operands!");
2087  const SmallVectorImpl<unsigned> &RegList = getRegList();
2089  I = RegList.begin(), E = RegList.end(); I != E; ++I)
2091  }
2092 
2093  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2094  addRegListOperands(Inst, N);
2095  }
2096 
2097  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2098  addRegListOperands(Inst, N);
2099  }
2100 
2101  void addRotImmOperands(MCInst &Inst, unsigned N) const {
2102  assert(N == 1 && "Invalid number of operands!");
2103  // Encoded as val>>3. The printer handles display as 8, 16, 24.
2104  Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2105  }
2106 
2107  void addModImmOperands(MCInst &Inst, unsigned N) const {
2108  assert(N == 1 && "Invalid number of operands!");
2109 
2110  // Support for fixups (MCFixup)
2111  if (isImm())
2112  return addImmOperands(Inst, N);
2113 
2114  Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2115  }
2116 
2117  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2118  assert(N == 1 && "Invalid number of operands!");
2119  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2120  uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2121  Inst.addOperand(MCOperand::createImm(Enc));
2122  }
2123 
2124  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2125  assert(N == 1 && "Invalid number of operands!");
2126  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2127  uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2128  Inst.addOperand(MCOperand::createImm(Enc));
2129  }
2130 
2131  void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2132  assert(N == 1 && "Invalid number of operands!");
2133  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2134  uint32_t Val = -CE->getValue();
2135  Inst.addOperand(MCOperand::createImm(Val));
2136  }
2137 
2138  void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2139  assert(N == 1 && "Invalid number of operands!");
2140  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141  uint32_t Val = -CE->getValue();
2142  Inst.addOperand(MCOperand::createImm(Val));
2143  }
2144 
2145  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2146  assert(N == 1 && "Invalid number of operands!");
2147  // Munge the lsb/width into a bitfield mask.
2148  unsigned lsb = Bitfield.LSB;
2149  unsigned width = Bitfield.Width;
2150  // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2151  uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2152  (32 - (lsb + width)));
2153  Inst.addOperand(MCOperand::createImm(Mask));
2154  }
2155 
2156  void addImmOperands(MCInst &Inst, unsigned N) const {
2157  assert(N == 1 && "Invalid number of operands!");
2158  addExpr(Inst, getImm());
2159  }
2160 
2161  void addFBits16Operands(MCInst &Inst, unsigned N) const {
2162  assert(N == 1 && "Invalid number of operands!");
2163  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2164  Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2165  }
2166 
2167  void addFBits32Operands(MCInst &Inst, unsigned N) const {
2168  assert(N == 1 && "Invalid number of operands!");
2169  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2170  Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2171  }
2172 
2173  void addFPImmOperands(MCInst &Inst, unsigned N) const {
2174  assert(N == 1 && "Invalid number of operands!");
2175  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2176  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2177  Inst.addOperand(MCOperand::createImm(Val));
2178  }
2179 
2180  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2181  assert(N == 1 && "Invalid number of operands!");
2182  // FIXME: We really want to scale the value here, but the LDRD/STRD
2183  // instruction don't encode operands that way yet.
2184  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2186  }
2187 
2188  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2189  assert(N == 1 && "Invalid number of operands!");
2190  // The immediate is scaled by four in the encoding and is stored
2191  // in the MCInst as such. Lop off the low two bits here.
2192  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2193  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2194  }
2195 
2196  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2197  assert(N == 1 && "Invalid number of operands!");
2198  // The immediate is scaled by four in the encoding and is stored
2199  // in the MCInst as such. Lop off the low two bits here.
2200  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2201  Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2202  }
2203 
2204  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2205  assert(N == 1 && "Invalid number of operands!");
2206  // The immediate is scaled by four in the encoding and is stored
2207  // in the MCInst as such. Lop off the low two bits here.
2208  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2209  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2210  }
2211 
2212  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2213  assert(N == 1 && "Invalid number of operands!");
2214  // The constant encodes as the immediate-1, and we store in the instruction
2215  // the bits as encoded, so subtract off one here.
2216  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2217  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2218  }
2219 
2220  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2221  assert(N == 1 && "Invalid number of operands!");
2222  // The constant encodes as the immediate-1, and we store in the instruction
2223  // the bits as encoded, so subtract off one here.
2224  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2225  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2226  }
2227 
2228  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2229  assert(N == 1 && "Invalid number of operands!");
2230  // The constant encodes as the immediate, except for 32, which encodes as
2231  // zero.
2232  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2233  unsigned Imm = CE->getValue();
2234  Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2235  }
2236 
2237  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2238  assert(N == 1 && "Invalid number of operands!");
2239  // An ASR value of 32 encodes as 0, so that's how we want to add it to
2240  // the instruction as well.
2241  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2242  int Val = CE->getValue();
2243  Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2244  }
2245 
2246  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2247  assert(N == 1 && "Invalid number of operands!");
2248  // The operand is actually a t2_so_imm, but we have its bitwise
2249  // negation in the assembly source, so twiddle it here.
2250  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2252  }
2253 
2254  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2255  assert(N == 1 && "Invalid number of operands!");
2256  // The operand is actually a t2_so_imm, but we have its
2257  // negation in the assembly source, so twiddle it here.
2258  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2260  }
2261 
2262  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2263  assert(N == 1 && "Invalid number of operands!");
2264  // The operand is actually an imm0_4095, but we have its
2265  // negation in the assembly source, so twiddle it here.
2266  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2268  }
2269 
2270  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2271  if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2272  Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2273  return;
2274  }
2275 
2276  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2277  assert(SR && "Unknown value type!");
2279  }
2280 
2281  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2282  assert(N == 1 && "Invalid number of operands!");
2283  if (isImm()) {
2284  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2285  if (CE) {
2287  return;
2288  }
2289 
2290  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2291 
2292  assert(SR && "Unknown value type!");
2294  return;
2295  }
2296 
2297  assert(isMem() && "Unknown value type!");
2298  assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2299  Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2300  }
2301 
2302  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2303  assert(N == 1 && "Invalid number of operands!");
2304  Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2305  }
2306 
2307  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2308  assert(N == 1 && "Invalid number of operands!");
2309  Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2310  }
2311 
2312  void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2313  assert(N == 1 && "Invalid number of operands!");
2314  Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2315  }
2316 
2317  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2318  assert(N == 1 && "Invalid number of operands!");
2319  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2320  }
2321 
2322  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2323  assert(N == 1 && "Invalid number of operands!");
2324  int32_t Imm = Memory.OffsetImm->getValue();
2325  Inst.addOperand(MCOperand::createImm(Imm));
2326  }
2327 
2328  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2329  assert(N == 1 && "Invalid number of operands!");
2330  assert(isImm() && "Not an immediate!");
2331 
2332  // If we have an immediate that's not a constant, treat it as a label
2333  // reference needing a fixup.
2334  if (!isa<MCConstantExpr>(getImm())) {
2335  Inst.addOperand(MCOperand::createExpr(getImm()));
2336  return;
2337  }
2338 
2339  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2340  int Val = CE->getValue();
2341  Inst.addOperand(MCOperand::createImm(Val));
2342  }
2343 
2344  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2345  assert(N == 2 && "Invalid number of operands!");
2346  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2347  Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2348  }
2349 
2350  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2351  addAlignedMemoryOperands(Inst, N);
2352  }
2353 
2354  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2355  addAlignedMemoryOperands(Inst, N);
2356  }
2357 
2358  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2359  addAlignedMemoryOperands(Inst, N);
2360  }
2361 
2362  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2363  addAlignedMemoryOperands(Inst, N);
2364  }
2365 
2366  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2367  addAlignedMemoryOperands(Inst, N);
2368  }
2369 
2370  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2371  addAlignedMemoryOperands(Inst, N);
2372  }
2373 
2374  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2375  addAlignedMemoryOperands(Inst, N);
2376  }
2377 
2378  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2379  addAlignedMemoryOperands(Inst, N);
2380  }
2381 
2382  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2383  addAlignedMemoryOperands(Inst, N);
2384  }
2385 
2386  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2387  addAlignedMemoryOperands(Inst, N);
2388  }
2389 
2390  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2391  addAlignedMemoryOperands(Inst, N);
2392  }
2393 
2394  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2395  assert(N == 3 && "Invalid number of operands!");
2396  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2397  if (!Memory.OffsetRegNum) {
2398  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2399  // Special case for #-0
2400  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2401  if (Val < 0) Val = -Val;
2402  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2403  } else {
2404  // For register offset, we encode the shift type and negation flag
2405  // here.
2406  Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2407  Memory.ShiftImm, Memory.ShiftType);
2408  }
2409  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2410  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2411  Inst.addOperand(MCOperand::createImm(Val));
2412  }
2413 
2414  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2415  assert(N == 2 && "Invalid number of operands!");
2416  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2417  assert(CE && "non-constant AM2OffsetImm operand!");
2418  int32_t Val = CE->getValue();
2419  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2420  // Special case for #-0
2421  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2422  if (Val < 0) Val = -Val;
2423  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2425  Inst.addOperand(MCOperand::createImm(Val));
2426  }
2427 
2428  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2429  assert(N == 3 && "Invalid number of operands!");
2430  // If we have an immediate that's not a constant, treat it as a label
2431  // reference needing a fixup. If it is a constant, it's something else
2432  // and we reject it.
2433  if (isImm()) {
2434  Inst.addOperand(MCOperand::createExpr(getImm()));
2437  return;
2438  }
2439 
2440  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2441  if (!Memory.OffsetRegNum) {
2442  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2443  // Special case for #-0
2444  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2445  if (Val < 0) Val = -Val;
2446  Val = ARM_AM::getAM3Opc(AddSub, Val);
2447  } else {
2448  // For register offset, we encode the shift type and negation flag
2449  // here.
2450  Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2451  }
2452  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2453  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2454  Inst.addOperand(MCOperand::createImm(Val));
2455  }
2456 
2457  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2458  assert(N == 2 && "Invalid number of operands!");
2459  if (Kind == k_PostIndexRegister) {
2460  int32_t Val =
2461  ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2462  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2463  Inst.addOperand(MCOperand::createImm(Val));
2464  return;
2465  }
2466 
2467  // Constant offset.
2468  const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2469  int32_t Val = CE->getValue();
2470  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2471  // Special case for #-0
2472  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2473  if (Val < 0) Val = -Val;
2474  Val = ARM_AM::getAM3Opc(AddSub, Val);
2476  Inst.addOperand(MCOperand::createImm(Val));
2477  }
2478 
2479  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2480  assert(N == 2 && "Invalid number of operands!");
2481  // If we have an immediate that's not a constant, treat it as a label
2482  // reference needing a fixup. If it is a constant, it's something else
2483  // and we reject it.
2484  if (isImm()) {
2485  Inst.addOperand(MCOperand::createExpr(getImm()));
2487  return;
2488  }
2489 
2490  // The lower two bits are always zero and as such are not encoded.
2491  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2492  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2493  // Special case for #-0
2494  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2495  if (Val < 0) Val = -Val;
2496  Val = ARM_AM::getAM5Opc(AddSub, Val);
2497  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2498  Inst.addOperand(MCOperand::createImm(Val));
2499  }
2500 
2501  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2502  assert(N == 2 && "Invalid number of operands!");
2503  // If we have an immediate that's not a constant, treat it as a label
2504  // reference needing a fixup. If it is a constant, it's something else
2505  // and we reject it.
2506  if (isImm()) {
2507  Inst.addOperand(MCOperand::createExpr(getImm()));
2509  return;
2510  }
2511 
2512  // The lower bit is always zero and as such is not encoded.
2513  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2514  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2515  // Special case for #-0
2516  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2517  if (Val < 0) Val = -Val;
2518  Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2519  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2520  Inst.addOperand(MCOperand::createImm(Val));
2521  }
2522 
2523  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2524  assert(N == 2 && "Invalid number of operands!");
2525  // If we have an immediate that's not a constant, treat it as a label
2526  // reference needing a fixup. If it is a constant, it's something else
2527  // and we reject it.
2528  if (isImm()) {
2529  Inst.addOperand(MCOperand::createExpr(getImm()));
2531  return;
2532  }
2533 
2534  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2535  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2536  Inst.addOperand(MCOperand::createImm(Val));
2537  }
2538 
2539  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2540  assert(N == 2 && "Invalid number of operands!");
2541  // The lower two bits are always zero and as such are not encoded.
2542  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2543  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2544  Inst.addOperand(MCOperand::createImm(Val));
2545  }
2546 
2547  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2548  assert(N == 2 && "Invalid number of operands!");
2549  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2550  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2551  Inst.addOperand(MCOperand::createImm(Val));
2552  }
2553 
2554  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2555  addMemImm8OffsetOperands(Inst, N);
2556  }
2557 
2558  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2559  addMemImm8OffsetOperands(Inst, N);
2560  }
2561 
2562  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2563  assert(N == 2 && "Invalid number of operands!");
2564  // If this is an immediate, it's a label reference.
2565  if (isImm()) {
2566  addExpr(Inst, getImm());
2568  return;
2569  }
2570 
2571  // Otherwise, it's a normal memory reg+offset.
2572  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2573  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2574  Inst.addOperand(MCOperand::createImm(Val));
2575  }
2576 
2577  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2578  assert(N == 2 && "Invalid number of operands!");
2579  // If this is an immediate, it's a label reference.
2580  if (isImm()) {
2581  addExpr(Inst, getImm());
2583  return;
2584  }
2585 
2586  // Otherwise, it's a normal memory reg+offset.
2587  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2588  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2589  Inst.addOperand(MCOperand::createImm(Val));
2590  }
2591 
2592  void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2593  assert(N == 1 && "Invalid number of operands!");
2594  // This is container for the immediate that we will create the constant
2595  // pool from
2596  addExpr(Inst, getConstantPoolImm());
2597  return;
2598  }
2599 
2600  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2601  assert(N == 2 && "Invalid number of operands!");
2602  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2603  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2604  }
2605 
2606  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2607  assert(N == 2 && "Invalid number of operands!");
2608  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2609  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2610  }
2611 
2612  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2613  assert(N == 3 && "Invalid number of operands!");
2614  unsigned Val =
2616  Memory.ShiftImm, Memory.ShiftType);
2617  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2618  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2619  Inst.addOperand(MCOperand::createImm(Val));
2620  }
2621 
2622  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2623  assert(N == 3 && "Invalid number of operands!");
2624  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2625  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2626  Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2627  }
2628 
2629  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2630  assert(N == 2 && "Invalid number of operands!");
2631  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2632  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2633  }
2634 
2635  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2636  assert(N == 2 && "Invalid number of operands!");
2637  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2638  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2639  Inst.addOperand(MCOperand::createImm(Val));
2640  }
2641 
2642  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2643  assert(N == 2 && "Invalid number of operands!");
2644  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2645  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2646  Inst.addOperand(MCOperand::createImm(Val));
2647  }
2648 
2649  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2650  assert(N == 2 && "Invalid number of operands!");
2651  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2652  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2653  Inst.addOperand(MCOperand::createImm(Val));
2654  }
2655 
2656  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2657  assert(N == 2 && "Invalid number of operands!");
2658  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2659  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2660  Inst.addOperand(MCOperand::createImm(Val));
2661  }
2662 
2663  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2664  assert(N == 1 && "Invalid number of operands!");
2665  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2666  assert(CE && "non-constant post-idx-imm8 operand!");
2667  int Imm = CE->getValue();
2668  bool isAdd = Imm >= 0;
2669  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2670  Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2671  Inst.addOperand(MCOperand::createImm(Imm));
2672  }
2673 
2674  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2675  assert(N == 1 && "Invalid number of operands!");
2676  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2677  assert(CE && "non-constant post-idx-imm8s4 operand!");
2678  int Imm = CE->getValue();
2679  bool isAdd = Imm >= 0;
2680  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2681  // Immediate is scaled by 4.
2682  Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2683  Inst.addOperand(MCOperand::createImm(Imm));
2684  }
2685 
2686  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2687  assert(N == 2 && "Invalid number of operands!");
2688  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2689  Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2690  }
2691 
2692  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2693  assert(N == 2 && "Invalid number of operands!");
2694  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2695  // The sign, shift type, and shift amount are encoded in a single operand
2696  // using the AM2 encoding helpers.
2697  ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2698  unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2699  PostIdxReg.ShiftTy);
2700  Inst.addOperand(MCOperand::createImm(Imm));
2701  }
2702 
2703  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2704  assert(N == 1 && "Invalid number of operands!");
2705  Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2706  }
2707 
2708  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2709  assert(N == 1 && "Invalid number of operands!");
2710  Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2711  }
2712 
2713  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2714  assert(N == 1 && "Invalid number of operands!");
2715  Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2716  }
2717 
2718  void addVecListOperands(MCInst &Inst, unsigned N) const {
2719  assert(N == 1 && "Invalid number of operands!");
2720  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2721  }
2722 
2723  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2724  assert(N == 2 && "Invalid number of operands!");
2725  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2726  Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2727  }
2728 
2729  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2730  assert(N == 1 && "Invalid number of operands!");
2731  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2732  }
2733 
2734  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2735  assert(N == 1 && "Invalid number of operands!");
2736  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2737  }
2738 
2739  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2740  assert(N == 1 && "Invalid number of operands!");
2741  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2742  }
2743 
2744  void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
2745  assert(N == 1 && "Invalid number of operands!");
2746  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2747  }
2748 
2749  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2750  assert(N == 1 && "Invalid number of operands!");
2751  // The immediate encodes the type of constant as well as the value.
2752  // Mask in that this is an i8 splat.
2753  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2754  Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2755  }
2756 
2757  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2758  assert(N == 1 && "Invalid number of operands!");
2759  // The immediate encodes the type of constant as well as the value.
2760  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2761  unsigned Value = CE->getValue();
2762  Value = ARM_AM::encodeNEONi16splat(Value);
2763  Inst.addOperand(MCOperand::createImm(Value));
2764  }
2765 
2766  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2767  assert(N == 1 && "Invalid number of operands!");
2768  // The immediate encodes the type of constant as well as the value.
2769  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2770  unsigned Value = CE->getValue();
2771  Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2772  Inst.addOperand(MCOperand::createImm(Value));
2773  }
2774 
2775  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2776  assert(N == 1 && "Invalid number of operands!");
2777  // The immediate encodes the type of constant as well as the value.
2778  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2779  unsigned Value = CE->getValue();
2780  Value = ARM_AM::encodeNEONi32splat(Value);
2781  Inst.addOperand(MCOperand::createImm(Value));
2782  }
2783 
2784  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2785  assert(N == 1 && "Invalid number of operands!");
2786  // The immediate encodes the type of constant as well as the value.
2787  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2788  unsigned Value = CE->getValue();
2789  Value = ARM_AM::encodeNEONi32splat(~Value);
2790  Inst.addOperand(MCOperand::createImm(Value));
2791  }
2792 
2793  void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
2794  // The immediate encodes the type of constant as well as the value.
2795  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2796  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2797  Inst.getOpcode() == ARM::VMOVv16i8) &&
2798  "All instructions that wants to replicate non-zero byte "
2799  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2800  unsigned Value = CE->getValue();
2801  if (Inv)
2802  Value = ~Value;
2803  unsigned B = Value & 0xff;
2804  B |= 0xe00; // cmode = 0b1110
2806  }
2807 
2808  void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2809  assert(N == 1 && "Invalid number of operands!");
2810  addNEONi8ReplicateOperands(Inst, true);
2811  }
2812 
2813  static unsigned encodeNeonVMOVImmediate(unsigned Value) {
2814  if (Value >= 256 && Value <= 0xffff)
2815  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2816  else if (Value > 0xffff && Value <= 0xffffff)
2817  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2818  else if (Value > 0xffffff)
2819  Value = (Value >> 24) | 0x600;
2820  return Value;
2821  }
2822 
2823  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2824  assert(N == 1 && "Invalid number of operands!");
2825  // The immediate encodes the type of constant as well as the value.
2826  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2827  unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
2828  Inst.addOperand(MCOperand::createImm(Value));
2829  }
2830 
2831  void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2832  assert(N == 1 && "Invalid number of operands!");
2833  addNEONi8ReplicateOperands(Inst, false);
2834  }
2835 
2836  void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
2837  assert(N == 1 && "Invalid number of operands!");
2838  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2839  assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
2840  Inst.getOpcode() == ARM::VMOVv8i16 ||
2841  Inst.getOpcode() == ARM::VMVNv4i16 ||
2842  Inst.getOpcode() == ARM::VMVNv8i16) &&
2843  "All instructions that want to replicate non-zero half-word "
2844  "always must be replaced with V{MOV,MVN}v{4,8}i16.");
2845  uint64_t Value = CE->getValue();
2846  unsigned Elem = Value & 0xffff;
2847  if (Elem >= 256)
2848  Elem = (Elem >> 8) | 0x200;
2849  Inst.addOperand(MCOperand::createImm(Elem));
2850  }
2851 
2852  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2853  assert(N == 1 && "Invalid number of operands!");
2854  // The immediate encodes the type of constant as well as the value.
2855  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2856  unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
2857  Inst.addOperand(MCOperand::createImm(Value));
2858  }
2859 
2860  void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
2861  assert(N == 1 && "Invalid number of operands!");
2862  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2863  assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
2864  Inst.getOpcode() == ARM::VMOVv4i32 ||
2865  Inst.getOpcode() == ARM::VMVNv2i32 ||
2866  Inst.getOpcode() == ARM::VMVNv4i32) &&
2867  "All instructions that want to replicate non-zero word "
2868  "always must be replaced with V{MOV,MVN}v{2,4}i32.");
2869  uint64_t Value = CE->getValue();
2870  unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
2871  Inst.addOperand(MCOperand::createImm(Elem));
2872  }
2873 
2874  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2875  assert(N == 1 && "Invalid number of operands!");
2876  // The immediate encodes the type of constant as well as the value.
2877  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2878  uint64_t Value = CE->getValue();
2879  unsigned Imm = 0;
2880  for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2881  Imm |= (Value & 1) << i;
2882  }
2883  Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2884  }
2885 
2886  void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
2887  assert(N == 1 && "Invalid number of operands!");
2888  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2889  Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
2890  }
2891 
2892  void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
2893  assert(N == 1 && "Invalid number of operands!");
2894  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2895  Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
2896  }
2897 
2898  void print(raw_ostream &OS) const override;
2899 
2900  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2901  auto Op = make_unique<ARMOperand>(k_ITCondMask);
2902  Op->ITMask.Mask = Mask;
2903  Op->StartLoc = S;
2904  Op->EndLoc = S;
2905  return Op;
2906  }
2907 
2908  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2909  SMLoc S) {
2910  auto Op = make_unique<ARMOperand>(k_CondCode);
2911  Op->CC.Val = CC;
2912  Op->StartLoc = S;
2913  Op->EndLoc = S;
2914  return Op;
2915  }
2916 
2917  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2918  auto Op = make_unique<ARMOperand>(k_CoprocNum);
2919  Op->Cop.Val = CopVal;
2920  Op->StartLoc = S;
2921  Op->EndLoc = S;
2922  return Op;
2923  }
2924 
2925  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2926  auto Op = make_unique<ARMOperand>(k_CoprocReg);
2927  Op->Cop.Val = CopVal;
2928  Op->StartLoc = S;
2929  Op->EndLoc = S;
2930  return Op;
2931  }
2932 
2933  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2934  SMLoc E) {
2935  auto Op = make_unique<ARMOperand>(k_CoprocOption);
2936  Op->Cop.Val = Val;
2937  Op->StartLoc = S;
2938  Op->EndLoc = E;
2939  return Op;
2940  }
2941 
2942  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2943  auto Op = make_unique<ARMOperand>(k_CCOut);
2944  Op->Reg.RegNum = RegNum;
2945  Op->StartLoc = S;
2946  Op->EndLoc = S;
2947  return Op;
2948  }
2949 
2950  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2951  auto Op = make_unique<ARMOperand>(k_Token);
2952  Op->Tok.Data = Str.data();
2953  Op->Tok.Length = Str.size();
2954  Op->StartLoc = S;
2955  Op->EndLoc = S;
2956  return Op;
2957  }
2958 
2959  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2960  SMLoc E) {
2961  auto Op = make_unique<ARMOperand>(k_Register);
2962  Op->Reg.RegNum = RegNum;
2963  Op->StartLoc = S;
2964  Op->EndLoc = E;
2965  return Op;
2966  }
2967 
2968  static std::unique_ptr<ARMOperand>
2969  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2970  unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2971  SMLoc E) {
2972  auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2973  Op->RegShiftedReg.ShiftTy = ShTy;
2974  Op->RegShiftedReg.SrcReg = SrcReg;
2975  Op->RegShiftedReg.ShiftReg = ShiftReg;
2976  Op->RegShiftedReg.ShiftImm = ShiftImm;
2977  Op->StartLoc = S;
2978  Op->EndLoc = E;
2979  return Op;
2980  }
2981 
2982  static std::unique_ptr<ARMOperand>
2983  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2984  unsigned ShiftImm, SMLoc S, SMLoc E) {
2985  auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2986  Op->RegShiftedImm.ShiftTy = ShTy;
2987  Op->RegShiftedImm.SrcReg = SrcReg;
2988  Op->RegShiftedImm.ShiftImm = ShiftImm;
2989  Op->StartLoc = S;
2990  Op->EndLoc = E;
2991  return Op;
2992  }
2993 
2994  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2995  SMLoc S, SMLoc E) {
2996  auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2997  Op->ShifterImm.isASR = isASR;
2998  Op->ShifterImm.Imm = Imm;
2999  Op->StartLoc = S;
3000  Op->EndLoc = E;
3001  return Op;
3002  }
3003 
3004  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3005  SMLoc E) {
3006  auto Op = make_unique<ARMOperand>(k_RotateImmediate);
3007  Op->RotImm.Imm = Imm;
3008  Op->StartLoc = S;
3009  Op->EndLoc = E;
3010  return Op;
3011  }
3012 
3013  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3014  SMLoc S, SMLoc E) {
3015  auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
3016  Op->ModImm.Bits = Bits;
3017  Op->ModImm.Rot = Rot;
3018  Op->StartLoc = S;
3019  Op->EndLoc = E;
3020  return Op;
3021  }
3022 
3023  static std::unique_ptr<ARMOperand>
3024  CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3025  auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
3026  Op->Imm.Val = Val;
3027  Op->StartLoc = S;
3028  Op->EndLoc = E;
3029  return Op;
3030  }
3031 
3032  static std::unique_ptr<ARMOperand>
3033  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3034  auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
3035  Op->Bitfield.LSB = LSB;
3036  Op->Bitfield.Width = Width;
3037  Op->StartLoc = S;
3038  Op->EndLoc = E;
3039  return Op;
3040  }
3041 
3042  static std::unique_ptr<ARMOperand>
3043  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3044  SMLoc StartLoc, SMLoc EndLoc) {
3045  assert(Regs.size() > 0 && "RegList contains no registers?");
3046  KindTy Kind = k_RegisterList;
3047 
3048  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
3049  Kind = k_DPRRegisterList;
3050  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
3051  contains(Regs.front().second))
3052  Kind = k_SPRRegisterList;
3053 
3054  // Sort based on the register encoding values.
3055  array_pod_sort(Regs.begin(), Regs.end());
3056 
3057  auto Op = make_unique<ARMOperand>(Kind);
3058  for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
3059  I = Regs.begin(), E = Regs.end(); I != E; ++I)
3060  Op->Registers.push_back(I->second);
3061  Op->StartLoc = StartLoc;
3062  Op->EndLoc = EndLoc;
3063  return Op;
3064  }
3065 
3066  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3067  unsigned Count,
3068  bool isDoubleSpaced,
3069  SMLoc S, SMLoc E) {
3070  auto Op = make_unique<ARMOperand>(k_VectorList);
3071  Op->VectorList.RegNum = RegNum;
3072  Op->VectorList.Count = Count;
3073  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3074  Op->StartLoc = S;
3075  Op->EndLoc = E;
3076  return Op;
3077  }
3078 
3079  static std::unique_ptr<ARMOperand>
3080  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3081  SMLoc S, SMLoc E) {
3082  auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
3083  Op->VectorList.RegNum = RegNum;
3084  Op->VectorList.Count = Count;
3085  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3086  Op->StartLoc = S;
3087  Op->EndLoc = E;
3088  return Op;
3089  }
3090 
3091  static std::unique_ptr<ARMOperand>
3092  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3093  bool isDoubleSpaced, SMLoc S, SMLoc E) {
3094  auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
3095  Op->VectorList.RegNum = RegNum;
3096  Op->VectorList.Count = Count;
3097  Op->VectorList.LaneIndex = Index;
3098  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3099  Op->StartLoc = S;
3100  Op->EndLoc = E;
3101  return Op;
3102  }
3103 
3104  static std::unique_ptr<ARMOperand>
3105  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3106  auto Op = make_unique<ARMOperand>(k_VectorIndex);
3107  Op->VectorIndex.Val = Idx;
3108  Op->StartLoc = S;
3109  Op->EndLoc = E;
3110  return Op;
3111  }
3112 
3113  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3114  SMLoc E) {
3115  auto Op = make_unique<ARMOperand>(k_Immediate);
3116  Op->Imm.Val = Val;
3117  Op->StartLoc = S;
3118  Op->EndLoc = E;
3119  return Op;
3120  }
3121 
3122  static std::unique_ptr<ARMOperand>
3123  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3124  unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3125  unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3126  SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3127  auto Op = make_unique<ARMOperand>(k_Memory);
3128  Op->Memory.BaseRegNum = BaseRegNum;
3129  Op->Memory.OffsetImm = OffsetImm;
3130  Op->Memory.OffsetRegNum = OffsetRegNum;
3131  Op->Memory.ShiftType = ShiftType;
3132  Op->Memory.ShiftImm = ShiftImm;
3133  Op->Memory.Alignment = Alignment;
3134  Op->Memory.isNegative = isNegative;
3135  Op->StartLoc = S;
3136  Op->EndLoc = E;
3137  Op->AlignmentLoc = AlignmentLoc;
3138  return Op;
3139  }
3140 
3141  static std::unique_ptr<ARMOperand>
3142  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3143  unsigned ShiftImm, SMLoc S, SMLoc E) {
3144  auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3145  Op->PostIdxReg.RegNum = RegNum;
3146  Op->PostIdxReg.isAdd = isAdd;
3147  Op->PostIdxReg.ShiftTy = ShiftTy;
3148  Op->PostIdxReg.ShiftImm = ShiftImm;
3149  Op->StartLoc = S;
3150  Op->EndLoc = E;
3151  return Op;
3152  }
3153 
3154  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3155  SMLoc S) {
3156  auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3157  Op->MBOpt.Val = Opt;
3158  Op->StartLoc = S;
3159  Op->EndLoc = S;
3160  return Op;
3161  }
3162 
3163  static std::unique_ptr<ARMOperand>
3164  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3165  auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3166  Op->ISBOpt.Val = Opt;
3167  Op->StartLoc = S;
3168  Op->EndLoc = S;
3169  return Op;
3170  }
3171 
3172  static std::unique_ptr<ARMOperand>
3173  CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3174  auto Op = make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3175  Op->TSBOpt.Val = Opt;
3176  Op->StartLoc = S;
3177  Op->EndLoc = S;
3178  return Op;
3179  }
3180 
3181  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3182  SMLoc S) {
3183  auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3184  Op->IFlags.Val = IFlags;
3185  Op->StartLoc = S;
3186  Op->EndLoc = S;
3187  return Op;
3188  }
3189 
3190  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3191  auto Op = make_unique<ARMOperand>(k_MSRMask);
3192  Op->MMask.Val = MMask;
3193  Op->StartLoc = S;
3194  Op->EndLoc = S;
3195  return Op;
3196  }
3197 
3198  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3199  auto Op = make_unique<ARMOperand>(k_BankedReg);
3200  Op->BankedReg.Val = Reg;
3201  Op->StartLoc = S;
3202  Op->EndLoc = S;
3203  return Op;
3204  }
3205 };
3206 
3207 } // end anonymous namespace.
3208 
3209 void ARMOperand::print(raw_ostream &OS) const {
3210  auto RegName = [](unsigned Reg) {
3211  if (Reg)
3213  else
3214  return "noreg";
3215  };
3216 
3217  switch (Kind) {
3218  case k_CondCode:
3219  OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3220  break;
3221  case k_CCOut:
3222  OS << "<ccout " << RegName(getReg()) << ">";
3223  break;
3224  case k_ITCondMask: {
3225  static const char *const MaskStr[] = {
3226  "(invalid)", "(teee)", "(tee)", "(teet)",
3227  "(te)", "(tete)", "(tet)", "(tett)",
3228  "(t)", "(ttee)", "(tte)", "(ttet)",
3229  "(tt)", "(ttte)", "(ttt)", "(tttt)"
3230  };
3231  assert((ITMask.Mask & 0xf) == ITMask.Mask);
3232  OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3233  break;
3234  }
3235  case k_CoprocNum:
3236  OS << "<coprocessor number: " << getCoproc() << ">";
3237  break;
3238  case k_CoprocReg:
3239  OS << "<coprocessor register: " << getCoproc() << ">";
3240  break;
3241  case k_CoprocOption:
3242  OS << "<coprocessor option: " << CoprocOption.Val << ">";
3243  break;
3244  case k_MSRMask:
3245  OS << "<mask: " << getMSRMask() << ">";
3246  break;
3247  case k_BankedReg:
3248  OS << "<banked reg: " << getBankedReg() << ">";
3249  break;
3250  case k_Immediate:
3251  OS << *getImm();
3252  break;
3253  case k_MemBarrierOpt:
3254  OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3255  break;
3256  case k_InstSyncBarrierOpt:
3257  OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3258  break;
3259  case k_TraceSyncBarrierOpt:
3260  OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3261  break;
3262  case k_Memory:
3263  OS << "<memory";
3264  if (Memory.BaseRegNum)
3265  OS << " base:" << RegName(Memory.BaseRegNum);
3266  if (Memory.OffsetImm)
3267  OS << " offset-imm:" << *Memory.OffsetImm;
3268  if (Memory.OffsetRegNum)
3269  OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3270  << RegName(Memory.OffsetRegNum);
3271  if (Memory.ShiftType != ARM_AM::no_shift) {
3272  OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3273  OS << " shift-imm:" << Memory.ShiftImm;
3274  }
3275  if (Memory.Alignment)
3276  OS << " alignment:" << Memory.Alignment;
3277  OS << ">";
3278  break;
3279  case k_PostIndexRegister:
3280  OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3281  << RegName(PostIdxReg.RegNum);
3282  if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3283  OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3284  << PostIdxReg.ShiftImm;
3285  OS << ">";
3286  break;
3287  case k_ProcIFlags: {
3288  OS << "<ARM_PROC::";
3289  unsigned IFlags = getProcIFlags();
3290  for (int i=2; i >= 0; --i)
3291  if (IFlags & (1 << i))
3292  OS << ARM_PROC::IFlagsToString(1 << i);
3293  OS << ">";
3294  break;
3295  }
3296  case k_Register:
3297  OS << "<register " << RegName(getReg()) << ">";
3298  break;
3299  case k_ShifterImmediate:
3300  OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3301  << " #" << ShifterImm.Imm << ">";
3302  break;
3303  case k_ShiftedRegister:
3304  OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3305  << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3306  << RegName(RegShiftedReg.ShiftReg) << ">";
3307  break;
3308  case k_ShiftedImmediate:
3309  OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3310  << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3311  << RegShiftedImm.ShiftImm << ">";
3312  break;
3313  case k_RotateImmediate:
3314  OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3315  break;
3316  case k_ModifiedImmediate:
3317  OS << "<mod_imm #" << ModImm.Bits << ", #"
3318  << ModImm.Rot << ")>";
3319  break;
3320  case k_ConstantPoolImmediate:
3321  OS << "<constant_pool_imm #" << *getConstantPoolImm();
3322  break;
3323  case k_BitfieldDescriptor:
3324  OS << "<bitfield " << "lsb: " << Bitfield.LSB
3325  << ", width: " << Bitfield.Width << ">";
3326  break;
3327  case k_RegisterList:
3328  case k_DPRRegisterList:
3329  case k_SPRRegisterList: {
3330  OS << "<register_list ";
3331 
3332  const SmallVectorImpl<unsigned> &RegList = getRegList();
3334  I = RegList.begin(), E = RegList.end(); I != E; ) {
3335  OS << RegName(*I);
3336  if (++I < E) OS << ", ";
3337  }
3338 
3339  OS << ">";
3340  break;
3341  }
3342  case k_VectorList:
3343  OS << "<vector_list " << VectorList.Count << " * "
3344  << RegName(VectorList.RegNum) << ">";
3345  break;
3346  case k_VectorListAllLanes:
3347  OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3348  << RegName(VectorList.RegNum) << ">";
3349  break;
3350  case k_VectorListIndexed:
3351  OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3352  << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3353  break;
3354  case k_Token:
3355  OS << "'" << getToken() << "'";
3356  break;
3357  case k_VectorIndex:
3358  OS << "<vectorindex " << getVectorIndex() << ">";
3359  break;
3360  }
3361 }
3362 
3363 /// @name Auto-generated Match Functions
3364 /// {
3365 
3366 static unsigned MatchRegisterName(StringRef Name);
3367 
3368 /// }
3369 
3370 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3371  SMLoc &StartLoc, SMLoc &EndLoc) {
3372  const AsmToken &Tok = getParser().getTok();
3373  StartLoc = Tok.getLoc();
3374  EndLoc = Tok.getEndLoc();
3375  RegNo = tryParseRegister();
3376 
3377  return (RegNo == (unsigned)-1);
3378 }
3379 
3380 /// Try to parse a register name. The token must be an Identifier when called,
3381 /// and if it is a register name the token is eaten and the register number is
3382 /// returned. Otherwise return -1.
3383 int ARMAsmParser::tryParseRegister() {
3384  MCAsmParser &Parser = getParser();
3385  const AsmToken &Tok = Parser.getTok();
3386  if (Tok.isNot(AsmToken::Identifier)) return -1;
3387 
3388  std::string lowerCase = Tok.getString().lower();
3389  unsigned RegNum = MatchRegisterName(lowerCase);
3390  if (!RegNum) {
3391  RegNum = StringSwitch<unsigned>(lowerCase)
3392  .Case("r13", ARM::SP)
3393  .Case("r14", ARM::LR)
3394  .Case("r15", ARM::PC)
3395  .Case("ip", ARM::R12)
3396  // Additional register name aliases for 'gas' compatibility.
3397  .Case("a1", ARM::R0)
3398  .Case("a2", ARM::R1)
3399  .Case("a3", ARM::R2)
3400  .Case("a4", ARM::R3)
3401  .Case("v1", ARM::R4)
3402  .Case("v2", ARM::R5)
3403  .Case("v3", ARM::R6)
3404  .Case("v4", ARM::R7)
3405  .Case("v5", ARM::R8)
3406  .Case("v6", ARM::R9)
3407  .Case("v7", ARM::R10)
3408  .Case("v8", ARM::R11)
3409  .Case("sb", ARM::R9)
3410  .Case("sl", ARM::R10)
3411  .Case("fp", ARM::R11)
3412  .Default(0);
3413  }
3414  if (!RegNum) {
3415  // Check for aliases registered via .req. Canonicalize to lower case.
3416  // That's more consistent since register names are case insensitive, and
3417  // it's how the original entry was passed in from MC/MCParser/AsmParser.
3418  StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3419  // If no match, return failure.
3420  if (Entry == RegisterReqs.end())
3421  return -1;
3422  Parser.Lex(); // Eat identifier token.
3423  return Entry->getValue();
3424  }
3425 
3426  // Some FPUs only have 16 D registers, so D16-D31 are invalid
3427  if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3428  return -1;
3429 
3430  Parser.Lex(); // Eat identifier token.
3431 
3432  return RegNum;
3433 }
3434 
3435 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3436 // If a recoverable error occurs, return 1. If an irrecoverable error
3437 // occurs, return -1. An irrecoverable error is one where tokens have been
3438 // consumed in the process of trying to parse the shifter (i.e., when it is
3439 // indeed a shifter operand, but malformed).
3440 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3441  MCAsmParser &Parser = getParser();
3442  SMLoc S = Parser.getTok().getLoc();
3443  const AsmToken &Tok = Parser.getTok();
3444  if (Tok.isNot(AsmToken::Identifier))
3445  return -1;
3446 
3447  std::string lowerCase = Tok.getString().lower();
3449  .Case("asl", ARM_AM::lsl)
3450  .Case("lsl", ARM_AM::lsl)
3451  .Case("lsr", ARM_AM::lsr)
3452  .Case("asr", ARM_AM::asr)
3453  .Case("ror", ARM_AM::ror)
3454  .Case("rrx", ARM_AM::rrx)
3456 
3457  if (ShiftTy == ARM_AM::no_shift)
3458  return 1;
3459 
3460  Parser.Lex(); // Eat the operator.
3461 
3462  // The source register for the shift has already been added to the
3463  // operand list, so we need to pop it off and combine it into the shifted
3464  // register operand instead.
3465  std::unique_ptr<ARMOperand> PrevOp(
3466  (ARMOperand *)Operands.pop_back_val().release());
3467  if (!PrevOp->isReg())
3468  return Error(PrevOp->getStartLoc(), "shift must be of a register");
3469  int SrcReg = PrevOp->getReg();
3470 
3471  SMLoc EndLoc;
3472  int64_t Imm = 0;
3473  int ShiftReg = 0;
3474  if (ShiftTy == ARM_AM::rrx) {
3475  // RRX Doesn't have an explicit shift amount. The encoder expects
3476  // the shift register to be the same as the source register. Seems odd,
3477  // but OK.
3478  ShiftReg = SrcReg;
3479  } else {
3480  // Figure out if this is shifted by a constant or a register (for non-RRX).
3481  if (Parser.getTok().is(AsmToken::Hash) ||
3482  Parser.getTok().is(AsmToken::Dollar)) {
3483  Parser.Lex(); // Eat hash.
3484  SMLoc ImmLoc = Parser.getTok().getLoc();
3485  const MCExpr *ShiftExpr = nullptr;
3486  if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3487  Error(ImmLoc, "invalid immediate shift value");
3488  return -1;
3489  }
3490  // The expression must be evaluatable as an immediate.
3491  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3492  if (!CE) {
3493  Error(ImmLoc, "invalid immediate shift value");
3494  return -1;
3495  }
3496  // Range check the immediate.
3497  // lsl, ror: 0 <= imm <= 31
3498  // lsr, asr: 0 <= imm <= 32
3499  Imm = CE->getValue();
3500  if (Imm < 0 ||
3501  ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3502  ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3503  Error(ImmLoc, "immediate shift value out of range");
3504  return -1;
3505  }
3506  // shift by zero is a nop. Always send it through as lsl.
3507  // ('as' compatibility)
3508  if (Imm == 0)
3509  ShiftTy = ARM_AM::lsl;
3510  } else if (Parser.getTok().is(AsmToken::Identifier)) {
3511  SMLoc L = Parser.getTok().getLoc();
3512  EndLoc = Parser.getTok().getEndLoc();
3513  ShiftReg = tryParseRegister();
3514  if (ShiftReg == -1) {
3515  Error(L, "expected immediate or register in shift operand");
3516  return -1;
3517  }
3518  } else {
3519  Error(Parser.getTok().getLoc(),
3520  "expected immediate or register in shift operand");
3521  return -1;
3522  }
3523  }
3524 
3525  if (ShiftReg && ShiftTy != ARM_AM::rrx)
3526  Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3527  ShiftReg, Imm,
3528  S, EndLoc));
3529  else
3530  Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3531  S, EndLoc));
3532 
3533  return 0;
3534 }
3535 
3536 /// Try to parse a register name. The token must be an Identifier when called.
3537 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3538 /// if there is a "writeback". 'true' if it's not a register.
3539 ///
3540 /// TODO this is likely to change to allow different register types and or to
3541 /// parse for a specific register type.
3542 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3543  MCAsmParser &Parser = getParser();
3544  SMLoc RegStartLoc = Parser.getTok().getLoc();
3545  SMLoc RegEndLoc = Parser.getTok().getEndLoc();
3546  int RegNo = tryParseRegister();
3547  if (RegNo == -1)
3548  return true;
3549 
3550  Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
3551 
3552  const AsmToken &ExclaimTok = Parser.getTok();
3553  if (ExclaimTok.is(AsmToken::Exclaim)) {
3554  Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3555  ExclaimTok.getLoc()));
3556  Parser.Lex(); // Eat exclaim token
3557  return false;
3558  }
3559 
3560  // Also check for an index operand. This is only legal for vector registers,
3561  // but that'll get caught OK in operand matching, so we don't need to
3562  // explicitly filter everything else out here.
3563  if (Parser.getTok().is(AsmToken::LBrac)) {
3564  SMLoc SIdx = Parser.getTok().getLoc();
3565  Parser.Lex(); // Eat left bracket token.
3566 
3567  const MCExpr *ImmVal;
3568  if (getParser().parseExpression(ImmVal))
3569  return true;
3570  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3571  if (!MCE)
3572  return TokError("immediate value expected for vector index");
3573 
3574  if (Parser.getTok().isNot(AsmToken::RBrac))
3575  return Error(Parser.getTok().getLoc(), "']' expected");
3576 
3577  SMLoc E = Parser.getTok().getEndLoc();
3578  Parser.Lex(); // Eat right bracket token.
3579 
3580  Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3581  SIdx, E,
3582  getContext()));
3583  }
3584 
3585  return false;
3586 }
3587 
3588 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3589 /// instruction with a symbolic operand name.
3590 /// We accept "crN" syntax for GAS compatibility.
3591 /// <operand-name> ::= <prefix><number>
3592 /// If CoprocOp is 'c', then:
3593 /// <prefix> ::= c | cr
3594 /// If CoprocOp is 'p', then :
3595 /// <prefix> ::= p
3596 /// <number> ::= integer in range [0, 15]
3597 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3598  // Use the same layout as the tablegen'erated register name matcher. Ugly,
3599  // but efficient.
3600  if (Name.size() < 2 || Name[0] != CoprocOp)
3601  return -1;
3602  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3603 
3604  switch (Name.size()) {
3605  default: return -1;
3606  case 1:
3607  switch (Name[0]) {
3608  default: return -1;
3609  case '0': return 0;
3610  case '1': return 1;
3611  case '2': return 2;
3612  case '3': return 3;
3613  case '4': return 4;
3614  case '5': return 5;
3615  case '6': return 6;
3616  case '7': return 7;
3617  case '8': return 8;
3618  case '9': return 9;
3619  }
3620  case 2:
3621  if (Name[0] != '1')
3622  return -1;
3623  switch (Name[1]) {
3624  default: return -1;
3625  // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3626  // However, old cores (v5/v6) did use them in that way.
3627  case '0': return 10;
3628  case '1': return 11;
3629  case '2': return 12;
3630  case '3': return 13;
3631  case '4': return 14;
3632  case '5': return 15;
3633  }
3634  }
3635 }
3636 
3637 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3639 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3640  MCAsmParser &Parser = getParser();
3641  SMLoc S = Parser.getTok().getLoc();
3642  const AsmToken &Tok = Parser.getTok();
3643  if (!Tok.is(AsmToken::Identifier))
3644  return MatchOperand_NoMatch;
3645  unsigned CC = ARMCondCodeFromString(Tok.getString());
3646  if (CC == ~0U)
3647  return MatchOperand_NoMatch;
3648  Parser.Lex(); // Eat the token.
3649 
3650  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3651 
3652  return MatchOperand_Success;
3653 }
3654 
3655 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3656 /// token must be an Identifier when called, and if it is a coprocessor
3657 /// number, the token is eaten and the operand is added to the operand list.
3659 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3660  MCAsmParser &Parser = getParser();
3661  SMLoc S = Parser.getTok().getLoc();
3662  const AsmToken &Tok = Parser.getTok();
3663  if (Tok.isNot(AsmToken::Identifier))
3664  return MatchOperand_NoMatch;
3665 
3666  int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
3667  if (Num == -1)
3668  return MatchOperand_NoMatch;
3669  // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3670  if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3671  return MatchOperand_NoMatch;
3672 
3673  Parser.Lex(); // Eat identifier token.
3674  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3675  return MatchOperand_Success;
3676 }
3677 
3678 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3679 /// token must be an Identifier when called, and if it is a coprocessor
3680 /// number, the token is eaten and the operand is added to the operand list.
3682 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3683  MCAsmParser &Parser = getParser();
3684  SMLoc S = Parser.getTok().getLoc();
3685  const AsmToken &Tok = Parser.getTok();
3686  if (Tok.isNot(AsmToken::Identifier))
3687  return MatchOperand_NoMatch;
3688 
3689  int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
3690  if (Reg == -1)
3691  return MatchOperand_NoMatch;
3692 
3693  Parser.Lex(); // Eat identifier token.
3694  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3695  return MatchOperand_Success;
3696 }
3697 
3698 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3699 /// coproc_option : '{' imm0_255 '}'
3701 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3702  MCAsmParser &Parser = getParser();
3703  SMLoc S = Parser.getTok().getLoc();
3704 
3705  // If this isn't a '{', this isn't a coprocessor immediate operand.
3706  if (Parser.getTok().isNot(AsmToken::LCurly))
3707  return MatchOperand_NoMatch;
3708  Parser.Lex(); // Eat the '{'
3709 
3710  const MCExpr *Expr;
3711  SMLoc Loc = Parser.getTok().getLoc();
3712  if (getParser().parseExpression(Expr)) {
3713  Error(Loc, "illegal expression");
3714  return MatchOperand_ParseFail;
3715  }
3716  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3717  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3718  Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3719  return MatchOperand_ParseFail;
3720  }
3721  int Val = CE->getValue();
3722 
3723  // Check for and consume the closing '}'
3724  if (Parser.getTok().isNot(AsmToken::RCurly))
3725  return MatchOperand_ParseFail;
3726  SMLoc E = Parser.getTok().getEndLoc();
3727  Parser.Lex(); // Eat the '}'
3728 
3729  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3730  return MatchOperand_Success;
3731 }
3732 
3733 // For register list parsing, we need to map from raw GPR register numbering
3734 // to the enumeration values. The enumeration values aren't sorted by
3735 // register number due to our using "sp", "lr" and "pc" as canonical names.
3736 static unsigned getNextRegister(unsigned Reg) {
3737  // If this is a GPR, we need to do it manually, otherwise we can rely
3738  // on the sort ordering of the enumeration since the other reg-classes
3739  // are sane.
3740  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3741  return Reg + 1;
3742  switch(Reg) {
3743  default: llvm_unreachable("Invalid GPR number!");
3744  case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3745  case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3746  case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3747  case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3748  case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3749  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3750  case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3751  case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3752  }
3753 }
3754 
3755 /// Parse a register list.
3756 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3757  MCAsmParser &Parser = getParser();
3758  if (Parser.getTok().isNot(AsmToken::LCurly))
3759  return TokError("Token is not a Left Curly Brace");
3760  SMLoc S = Parser.getTok().getLoc();
3761  Parser.Lex(); // Eat '{' token.
3762  SMLoc RegLoc = Parser.getTok().getLoc();
3763 
3764  // Check the first register in the list to see what register class
3765  // this is a list of.
3766  int Reg = tryParseRegister();
3767  if (Reg == -1)
3768  return Error(RegLoc, "register expected");
3769 
3770  // The reglist instructions have at most 16 registers, so reserve
3771  // space for that many.
3772  int EReg = 0;
3774 
3775  // Allow Q regs and just interpret them as the two D sub-registers.
3776  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3777  Reg = getDRegFromQReg(Reg);
3778  EReg = MRI->getEncodingValue(Reg);
3779  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3780  ++Reg;
3781  }
3782  const MCRegisterClass *RC;
3783  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3784  RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3785  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3786  RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3787  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3788  RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3789  else
3790  return Error(RegLoc, "invalid register in register list");
3791 
3792  // Store the register.
3793  EReg = MRI->getEncodingValue(Reg);
3794  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3795 
3796  // This starts immediately after the first register token in the list,
3797  // so we can see either a comma or a minus (range separator) as a legal
3798  // next token.
3799  while (Parser.getTok().is(AsmToken::Comma) ||
3800  Parser.getTok().is(AsmToken::Minus)) {
3801  if (Parser.getTok().is(AsmToken::Minus)) {
3802  Parser.Lex(); // Eat the minus.
3803  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3804  int EndReg = tryParseRegister();
3805  if (EndReg == -1)
3806  return Error(AfterMinusLoc, "register expected");
3807  // Allow Q regs and just interpret them as the two D sub-registers.
3808  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3809  EndReg = getDRegFromQReg(EndReg) + 1;
3810  // If the register is the same as the start reg, there's nothing
3811  // more to do.
3812  if (Reg == EndReg)
3813  continue;
3814  // The register must be in the same register class as the first.
3815  if (!RC->contains(EndReg))
3816  return Error(AfterMinusLoc, "invalid register in register list");
3817  // Ranges must go from low to high.
3818  if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3819  return Error(AfterMinusLoc, "bad range in register list");
3820 
3821  // Add all the registers in the range to the register list.
3822  while (Reg != EndReg) {
3823  Reg = getNextRegister(Reg);
3824  EReg = MRI->getEncodingValue(Reg);
3825  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3826  }
3827  continue;
3828  }
3829  Parser.Lex(); // Eat the comma.
3830  RegLoc = Parser.getTok().getLoc();
3831  int OldReg = Reg;
3832  const AsmToken RegTok = Parser.getTok();
3833  Reg = tryParseRegister();
3834  if (Reg == -1)
3835  return Error(RegLoc, "register expected");
3836  // Allow Q regs and just interpret them as the two D sub-registers.
3837  bool isQReg = false;
3838  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3839  Reg = getDRegFromQReg(Reg);
3840  isQReg = true;
3841  }
3842  // The register must be in the same register class as the first.
3843  if (!RC->contains(Reg))
3844  return Error(RegLoc, "invalid register in register list");
3845  // List must be monotonically increasing.
3846  if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3847  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3848  Warning(RegLoc, "register list not in ascending order");
3849  else
3850  return Error(RegLoc, "register list not in ascending order");
3851  }
3852  if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3853  Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3854  ") in register list");
3855  continue;
3856  }
3857  // VFP register lists must also be contiguous.
3858  if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3859  Reg != OldReg + 1)
3860  return Error(RegLoc, "non-contiguous register range");
3861  EReg = MRI->getEncodingValue(Reg);
3862  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3863  if (isQReg) {
3864  EReg = MRI->getEncodingValue(++Reg);
3865  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3866  }
3867  }
3868 
3869  if (Parser.getTok().isNot(AsmToken::RCurly))
3870  return Error(Parser.getTok().getLoc(), "'}' expected");
3871  SMLoc E = Parser.getTok().getEndLoc();
3872  Parser.Lex(); // Eat '}' token.
3873 
3874  // Push the register list operand.
3875  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3876 
3877  // The ARM system instruction variants for LDM/STM have a '^' token here.
3878  if (Parser.getTok().is(AsmToken::Caret)) {
3879  Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3880  Parser.Lex(); // Eat '^' token.
3881  }
3882 
3883  return false;
3884 }
3885 
3886 // Helper function to parse the lane index for vector lists.
3887 OperandMatchResultTy ARMAsmParser::
3888 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3889  MCAsmParser &Parser = getParser();
3890  Index = 0; // Always return a defined index value.
3891  if (Parser.getTok().is(AsmToken::LBrac)) {
3892  Parser.Lex(); // Eat the '['.
3893  if (Parser.getTok().is(AsmToken::RBrac)) {
3894  // "Dn[]" is the 'all lanes' syntax.
3895  LaneKind = AllLanes;
3896  EndLoc = Parser.getTok().getEndLoc();
3897  Parser.Lex(); // Eat the ']'.
3898  return MatchOperand_Success;
3899  }
3900 
3901  // There's an optional '#' token here. Normally there wouldn't be, but
3902  // inline assemble puts one in, and it's friendly to accept that.
3903  if (Parser.getTok().is(AsmToken::Hash))
3904  Parser.Lex(); // Eat '#' or '$'.
3905 
3906  const MCExpr *LaneIndex;
3907  SMLoc Loc = Parser.getTok().getLoc();
3908  if (getParser().parseExpression(LaneIndex)) {
3909  Error(Loc, "illegal expression");
3910  return MatchOperand_ParseFail;
3911  }
3912  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3913  if (!CE) {
3914  Error(Loc, "lane index must be empty or an integer");
3915  return MatchOperand_ParseFail;
3916  }
3917  if (Parser.getTok().isNot(AsmToken::RBrac)) {
3918  Error(Parser.getTok().getLoc(), "']' expected");
3919  return MatchOperand_ParseFail;
3920  }
3921  EndLoc = Parser.getTok().getEndLoc();
3922  Parser.Lex(); // Eat the ']'.
3923  int64_t Val = CE->getValue();
3924 
3925  // FIXME: Make this range check context sensitive for .8, .16, .32.
3926  if (Val < 0 || Val > 7) {
3927  Error(Parser.getTok().getLoc(), "lane index out of range");
3928  return MatchOperand_ParseFail;
3929  }
3930  Index = Val;
3931  LaneKind = IndexedLane;
3932  return MatchOperand_Success;
3933  }
3934  LaneKind = NoLanes;
3935  return MatchOperand_Success;
3936 }
3937 
3938 // parse a vector register list
3940 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3941  MCAsmParser &Parser = getParser();
3942  VectorLaneTy LaneKind;
3943  unsigned LaneIndex;
3944  SMLoc S = Parser.getTok().getLoc();
3945  // As an extension (to match gas), support a plain D register or Q register
3946  // (without encosing curly braces) as a single or double entry list,
3947  // respectively.
3948  if (Parser.getTok().is(AsmToken::Identifier)) {
3949  SMLoc E = Parser.getTok().getEndLoc();
3950  int Reg = tryParseRegister();
3951  if (Reg == -1)
3952  return MatchOperand_NoMatch;
3953  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3954  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3955  if (Res != MatchOperand_Success)
3956  return Res;
3957  switch (LaneKind) {
3958  case NoLanes:
3959  Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3960  break;
3961  case AllLanes:
3962  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3963  S, E));
3964  break;
3965  case IndexedLane:
3966  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3967  LaneIndex,
3968  false, S, E));
3969  break;
3970  }
3971  return MatchOperand_Success;
3972  }
3973  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3974  Reg = getDRegFromQReg(Reg);
3975  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3976  if (Res != MatchOperand_Success)
3977  return Res;
3978  switch (LaneKind) {
3979  case NoLanes:
3980  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3981  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3982  Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3983  break;
3984  case AllLanes:
3985  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3986  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3987  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3988  S, E));
3989  break;
3990  case IndexedLane:
3991  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3992  LaneIndex,
3993  false, S, E));
3994  break;
3995  }
3996  return MatchOperand_Success;
3997  }
3998  Error(S, "vector register expected");
3999  return MatchOperand_ParseFail;
4000  }
4001 
4002  if (Parser.getTok().isNot(AsmToken::LCurly))
4003  return MatchOperand_NoMatch;
4004 
4005  Parser.Lex(); // Eat '{' token.
4006  SMLoc RegLoc = Parser.getTok().getLoc();
4007 
4008  int Reg = tryParseRegister();
4009  if (Reg == -1) {
4010  Error(RegLoc, "register expected");
4011  return MatchOperand_ParseFail;
4012  }
4013  unsigned Count = 1;
4014  int Spacing = 0;
4015  unsigned FirstReg = Reg;
4016  // The list is of D registers, but we also allow Q regs and just interpret
4017  // them as the two D sub-registers.
4018  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4019  FirstReg = Reg = getDRegFromQReg(Reg);
4020  Spacing = 1; // double-spacing requires explicit D registers, otherwise
4021  // it's ambiguous with four-register single spaced.
4022  ++Reg;
4023  ++Count;
4024  }
4025 
4026  SMLoc E;
4027  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4028  return MatchOperand_ParseFail;
4029 
4030  while (Parser.getTok().is(AsmToken::Comma) ||
4031  Parser.getTok().is(AsmToken::Minus)) {
4032  if (Parser.getTok().is(AsmToken::Minus)) {
4033  if (!Spacing)
4034  Spacing = 1; // Register range implies a single spaced list.
4035  else if (Spacing == 2) {
4036  Error(Parser.getTok().getLoc(),
4037  "sequential registers in double spaced list");
4038  return MatchOperand_ParseFail;
4039  }
4040  Parser.Lex(); // Eat the minus.
4041  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4042  int EndReg = tryParseRegister();
4043  if (EndReg == -1) {
4044  Error(AfterMinusLoc, "register expected");
4045  return MatchOperand_ParseFail;
4046  }
4047  // Allow Q regs and just interpret them as the two D sub-registers.
4048  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4049  EndReg = getDRegFromQReg(EndReg) + 1;
4050  // If the register is the same as the start reg, there's nothing
4051  // more to do.
4052  if (Reg == EndReg)
4053  continue;
4054  // The register must be in the same register class as the first.
4055  if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
4056  Error(AfterMinusLoc, "invalid register in register list");
4057  return MatchOperand_ParseFail;
4058  }
4059  // Ranges must go from low to high.
4060  if (Reg > EndReg) {
4061  Error(AfterMinusLoc, "bad range in register list");
4062  return MatchOperand_ParseFail;
4063  }
4064  // Parse the lane specifier if present.
4065  VectorLaneTy NextLaneKind;
4066  unsigned NextLaneIndex;
4067  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4069  return MatchOperand_ParseFail;
4070  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4071  Error(AfterMinusLoc, "mismatched lane index in register list");
4072  return MatchOperand_ParseFail;
4073  }
4074 
4075  // Add all the registers in the range to the register list.
4076  Count += EndReg - Reg;
4077  Reg = EndReg;
4078  continue;
4079  }
4080  Parser.Lex(); // Eat the comma.
4081  RegLoc = Parser.getTok().getLoc();
4082  int OldReg = Reg;
4083  Reg = tryParseRegister();
4084  if (Reg == -1) {
4085  Error(RegLoc, "register expected");
4086  return MatchOperand_ParseFail;
4087  }
4088  // vector register lists must be contiguous.
4089  // It's OK to use the enumeration values directly here rather, as the
4090  // VFP register classes have the enum sorted properly.
4091  //
4092  // The list is of D registers, but we also allow Q regs and just interpret
4093  // them as the two D sub-registers.
4094  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4095  if (!Spacing)
4096  Spacing = 1; // Register range implies a single spaced list.
4097  else if (Spacing == 2) {
4098  Error(RegLoc,
4099  "invalid register in double-spaced list (must be 'D' register')");
4100  return MatchOperand_ParseFail;
4101  }
4102  Reg = getDRegFromQReg(Reg);
4103  if (Reg != OldReg + 1) {
4104  Error(RegLoc, "non-contiguous register range");
4105  return MatchOperand_ParseFail;
4106  }
4107  ++Reg;
4108  Count += 2;
4109  // Parse the lane specifier if present.
4110  VectorLaneTy NextLaneKind;
4111  unsigned NextLaneIndex;
4112  SMLoc LaneLoc = Parser.getTok().getLoc();
4113  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4115  return MatchOperand_ParseFail;
4116  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4117  Error(LaneLoc, "mismatched lane index in register list");
4118  return MatchOperand_ParseFail;
4119  }
4120  continue;
4121  }
4122  // Normal D register.
4123  // Figure out the register spacing (single or double) of the list if
4124  // we don't know it already.
4125  if (!Spacing)
4126  Spacing = 1 + (Reg == OldReg + 2);
4127 
4128  // Just check that it's contiguous and keep going.
4129  if (Reg != OldReg + Spacing) {
4130  Error(RegLoc, "non-contiguous register range");
4131  return MatchOperand_ParseFail;
4132  }
4133  ++Count;
4134  // Parse the lane specifier if present.
4135  VectorLaneTy NextLaneKind;
4136  unsigned NextLaneIndex;
4137  SMLoc EndLoc = Parser.getTok().getLoc();
4138  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4139  return MatchOperand_ParseFail;
4140  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4141  Error(EndLoc, "mismatched lane index in register list");
4142  return MatchOperand_ParseFail;
4143  }
4144  }
4145 
4146  if (Parser.getTok().isNot(AsmToken::RCurly)) {
4147  Error(Parser.getTok().getLoc(), "'}' expected");
4148  return MatchOperand_ParseFail;
4149  }
4150  E = Parser.getTok().getEndLoc();
4151  Parser.Lex(); // Eat '}' token.
4152 
4153  switch (LaneKind) {
4154  case NoLanes:
4155  // Two-register operands have been converted to the
4156  // composite register classes.
4157  if (Count == 2) {
4158  const MCRegisterClass *RC = (Spacing == 1) ?
4159  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4160  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4161  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4162  }
4163  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4164  (Spacing == 2), S, E));
4165  break;
4166  case AllLanes:
4167  // Two-register operands have been converted to the
4168  // composite register classes.
4169  if (Count == 2) {
4170  const MCRegisterClass *RC = (Spacing == 1) ?
4171  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4172  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4173  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4174  }
4175  Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4176  (Spacing == 2),
4177  S, E));
4178  break;
4179  case IndexedLane:
4180  Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4181  LaneIndex,
4182  (Spacing == 2),
4183  S, E));
4184  break;
4185  }
4186  return MatchOperand_Success;
4187 }
4188 
4189 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4191 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4192  MCAsmParser &Parser = getParser();
4193  SMLoc S = Parser.getTok().getLoc();
4194  const AsmToken &Tok = Parser.getTok();
4195  unsigned Opt;
4196 
4197  if (Tok.is(AsmToken::Identifier)) {
4198  StringRef OptStr = Tok.getString();
4199 
4200  Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4201  .Case("sy", ARM_MB::SY)
4202  .Case("st", ARM_MB::ST)
4203  .Case("ld", ARM_MB::LD)
4204  .Case("sh", ARM_MB::ISH)
4205  .Case("ish", ARM_MB::ISH)
4206  .Case("shst", ARM_MB::ISHST)
4207  .Case("ishst", ARM_MB::ISHST)
4208  .Case("ishld", ARM_MB::ISHLD)
4209  .Case("nsh", ARM_MB::NSH)
4210  .Case("un", ARM_MB::NSH)
4211  .Case("nshst", ARM_MB::NSHST)
4212  .Case("nshld", ARM_MB::NSHLD)
4213  .Case("unst", ARM_MB::NSHST)
4214  .Case("osh", ARM_MB::OSH)
4215  .Case("oshst", ARM_MB::OSHST)
4216  .Case("oshld", ARM_MB::OSHLD)
4217  .Default(~0U);
4218 
4219  // ishld, oshld, nshld and ld are only available from ARMv8.
4220  if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4221  Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4222  Opt = ~0U;
4223 
4224  if (Opt == ~0U)
4225  return MatchOperand_NoMatch;
4226 
4227  Parser.Lex(); // Eat identifier token.
4228  } else if (Tok.is(AsmToken::Hash) ||
4229  Tok.is(AsmToken::Dollar) ||
4230  Tok.is(AsmToken::Integer)) {
4231  if (Parser.getTok().isNot(AsmToken::Integer))
4232  Parser.Lex(); // Eat '#' or '$'.
4233  SMLoc Loc = Parser.getTok().getLoc();
4234 
4235  const MCExpr *MemBarrierID;
4236  if (getParser().parseExpression(MemBarrierID)) {
4237  Error(Loc, "illegal expression");
4238  return MatchOperand_ParseFail;
4239  }
4240 
4241  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4242  if (!CE) {
4243  Error(Loc, "constant expression expected");
4244  return MatchOperand_ParseFail;
4245  }
4246 
4247  int Val = CE->getValue();
4248  if (Val & ~0xf) {
4249  Error(Loc, "immediate value out of range");
4250  return MatchOperand_ParseFail;
4251  }
4252 
4253  Opt = ARM_MB::RESERVED_0 + Val;
4254  } else
4255  return MatchOperand_ParseFail;
4256 
4257  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4258  return MatchOperand_Success;
4259 }
4260 
4262 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4263  MCAsmParser &Parser = getParser();
4264  SMLoc S = Parser.getTok().getLoc();
4265  const AsmToken &Tok = Parser.getTok();
4266 
4267  if (Tok.isNot(AsmToken::Identifier))
4268  return MatchOperand_NoMatch;
4269 
4270  if (!Tok.getString().equals_lower("csync"))
4271  return MatchOperand_NoMatch;
4272 
4273  Parser.Lex(); // Eat identifier token.
4274 
4275  Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4276  return MatchOperand_Success;
4277 }
4278 
4279 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4281 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4282  MCAsmParser &Parser = getParser();
4283  SMLoc S = Parser.getTok().getLoc();
4284  const AsmToken &Tok = Parser.getTok();
4285  unsigned Opt;
4286 
4287  if (Tok.is(AsmToken::Identifier)) {
4288  StringRef OptStr = Tok.getString();
4289 
4290  if (OptStr.equals_lower("sy"))
4291  Opt = ARM_ISB::SY;
4292  else
4293  return MatchOperand_NoMatch;
4294 
4295  Parser.Lex(); // Eat identifier token.
4296  } else if (Tok.is(AsmToken::Hash) ||
4297  Tok.is(AsmToken::Dollar) ||
4298  Tok.is(AsmToken::Integer)) {
4299  if (Parser.getTok().isNot(AsmToken::Integer))
4300  Parser.Lex(); // Eat '#' or '$'.
4301  SMLoc Loc = Parser.getTok().getLoc();
4302 
4303  const MCExpr *ISBarrierID;
4304  if (getParser().parseExpression(ISBarrierID)) {
4305  Error(Loc, "illegal expression");
4306  return MatchOperand_ParseFail;
4307  }
4308 
4309  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4310  if (!CE) {
4311  Error(Loc, "constant expression expected");
4312  return MatchOperand_ParseFail;
4313  }
4314 
4315  int Val = CE->getValue();
4316  if (Val & ~0xf) {
4317  Error(Loc, "immediate value out of range");
4318  return MatchOperand_ParseFail;
4319  }
4320 
4321  Opt = ARM_ISB::RESERVED_0 + Val;
4322  } else
4323  return MatchOperand_ParseFail;
4324 
4325  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4326  (ARM_ISB::InstSyncBOpt)Opt, S));
4327  return MatchOperand_Success;
4328 }
4329 
4330 
4331 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4333 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4334  MCAsmParser &Parser = getParser();
4335  SMLoc S = Parser.getTok().getLoc();
4336  const AsmToken &Tok = Parser.getTok();
4337  if (!Tok.is(AsmToken::Identifier))
4338  return MatchOperand_NoMatch;
4339  StringRef IFlagsStr = Tok.getString();
4340 
4341  // An iflags string of "none" is interpreted to mean that none of the AIF
4342  // bits are set. Not a terribly useful instruction, but a valid encoding.
4343  unsigned IFlags = 0;
4344  if (IFlagsStr != "none") {
4345  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4346  unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4347  .Case("a", ARM_PROC::A)
4348  .Case("i", ARM_PROC::I)
4349  .Case("f", ARM_PROC::F)
4350  .Default(~0U);
4351 
4352  // If some specific iflag is already set, it means that some letter is
4353  // present more than once, this is not acceptable.
4354  if (Flag == ~0U || (IFlags & Flag))
4355  return MatchOperand_NoMatch;
4356 
4357  IFlags |= Flag;
4358  }
4359  }
4360 
4361  Parser.Lex(); // Eat identifier token.
4362  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4363  return MatchOperand_Success;
4364 }
4365 
4366 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4368 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4369  MCAsmParser &Parser = getParser();
4370  SMLoc S = Parser.getTok().getLoc();
4371  const AsmToken &Tok = Parser.getTok();
4372 
4373  if (Tok.is(AsmToken::Integer)) {
4374  int64_t Val = Tok.getIntVal();
4375  if (Val > 255 || Val < 0) {
4376  return MatchOperand_NoMatch;
4377  }
4378  unsigned SYSmvalue = Val & 0xFF;
4379  Parser.Lex();
4380  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4381  return MatchOperand_Success;
4382  }
4383 
4384  if (!Tok.is(AsmToken::Identifier))
4385  return MatchOperand_NoMatch;
4386  StringRef Mask = Tok.getString();
4387 
4388  if (isMClass()) {
4389  auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4390  if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4391  return MatchOperand_NoMatch;
4392 
4393  unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4394 
4395  Parser.Lex(); // Eat identifier token.
4396  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4397  return MatchOperand_Success;
4398  }
4399 
4400  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4401  size_t Start = 0, Next = Mask.find('_');
4402  StringRef Flags = "";
4403  std::string SpecReg = Mask.slice(Start, Next).lower();
4404  if (Next != StringRef::npos)
4405  Flags = Mask.slice(Next+1, Mask.size());
4406 
4407  // FlagsVal contains the complete mask:
4408  // 3-0: Mask
4409  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4410  unsigned FlagsVal = 0;
4411 
4412  if (SpecReg == "apsr") {
4413  FlagsVal = StringSwitch<unsigned>(Flags)
4414  .Case("nzcvq", 0x8) // same as CPSR_f
4415  .Case("g", 0x4) // same as CPSR_s
4416  .Case("nzcvqg", 0xc) // same as CPSR_fs
4417  .Default(~0U);
4418 
4419  if (FlagsVal == ~0U) {
4420  if (!Flags.empty())
4421  return MatchOperand_NoMatch;
4422  else
4423  FlagsVal = 8; // No flag
4424  }
4425  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4426  // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4427  if (Flags == "all" || Flags == "")
4428  Flags = "fc";
4429  for (int i = 0, e = Flags.size(); i != e; ++i) {
4430  unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4431  .Case("c", 1)
4432  .Case("x", 2)
4433  .Case("s", 4)
4434  .Case("f", 8)
4435  .Default(~0U);
4436 
4437  // If some specific flag is already set, it means that some letter is
4438  // present more than once, this is not acceptable.
4439  if (Flag == ~0U || (FlagsVal & Flag))
4440  return MatchOperand_NoMatch;
4441  FlagsVal |= Flag;
4442  }
4443  } else // No match for special register.
4444  return MatchOperand_NoMatch;
4445 
4446  // Special register without flags is NOT equivalent to "fc" flags.
4447  // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4448  // two lines would enable gas compatibility at the expense of breaking
4449  // round-tripping.
4450  //
4451  // if (!FlagsVal)
4452  // FlagsVal = 0x9;
4453 
4454  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4455  if (SpecReg == "spsr")
4456  FlagsVal |= 16;
4457 
4458  Parser.Lex(); // Eat identifier token.
4459  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4460  return MatchOperand_Success;
4461 }
4462 
4463 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4464 /// use in the MRS/MSR instructions added to support virtualization.
4466 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4467  MCAsmParser &Parser = getParser();
4468  SMLoc S = Parser.getTok().getLoc();
4469  const AsmToken &Tok = Parser.getTok();
4470  if (!Tok.is(AsmToken::Identifier))
4471  return MatchOperand_NoMatch;
4472  StringRef RegName = Tok.getString();
4473 
4474  auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
4475  if (!TheReg)
4476  return MatchOperand_NoMatch;
4477  unsigned Encoding = TheReg->Encoding;
4478 
4479  Parser.Lex(); // Eat identifier token.
4480  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4481  return MatchOperand_Success;
4482 }
4483 
4485 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4486  int High) {
4487  MCAsmParser &Parser = getParser();
4488  const AsmToken &Tok = Parser.getTok();
4489  if (Tok.isNot(AsmToken::Identifier)) {
4490  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4491  return MatchOperand_ParseFail;
4492  }
4493  StringRef ShiftName = Tok.getString();
4494  std::string LowerOp = Op.lower();
4495  std::string UpperOp = Op.upper();
4496  if (ShiftName != LowerOp && ShiftName != UpperOp) {
4497  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4498  return MatchOperand_ParseFail;
4499  }
4500  Parser.Lex(); // Eat shift type token.
4501 
4502  // There must be a '#' and a shift amount.
4503  if (Parser.getTok().isNot(AsmToken::Hash) &&
4504  Parser.getTok().isNot(AsmToken::Dollar)) {
4505  Error(Parser.getTok().getLoc(), "'#' expected");
4506  return MatchOperand_ParseFail;
4507  }
4508  Parser.Lex(); // Eat hash token.
4509 
4510  const MCExpr *ShiftAmount;
4511  SMLoc Loc = Parser.getTok().getLoc();
4512  SMLoc EndLoc;
4513  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4514  Error(Loc, "illegal expression");
4515  return MatchOperand_ParseFail;
4516  }
4517  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4518  if (!CE) {
4519  Error(Loc, "constant expression expected");
4520  return MatchOperand_ParseFail;
4521  }
4522  int Val = CE->getValue();
4523  if (Val < Low || Val > High) {
4524  Error(Loc, "immediate value out of range");
4525  return MatchOperand_ParseFail;
4526  }
4527 
4528  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4529 
4530  return MatchOperand_Success;
4531 }
4532 
4534 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4535  MCAsmParser &Parser = getParser();
4536  const AsmToken &Tok = Parser.getTok();
4537  SMLoc S = Tok.getLoc();
4538  if (Tok.isNot(AsmToken::Identifier)) {
4539  Error(S, "'be' or 'le' operand expected");
4540  return MatchOperand_ParseFail;
4541  }
4542  int Val = StringSwitch<int>(Tok.getString().lower())
4543  .Case("be", 1)
4544  .Case("le", 0)
4545  .Default(-1);
4546  Parser.Lex(); // Eat the token.
4547 
4548  if (Val == -1) {
4549  Error(S, "'be' or 'le' operand expected");
4550  return MatchOperand_ParseFail;
4551  }
4552  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4553  getContext()),
4554  S, Tok.getEndLoc()));
4555  return MatchOperand_Success;
4556 }
4557 
4558 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4559 /// instructions. Legal values are:
4560 /// lsl #n 'n' in [0,31]
4561 /// asr #n 'n' in [1,32]
4562 /// n == 32 encoded as n == 0.
4564 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4565  MCAsmParser &Parser = getParser();
4566  const AsmToken &Tok = Parser.getTok();
4567  SMLoc S = Tok.getLoc();
4568  if (Tok.isNot(AsmToken::Identifier)) {
4569  Error(S, "shift operator 'asr' or 'lsl' expected");
4570  return MatchOperand_ParseFail;
4571  }
4572  StringRef ShiftName = Tok.getString();
4573  bool isASR;
4574  if (ShiftName == "lsl" || ShiftName == "LSL")
4575  isASR = false;
4576  else if (ShiftName == "asr" || ShiftName == "ASR")
4577  isASR = true;
4578  else {
4579  Error(S, "shift operator 'asr' or 'lsl' expected");
4580  return MatchOperand_ParseFail;
4581  }
4582  Parser.Lex(); // Eat the operator.
4583 
4584  // A '#' and a shift amount.
4585  if (Parser.getTok().isNot(AsmToken::Hash) &&
4586  Parser.getTok().isNot(AsmToken::Dollar)) {
4587  Error(Parser.getTok().getLoc(), "'#' expected");
4588  return MatchOperand_ParseFail;
4589  }
4590  Parser.Lex(); // Eat hash token.
4591  SMLoc ExLoc = Parser.getTok().getLoc();
4592 
4593  const MCExpr *ShiftAmount;
4594  SMLoc EndLoc;
4595  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4596  Error(ExLoc, "malformed shift expression");
4597  return MatchOperand_ParseFail;
4598  }
4599  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4600  if (!CE) {
4601  Error(ExLoc, "shift amount must be an immediate");
4602  return MatchOperand_ParseFail;
4603  }
4604 
4605  int64_t Val = CE->getValue();
4606  if (isASR) {
4607  // Shift amount must be in [1,32]
4608  if (Val < 1 || Val > 32) {
4609  Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4610  return MatchOperand_ParseFail;
4611  }
4612  // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4613  if (isThumb() && Val == 32) {
4614  Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4615  return MatchOperand_ParseFail;
4616  }
4617  if (Val == 32) Val = 0;
4618  } else {
4619  // Shift amount must be in [1,32]
4620  if (Val < 0 || Val > 31) {
4621  Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4622  return MatchOperand_ParseFail;
4623  }
4624  }
4625 
4626  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4627 
4628  return MatchOperand_Success;
4629 }
4630 
4631 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4632 /// of instructions. Legal values are:
4633 /// ror #n 'n' in {0, 8, 16, 24}
4635 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4636  MCAsmParser &Parser = getParser();
4637  const AsmToken &Tok = Parser.getTok();
4638  SMLoc S = Tok.getLoc();
4639  if (Tok.isNot(AsmToken::Identifier))
4640  return MatchOperand_NoMatch;
4641  StringRef ShiftName = Tok.getString();
4642  if (ShiftName != "ror" && ShiftName != "ROR")
4643  return MatchOperand_NoMatch;
4644  Parser.Lex(); // Eat the operator.
4645 
4646  // A '#' and a rotate amount.
4647  if (Parser.getTok().isNot(AsmToken::Hash) &&
4648  Parser.getTok().isNot(AsmToken::Dollar)) {
4649  Error(Parser.getTok().getLoc(), "'#' expected");
4650  return MatchOperand_ParseFail;
4651  }
4652  Parser.Lex(); // Eat hash token.
4653  SMLoc ExLoc = Parser.getTok().getLoc();
4654 
4655  const MCExpr *ShiftAmount;
4656  SMLoc EndLoc;
4657  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4658  Error(ExLoc, "malformed rotate expression");
4659  return MatchOperand_ParseFail;
4660  }
4661  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4662  if (!CE) {
4663  Error(ExLoc, "rotate amount must be an immediate");
4664  return MatchOperand_ParseFail;
4665  }
4666 
4667  int64_t Val = CE->getValue();
4668  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4669  // normally, zero is represented in asm by omitting the rotate operand
4670  // entirely.
4671  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4672  Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4673  return MatchOperand_ParseFail;
4674  }
4675 
4676  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4677 
4678  return MatchOperand_Success;
4679 }
4680 
4682 ARMAsmParser::parseModImm(OperandVector &Operands) {
4683  MCAsmParser &Parser = getParser();
4684  MCAsmLexer &Lexer = getLexer();
4685  int64_t Imm1, Imm2;
4686 
4687  SMLoc S = Parser.getTok().getLoc();
4688 
4689  // 1) A mod_imm operand can appear in the place of a register name:
4690  // add r0, #mod_imm
4691  // add r0, r0, #mod_imm
4692  // to correctly handle the latter, we bail out as soon as we see an
4693  // identifier.
4694  //
4695  // 2) Similarly, we do not want to parse into complex operands:
4696  // mov r0, #mod_imm
4697  // mov r0, :lower16:(_foo)
4698  if (Parser.getTok().is(AsmToken::Identifier) ||
4699  Parser.getTok().is(AsmToken::Colon))
4700  return MatchOperand_NoMatch;
4701 
4702  // Hash (dollar) is optional as per the ARMARM
4703  if (Parser.getTok().is(AsmToken::Hash) ||
4704  Parser.getTok().is(AsmToken::Dollar)) {
4705  // Avoid parsing into complex operands (#:)
4706  if (Lexer.peekTok().is(AsmToken::Colon))
4707  return MatchOperand_NoMatch;
4708 
4709  // Eat the hash (dollar)
4710  Parser.Lex();
4711  }
4712 
4713  SMLoc Sx1, Ex1;
4714  Sx1 = Parser.getTok().getLoc();
4715  const MCExpr *Imm1Exp;
4716  if (getParser().parseExpression(Imm1Exp, Ex1)) {
4717  Error(Sx1, "malformed expression");
4718  return MatchOperand_ParseFail;
4719  }
4720 
4721  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4722 
4723  if (CE) {
4724  // Immediate must fit within 32-bits
4725  Imm1 = CE->getValue();
4726  int Enc = ARM_AM::getSOImmVal(Imm1);
4727  if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4728  // We have a match!
4729  Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4730  (Enc & 0xF00) >> 7,
4731  Sx1, Ex1));
4732  return MatchOperand_Success;
4733  }
4734 
4735  // We have parsed an immediate which is not for us, fallback to a plain
4736  // immediate. This can happen for instruction aliases. For an example,
4737  // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4738  // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4739  // instruction with a mod_imm operand. The alias is defined such that the
4740  // parser method is shared, that's why we have to do this here.
4741  if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4742  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4743  return MatchOperand_Success;
4744  }
4745  } else {
4746  // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4747  // MCFixup). Fallback to a plain immediate.
4748  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4749  return MatchOperand_Success;
4750  }
4751 
4752  // From this point onward, we expect the input to be a (#bits, #rot) pair
4753  if (Parser.getTok().isNot(AsmToken::Comma)) {
4754  Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4755  return MatchOperand_ParseFail;
4756  }
4757 
4758  if (Imm1 & ~0xFF) {
4759  Error(Sx1, "immediate operand must a number in the range [0, 255]");
4760  return MatchOperand_ParseFail;
4761  }
4762 
4763  // Eat the comma
4764  Parser.Lex();
4765 
4766  // Repeat for #rot
4767  SMLoc Sx2, Ex2;
4768  Sx2 = Parser.getTok().getLoc();
4769 
4770  // Eat the optional hash (dollar)
4771  if (Parser.getTok().is(AsmToken::Hash) ||
4772  Parser.getTok().is(AsmToken::Dollar))
4773  Parser.Lex();
4774 
4775  const MCExpr *Imm2Exp;
4776  if (getParser().parseExpression(Imm2Exp, Ex2)) {
4777  Error(Sx2, "malformed expression");
4778  return MatchOperand_ParseFail;
4779  }
4780 
4781  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4782 
4783  if (CE) {
4784  Imm2 = CE->getValue();
4785  if (!(Imm2 & ~0x1E)) {
4786  // We have a match!
4787  Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4788  return MatchOperand_Success;
4789  }
4790  Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4791  return MatchOperand_ParseFail;
4792  } else {
4793  Error(Sx2, "constant expression expected");
4794  return MatchOperand_ParseFail;
4795  }
4796 }
4797 
4799 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4800  MCAsmParser &Parser = getParser();
4801  SMLoc S = Parser.getTok().getLoc();
4802  // The bitfield descriptor is really two operands, the LSB and the width.
4803  if (Parser.getTok().isNot(AsmToken::Hash) &&
4804  Parser.getTok().isNot(AsmToken::Dollar)) {
4805  Error(Parser.getTok().getLoc(), "'#' expected");
4806  return MatchOperand_ParseFail;
4807  }
4808  Parser.Lex(); // Eat hash token.
4809 
4810  const MCExpr *LSBExpr;
4811  SMLoc E = Parser.getTok().getLoc();
4812  if (getParser().parseExpression(LSBExpr)) {
4813  Error(E, "malformed immediate expression");
4814  return MatchOperand_ParseFail;
4815  }
4816  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4817  if (!CE) {
4818  Error(E, "'lsb' operand must be an immediate");
4819  return MatchOperand_ParseFail;
4820  }
4821 
4822  int64_t LSB = CE->getValue();
4823  // The LSB must be in the range [0,31]
4824  if (LSB < 0 || LSB > 31) {
4825  Error(E, "'lsb' operand must be in the range [0,31]");
4826  return MatchOperand_ParseFail;
4827  }
4828  E = Parser.getTok().getLoc();
4829 
4830  // Expect another immediate operand.
4831  if (Parser.getTok().isNot(AsmToken::Comma)) {
4832  Error(Parser.getTok().getLoc(), "too few operands");
4833  return MatchOperand_ParseFail;
4834  }
4835  Parser.Lex(); // Eat hash token.
4836  if (Parser.getTok().isNot(AsmToken::Hash) &&
4837  Parser.getTok().isNot(AsmToken::Dollar)) {
4838  Error(Parser.getTok().getLoc(), "'#' expected");
4839  return MatchOperand_ParseFail;
4840  }
4841  Parser.Lex(); // Eat hash token.
4842 
4843  const MCExpr *WidthExpr;
4844  SMLoc EndLoc;
4845  if (getParser().parseExpression(WidthExpr, EndLoc)) {
4846  Error(E, "malformed immediate expression");
4847  return MatchOperand_ParseFail;
4848  }
4849  CE = dyn_cast<MCConstantExpr>(WidthExpr);
4850  if (!CE) {
4851  Error(E, "'width' operand must be an immediate");
4852  return MatchOperand_ParseFail;
4853  }
4854 
4855  int64_t Width = CE->getValue();
4856  // The LSB must be in the range [1,32-lsb]
4857  if (Width < 1 || Width > 32 - LSB) {
4858  Error(E, "'width' operand must be in the range [1,32-lsb]");
4859  return MatchOperand_ParseFail;
4860  }
4861 
4862  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4863 
4864  return MatchOperand_Success;
4865 }
4866 
4868 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4869  // Check for a post-index addressing register operand. Specifically:
4870  // postidx_reg := '+' register {, shift}
4871  // | '-' register {, shift}
4872  // | register {, shift}
4873 
4874  // This method must return MatchOperand_NoMatch without consuming any tokens
4875  // in the case where there is no match, as other alternatives take other
4876  // parse methods.
4877  MCAsmParser &Parser = getParser();
4878  AsmToken Tok = Parser.getTok();
4879  SMLoc S = Tok.getLoc();
4880  bool haveEaten = false;
4881  bool isAdd = true;
4882  if (Tok.is(AsmToken::Plus)) {
4883  Parser.Lex(); // Eat the '+' token.
4884  haveEaten = true;
4885  } else if (Tok.is(AsmToken::Minus)) {
4886  Parser.Lex(); // Eat the '-' token.
4887  isAdd = false;
4888  haveEaten = true;
4889  }
4890 
4891  SMLoc E = Parser.getTok().getEndLoc();
4892  int Reg = tryParseRegister();
4893  if (Reg == -1) {
4894  if (!haveEaten)
4895  return MatchOperand_NoMatch;
4896  Error(Parser.getTok().getLoc(), "register expected");
4897  return MatchOperand_ParseFail;
4898  }
4899 
4901  unsigned ShiftImm = 0;
4902  if (Parser.getTok().is(AsmToken::Comma)) {
4903  Parser.Lex(); // Eat the ','.
4904  if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4905  return MatchOperand_ParseFail;
4906 
4907  // FIXME: Only approximates end...may include intervening whitespace.
4908  E = Parser.getTok().getLoc();
4909  }
4910 
4911  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4912  ShiftImm, S, E));
4913 
4914  return MatchOperand_Success;
4915 }
4916 
4918 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4919  // Check for a post-index addressing register operand. Specifically:
4920  // am3offset := '+' register
4921  // | '-' register
4922  // | register
4923  // | # imm
4924  // | # + imm
4925  // | # - imm
4926 
4927  // This method must return MatchOperand_NoMatch without consuming any tokens
4928  // in the case where there is no match, as other alternatives take other
4929  // parse methods.
4930  MCAsmParser &Parser = getParser();
4931  AsmToken Tok = Parser.getTok();
4932  SMLoc S = Tok.getLoc();
4933 
4934  // Do immediates first, as we always parse those if we have a '#'.
4935  if (Parser.getTok().is(AsmToken::Hash) ||
4936  Parser.getTok().is(AsmToken::Dollar)) {
4937  Parser.Lex(); // Eat '#' or '$'.
4938  // Explicitly look for a '-', as we need to encode negative zero
4939  // differently.
4940  bool isNegative = Parser.getTok().is(AsmToken::Minus);
4941  const MCExpr *Offset;
4942  SMLoc E;
4943  if (getParser().parseExpression(Offset, E))
4944  return MatchOperand_ParseFail;
4946  if (!CE) {
4947  Error(S, "constant expression expected");
4948  return MatchOperand_ParseFail;
4949  }
4950  // Negative zero is encoded as the flag value
4951  // std::numeric_limits<int32_t>::min().
4952  int32_t Val = CE->getValue();
4953  if (isNegative && Val == 0)
4954  Val = std::numeric_limits<int32_t>::min();
4955 
4956  Operands.push_back(
4957  ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4958 
4959  return MatchOperand_Success;
4960  }
4961 
4962  bool haveEaten = false;
4963  bool isAdd = true;
4964  if (Tok.is(AsmToken::Plus)) {
4965  Parser.Lex(); // Eat the '+' token.
4966  haveEaten = true;
4967  } else if (Tok.is(AsmToken::Minus)) {
4968  Parser.Lex(); // Eat the '-' token.
4969  isAdd = false;
4970  haveEaten = true;
4971  }
4972 
4973  Tok = Parser.getTok();
4974  int Reg = tryParseRegister();
4975  if (Reg == -1) {
4976  if (!haveEaten)
4977  return MatchOperand_NoMatch;
4978  Error(Tok.getLoc(), "register expected");
4979  return MatchOperand_ParseFail;
4980  }
4981 
4982  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4983  0, S, Tok.getEndLoc()));
4984 
4985  return MatchOperand_Success;
4986 }
4987 
4988 /// Convert parsed operands to MCInst. Needed here because this instruction
4989 /// only has two register operands, but multiplication is commutative so
4990 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4991 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4992  const OperandVector &Operands) {
4993  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4994  ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4995  // If we have a three-operand form, make sure to set Rn to be the operand
4996  // that isn't the same as Rd.
4997  unsigned RegOp = 4;
4998  if (Operands.size() == 6 &&
4999  ((ARMOperand &)*Operands[4]).getReg() ==
5000  ((ARMOperand &)*Operands[3]).getReg())
5001  RegOp = 5;
5002  ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5003  Inst.addOperand(Inst.getOperand(0));
5004  ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5005 }
5006 
5007 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5008  const OperandVector &Operands) {
5009  int CondOp = -1, ImmOp = -1;
5010  switch(Inst.getOpcode()) {
5011  case ARM::tB:
5012  case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
5013 
5014  case ARM::t2B:
5015  case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5016 
5017  default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
5018  }
5019  // first decide whether or not the branch should be conditional
5020  // by looking at it's location relative to an IT block
5021  if(inITBlock()) {
5022  // inside an IT block we cannot have any conditional branches. any
5023  // such instructions needs to be converted to unconditional form
5024  switch(Inst.getOpcode()) {
5025  case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5026  case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5027  }
5028  } else {
5029  // outside IT blocks we can only have unconditional branches with AL
5030  // condition code or conditional branches with non-AL condition code
5031  unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5032  switch(Inst.getOpcode()) {
5033  case ARM::tB:
5034  case ARM::tBcc:
5035  Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5036  break;
5037  case ARM::t2B:
5038  case ARM::t2Bcc:
5039  Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5040  break;
5041  }
5042  }
5043 
5044  // now decide on encoding size based on branch target range
5045  switch(Inst.getOpcode()) {
5046  // classify tB as either t2B or t1B based on range of immediate operand
5047  case ARM::tB: {
5048  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5049  if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5050  Inst.setOpcode(ARM::t2B);
5051  break;
5052  }
5053  // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5054  case ARM::tBcc: {
5055  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5056  if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5057  Inst.setOpcode(ARM::t2Bcc);
5058  break;
5059  }
5060  }
5061  ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5062  ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5063 }
5064 
5065 /// Parse an ARM memory expression, return false if successful else return true
5066 /// or an error. The first token must be a '[' when called.
5067 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5068  MCAsmParser &Parser = getParser();
5069  SMLoc S, E;
5070  if (Parser.getTok().isNot(AsmToken::LBrac))
5071  return TokError("Token is not a Left Bracket");
5072  S = Parser.getTok().getLoc();
5073  Parser.Lex(); // Eat left bracket token.
5074 
5075  const AsmToken &BaseRegTok = Parser.getTok();
5076  int BaseRegNum = tryParseRegister();
5077  if (BaseRegNum == -1)
5078  return Error(BaseRegTok.getLoc(), "register expected");
5079 
5080  // The next token must either be a comma, a colon or a closing bracket.
5081  const AsmToken &Tok = Parser.getTok();
5082  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5083  !Tok.is(AsmToken::RBrac))
5084  return Error(Tok.getLoc(), "malformed memory operand");
5085 
5086  if (Tok.is(AsmToken::RBrac)) {
5087  E = Tok.getEndLoc();
5088  Parser.Lex(); // Eat right bracket token.
5089 
5090  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5091  ARM_AM::no_shift, 0, 0, false,
5092  S, E));
5093 
5094  // If there's a pre-indexing writeback marker, '!', just add it as a token
5095  // operand. It's rather odd, but syntactically valid.
5096  if (Parser.getTok().is(AsmToken::Exclaim)) {
5097  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5098  Parser.Lex(); // Eat the '!'.
5099  }
5100 
5101  return false;
5102  }
5103 
5104  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5105  "Lost colon or comma in memory operand?!");
5106  if (Tok.is(AsmToken::Comma)) {
5107  Parser.Lex(); // Eat the comma.
5108  }
5109 
5110  // If we have a ':', it's an alignment specifier.
5111  if (Parser.getTok().is(AsmToken::Colon)) {
5112  Parser.Lex(); // Eat the ':'.
5113  E = Parser.getTok().getLoc();
5114  SMLoc AlignmentLoc = Tok.getLoc();
5115 
5116  const MCExpr *Expr;
5117  if (getParser().parseExpression(Expr))
5118  return true;
5119 
5120  // The expression has to be a constant. Memory references with relocations
5121  // don't come through here, as they use the <label> forms of the relevant
5122  // instructions.
5123  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5124  if (!CE)
5125  return Error (E, "constant expression expected");
5126 
5127  unsigned Align = 0;
5128  switch (CE->getValue()) {
5129  default:
5130  return Error(E,
5131  "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5132  case 16: Align = 2; break;
5133  case 32: Align = 4; break;
5134  case 64: Align = 8; break;
5135  case 128: Align = 16; break;
5136  case 256: Align = 32; break;
5137  }
5138 
5139  // Now we should have the closing ']'
5140  if (Parser.getTok().isNot(AsmToken::RBrac))
5141  return Error(Parser.getTok().getLoc(), "']' expected");
5142  E = Parser.getTok().getEndLoc();
5143  Parser.Lex(); // Eat right bracket token.
5144 
5145  // Don't worry about range checking the value here. That's handled by
5146  // the is*() predicates.
5147  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5148  ARM_AM::no_shift, 0, Align,
5149  false, S, E, AlignmentLoc));
5150 
5151  // If there's a pre-indexing writeback marker, '!', just add it as a token
5152  // operand.
5153  if (Parser.getTok().is(AsmToken::Exclaim)) {
5154  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5155  Parser.Lex(); // Eat the '!'.
5156  }
5157 
5158  return false;
5159  }
5160 
5161  // If we have a '#', it's an immediate offset, else assume it's a register
5162  // offset. Be friendly and also accept a plain integer (without a leading
5163  // hash) for gas compatibility.
5164  if (Parser.getTok().is(AsmToken::Hash) ||
5165  Parser.getTok().is(AsmToken::Dollar) ||
5166  Parser.getTok().is(AsmToken::Integer)) {
5167  if (Parser.getTok().isNot(AsmToken::Integer))
5168  Parser.Lex(); // Eat '#' or '$'.
5169  E = Parser.getTok().getLoc();
5170 
5171  bool isNegative = getParser().getTok().is(AsmToken::Minus);
5172  const MCExpr *Offset;
5173  if (getParser().parseExpression(Offset))
5174  return true;
5175 
5176  // The expression has to be a constant. Memory references with relocations
5177  // don't come through here, as they use the <label> forms of the relevant
5178  // instructions.
5180  if (!CE)
5181  return Error (E, "constant expression expected");
5182 
5183  // If the constant was #-0, represent it as
5184  // std::numeric_limits<int32_t>::min().
5185  int32_t Val = CE->getValue();
5186  if (isNegative && Val == 0)
5187  CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5188  getContext());
5189 
5190  // Now we should have the closing ']'
5191  if (Parser.getTok().isNot(AsmToken::RBrac))
5192  return Error(Parser.getTok().getLoc(), "']' expected");
5193  E = Parser.getTok().getEndLoc();
5194  Parser.Lex(); // Eat right bracket token.
5195 
5196  // Don't worry about range checking the value here. That's handled by
5197  // the is*() predicates.
5198  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5199  ARM_AM::no_shift, 0, 0,
5200  false, S, E));
5201 
5202  // If there's a pre-indexing writeback marker, '!', just add it as a token
5203  // operand.
5204  if (Parser.getTok().is(AsmToken::Exclaim)) {
5205  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5206  Parser.Lex(); // Eat the '!'.
5207  }
5208 
5209  return false;
5210  }
5211 
5212  // The register offset is optionally preceded by a '+' or '-'
5213  bool isNegative = false;
5214  if (Parser.getTok().is(AsmToken::Minus)) {
5215  isNegative = true;
5216  Parser.Lex(); // Eat the '-'.
5217  } else if (Parser.getTok().is(AsmToken::Plus)) {
5218  // Nothing to do.
5219  Parser.Lex(); // Eat the '+'.
5220  }
5221 
5222  E = Parser.getTok().getLoc();
5223  int OffsetRegNum = tryParseRegister();
5224  if (OffsetRegNum == -1)
5225  return Error(E, "register expected");
5226 
5227  // If there's a shift operator, handle it.
5228  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5229  unsigned ShiftImm = 0;
5230  if (Parser.getTok().is(AsmToken::Comma)) {
5231  Parser.Lex(); // Eat the ','.
5232  if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5233  return true;
5234  }
5235 
5236  // Now we should have the closing ']'
5237  if (Parser.getTok().isNot(AsmToken::RBrac))
5238  return Error(Parser.getTok().getLoc(), "']' expected");
5239  E = Parser.getTok().getEndLoc();
5240  Parser.Lex(); // Eat right bracket token.
5241 
5242  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5243  ShiftType, ShiftImm, 0, isNegative,
5244  S, E));
5245 
5246  // If there's a pre-indexing writeback marker, '!', just add it as a token
5247  // operand.
5248  if (Parser.getTok().is(AsmToken::Exclaim)) {
5249  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5250  Parser.Lex(); // Eat the '!'.
5251  }
5252 
5253  return false;
5254 }
5255 
5256 /// parseMemRegOffsetShift - one of these two:
5257 /// ( lsl | lsr | asr | ror ) , # shift_amount
5258 /// rrx
5259 /// return true if it parses a shift otherwise it returns false.
5260 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5261  unsigned &Amount) {
5262  MCAsmParser &Parser = getParser();
5263  SMLoc Loc = Parser.getTok().getLoc();
5264  const AsmToken &Tok = Parser.getTok();
5265  if (Tok.isNot(AsmToken::Identifier))
5266  return Error(Loc, "illegal shift operator");
5267  StringRef ShiftName = Tok.getString();
5268  if (ShiftName == "lsl" || ShiftName == "LSL" ||
5269  ShiftName == "asl" || ShiftName == "ASL")
5270  St = ARM_AM::lsl;
5271  else if (ShiftName == "lsr" || ShiftName == "LSR")
5272  St = ARM_AM::lsr;
5273  else if (ShiftName == "asr" || ShiftName == "ASR")
5274  St = ARM_AM::asr;
5275  else if (ShiftName == "ror" || ShiftName == "ROR")
5276  St = ARM_AM::ror;
5277  else if (ShiftName == "rrx" || ShiftName == "RRX")
5278  St = ARM_AM::rrx;
5279  else
5280  return Error(Loc, "illegal shift operator");
5281  Parser.Lex(); // Eat shift type token.
5282 
5283  // rrx stands alone.
5284  Amount = 0;
5285  if (St != ARM_AM::rrx) {
5286  Loc = Parser.getTok().getLoc();
5287  // A '#' and a shift amount.
5288  const AsmToken &HashTok = Parser.getTok();
5289  if (HashTok.isNot(AsmToken::Hash) &&
5290  HashTok.isNot(AsmToken::Dollar))
5291  return Error(HashTok.getLoc(), "'#' expected");
5292  Parser.Lex(); // Eat hash token.
5293 
5294  const MCExpr *Expr;
5295  if (getParser().parseExpression(Expr))
5296  return true;
5297  // Range check the immediate.
5298  // lsl, ror: 0 <= imm <= 31
5299  // lsr, asr: 0 <= imm <= 32
5300  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5301  if (!CE)
5302  return Error(Loc, "shift amount must be an immediate");
5303  int64_t Imm = CE->getValue();
5304  if (Imm < 0 ||
5305  ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5306  ((St ==