LLVM  9.0.0svn
MipsAsmParser.cpp
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1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include "MipsTargetStreamer.h"
16 #include "llvm/ADT/APFloat.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSectionELF.h"
36 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCSymbolELF.h"
40 #include "llvm/MC/MCValue.h"
42 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/SMLoc.h"
49 #include "llvm/Support/SourceMgr.h"
52 #include <algorithm>
53 #include <cassert>
54 #include <cstdint>
55 #include <memory>
56 #include <string>
57 #include <utility>
58 
59 using namespace llvm;
60 
61 #define DEBUG_TYPE "mips-asm-parser"
62 
63 namespace llvm {
64 
65 class MCInstrInfo;
66 
67 } // end namespace llvm
68 
70 
71 namespace {
72 
73 class MipsAssemblerOptions {
74 public:
75  MipsAssemblerOptions(const FeatureBitset &Features_) : Features(Features_) {}
76 
77  MipsAssemblerOptions(const MipsAssemblerOptions *Opts) {
78  ATReg = Opts->getATRegIndex();
79  Reorder = Opts->isReorder();
80  Macro = Opts->isMacro();
81  Features = Opts->getFeatures();
82  }
83 
84  unsigned getATRegIndex() const { return ATReg; }
85  bool setATRegIndex(unsigned Reg) {
86  if (Reg > 31)
87  return false;
88 
89  ATReg = Reg;
90  return true;
91  }
92 
93  bool isReorder() const { return Reorder; }
94  void setReorder() { Reorder = true; }
95  void setNoReorder() { Reorder = false; }
96 
97  bool isMacro() const { return Macro; }
98  void setMacro() { Macro = true; }
99  void setNoMacro() { Macro = false; }
100 
101  const FeatureBitset &getFeatures() const { return Features; }
102  void setFeatures(const FeatureBitset &Features_) { Features = Features_; }
103 
104  // Set of features that are either architecture features or referenced
105  // by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6).
106  // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
107  // The reason we need this mask is explained in the selectArch function.
108  // FIXME: Ideally we would like TableGen to generate this information.
109  static const FeatureBitset AllArchRelatedMask;
110 
111 private:
112  unsigned ATReg = 1;
113  bool Reorder = true;
114  bool Macro = true;
115  FeatureBitset Features;
116 };
117 
118 } // end anonymous namespace
119 
120 const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
121  Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
122  Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
123  Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
124  Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
125  Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
126  Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
127  Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
128  Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
129 };
130 
131 namespace {
132 
133 class MipsAsmParser : public MCTargetAsmParser {
134  MipsTargetStreamer &getTargetStreamer() {
135  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
136  return static_cast<MipsTargetStreamer &>(TS);
137  }
138 
141  MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
142  // nullptr, which indicates that no function is currently
143  // selected. This usually happens after an '.end func'
144  // directive.
145  bool IsLittleEndian;
146  bool IsPicEnabled;
147  bool IsCpRestoreSet;
148  int CpRestoreOffset;
149  unsigned CpSaveLocation;
150  /// If true, then CpSaveLocation is a register, otherwise it's an offset.
151  bool CpSaveLocationIsRegister;
152 
153  // Map of register aliases created via the .set directive.
154  StringMap<AsmToken> RegisterSets;
155 
156  // Print a warning along with its fix-it message at the given range.
157  void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
158  SMRange Range, bool ShowColors = true);
159 
160  void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);
161 
162 #define GET_ASSEMBLER_HEADER
163 #include "MipsGenAsmMatcher.inc"
164 
165  unsigned
166  checkEarlyTargetMatchPredicate(MCInst &Inst,
167  const OperandVector &Operands) override;
168  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
169 
170  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
171  OperandVector &Operands, MCStreamer &Out,
172  uint64_t &ErrorInfo,
173  bool MatchingInlineAsm) override;
174 
175  /// Parse a register as used in CFI directives
176  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
177 
178  bool parseParenSuffix(StringRef Name, OperandVector &Operands);
179 
180  bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
181 
182  bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
183 
184  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
185  SMLoc NameLoc, OperandVector &Operands) override;
186 
187  bool ParseDirective(AsmToken DirectiveID) override;
188 
189  OperandMatchResultTy parseMemOperand(OperandVector &Operands);
191  matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
192  StringRef Identifier, SMLoc S);
193  OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
194  const AsmToken &Token,
195  SMLoc S);
196  OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
197  SMLoc S);
198  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
199  OperandMatchResultTy parseImm(OperandVector &Operands);
200  OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
201  OperandMatchResultTy parseInvNum(OperandVector &Operands);
202  OperandMatchResultTy parseRegisterList(OperandVector &Operands);
203 
204  bool searchSymbolAlias(OperandVector &Operands);
205 
206  bool parseOperand(OperandVector &, StringRef Mnemonic);
207 
208  enum MacroExpanderResultTy {
209  MER_NotAMacro,
210  MER_Success,
211  MER_Fail,
212  };
213 
214  // Expands assembly pseudo instructions.
215  MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
216  MCStreamer &Out,
217  const MCSubtargetInfo *STI);
218 
219  bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
220  const MCSubtargetInfo *STI);
221 
222  bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
223  bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
224  MCStreamer &Out, const MCSubtargetInfo *STI);
225 
226  bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
227  unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
228  MCStreamer &Out, const MCSubtargetInfo *STI);
229 
230  bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
231 
232  bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
233  MCStreamer &Out, const MCSubtargetInfo *STI);
234 
235  bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
236  SMLoc IDLoc, MCStreamer &Out,
237  const MCSubtargetInfo *STI);
238 
239  bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
240  const MCOperand &Offset, bool Is32BitAddress,
241  SMLoc IDLoc, MCStreamer &Out,
242  const MCSubtargetInfo *STI);
243 
244  bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
245  const MCSubtargetInfo *STI);
246 
247  void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
248  const MCSubtargetInfo *STI, bool IsLoad);
249 
250  bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
251  const MCSubtargetInfo *STI);
252 
253  bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
254  const MCSubtargetInfo *STI);
255 
256  bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
257  const MCSubtargetInfo *STI);
258 
259  bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
260  const MCSubtargetInfo *STI);
261 
262  bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
263  const MCSubtargetInfo *STI, const bool IsMips64,
264  const bool Signed);
265 
266  bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
267  MCStreamer &Out, const MCSubtargetInfo *STI);
268 
269  bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
270  const MCSubtargetInfo *STI);
271 
272  bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
273  const MCSubtargetInfo *STI);
274 
275  bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
276  const MCSubtargetInfo *STI);
277 
278  bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
279  const MCSubtargetInfo *STI);
280 
281  bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
282  const MCSubtargetInfo *STI);
283 
284  bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
285  const MCSubtargetInfo *STI);
286 
287  bool expandRotation(MCInst &Inst, SMLoc IDLoc,
288  MCStreamer &Out, const MCSubtargetInfo *STI);
289  bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
290  const MCSubtargetInfo *STI);
291  bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
292  const MCSubtargetInfo *STI);
293  bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
294  const MCSubtargetInfo *STI);
295 
296  bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
297  const MCSubtargetInfo *STI);
298 
299  bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
300  const MCSubtargetInfo *STI);
301 
302  bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
303  const MCSubtargetInfo *STI);
304 
305  bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
306  const MCSubtargetInfo *STI);
307 
308  bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
309  const MCSubtargetInfo *STI);
310 
311  bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
312  const MCSubtargetInfo *STI, bool IsLoad);
313 
314  bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
315  const MCSubtargetInfo *STI);
316 
317  bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
318  const MCSubtargetInfo *STI);
319 
320  bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
321  const MCSubtargetInfo *STI);
322 
323  bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
324  const MCSubtargetInfo *STI);
325 
326  bool reportParseError(Twine ErrorMsg);
327  bool reportParseError(SMLoc Loc, Twine ErrorMsg);
328 
329  bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
330 
331  bool isEvaluated(const MCExpr *Expr);
332  bool parseSetMips0Directive();
333  bool parseSetArchDirective();
334  bool parseSetFeature(uint64_t Feature);
335  bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup.
336  bool parseDirectiveCpLoad(SMLoc Loc);
337  bool parseDirectiveCpRestore(SMLoc Loc);
338  bool parseDirectiveCPSetup();
339  bool parseDirectiveCPReturn();
340  bool parseDirectiveNaN();
341  bool parseDirectiveSet();
342  bool parseDirectiveOption();
343  bool parseInsnDirective();
344  bool parseRSectionDirective(StringRef Section);
345  bool parseSSectionDirective(StringRef Section, unsigned Type);
346 
347  bool parseSetAtDirective();
348  bool parseSetNoAtDirective();
349  bool parseSetMacroDirective();
350  bool parseSetNoMacroDirective();
351  bool parseSetMsaDirective();
352  bool parseSetNoMsaDirective();
353  bool parseSetNoDspDirective();
354  bool parseSetReorderDirective();
355  bool parseSetNoReorderDirective();
356  bool parseSetMips16Directive();
357  bool parseSetNoMips16Directive();
358  bool parseSetFpDirective();
359  bool parseSetOddSPRegDirective();
360  bool parseSetNoOddSPRegDirective();
361  bool parseSetPopDirective();
362  bool parseSetPushDirective();
363  bool parseSetSoftFloatDirective();
364  bool parseSetHardFloatDirective();
365  bool parseSetMtDirective();
366  bool parseSetNoMtDirective();
367  bool parseSetNoCRCDirective();
368  bool parseSetNoVirtDirective();
369  bool parseSetNoGINVDirective();
370 
371  bool parseSetAssignment();
372 
373  bool parseDirectiveGpWord();
374  bool parseDirectiveGpDWord();
375  bool parseDirectiveDtpRelWord();
376  bool parseDirectiveDtpRelDWord();
377  bool parseDirectiveTpRelWord();
378  bool parseDirectiveTpRelDWord();
379  bool parseDirectiveModule();
380  bool parseDirectiveModuleFP();
381  bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
382  StringRef Directive);
383 
384  bool parseInternalDirectiveReallowModule();
385 
386  bool eatComma(StringRef ErrorStr);
387 
388  int matchCPURegisterName(StringRef Symbol);
389 
390  int matchHWRegsRegisterName(StringRef Symbol);
391 
392  int matchFPURegisterName(StringRef Name);
393 
394  int matchFCCRegisterName(StringRef Name);
395 
396  int matchACRegisterName(StringRef Name);
397 
398  int matchMSA128RegisterName(StringRef Name);
399 
400  int matchMSA128CtrlRegisterName(StringRef Name);
401 
402  unsigned getReg(int RC, int RegNo);
403 
404  /// Returns the internal register number for the current AT. Also checks if
405  /// the current AT is unavailable (set to $0) and gives an error if it is.
406  /// This should be used in pseudo-instruction expansions which need AT.
407  unsigned getATReg(SMLoc Loc);
408 
409  bool canUseATReg();
410 
411  bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
412  const MCSubtargetInfo *STI);
413 
414  // Helper function that checks if the value of a vector index is within the
415  // boundaries of accepted values for each RegisterKind
416  // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
417  bool validateMSAIndex(int Val, int RegKind);
418 
419  // Selects a new architecture by updating the FeatureBits with the necessary
420  // info including implied dependencies.
421  // Internally, it clears all the feature bits related to *any* architecture
422  // and selects the new one using the ToggleFeature functionality of the
423  // MCSubtargetInfo object that handles implied dependencies. The reason we
424  // clear all the arch related bits manually is because ToggleFeature only
425  // clears the features that imply the feature being cleared and not the
426  // features implied by the feature being cleared. This is easier to see
427  // with an example:
428  // --------------------------------------------------
429  // | Feature | Implies |
430  // | -------------------------------------------------|
431  // | FeatureMips1 | None |
432  // | FeatureMips2 | FeatureMips1 |
433  // | FeatureMips3 | FeatureMips2 | FeatureMipsGP64 |
434  // | FeatureMips4 | FeatureMips3 |
435  // | ... | |
436  // --------------------------------------------------
437  //
438  // Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 |
439  // FeatureMipsGP64 | FeatureMips1)
440  // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
441  void selectArch(StringRef ArchFeature) {
442  MCSubtargetInfo &STI = copySTI();
443  FeatureBitset FeatureBits = STI.getFeatureBits();
444  FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
445  STI.setFeatureBits(FeatureBits);
446  setAvailableFeatures(
447  ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
448  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
449  }
450 
451  void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
452  if (!(getSTI().getFeatureBits()[Feature])) {
453  MCSubtargetInfo &STI = copySTI();
454  setAvailableFeatures(
455  ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
456  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
457  }
458  }
459 
460  void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
461  if (getSTI().getFeatureBits()[Feature]) {
462  MCSubtargetInfo &STI = copySTI();
463  setAvailableFeatures(
464  ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
465  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
466  }
467  }
468 
469  void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
470  setFeatureBits(Feature, FeatureString);
471  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
472  }
473 
474  void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
475  clearFeatureBits(Feature, FeatureString);
476  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
477  }
478 
479 public:
480  enum MipsMatchResultTy {
481  Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
482  Match_RequiresDifferentOperands,
483  Match_RequiresNoZeroRegister,
484  Match_RequiresSameSrcAndDst,
485  Match_NoFCCRegisterForCurrentISA,
486  Match_NonZeroOperandForSync,
487  Match_NonZeroOperandForMTCX,
488  Match_RequiresPosSizeRange0_32,
489  Match_RequiresPosSizeRange33_64,
490  Match_RequiresPosSizeUImm6,
491 #define GET_OPERAND_DIAGNOSTIC_TYPES
492 #include "MipsGenAsmMatcher.inc"
493 #undef GET_OPERAND_DIAGNOSTIC_TYPES
494  };
495 
496  MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
497  const MCInstrInfo &MII, const MCTargetOptions &Options)
498  : MCTargetAsmParser(Options, sti, MII),
499  ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
500  sti.getCPU(), Options)) {
502 
503  parser.addAliasForDirective(".asciiz", ".asciz");
504  parser.addAliasForDirective(".hword", ".2byte");
505  parser.addAliasForDirective(".word", ".4byte");
506  parser.addAliasForDirective(".dword", ".8byte");
507 
508  // Initialize the set of available features.
509  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
510 
511  // Remember the initial assembler options. The user can not modify these.
512  AssemblerOptions.push_back(
513  llvm::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
514 
515  // Create an assembler options environment for the user to modify.
516  AssemblerOptions.push_back(
517  llvm::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
518 
519  getTargetStreamer().updateABIInfo(*this);
520 
521  if (!isABI_O32() && !useOddSPReg() != 0)
522  report_fatal_error("-mno-odd-spreg requires the O32 ABI");
523 
524  CurrentFn = nullptr;
525 
526  IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
527 
528  IsCpRestoreSet = false;
529  CpRestoreOffset = -1;
530 
531  const Triple &TheTriple = sti.getTargetTriple();
532  IsLittleEndian = TheTriple.isLittleEndian();
533 
534  if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
535  report_fatal_error("microMIPS64R6 is not supported", false);
536 
537  if (!isABI_O32() && inMicroMipsMode())
538  report_fatal_error("microMIPS64 is not supported", false);
539  }
540 
541  /// True if all of $fcc0 - $fcc7 exist for the current ISA.
542  bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
543 
544  bool isGP64bit() const {
545  return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
546  }
547 
548  bool isFP64bit() const {
549  return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
550  }
551 
552  const MipsABIInfo &getABI() const { return ABI; }
553  bool isABI_N32() const { return ABI.IsN32(); }
554  bool isABI_N64() const { return ABI.IsN64(); }
555  bool isABI_O32() const { return ABI.IsO32(); }
556  bool isABI_FPXX() const {
557  return getSTI().getFeatureBits()[Mips::FeatureFPXX];
558  }
559 
560  bool useOddSPReg() const {
561  return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
562  }
563 
564  bool inMicroMipsMode() const {
565  return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
566  }
567 
568  bool hasMips1() const {
569  return getSTI().getFeatureBits()[Mips::FeatureMips1];
570  }
571 
572  bool hasMips2() const {
573  return getSTI().getFeatureBits()[Mips::FeatureMips2];
574  }
575 
576  bool hasMips3() const {
577  return getSTI().getFeatureBits()[Mips::FeatureMips3];
578  }
579 
580  bool hasMips4() const {
581  return getSTI().getFeatureBits()[Mips::FeatureMips4];
582  }
583 
584  bool hasMips5() const {
585  return getSTI().getFeatureBits()[Mips::FeatureMips5];
586  }
587 
588  bool hasMips32() const {
589  return getSTI().getFeatureBits()[Mips::FeatureMips32];
590  }
591 
592  bool hasMips64() const {
593  return getSTI().getFeatureBits()[Mips::FeatureMips64];
594  }
595 
596  bool hasMips32r2() const {
597  return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
598  }
599 
600  bool hasMips64r2() const {
601  return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
602  }
603 
604  bool hasMips32r3() const {
605  return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
606  }
607 
608  bool hasMips64r3() const {
609  return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
610  }
611 
612  bool hasMips32r5() const {
613  return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
614  }
615 
616  bool hasMips64r5() const {
617  return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
618  }
619 
620  bool hasMips32r6() const {
621  return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
622  }
623 
624  bool hasMips64r6() const {
625  return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
626  }
627 
628  bool hasDSP() const {
629  return getSTI().getFeatureBits()[Mips::FeatureDSP];
630  }
631 
632  bool hasDSPR2() const {
633  return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
634  }
635 
636  bool hasDSPR3() const {
637  return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
638  }
639 
640  bool hasMSA() const {
641  return getSTI().getFeatureBits()[Mips::FeatureMSA];
642  }
643 
644  bool hasCnMips() const {
645  return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
646  }
647 
648  bool inPicMode() {
649  return IsPicEnabled;
650  }
651 
652  bool inMips16Mode() const {
653  return getSTI().getFeatureBits()[Mips::FeatureMips16];
654  }
655 
656  bool useTraps() const {
657  return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
658  }
659 
660  bool useSoftFloat() const {
661  return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
662  }
663  bool hasMT() const {
664  return getSTI().getFeatureBits()[Mips::FeatureMT];
665  }
666 
667  bool hasCRC() const {
668  return getSTI().getFeatureBits()[Mips::FeatureCRC];
669  }
670 
671  bool hasVirt() const {
672  return getSTI().getFeatureBits()[Mips::FeatureVirt];
673  }
674 
675  bool hasGINV() const {
676  return getSTI().getFeatureBits()[Mips::FeatureGINV];
677  }
678 
679  /// Warn if RegIndex is the same as the current AT.
680  void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
681 
682  void warnIfNoMacro(SMLoc Loc);
683 
684  bool isLittle() const { return IsLittleEndian; }
685 
686  const MCExpr *createTargetUnaryExpr(const MCExpr *E,
687  AsmToken::TokenKind OperatorToken,
688  MCContext &Ctx) override {
689  switch(OperatorToken) {
690  default:
691  llvm_unreachable("Unknown token");
692  return nullptr;
704  return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx);
719  case AsmToken::PercentHi:
720  return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx);
725  case AsmToken::PercentLo:
726  return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx);
728  return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx);
741  }
742  }
743 };
744 
745 /// MipsOperand - Instances of this class represent a parsed Mips machine
746 /// instruction.
747 class MipsOperand : public MCParsedAsmOperand {
748 public:
749  /// Broad categories of register classes
750  /// The exact class is finalized by the render method.
751  enum RegKind {
752  RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64bit())
753  RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
754  /// isFP64bit())
755  RegKind_FCC = 4, /// FCC
756  RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
757  RegKind_MSACtrl = 16, /// MSA control registers
758  RegKind_COP2 = 32, /// COP2
759  RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
760  /// context).
761  RegKind_CCR = 128, /// CCR
762  RegKind_HWRegs = 256, /// HWRegs
763  RegKind_COP3 = 512, /// COP3
764  RegKind_COP0 = 1024, /// COP0
765  /// Potentially any (e.g. $1)
766  RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
767  RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
768  RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
769  };
770 
771 private:
772  enum KindTy {
773  k_Immediate, /// An immediate (possibly involving symbol references)
774  k_Memory, /// Base + Offset Memory Address
775  k_RegisterIndex, /// A register index in one or more RegKind.
776  k_Token, /// A simple token
777  k_RegList, /// A physical register list
778  } Kind;
779 
780 public:
781  MipsOperand(KindTy K, MipsAsmParser &Parser)
782  : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
783 
784  ~MipsOperand() override {
785  switch (Kind) {
786  case k_Memory:
787  delete Mem.Base;
788  break;
789  case k_RegList:
790  delete RegList.List;
791  break;
792  case k_Immediate:
793  case k_RegisterIndex:
794  case k_Token:
795  break;
796  }
797  }
798 
799 private:
800  /// For diagnostics, and checking the assembler temporary
801  MipsAsmParser &AsmParser;
802 
803  struct Token {
804  const char *Data;
805  unsigned Length;
806  };
807 
808  struct RegIdxOp {
809  unsigned Index; /// Index into the register class
810  RegKind Kind; /// Bitfield of the kinds it could possibly be
811  struct Token Tok; /// The input token this operand originated from.
812  const MCRegisterInfo *RegInfo;
813  };
814 
815  struct ImmOp {
816  const MCExpr *Val;
817  };
818 
819  struct MemOp {
820  MipsOperand *Base;
821  const MCExpr *Off;
822  };
823 
824  struct RegListOp {
826  };
827 
828  union {
829  struct Token Tok;
830  struct RegIdxOp RegIdx;
831  struct ImmOp Imm;
832  struct MemOp Mem;
833  struct RegListOp RegList;
834  };
835 
836  SMLoc StartLoc, EndLoc;
837 
838  /// Internal constructor for register kinds
839  static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str,
841  const MCRegisterInfo *RegInfo,
842  SMLoc S, SMLoc E,
843  MipsAsmParser &Parser) {
844  auto Op = llvm::make_unique<MipsOperand>(k_RegisterIndex, Parser);
845  Op->RegIdx.Index = Index;
846  Op->RegIdx.RegInfo = RegInfo;
847  Op->RegIdx.Kind = RegKind;
848  Op->RegIdx.Tok.Data = Str.data();
849  Op->RegIdx.Tok.Length = Str.size();
850  Op->StartLoc = S;
851  Op->EndLoc = E;
852  return Op;
853  }
854 
855 public:
856  /// Coerce the register to GPR32 and return the real register for the current
857  /// target.
858  unsigned getGPR32Reg() const {
859  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
860  AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
861  unsigned ClassID = Mips::GPR32RegClassID;
862  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
863  }
864 
865  /// Coerce the register to GPR32 and return the real register for the current
866  /// target.
867  unsigned getGPRMM16Reg() const {
868  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
869  unsigned ClassID = Mips::GPR32RegClassID;
870  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
871  }
872 
873  /// Coerce the register to GPR64 and return the real register for the current
874  /// target.
875  unsigned getGPR64Reg() const {
876  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
877  unsigned ClassID = Mips::GPR64RegClassID;
878  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
879  }
880 
881 private:
882  /// Coerce the register to AFGR64 and return the real register for the current
883  /// target.
884  unsigned getAFGR64Reg() const {
885  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
886  if (RegIdx.Index % 2 != 0)
887  AsmParser.Warning(StartLoc, "Float register should be even.");
888  return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
889  .getRegister(RegIdx.Index / 2);
890  }
891 
892  /// Coerce the register to FGR64 and return the real register for the current
893  /// target.
894  unsigned getFGR64Reg() const {
895  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
896  return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
897  .getRegister(RegIdx.Index);
898  }
899 
900  /// Coerce the register to FGR32 and return the real register for the current
901  /// target.
902  unsigned getFGR32Reg() const {
903  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
904  return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
905  .getRegister(RegIdx.Index);
906  }
907 
908  /// Coerce the register to FCC and return the real register for the current
909  /// target.
910  unsigned getFCCReg() const {
911  assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
912  return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
913  .getRegister(RegIdx.Index);
914  }
915 
916  /// Coerce the register to MSA128 and return the real register for the current
917  /// target.
918  unsigned getMSA128Reg() const {
919  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
920  // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
921  // identical
922  unsigned ClassID = Mips::MSA128BRegClassID;
923  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
924  }
925 
926  /// Coerce the register to MSACtrl and return the real register for the
927  /// current target.
928  unsigned getMSACtrlReg() const {
929  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
930  unsigned ClassID = Mips::MSACtrlRegClassID;
931  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
932  }
933 
934  /// Coerce the register to COP0 and return the real register for the
935  /// current target.
936  unsigned getCOP0Reg() const {
937  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
938  unsigned ClassID = Mips::COP0RegClassID;
939  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
940  }
941 
942  /// Coerce the register to COP2 and return the real register for the
943  /// current target.
944  unsigned getCOP2Reg() const {
945  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
946  unsigned ClassID = Mips::COP2RegClassID;
947  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
948  }
949 
950  /// Coerce the register to COP3 and return the real register for the
951  /// current target.
952  unsigned getCOP3Reg() const {
953  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
954  unsigned ClassID = Mips::COP3RegClassID;
955  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
956  }
957 
958  /// Coerce the register to ACC64DSP and return the real register for the
959  /// current target.
960  unsigned getACC64DSPReg() const {
961  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
962  unsigned ClassID = Mips::ACC64DSPRegClassID;
963  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
964  }
965 
966  /// Coerce the register to HI32DSP and return the real register for the
967  /// current target.
968  unsigned getHI32DSPReg() const {
969  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
970  unsigned ClassID = Mips::HI32DSPRegClassID;
971  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
972  }
973 
974  /// Coerce the register to LO32DSP and return the real register for the
975  /// current target.
976  unsigned getLO32DSPReg() const {
977  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
978  unsigned ClassID = Mips::LO32DSPRegClassID;
979  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
980  }
981 
982  /// Coerce the register to CCR and return the real register for the
983  /// current target.
984  unsigned getCCRReg() const {
985  assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
986  unsigned ClassID = Mips::CCRRegClassID;
987  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
988  }
989 
990  /// Coerce the register to HWRegs and return the real register for the
991  /// current target.
992  unsigned getHWRegsReg() const {
993  assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
994  unsigned ClassID = Mips::HWRegsRegClassID;
995  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
996  }
997 
998 public:
999  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1000  // Add as immediate when possible. Null MCExpr = 0.
1001  if (!Expr)
1003  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1004  Inst.addOperand(MCOperand::createImm(CE->getValue()));
1005  else
1006  Inst.addOperand(MCOperand::createExpr(Expr));
1007  }
1008 
1009  void addRegOperands(MCInst &Inst, unsigned N) const {
1010  llvm_unreachable("Use a custom parser instead");
1011  }
1012 
1013  /// Render the operand to an MCInst as a GPR32
1014  /// Asserts if the wrong number of operands are requested, or the operand
1015  /// is not a k_RegisterIndex compatible with RegKind_GPR
1016  void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1017  assert(N == 1 && "Invalid number of operands!");
1018  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1019  }
1020 
1021  void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1022  assert(N == 1 && "Invalid number of operands!");
1023  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1024  }
1025 
1026  void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1027  assert(N == 1 && "Invalid number of operands!");
1028  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1029  }
1030 
1031  void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
1032  assert(N == 1 && "Invalid number of operands!");
1033  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1034  }
1035 
1036  void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
1037  assert(N == 1 && "Invalid number of operands!");
1038  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1039  }
1040 
1041  void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
1042  assert(N == 1 && "Invalid number of operands!");
1043  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1044  }
1045 
1046  void addGPRMM16AsmRegMovePPairFirstOperands(MCInst &Inst, unsigned N) const {
1047  assert(N == 1 && "Invalid number of operands!");
1048  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1049  }
1050 
1051  void addGPRMM16AsmRegMovePPairSecondOperands(MCInst &Inst,
1052  unsigned N) const {
1053  assert(N == 1 && "Invalid number of operands!");
1054  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1055  }
1056 
1057  /// Render the operand to an MCInst as a GPR64
1058  /// Asserts if the wrong number of operands are requested, or the operand
1059  /// is not a k_RegisterIndex compatible with RegKind_GPR
1060  void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1061  assert(N == 1 && "Invalid number of operands!");
1062  Inst.addOperand(MCOperand::createReg(getGPR64Reg()));
1063  }
1064 
1065  void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1066  assert(N == 1 && "Invalid number of operands!");
1067  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
1068  }
1069 
1070  void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1071  assert(N == 1 && "Invalid number of operands!");
1072  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
1073  }
1074 
1075  void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1076  assert(N == 1 && "Invalid number of operands!");
1077  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
1078  }
1079 
1080  void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1081  assert(N == 1 && "Invalid number of operands!");
1082  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
1083  }
1084 
1085  void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1086  assert(N == 1 && "Invalid number of operands!");
1087  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
1088  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1089  // FIXME: This should propagate failure up to parseStatement.
1090  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
1091  AsmParser.getParser().printError(
1092  StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1093  "registers");
1094  }
1095 
1096  void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1097  assert(N == 1 && "Invalid number of operands!");
1098  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
1099  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1100  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
1101  AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1102  "registers");
1103  }
1104 
1105  void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
1106  assert(N == 1 && "Invalid number of operands!");
1107  Inst.addOperand(MCOperand::createReg(getFCCReg()));
1108  }
1109 
1110  void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
1111  assert(N == 1 && "Invalid number of operands!");
1112  Inst.addOperand(MCOperand::createReg(getMSA128Reg()));
1113  }
1114 
1115  void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
1116  assert(N == 1 && "Invalid number of operands!");
1117  Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
1118  }
1119 
1120  void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
1121  assert(N == 1 && "Invalid number of operands!");
1122  Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
1123  }
1124 
1125  void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
1126  assert(N == 1 && "Invalid number of operands!");
1127  Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
1128  }
1129 
1130  void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
1131  assert(N == 1 && "Invalid number of operands!");
1132  Inst.addOperand(MCOperand::createReg(getCOP3Reg()));
1133  }
1134 
1135  void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1136  assert(N == 1 && "Invalid number of operands!");
1137  Inst.addOperand(MCOperand::createReg(getACC64DSPReg()));
1138  }
1139 
1140  void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1141  assert(N == 1 && "Invalid number of operands!");
1142  Inst.addOperand(MCOperand::createReg(getHI32DSPReg()));
1143  }
1144 
1145  void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1146  assert(N == 1 && "Invalid number of operands!");
1147  Inst.addOperand(MCOperand::createReg(getLO32DSPReg()));
1148  }
1149 
1150  void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
1151  assert(N == 1 && "Invalid number of operands!");
1152  Inst.addOperand(MCOperand::createReg(getCCRReg()));
1153  }
1154 
1155  void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
1156  assert(N == 1 && "Invalid number of operands!");
1157  Inst.addOperand(MCOperand::createReg(getHWRegsReg()));
1158  }
1159 
1160  template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
1161  void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
1162  assert(N == 1 && "Invalid number of operands!");
1163  uint64_t Imm = getConstantImm() - Offset;
1164  Imm &= (1ULL << Bits) - 1;
1165  Imm += Offset;
1166  Imm += AdjustOffset;
1167  Inst.addOperand(MCOperand::createImm(Imm));
1168  }
1169 
1170  template <unsigned Bits>
1171  void addSImmOperands(MCInst &Inst, unsigned N) const {
1172  if (isImm() && !isConstantImm()) {
1173  addExpr(Inst, getImm());
1174  return;
1175  }
1176  addConstantSImmOperands<Bits, 0, 0>(Inst, N);
1177  }
1178 
1179  template <unsigned Bits>
1180  void addUImmOperands(MCInst &Inst, unsigned N) const {
1181  if (isImm() && !isConstantImm()) {
1182  addExpr(Inst, getImm());
1183  return;
1184  }
1185  addConstantUImmOperands<Bits, 0, 0>(Inst, N);
1186  }
1187 
1188  template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
1189  void addConstantSImmOperands(MCInst &Inst, unsigned N) const {
1190  assert(N == 1 && "Invalid number of operands!");
1191  int64_t Imm = getConstantImm() - Offset;
1192  Imm = SignExtend64<Bits>(Imm);
1193  Imm += Offset;
1194  Imm += AdjustOffset;
1195  Inst.addOperand(MCOperand::createImm(Imm));
1196  }
1197 
1198  void addImmOperands(MCInst &Inst, unsigned N) const {
1199  assert(N == 1 && "Invalid number of operands!");
1200  const MCExpr *Expr = getImm();
1201  addExpr(Inst, Expr);
1202  }
1203 
1204  void addMemOperands(MCInst &Inst, unsigned N) const {
1205  assert(N == 2 && "Invalid number of operands!");
1206 
1207  Inst.addOperand(MCOperand::createReg(AsmParser.getABI().ArePtrs64bit()
1208  ? getMemBase()->getGPR64Reg()
1209  : getMemBase()->getGPR32Reg()));
1210 
1211  const MCExpr *Expr = getMemOff();
1212  addExpr(Inst, Expr);
1213  }
1214 
1215  void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const {
1216  assert(N == 2 && "Invalid number of operands!");
1217 
1218  Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));
1219 
1220  const MCExpr *Expr = getMemOff();
1221  addExpr(Inst, Expr);
1222  }
1223 
1224  void addRegListOperands(MCInst &Inst, unsigned N) const {
1225  assert(N == 1 && "Invalid number of operands!");
1226 
1227  for (auto RegNo : getRegList())
1228  Inst.addOperand(MCOperand::createReg(RegNo));
1229  }
1230 
1231  bool isReg() const override {
1232  // As a special case until we sort out the definition of div/divu, accept
1233  // $0/$zero here so that MCK_ZERO works correctly.
1234  return isGPRAsmReg() && RegIdx.Index == 0;
1235  }
1236 
1237  bool isRegIdx() const { return Kind == k_RegisterIndex; }
1238  bool isImm() const override { return Kind == k_Immediate; }
1239 
1240  bool isConstantImm() const {
1241  int64_t Res;
1242  return isImm() && getImm()->evaluateAsAbsolute(Res);
1243  }
1244 
1245  bool isConstantImmz() const {
1246  return isConstantImm() && getConstantImm() == 0;
1247  }
1248 
1249  template <unsigned Bits, int Offset = 0> bool isConstantUImm() const {
1250  return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
1251  }
1252 
1253  template <unsigned Bits> bool isSImm() const {
1254  return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
1255  }
1256 
1257  template <unsigned Bits> bool isUImm() const {
1258  return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm();
1259  }
1260 
1261  template <unsigned Bits> bool isAnyImm() const {
1262  return isConstantImm() ? (isInt<Bits>(getConstantImm()) ||
1263  isUInt<Bits>(getConstantImm()))
1264  : isImm();
1265  }
1266 
1267  template <unsigned Bits, int Offset = 0> bool isConstantSImm() const {
1268  return isConstantImm() && isInt<Bits>(getConstantImm() - Offset);
1269  }
1270 
1271  template <unsigned Bottom, unsigned Top> bool isConstantUImmRange() const {
1272  return isConstantImm() && getConstantImm() >= Bottom &&
1273  getConstantImm() <= Top;
1274  }
1275 
1276  bool isToken() const override {
1277  // Note: It's not possible to pretend that other operand kinds are tokens.
1278  // The matcher emitter checks tokens first.
1279  return Kind == k_Token;
1280  }
1281 
1282  bool isMem() const override { return Kind == k_Memory; }
1283 
1284  bool isConstantMemOff() const {
1285  return isMem() && isa<MCConstantExpr>(getMemOff());
1286  }
1287 
1288  // Allow relocation operators.
1289  // FIXME: This predicate and others need to look through binary expressions
1290  // and determine whether a Value is a constant or not.
1291  template <unsigned Bits, unsigned ShiftAmount = 0>
1292  bool isMemWithSimmOffset() const {
1293  if (!isMem())
1294  return false;
1295  if (!getMemBase()->isGPRAsmReg())
1296  return false;
1297  if (isa<MCTargetExpr>(getMemOff()) ||
1298  (isConstantMemOff() &&
1299  isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1300  return true;
1301  MCValue Res;
1302  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1303  return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
1304  }
1305 
1306  bool isMemWithPtrSizeOffset() const {
1307  if (!isMem())
1308  return false;
1309  if (!getMemBase()->isGPRAsmReg())
1310  return false;
1311  const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32;
1312  if (isa<MCTargetExpr>(getMemOff()) ||
1313  (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
1314  return true;
1315  MCValue Res;
1316  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1317  return IsReloc && isIntN(PtrBits, Res.getConstant());
1318  }
1319 
1320  bool isMemWithGRPMM16Base() const {
1321  return isMem() && getMemBase()->isMM16AsmReg();
1322  }
1323 
1324  template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
1325  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
1326  && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1327  }
1328 
1329  template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const {
1330  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
1331  && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1332  && (getMemBase()->getGPR32Reg() == Mips::SP);
1333  }
1334 
1335  template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const {
1336  return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
1337  && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1338  && (getMemBase()->getGPR32Reg() == Mips::GP);
1339  }
1340 
1341  template <unsigned Bits, unsigned ShiftLeftAmount>
1342  bool isScaledUImm() const {
1343  return isConstantImm() &&
1344  isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm());
1345  }
1346 
1347  template <unsigned Bits, unsigned ShiftLeftAmount>
1348  bool isScaledSImm() const {
1349  if (isConstantImm() &&
1350  isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))
1351  return true;
1352  // Operand can also be a symbol or symbol plus
1353  // offset in case of relocations.
1354  if (Kind != k_Immediate)
1355  return false;
1356  MCValue Res;
1357  bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
1358  return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());
1359  }
1360 
1361  bool isRegList16() const {
1362  if (!isRegList())
1363  return false;
1364 
1365  int Size = RegList.List->size();
1366  if (Size < 2 || Size > 5)
1367  return false;
1368 
1369  unsigned R0 = RegList.List->front();
1370  unsigned R1 = RegList.List->back();
1371  if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
1372  (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
1373  return false;
1374 
1375  int PrevReg = *RegList.List->begin();
1376  for (int i = 1; i < Size - 1; i++) {
1377  int Reg = (*(RegList.List))[i];
1378  if ( Reg != PrevReg + 1)
1379  return false;
1380  PrevReg = Reg;
1381  }
1382 
1383  return true;
1384  }
1385 
1386  bool isInvNum() const { return Kind == k_Immediate; }
1387 
1388  bool isLSAImm() const {
1389  if (!isConstantImm())
1390  return false;
1391  int64_t Val = getConstantImm();
1392  return 1 <= Val && Val <= 4;
1393  }
1394 
1395  bool isRegList() const { return Kind == k_RegList; }
1396 
1397  StringRef getToken() const {
1398  assert(Kind == k_Token && "Invalid access!");
1399  return StringRef(Tok.Data, Tok.Length);
1400  }
1401 
1402  unsigned getReg() const override {
1403  // As a special case until we sort out the definition of div/divu, accept
1404  // $0/$zero here so that MCK_ZERO works correctly.
1405  if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
1406  RegIdx.Kind & RegKind_GPR)
1407  return getGPR32Reg(); // FIXME: GPR64 too
1408 
1409  llvm_unreachable("Invalid access!");
1410  return 0;
1411  }
1412 
1413  const MCExpr *getImm() const {
1414  assert((Kind == k_Immediate) && "Invalid access!");
1415  return Imm.Val;
1416  }
1417 
1418  int64_t getConstantImm() const {
1419  const MCExpr *Val = getImm();
1420  int64_t Value = 0;
1421  (void)Val->evaluateAsAbsolute(Value);
1422  return Value;
1423  }
1424 
1425  MipsOperand *getMemBase() const {
1426  assert((Kind == k_Memory) && "Invalid access!");
1427  return Mem.Base;
1428  }
1429 
1430  const MCExpr *getMemOff() const {
1431  assert((Kind == k_Memory) && "Invalid access!");
1432  return Mem.Off;
1433  }
1434 
1435  int64_t getConstantMemOff() const {
1436  return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
1437  }
1438 
1439  const SmallVectorImpl<unsigned> &getRegList() const {
1440  assert((Kind == k_RegList) && "Invalid access!");
1441  return *(RegList.List);
1442  }
1443 
1444  static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
1445  MipsAsmParser &Parser) {
1446  auto Op = llvm::make_unique<MipsOperand>(k_Token, Parser);
1447  Op->Tok.Data = Str.data();
1448  Op->Tok.Length = Str.size();
1449  Op->StartLoc = S;
1450  Op->EndLoc = S;
1451  return Op;
1452  }
1453 
1454  /// Create a numeric register (e.g. $1). The exact register remains
1455  /// unresolved until an instruction successfully matches
1456  static std::unique_ptr<MipsOperand>
1457  createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1458  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1459  LLVM_DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n");
1460  return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
1461  }
1462 
1463  /// Create a register that is definitely a GPR.
1464  /// This is typically only used for named registers such as $gp.
1465  static std::unique_ptr<MipsOperand>
1466  createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1467  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1468  return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
1469  }
1470 
1471  /// Create a register that is definitely a FGR.
1472  /// This is typically only used for named registers such as $f0.
1473  static std::unique_ptr<MipsOperand>
1474  createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1475  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1476  return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
1477  }
1478 
1479  /// Create a register that is definitely a HWReg.
1480  /// This is typically only used for named registers such as $hwr_cpunum.
1481  static std::unique_ptr<MipsOperand>
1482  createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1483  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1484  return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
1485  }
1486 
1487  /// Create a register that is definitely an FCC.
1488  /// This is typically only used for named registers such as $fcc0.
1489  static std::unique_ptr<MipsOperand>
1490  createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1491  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1492  return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
1493  }
1494 
1495  /// Create a register that is definitely an ACC.
1496  /// This is typically only used for named registers such as $ac0.
1497  static std::unique_ptr<MipsOperand>
1498  createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1499  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1500  return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
1501  }
1502 
1503  /// Create a register that is definitely an MSA128.
1504  /// This is typically only used for named registers such as $w0.
1505  static std::unique_ptr<MipsOperand>
1506  createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1507  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1508  return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
1509  }
1510 
1511  /// Create a register that is definitely an MSACtrl.
1512  /// This is typically only used for named registers such as $msaaccess.
1513  static std::unique_ptr<MipsOperand>
1514  createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1515  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1516  return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
1517  }
1518 
1519  static std::unique_ptr<MipsOperand>
1520  CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1521  auto Op = llvm::make_unique<MipsOperand>(k_Immediate, Parser);
1522  Op->Imm.Val = Val;
1523  Op->StartLoc = S;
1524  Op->EndLoc = E;
1525  return Op;
1526  }
1527 
1528  static std::unique_ptr<MipsOperand>
1529  CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
1530  SMLoc E, MipsAsmParser &Parser) {
1531  auto Op = llvm::make_unique<MipsOperand>(k_Memory, Parser);
1532  Op->Mem.Base = Base.release();
1533  Op->Mem.Off = Off;
1534  Op->StartLoc = S;
1535  Op->EndLoc = E;
1536  return Op;
1537  }
1538 
1539  static std::unique_ptr<MipsOperand>
1540  CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc,
1541  MipsAsmParser &Parser) {
1542  assert(Regs.size() > 0 && "Empty list not allowed");
1543 
1544  auto Op = llvm::make_unique<MipsOperand>(k_RegList, Parser);
1545  Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
1546  Op->StartLoc = StartLoc;
1547  Op->EndLoc = EndLoc;
1548  return Op;
1549  }
1550 
1551  bool isGPRZeroAsmReg() const {
1552  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0;
1553  }
1554 
1555  bool isGPRNonZeroAsmReg() const {
1556  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 &&
1557  RegIdx.Index <= 31;
1558  }
1559 
1560  bool isGPRAsmReg() const {
1561  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
1562  }
1563 
1564  bool isMM16AsmReg() const {
1565  if (!(isRegIdx() && RegIdx.Kind))
1566  return false;
1567  return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
1568  || RegIdx.Index == 16 || RegIdx.Index == 17);
1569 
1570  }
1571  bool isMM16AsmRegZero() const {
1572  if (!(isRegIdx() && RegIdx.Kind))
1573  return false;
1574  return (RegIdx.Index == 0 ||
1575  (RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
1576  RegIdx.Index == 17);
1577  }
1578 
1579  bool isMM16AsmRegMoveP() const {
1580  if (!(isRegIdx() && RegIdx.Kind))
1581  return false;
1582  return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
1583  (RegIdx.Index >= 16 && RegIdx.Index <= 20));
1584  }
1585 
1586  bool isMM16AsmRegMovePPairFirst() const {
1587  if (!(isRegIdx() && RegIdx.Kind))
1588  return false;
1589  return RegIdx.Index >= 4 && RegIdx.Index <= 6;
1590  }
1591 
1592  bool isMM16AsmRegMovePPairSecond() const {
1593  if (!(isRegIdx() && RegIdx.Kind))
1594  return false;
1595  return (RegIdx.Index == 21 || RegIdx.Index == 22 ||
1596  (RegIdx.Index >= 5 && RegIdx.Index <= 7));
1597  }
1598 
1599  bool isFGRAsmReg() const {
1600  // AFGR64 is $0-$15 but we handle this in getAFGR64()
1601  return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
1602  }
1603 
1604  bool isStrictlyFGRAsmReg() const {
1605  // AFGR64 is $0-$15 but we handle this in getAFGR64()
1606  return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31;
1607  }
1608 
1609  bool isHWRegsAsmReg() const {
1610  return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
1611  }
1612 
1613  bool isCCRAsmReg() const {
1614  return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
1615  }
1616 
1617  bool isFCCAsmReg() const {
1618  if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
1619  return false;
1620  return RegIdx.Index <= 7;
1621  }
1622 
1623  bool isACCAsmReg() const {
1624  return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
1625  }
1626 
1627  bool isCOP0AsmReg() const {
1628  return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
1629  }
1630 
1631  bool isCOP2AsmReg() const {
1632  return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
1633  }
1634 
1635  bool isCOP3AsmReg() const {
1636  return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
1637  }
1638 
1639  bool isMSA128AsmReg() const {
1640  return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
1641  }
1642 
1643  bool isMSACtrlAsmReg() const {
1644  return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
1645  }
1646 
1647  /// getStartLoc - Get the location of the first token of this operand.
1648  SMLoc getStartLoc() const override { return StartLoc; }
1649  /// getEndLoc - Get the location of the last token of this operand.
1650  SMLoc getEndLoc() const override { return EndLoc; }
1651 
1652  void print(raw_ostream &OS) const override {
1653  switch (Kind) {
1654  case k_Immediate:
1655  OS << "Imm<";
1656  OS << *Imm.Val;
1657  OS << ">";
1658  break;
1659  case k_Memory:
1660  OS << "Mem<";
1661  Mem.Base->print(OS);
1662  OS << ", ";
1663  OS << *Mem.Off;
1664  OS << ">";
1665  break;
1666  case k_RegisterIndex:
1667  OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", "
1668  << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">";
1669  break;
1670  case k_Token:
1671  OS << getToken();
1672  break;
1673  case k_RegList:
1674  OS << "RegList< ";
1675  for (auto Reg : (*RegList.List))
1676  OS << Reg << " ";
1677  OS << ">";
1678  break;
1679  }
1680  }
1681 
1682  bool isValidForTie(const MipsOperand &Other) const {
1683  if (Kind != Other.Kind)
1684  return false;
1685 
1686  switch (Kind) {
1687  default:
1688  llvm_unreachable("Unexpected kind");
1689  return false;
1690  case k_RegisterIndex: {
1691  StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length);
1692  StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length);
1693  return Token == OtherToken;
1694  }
1695  }
1696  }
1697 }; // class MipsOperand
1698 
1699 } // end anonymous namespace
1700 
1701 namespace llvm {
1702 
1703 extern const MCInstrDesc MipsInsts[];
1704 
1705 } // end namespace llvm
1706 
1707 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
1708  return MipsInsts[Opcode];
1709 }
1710 
1711 static bool hasShortDelaySlot(MCInst &Inst) {
1712  switch (Inst.getOpcode()) {
1713  case Mips::BEQ_MM:
1714  case Mips::BNE_MM:
1715  case Mips::BLTZ_MM:
1716  case Mips::BGEZ_MM:
1717  case Mips::BLEZ_MM:
1718  case Mips::BGTZ_MM:
1719  case Mips::JRC16_MM:
1720  case Mips::JALS_MM:
1721  case Mips::JALRS_MM:
1722  case Mips::JALRS16_MM:
1723  case Mips::BGEZALS_MM:
1724  case Mips::BLTZALS_MM:
1725  return true;
1726  case Mips::J_MM:
1727  return !Inst.getOperand(0).isReg();
1728  default:
1729  return false;
1730  }
1731 }
1732 
1733 static const MCSymbol *getSingleMCSymbol(const MCExpr *Expr) {
1734  if (const MCSymbolRefExpr *SRExpr = dyn_cast<MCSymbolRefExpr>(Expr)) {
1735  return &SRExpr->getSymbol();
1736  }
1737 
1738  if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr)) {
1739  const MCSymbol *LHSSym = getSingleMCSymbol(BExpr->getLHS());
1740  const MCSymbol *RHSSym = getSingleMCSymbol(BExpr->getRHS());
1741 
1742  if (LHSSym)
1743  return LHSSym;
1744 
1745  if (RHSSym)
1746  return RHSSym;
1747 
1748  return nullptr;
1749  }
1750 
1751  if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
1752  return getSingleMCSymbol(UExpr->getSubExpr());
1753 
1754  return nullptr;
1755 }
1756 
1757 static unsigned countMCSymbolRefExpr(const MCExpr *Expr) {
1758  if (isa<MCSymbolRefExpr>(Expr))
1759  return 1;
1760 
1761  if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr))
1762  return countMCSymbolRefExpr(BExpr->getLHS()) +
1763  countMCSymbolRefExpr(BExpr->getRHS());
1764 
1765  if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
1766  return countMCSymbolRefExpr(UExpr->getSubExpr());
1767 
1768  return 0;
1769 }
1770 
1771 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
1772  MCStreamer &Out,
1773  const MCSubtargetInfo *STI) {
1774  MipsTargetStreamer &TOut = getTargetStreamer();
1775  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
1776  bool ExpandedJalSym = false;
1777 
1778  Inst.setLoc(IDLoc);
1779 
1780  if (MCID.isBranch() || MCID.isCall()) {
1781  const unsigned Opcode = Inst.getOpcode();
1782  MCOperand Offset;
1783 
1784  switch (Opcode) {
1785  default:
1786  break;
1787  case Mips::BBIT0:
1788  case Mips::BBIT032:
1789  case Mips::BBIT1:
1790  case Mips::BBIT132:
1791  assert(hasCnMips() && "instruction only valid for octeon cpus");
1793 
1794  case Mips::BEQ:
1795  case Mips::BNE:
1796  case Mips::BEQ_MM:
1797  case Mips::BNE_MM:
1798  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1799  Offset = Inst.getOperand(2);
1800  if (!Offset.isImm())
1801  break; // We'll deal with this situation later on when applying fixups.
1802  if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
1803  return Error(IDLoc, "branch target out of range");
1804  if (OffsetToAlignment(Offset.getImm(),
1805  1LL << (inMicroMipsMode() ? 1 : 2)))
1806  return Error(IDLoc, "branch to misaligned address");
1807  break;
1808  case Mips::BGEZ:
1809  case Mips::BGTZ:
1810  case Mips::BLEZ:
1811  case Mips::BLTZ:
1812  case Mips::BGEZAL:
1813  case Mips::BLTZAL:
1814  case Mips::BC1F:
1815  case Mips::BC1T:
1816  case Mips::BGEZ_MM:
1817  case Mips::BGTZ_MM:
1818  case Mips::BLEZ_MM:
1819  case Mips::BLTZ_MM:
1820  case Mips::BGEZAL_MM:
1821  case Mips::BLTZAL_MM:
1822  case Mips::BC1F_MM:
1823  case Mips::BC1T_MM:
1824  case Mips::BC1EQZC_MMR6:
1825  case Mips::BC1NEZC_MMR6:
1826  case Mips::BC2EQZC_MMR6:
1827  case Mips::BC2NEZC_MMR6:
1828  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1829  Offset = Inst.getOperand(1);
1830  if (!Offset.isImm())
1831  break; // We'll deal with this situation later on when applying fixups.
1832  if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
1833  return Error(IDLoc, "branch target out of range");
1834  if (OffsetToAlignment(Offset.getImm(),
1835  1LL << (inMicroMipsMode() ? 1 : 2)))
1836  return Error(IDLoc, "branch to misaligned address");
1837  break;
1838  case Mips::BGEC: case Mips::BGEC_MMR6:
1839  case Mips::BLTC: case Mips::BLTC_MMR6:
1840  case Mips::BGEUC: case Mips::BGEUC_MMR6:
1841  case Mips::BLTUC: case Mips::BLTUC_MMR6:
1842  case Mips::BEQC: case Mips::BEQC_MMR6:
1843  case Mips::BNEC: case Mips::BNEC_MMR6:
1844  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1845  Offset = Inst.getOperand(2);
1846  if (!Offset.isImm())
1847  break; // We'll deal with this situation later on when applying fixups.
1848  if (!isIntN(18, Offset.getImm()))
1849  return Error(IDLoc, "branch target out of range");
1850  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1851  return Error(IDLoc, "branch to misaligned address");
1852  break;
1853  case Mips::BLEZC: case Mips::BLEZC_MMR6:
1854  case Mips::BGEZC: case Mips::BGEZC_MMR6:
1855  case Mips::BGTZC: case Mips::BGTZC_MMR6:
1856  case Mips::BLTZC: case Mips::BLTZC_MMR6:
1857  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1858  Offset = Inst.getOperand(1);
1859  if (!Offset.isImm())
1860  break; // We'll deal with this situation later on when applying fixups.
1861  if (!isIntN(18, Offset.getImm()))
1862  return Error(IDLoc, "branch target out of range");
1863  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1864  return Error(IDLoc, "branch to misaligned address");
1865  break;
1866  case Mips::BEQZC: case Mips::BEQZC_MMR6:
1867  case Mips::BNEZC: case Mips::BNEZC_MMR6:
1868  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1869  Offset = Inst.getOperand(1);
1870  if (!Offset.isImm())
1871  break; // We'll deal with this situation later on when applying fixups.
1872  if (!isIntN(23, Offset.getImm()))
1873  return Error(IDLoc, "branch target out of range");
1874  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1875  return Error(IDLoc, "branch to misaligned address");
1876  break;
1877  case Mips::BEQZ16_MM:
1878  case Mips::BEQZC16_MMR6:
1879  case Mips::BNEZ16_MM:
1880  case Mips::BNEZC16_MMR6:
1881  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1882  Offset = Inst.getOperand(1);
1883  if (!Offset.isImm())
1884  break; // We'll deal with this situation later on when applying fixups.
1885  if (!isInt<8>(Offset.getImm()))
1886  return Error(IDLoc, "branch target out of range");
1887  if (OffsetToAlignment(Offset.getImm(), 2LL))
1888  return Error(IDLoc, "branch to misaligned address");
1889  break;
1890  }
1891  }
1892 
1893  // SSNOP is deprecated on MIPS32r6/MIPS64r6
1894  // We still accept it but it is a normal nop.
1895  if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
1896  std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
1897  Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
1898  "nop instruction");
1899  }
1900 
1901  if (hasCnMips()) {
1902  const unsigned Opcode = Inst.getOpcode();
1903  MCOperand Opnd;
1904  int Imm;
1905 
1906  switch (Opcode) {
1907  default:
1908  break;
1909 
1910  case Mips::BBIT0:
1911  case Mips::BBIT032:
1912  case Mips::BBIT1:
1913  case Mips::BBIT132:
1914  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1915  // The offset is handled above
1916  Opnd = Inst.getOperand(1);
1917  if (!Opnd.isImm())
1918  return Error(IDLoc, "expected immediate operand kind");
1919  Imm = Opnd.getImm();
1920  if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
1921  Opcode == Mips::BBIT1 ? 63 : 31))
1922  return Error(IDLoc, "immediate operand value out of range");
1923  if (Imm > 31) {
1924  Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
1925  : Mips::BBIT132);
1926  Inst.getOperand(1).setImm(Imm - 32);
1927  }
1928  break;
1929 
1930  case Mips::SEQi:
1931  case Mips::SNEi:
1932  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1933  Opnd = Inst.getOperand(2);
1934  if (!Opnd.isImm())
1935  return Error(IDLoc, "expected immediate operand kind");
1936  Imm = Opnd.getImm();
1937  if (!isInt<10>(Imm))
1938  return Error(IDLoc, "immediate operand value out of range");
1939  break;
1940  }
1941  }
1942 
1943  // Warn on division by zero. We're checking here as all instructions get
1944  // processed here, not just the macros that need expansion.
1945  //
1946  // The MIPS backend models most of the divison instructions and macros as
1947  // three operand instructions. The pre-R6 divide instructions however have
1948  // two operands and explicitly define HI/LO as part of the instruction,
1949  // not in the operands.
1950  unsigned FirstOp = 1;
1951  unsigned SecondOp = 2;
1952  switch (Inst.getOpcode()) {
1953  default:
1954  break;
1955  case Mips::SDivIMacro:
1956  case Mips::UDivIMacro:
1957  case Mips::DSDivIMacro:
1958  case Mips::DUDivIMacro:
1959  if (Inst.getOperand(2).getImm() == 0) {
1960  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
1961  Inst.getOperand(1).getReg() == Mips::ZERO_64)
1962  Warning(IDLoc, "dividing zero by zero");
1963  else
1964  Warning(IDLoc, "division by zero");
1965  }
1966  break;
1967  case Mips::DSDIV:
1968  case Mips::SDIV:
1969  case Mips::UDIV:
1970  case Mips::DUDIV:
1971  case Mips::UDIV_MM:
1972  case Mips::SDIV_MM:
1973  FirstOp = 0;
1974  SecondOp = 1;
1976  case Mips::SDivMacro:
1977  case Mips::DSDivMacro:
1978  case Mips::UDivMacro:
1979  case Mips::DUDivMacro:
1980  case Mips::DIV:
1981  case Mips::DIVU:
1982  case Mips::DDIV:
1983  case Mips::DDIVU:
1984  case Mips::DIVU_MMR6:
1985  case Mips::DIV_MMR6:
1986  if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
1987  Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
1988  if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
1989  Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
1990  Warning(IDLoc, "dividing zero by zero");
1991  else
1992  Warning(IDLoc, "division by zero");
1993  }
1994  break;
1995  }
1996 
1997  // For PIC code convert unconditional jump to unconditional branch.
1998  if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
1999  inPicMode()) {
2000  MCInst BInst;
2001  BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
2002  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2003  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2004  BInst.addOperand(Inst.getOperand(0));
2005  Inst = BInst;
2006  }
2007 
2008  // This expansion is not in a function called by tryExpandInstruction()
2009  // because the pseudo-instruction doesn't have a distinct opcode.
2010  if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
2011  inPicMode()) {
2012  warnIfNoMacro(IDLoc);
2013 
2014  const MCExpr *JalExpr = Inst.getOperand(0).getExpr();
2015 
2016  // We can do this expansion if there's only 1 symbol in the argument
2017  // expression.
2018  if (countMCSymbolRefExpr(JalExpr) > 1)
2019  return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode");
2020 
2021  // FIXME: This is checking the expression can be handled by the later stages
2022  // of the assembler. We ought to leave it to those later stages.
2023  const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);
2024 
2025  // FIXME: Add support for label+offset operands (currently causes an error).
2026  // FIXME: Add support for forward-declared local symbols.
2027  // FIXME: Add expansion for when the LargeGOT option is enabled.
2028  if (JalSym->isInSection() || JalSym->isTemporary() ||
2029  (JalSym->isELF() &&
2030  cast<MCSymbolELF>(JalSym)->getBinding() == ELF::STB_LOCAL)) {
2031  if (isABI_O32()) {
2032  // If it's a local symbol and the O32 ABI is being used, we expand to:
2033  // lw $25, 0($gp)
2034  // R_(MICRO)MIPS_GOT16 label
2035  // addiu $25, $25, 0
2036  // R_(MICRO)MIPS_LO16 label
2037  // jalr $25
2038  const MCExpr *Got16RelocExpr =
2039  MipsMCExpr::create(MipsMCExpr::MEK_GOT, JalExpr, getContext());
2040  const MCExpr *Lo16RelocExpr =
2041  MipsMCExpr::create(MipsMCExpr::MEK_LO, JalExpr, getContext());
2042 
2043  TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP,
2044  MCOperand::createExpr(Got16RelocExpr), IDLoc, STI);
2045  TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
2046  MCOperand::createExpr(Lo16RelocExpr), IDLoc, STI);
2047  } else if (isABI_N32() || isABI_N64()) {
2048  // If it's a local symbol and the N32/N64 ABIs are being used,
2049  // we expand to:
2050  // lw/ld $25, 0($gp)
2051  // R_(MICRO)MIPS_GOT_DISP label
2052  // jalr $25
2053  const MCExpr *GotDispRelocExpr =
2054  MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, JalExpr, getContext());
2055 
2056  TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9,
2057  Mips::GP, MCOperand::createExpr(GotDispRelocExpr), IDLoc,
2058  STI);
2059  }
2060  } else {
2061  // If it's an external/weak symbol, we expand to:
2062  // lw/ld $25, 0($gp)
2063  // R_(MICRO)MIPS_CALL16 label
2064  // jalr $25
2065  const MCExpr *Call16RelocExpr =
2066  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, JalExpr, getContext());
2067 
2068  TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
2069  MCOperand::createExpr(Call16RelocExpr), IDLoc, STI);
2070  }
2071 
2072  MCInst JalrInst;
2073  if (IsCpRestoreSet && inMicroMipsMode())
2074  JalrInst.setOpcode(Mips::JALRS_MM);
2075  else
2076  JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2078  JalrInst.addOperand(MCOperand::createReg(Mips::T9));
2079 
2080  if (EmitJalrReloc) {
2081  // As an optimization hint for the linker, before the JALR we add:
2082  // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
2083  // tmplabel:
2084  MCSymbol *TmpLabel = getContext().createTempSymbol();
2085  const MCExpr *TmpExpr = MCSymbolRefExpr::create(TmpLabel, getContext());
2086  const MCExpr *RelocJalrExpr =
2088  getContext(), IDLoc);
2089 
2090  TOut.getStreamer().EmitRelocDirective(*TmpExpr,
2091  inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
2092  RelocJalrExpr, IDLoc, *STI);
2093  TOut.getStreamer().EmitLabel(TmpLabel);
2094  }
2095 
2096  Inst = JalrInst;
2097  ExpandedJalSym = true;
2098  }
2099 
2100  bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0;
2101  if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
2102  // Check the offset of memory operand, if it is a symbol
2103  // reference or immediate we may have to expand instructions.
2104  for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
2105  const MCOperandInfo &OpInfo = MCID.OpInfo[i];
2106  if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
2107  (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
2108  MCOperand &Op = Inst.getOperand(i);
2109  if (Op.isImm()) {
2110  int64_t MemOffset = Op.getImm();
2111  if (MemOffset < -32768 || MemOffset > 32767) {
2112  // Offset can't exceed 16bit value.
2113  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2114  return getParser().hasPendingError();
2115  }
2116  } else if (Op.isExpr()) {
2117  const MCExpr *Expr = Op.getExpr();
2118  if (Expr->getKind() == MCExpr::SymbolRef) {
2119  const MCSymbolRefExpr *SR =
2120  static_cast<const MCSymbolRefExpr *>(Expr);
2121  if (SR->getKind() == MCSymbolRefExpr::VK_None) {
2122  // Expand symbol.
2123  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2124  return getParser().hasPendingError();
2125  }
2126  } else if (!isEvaluated(Expr)) {
2127  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2128  return getParser().hasPendingError();
2129  }
2130  }
2131  }
2132  } // for
2133  } // if load/store
2134 
2135  if (inMicroMipsMode()) {
2136  if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) {
2137  // Try to create 16-bit GP relative load instruction.
2138  for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
2139  const MCOperandInfo &OpInfo = MCID.OpInfo[i];
2140  if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
2141  (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
2142  MCOperand &Op = Inst.getOperand(i);
2143  if (Op.isImm()) {
2144  int MemOffset = Op.getImm();
2145  MCOperand &DstReg = Inst.getOperand(0);
2146  MCOperand &BaseReg = Inst.getOperand(1);
2147  if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
2148  getContext().getRegisterInfo()->getRegClass(
2149  Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
2150  (BaseReg.getReg() == Mips::GP ||
2151  BaseReg.getReg() == Mips::GP_64)) {
2152 
2153  TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
2154  IDLoc, STI);
2155  return false;
2156  }
2157  }
2158  }
2159  } // for
2160  } // if load
2161 
2162  // TODO: Handle this with the AsmOperandClass.PredicateMethod.
2163 
2164  MCOperand Opnd;
2165  int Imm;
2166 
2167  switch (Inst.getOpcode()) {
2168  default:
2169  break;
2170  case Mips::ADDIUSP_MM:
2171  Opnd = Inst.getOperand(0);
2172  if (!Opnd.isImm())
2173  return Error(IDLoc, "expected immediate operand kind");
2174  Imm = Opnd.getImm();
2175  if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) ||
2176  Imm % 4 != 0)
2177  return Error(IDLoc, "immediate operand value out of range");
2178  break;
2179  case Mips::SLL16_MM:
2180  case Mips::SRL16_MM:
2181  Opnd = Inst.getOperand(2);
2182  if (!Opnd.isImm())
2183  return Error(IDLoc, "expected immediate operand kind");
2184  Imm = Opnd.getImm();
2185  if (Imm < 1 || Imm > 8)
2186  return Error(IDLoc, "immediate operand value out of range");
2187  break;
2188  case Mips::LI16_MM:
2189  Opnd = Inst.getOperand(1);
2190  if (!Opnd.isImm())
2191  return Error(IDLoc, "expected immediate operand kind");
2192  Imm = Opnd.getImm();
2193  if (Imm < -1 || Imm > 126)
2194  return Error(IDLoc, "immediate operand value out of range");
2195  break;
2196  case Mips::ADDIUR2_MM:
2197  Opnd = Inst.getOperand(2);
2198  if (!Opnd.isImm())
2199  return Error(IDLoc, "expected immediate operand kind");
2200  Imm = Opnd.getImm();
2201  if (!(Imm == 1 || Imm == -1 ||
2202  ((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
2203  return Error(IDLoc, "immediate operand value out of range");
2204  break;
2205  case Mips::ANDI16_MM:
2206  Opnd = Inst.getOperand(2);
2207  if (!Opnd.isImm())
2208  return Error(IDLoc, "expected immediate operand kind");
2209  Imm = Opnd.getImm();
2210  if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
2211  Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
2212  Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
2213  return Error(IDLoc, "immediate operand value out of range");
2214  break;
2215  case Mips::LBU16_MM:
2216  Opnd = Inst.getOperand(2);
2217  if (!Opnd.isImm())
2218  return Error(IDLoc, "expected immediate operand kind");
2219  Imm = Opnd.getImm();
2220  if (Imm < -1 || Imm > 14)
2221  return Error(IDLoc, "immediate operand value out of range");
2222  break;
2223  case Mips::SB16_MM:
2224  case Mips::SB16_MMR6:
2225  Opnd = Inst.getOperand(2);
2226  if (!Opnd.isImm())
2227  return Error(IDLoc, "expected immediate operand kind");
2228  Imm = Opnd.getImm();
2229  if (Imm < 0 || Imm > 15)
2230  return Error(IDLoc, "immediate operand value out of range");
2231  break;
2232  case Mips::LHU16_MM:
2233  case Mips::SH16_MM:
2234  case Mips::SH16_MMR6:
2235  Opnd = Inst.getOperand(2);
2236  if (!Opnd.isImm())
2237  return Error(IDLoc, "expected immediate operand kind");
2238  Imm = Opnd.getImm();
2239  if (Imm < 0 || Imm > 30 || (Imm % 2 != 0))
2240  return Error(IDLoc, "immediate operand value out of range");
2241  break;
2242  case Mips::LW16_MM:
2243  case Mips::SW16_MM:
2244  case Mips::SW16_MMR6:
2245  Opnd = Inst.getOperand(2);
2246  if (!Opnd.isImm())
2247  return Error(IDLoc, "expected immediate operand kind");
2248  Imm = Opnd.getImm();
2249  if (Imm < 0 || Imm > 60 || (Imm % 4 != 0))
2250  return Error(IDLoc, "immediate operand value out of range");
2251  break;
2252  case Mips::ADDIUPC_MM:
2253  Opnd = Inst.getOperand(1);
2254  if (!Opnd.isImm())
2255  return Error(IDLoc, "expected immediate operand kind");
2256  Imm = Opnd.getImm();
2257  if ((Imm % 4 != 0) || !isInt<25>(Imm))
2258  return Error(IDLoc, "immediate operand value out of range");
2259  break;
2260  case Mips::LWP_MM:
2261  case Mips::SWP_MM:
2262  if (Inst.getOperand(0).getReg() == Mips::RA)
2263  return Error(IDLoc, "invalid operand for instruction");
2264  break;
2265  case Mips::MOVEP_MM:
2266  case Mips::MOVEP_MMR6: {
2267  unsigned R0 = Inst.getOperand(0).getReg();
2268  unsigned R1 = Inst.getOperand(1).getReg();
2269  bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
2270  (R0 == Mips::A1 && R1 == Mips::A3) ||
2271  (R0 == Mips::A2 && R1 == Mips::A3) ||
2272  (R0 == Mips::A0 && R1 == Mips::S5) ||
2273  (R0 == Mips::A0 && R1 == Mips::S6) ||
2274  (R0 == Mips::A0 && R1 == Mips::A1) ||
2275  (R0 == Mips::A0 && R1 == Mips::A2) ||
2276  (R0 == Mips::A0 && R1 == Mips::A3));
2277  if (!RegPair)
2278  return Error(IDLoc, "invalid operand for instruction");
2279  break;
2280  }
2281  }
2282  }
2283 
2284  bool FillDelaySlot =
2285  MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
2286  if (FillDelaySlot)
2288 
2289  MacroExpanderResultTy ExpandResult =
2290  tryExpandInstruction(Inst, IDLoc, Out, STI);
2291  switch (ExpandResult) {
2292  case MER_NotAMacro:
2293  Out.EmitInstruction(Inst, *STI);
2294  break;
2295  case MER_Success:
2296  break;
2297  case MER_Fail:
2298  return true;
2299  }
2300 
2301  // We know we emitted an instruction on the MER_NotAMacro or MER_Success path.
2302  // If we're in microMIPS mode then we must also set EF_MIPS_MICROMIPS.
2303  if (inMicroMipsMode()) {
2304  TOut.setUsesMicroMips();
2305  TOut.updateABIInfo(*this);
2306  }
2307 
2308  // If this instruction has a delay slot and .set reorder is active,
2309  // emit a NOP after it.
2310  if (FillDelaySlot) {
2311  TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
2312  TOut.emitDirectiveSetReorder();
2313  }
2314 
2315  if ((Inst.getOpcode() == Mips::JalOneReg ||
2316  Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
2317  isPicAndNotNxxAbi()) {
2318  if (IsCpRestoreSet) {
2319  // We need a NOP between the JALR and the LW:
2320  // If .set reorder has been used, we've already emitted a NOP.
2321  // If .set noreorder has been used, we need to emit a NOP at this point.
2322  if (!AssemblerOptions.back()->isReorder())
2323  TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc,
2324  STI);
2325 
2326  // Load the $gp from the stack.
2327  TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
2328  } else
2329  Warning(IDLoc, "no .cprestore used in PIC mode");
2330  }
2331 
2332  return false;
2333 }
2334 
2335 MipsAsmParser::MacroExpanderResultTy
2336 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
2337  const MCSubtargetInfo *STI) {
2338  switch (Inst.getOpcode()) {
2339  default:
2340  return MER_NotAMacro;
2341  case Mips::LoadImm32:
2342  return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2343  case Mips::LoadImm64:
2344  return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2345  case Mips::LoadAddrImm32:
2346  case Mips::LoadAddrImm64:
2347  assert(Inst.getOperand(0).isReg() && "expected register operand kind");
2348  assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) &&
2349  "expected immediate operand kind");
2350 
2351  return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
2352  Inst.getOperand(1),
2353  Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
2354  Out, STI)
2355  ? MER_Fail
2356  : MER_Success;
2357  case Mips::LoadAddrReg32:
2358  case Mips::LoadAddrReg64:
2359  assert(Inst.getOperand(0).isReg() && "expected register operand kind");
2360  assert(Inst.getOperand(1).isReg() && "expected register operand kind");
2361  assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) &&
2362  "expected immediate operand kind");
2363 
2364  return expandLoadAddress(Inst.getOperand(0).getReg(),
2365  Inst.getOperand(1).getReg(), Inst.getOperand(2),
2366  Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
2367  Out, STI)
2368  ? MER_Fail
2369  : MER_Success;
2370  case Mips::B_MM_Pseudo:
2371  case Mips::B_MMR6_Pseudo:
2372  return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail
2373  : MER_Success;
2374  case Mips::SWM_MM:
2375  case Mips::LWM_MM:
2376  return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail
2377  : MER_Success;
2378  case Mips::JalOneReg:
2379  case Mips::JalTwoReg:
2380  return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2381  case Mips::BneImm:
2382  case Mips::BeqImm:
2383  case Mips::BEQLImmMacro:
2384  case Mips::BNELImmMacro:
2385  return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2386  case Mips::BLT:
2387  case Mips::BLE:
2388  case Mips::BGE:
2389  case Mips::BGT:
2390  case Mips::BLTU:
2391  case Mips::BLEU:
2392  case Mips::BGEU:
2393  case Mips::BGTU:
2394  case Mips::BLTL:
2395  case Mips::BLEL:
2396  case Mips::BGEL:
2397  case Mips::BGTL:
2398  case Mips::BLTUL:
2399  case Mips::BLEUL:
2400  case Mips::BGEUL:
2401  case Mips::BGTUL:
2402  case Mips::BLTImmMacro:
2403  case Mips::BLEImmMacro:
2404  case Mips::BGEImmMacro:
2405  case Mips::BGTImmMacro:
2406  case Mips::BLTUImmMacro:
2407  case Mips::BLEUImmMacro:
2408  case Mips::BGEUImmMacro:
2409  case Mips::BGTUImmMacro:
2410  case Mips::BLTLImmMacro:
2411  case Mips::BLELImmMacro:
2412  case Mips::BGELImmMacro:
2413  case Mips::BGTLImmMacro:
2414  case Mips::BLTULImmMacro:
2415  case Mips::BLEULImmMacro:
2416  case Mips::BGEULImmMacro:
2417  case Mips::BGTULImmMacro:
2418  return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2419  case Mips::SDivMacro:
2420  case Mips::SDivIMacro:
2421  case Mips::SRemMacro:
2422  case Mips::SRemIMacro:
2423  return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail
2424  : MER_Success;
2425  case Mips::DSDivMacro:
2426  case Mips::DSDivIMacro:
2427  case Mips::DSRemMacro:
2428  case Mips::DSRemIMacro:
2429  return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail
2430  : MER_Success;
2431  case Mips::UDivMacro:
2432  case Mips::UDivIMacro:
2433  case Mips::URemMacro:
2434  case Mips::URemIMacro:
2435  return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail
2436  : MER_Success;
2437  case Mips::DUDivMacro:
2438  case Mips::DUDivIMacro:
2439  case Mips::DURemMacro:
2440  case Mips::DURemIMacro:
2441  return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail
2442  : MER_Success;
2443  case Mips::PseudoTRUNC_W_S:
2444  return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail
2445  : MER_Success;
2446  case Mips::PseudoTRUNC_W_D32:
2447  return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail
2448  : MER_Success;
2449  case Mips::PseudoTRUNC_W_D:
2450  return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail
2451  : MER_Success;
2452 
2453  case Mips::LoadImmSingleGPR:
2454  return expandLoadImmReal(Inst, true, true, false, IDLoc, Out, STI)
2455  ? MER_Fail
2456  : MER_Success;
2457  case Mips::LoadImmSingleFGR:
2458  return expandLoadImmReal(Inst, true, false, false, IDLoc, Out, STI)
2459  ? MER_Fail
2460  : MER_Success;
2461  case Mips::LoadImmDoubleGPR:
2462  return expandLoadImmReal(Inst, false, true, false, IDLoc, Out, STI)
2463  ? MER_Fail
2464  : MER_Success;
2465  case Mips::LoadImmDoubleFGR:
2466  return expandLoadImmReal(Inst, false, false, true, IDLoc, Out, STI)
2467  ? MER_Fail
2468  : MER_Success;
2469  case Mips::LoadImmDoubleFGR_32:
2470  return expandLoadImmReal(Inst, false, false, false, IDLoc, Out, STI)
2471  ? MER_Fail
2472  : MER_Success;
2473  case Mips::Ulh:
2474  return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2475  case Mips::Ulhu:
2476  return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2477  case Mips::Ush:
2478  return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2479  case Mips::Ulw:
2480  case Mips::Usw:
2481  return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2482  case Mips::NORImm:
2483  case Mips::NORImm64:
2484  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2485  case Mips::SGE:
2486  case Mips::SGEU:
2487  return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2488  case Mips::SGEImm:
2489  case Mips::SGEUImm:
2490  case Mips::SGEImm64:
2491  case Mips::SGEUImm64:
2492  return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2493  case Mips::SGTImm:
2494  case Mips::SGTUImm:
2495  case Mips::SGTImm64:
2496  case Mips::SGTUImm64:
2497  return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2498  case Mips::SLTImm64:
2499  if (isInt<16>(Inst.getOperand(2).getImm())) {
2500  Inst.setOpcode(Mips::SLTi64);
2501  return MER_NotAMacro;
2502  }
2503  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2504  case Mips::SLTUImm64:
2505  if (isInt<16>(Inst.getOperand(2).getImm())) {
2506  Inst.setOpcode(Mips::SLTiu64);
2507  return MER_NotAMacro;
2508  }
2509  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2510  case Mips::ADDi: case Mips::ADDi_MM:
2511  case Mips::ADDiu: case Mips::ADDiu_MM:
2512  case Mips::SLTi: case Mips::SLTi_MM:
2513  case Mips::SLTiu: case Mips::SLTiu_MM:
2514  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
2515  Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
2516  int64_t ImmValue = Inst.getOperand(2).getImm();
2517  if (isInt<16>(ImmValue))
2518  return MER_NotAMacro;
2519  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2520  : MER_Success;
2521  }
2522  return MER_NotAMacro;
2523  case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64:
2524  case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64:
2525  case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64:
2526  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
2527  Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
2528  int64_t ImmValue = Inst.getOperand(2).getImm();
2529  if (isUInt<16>(ImmValue))
2530  return MER_NotAMacro;
2531  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2532  : MER_Success;
2533  }
2534  return MER_NotAMacro;
2535  case Mips::ROL:
2536  case Mips::ROR:
2537  return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2538  case Mips::ROLImm:
2539  case Mips::RORImm:
2540  return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2541  case Mips::DROL:
2542  case Mips::DROR:
2543  return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2544  case Mips::DROLImm:
2545  case Mips::DRORImm:
2546  return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2547  case Mips::ABSMacro:
2548  return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2549  case Mips::MULImmMacro:
2550  case Mips::DMULImmMacro:
2551  return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2552  case Mips::MULOMacro:
2553  case Mips::DMULOMacro:
2554  return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2555  case Mips::MULOUMacro:
2556  case Mips::DMULOUMacro:
2557  return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2558  case Mips::DMULMacro:
2559  return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2560  case Mips::LDMacro:
2561  case Mips::SDMacro:
2562  return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
2563  Inst.getOpcode() == Mips::LDMacro)
2564  ? MER_Fail
2565  : MER_Success;
2566  case Mips::SDC1_M1:
2567  return expandStoreDM1Macro(Inst, IDLoc, Out, STI)
2568  ? MER_Fail
2569  : MER_Success;
2570  case Mips::SEQMacro:
2571  return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2572  case Mips::SEQIMacro:
2573  return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2574  case Mips::MFTC0: case Mips::MTTC0:
2575  case Mips::MFTGPR: case Mips::MTTGPR:
2576  case Mips::MFTLO: case Mips::MTTLO:
2577  case Mips::MFTHI: case Mips::MTTHI:
2578  case Mips::MFTACX: case Mips::MTTACX:
2579  case Mips::MFTDSP: case Mips::MTTDSP:
2580  case Mips::MFTC1: case Mips::MTTC1:
2581  case Mips::MFTHC1: case Mips::MTTHC1:
2582  case Mips::CFTC1: case Mips::CTTC1:
2583  return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2584  }
2585 }
2586 
2587 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
2588  MCStreamer &Out,
2589  const MCSubtargetInfo *STI) {
2590  MipsTargetStreamer &TOut = getTargetStreamer();
2591 
2592  // Create a JALR instruction which is going to replace the pseudo-JAL.
2593  MCInst JalrInst;
2594  JalrInst.setLoc(IDLoc);
2595  const MCOperand FirstRegOp = Inst.getOperand(0);
2596  const unsigned Opcode = Inst.getOpcode();
2597 
2598  if (Opcode == Mips::JalOneReg) {
2599  // jal $rs => jalr $rs
2600  if (IsCpRestoreSet && inMicroMipsMode()) {
2601  JalrInst.setOpcode(Mips::JALRS16_MM);
2602  JalrInst.addOperand(FirstRegOp);
2603  } else if (inMicroMipsMode()) {
2604  JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
2605  JalrInst.addOperand(FirstRegOp);
2606  } else {
2607  JalrInst.setOpcode(Mips::JALR);
2609  JalrInst.addOperand(FirstRegOp);
2610  }
2611  } else if (Opcode == Mips::JalTwoReg) {
2612  // jal $rd, $rs => jalr $rd, $rs
2613  if (IsCpRestoreSet && inMicroMipsMode())
2614  JalrInst.setOpcode(Mips::JALRS_MM);
2615  else
2616  JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2617  JalrInst.addOperand(FirstRegOp);
2618  const MCOperand SecondRegOp = Inst.getOperand(1);
2619  JalrInst.addOperand(SecondRegOp);
2620  }
2621  Out.EmitInstruction(JalrInst, *STI);
2622 
2623  // If .set reorder is active and branch instruction has a delay slot,
2624  // emit a NOP after it.
2625  const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
2626  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
2627  TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc,
2628  STI);
2629 
2630  return false;
2631 }
2632 
2633 /// Can the value be represented by a unsigned N-bit value and a shift left?
2634 template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) {
2635  unsigned BitNum = findFirstSet(x);
2636 
2637  return (x == x >> BitNum << BitNum) && isUInt<N>(x >> BitNum);
2638 }
2639 
2640 /// Load (or add) an immediate into a register.
2641 ///
2642 /// @param ImmValue The immediate to load.
2643 /// @param DstReg The register that will hold the immediate.
2644 /// @param SrcReg A register to add to the immediate or Mips::NoRegister
2645 /// for a simple initialization.
2646 /// @param Is32BitImm Is ImmValue 32-bit or 64-bit?
2647 /// @param IsAddress True if the immediate represents an address. False if it
2648 /// is an integer.
2649 /// @param IDLoc Location of the immediate in the source file.
2650 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
2651  unsigned SrcReg, bool Is32BitImm,
2652  bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
2653  const MCSubtargetInfo *STI) {
2654  MipsTargetStreamer &TOut = getTargetStreamer();
2655 
2656  if (!Is32BitImm && !isGP64bit()) {
2657  Error(IDLoc, "instruction requires a 64-bit architecture");
2658  return true;
2659  }
2660 
2661  if (Is32BitImm) {
2662  if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
2663  // Sign extend up to 64-bit so that the predicates match the hardware
2664  // behaviour. In particular, isInt<16>(0xffff8000) and similar should be
2665  // true.
2666  ImmValue = SignExtend64<32>(ImmValue);
2667  } else {
2668  Error(IDLoc, "instruction requires a 32-bit immediate");
2669  return true;
2670  }
2671  }
2672 
2673  unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
2674  unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
2675 
2676  bool UseSrcReg = false;
2677  if (SrcReg != Mips::NoRegister)
2678  UseSrcReg = true;
2679 
2680  unsigned TmpReg = DstReg;
2681  if (UseSrcReg &&
2682  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
2683  // At this point we need AT to perform the expansions and we exit if it is
2684  // not available.
2685  unsigned ATReg = getATReg(IDLoc);
2686  if (!ATReg)
2687  return true;
2688  TmpReg = ATReg;
2689  }
2690 
2691  if (isInt<16>(ImmValue)) {
2692  if (!UseSrcReg)
2693  SrcReg = ZeroReg;
2694 
2695  // This doesn't quite follow the usual ABI expectations for N32 but matches
2696  // traditional assembler behaviour. N32 would normally use addiu for both
2697  // integers and addresses.
2698  if (IsAddress && !Is32BitImm) {
2699  TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2700  return false;
2701  }
2702 
2703  TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2704  return false;
2705  }
2706 
2707  if (isUInt<16>(ImmValue)) {
2708  unsigned TmpReg = DstReg;
2709  if (SrcReg == DstReg) {
2710  TmpReg = getATReg(IDLoc);
2711  if (!TmpReg)
2712  return true;
2713  }
2714 
2715  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2716  if (UseSrcReg)
2717  TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2718  return false;
2719  }
2720 
2721  if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
2722  warnIfNoMacro(IDLoc);
2723 
2724  uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
2725  uint16_t Bits15To0 = ImmValue & 0xffff;
2726  if (!Is32BitImm && !isInt<32>(ImmValue)) {
2727  // Traditional behaviour seems to special case this particular value. It's
2728  // not clear why other masks are handled differently.
2729  if (ImmValue == 0xffffffff) {
2730  TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2731  TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2732  if (UseSrcReg)
2733  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2734  return false;
2735  }
2736 
2737  // Expand to an ORi instead of a LUi to avoid sign-extending into the
2738  // upper 32 bits.
2739  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2740  TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2741  if (Bits15To0)
2742  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2743  if (UseSrcReg)
2744  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2745  return false;
2746  }
2747 
2748  TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2749  if (Bits15To0)
2750  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2751  if (UseSrcReg)
2752  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2753  return false;
2754  }
2755 
2756  if (isShiftedUIntAtAnyPosition<16>(ImmValue)) {
2757  if (Is32BitImm) {
2758  Error(IDLoc, "instruction requires a 32-bit immediate");
2759  return true;
2760  }
2761 
2762  // Traditionally, these immediates are shifted as little as possible and as
2763  // such we align the most significant bit to bit 15 of our temporary.
2764  unsigned FirstSet = findFirstSet((uint64_t)ImmValue);
2765  unsigned LastSet = findLastSet((uint64_t)ImmValue);
2766  unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
2767  uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2768  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2769  TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2770 
2771  if (UseSrcReg)
2772  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2773 
2774  return false;
2775  }
2776 
2777  warnIfNoMacro(IDLoc);
2778 
2779  // The remaining case is packed with a sequence of dsll and ori with zeros
2780  // being omitted and any neighbouring dsll's being coalesced.
2781  // The highest 32-bit's are equivalent to a 32-bit immediate load.
2782 
2783  // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register.
2784  if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
2785  IDLoc, Out, STI))
2786  return false;
2787 
2788  // Shift and accumulate into the register. If a 16-bit chunk is zero, then
2789  // skip it and defer the shift to the next chunk.
2790  unsigned ShiftCarriedForwards = 16;
2791  for (int BitNum = 16; BitNum >= 0; BitNum -= 16) {
2792  uint16_t ImmChunk = (ImmValue >> BitNum) & 0xffff;
2793 
2794  if (ImmChunk != 0) {
2795  TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2796  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2797  ShiftCarriedForwards = 0;
2798  }
2799 
2800  ShiftCarriedForwards += 16;
2801  }
2802  ShiftCarriedForwards -= 16;
2803 
2804  // Finish any remaining shifts left by trailing zeros.
2805  if (ShiftCarriedForwards)
2806  TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2807 
2808  if (UseSrcReg)
2809  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2810 
2811  return false;
2812 }
2813 
2814 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
2815  MCStreamer &Out, const MCSubtargetInfo *STI) {
2816  const MCOperand &ImmOp = Inst.getOperand(1);
2817  assert(ImmOp.isImm() && "expected immediate operand kind");
2818  const MCOperand &DstRegOp = Inst.getOperand(0);
2819  assert(DstRegOp.isReg() && "expected register operand kind");
2820 
2821  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
2822  Is32BitImm, false, IDLoc, Out, STI))
2823  return true;
2824 
2825  return false;
2826 }
2827 
2828 bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
2829  const MCOperand &Offset,
2830  bool Is32BitAddress, SMLoc IDLoc,
2831  MCStreamer &Out,
2832  const MCSubtargetInfo *STI) {
2833  // la can't produce a usable address when addresses are 64-bit.
2834  if (Is32BitAddress && ABI.ArePtrs64bit()) {
2835  // FIXME: Demote this to a warning and continue as if we had 'dla' instead.
2836  // We currently can't do this because we depend on the equality
2837  // operator and N64 can end up with a GPR32/GPR64 mismatch.
2838  Error(IDLoc, "la used to load 64-bit address");
2839  // Continue as if we had 'dla' instead.
2840  Is32BitAddress = false;
2841  return true;
2842  }
2843 
2844  // dla requires 64-bit addresses.
2845  if (!Is32BitAddress && !hasMips3()) {
2846  Error(IDLoc, "instruction requires a 64-bit architecture");
2847  return true;
2848  }
2849 
2850  if (!Offset.isImm())
2851  return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg,
2852  Is32BitAddress, IDLoc, Out, STI);
2853 
2854  if (!ABI.ArePtrs64bit()) {
2855  // Continue as if we had 'la' whether we had 'la' or 'dla'.
2856  Is32BitAddress = true;
2857  }
2858 
2859  return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true,
2860  IDLoc, Out, STI);
2861 }
2862 
2863 bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
2864  unsigned DstReg, unsigned SrcReg,
2865  bool Is32BitSym, SMLoc IDLoc,
2866  MCStreamer &Out,
2867  const MCSubtargetInfo *STI) {
2868  // FIXME: These expansions do not respect -mxgot.
2869  MipsTargetStreamer &TOut = getTargetStreamer();
2870  bool UseSrcReg = SrcReg != Mips::NoRegister;
2871  warnIfNoMacro(IDLoc);
2872 
2873  if (inPicMode() && ABI.IsO32()) {
2874  MCValue Res;
2875  if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
2876  Error(IDLoc, "expected relocatable expression");
2877  return true;
2878  }
2879  if (Res.getSymB() != nullptr) {
2880  Error(IDLoc, "expected relocatable expression with only one symbol");
2881  return true;
2882  }
2883 
2884  // The case where the result register is $25 is somewhat special. If the
2885  // symbol in the final relocation is external and not modified with a
2886  // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16.
2887  if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
2888  Res.getConstant() == 0 &&
2889  !(Res.getSymA()->getSymbol().isInSection() ||
2890  Res.getSymA()->getSymbol().isTemporary() ||
2891  (Res.getSymA()->getSymbol().isELF() &&
2892  cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
2893  ELF::STB_LOCAL))) {
2894  const MCExpr *CallExpr =
2895  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext());
2896  TOut.emitRRX(Mips::LW, DstReg, ABI.GetGlobalPtr(),
2897  MCOperand::createExpr(CallExpr), IDLoc, STI);
2898  return false;
2899  }
2900 
2901  // The remaining cases are:
2902  // External GOT: lw $tmp, %got(symbol+offset)($gp)
2903  // >addiu $tmp, $tmp, %lo(offset)
2904  // >addiu $rd, $tmp, $rs
2905  // Local GOT: lw $tmp, %got(symbol+offset)($gp)
2906  // addiu $tmp, $tmp, %lo(symbol+offset)($gp)
2907  // >addiu $rd, $tmp, $rs
2908  // The addiu's marked with a '>' may be omitted if they are redundant. If
2909  // this happens then the last instruction must use $rd as the result
2910  // register.
2911  const MipsMCExpr *GotExpr =
2912  MipsMCExpr::create(MipsMCExpr::MEK_GOT, SymExpr, getContext());
2913  const MCExpr *LoExpr = nullptr;
2914  if (Res.getSymA()->getSymbol().isInSection() ||
2915  Res.getSymA()->getSymbol().isTemporary())
2916  LoExpr = MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());
2917  else if (Res.getConstant() != 0) {
2918  // External symbols fully resolve the symbol with just the %got(symbol)
2919  // but we must still account for any offset to the symbol for expressions
2920  // like symbol+8.
2921  LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());
2922  }
2923 
2924  unsigned TmpReg = DstReg;
2925  if (UseSrcReg &&
2926  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
2927  SrcReg)) {
2928  // If $rs is the same as $rd, we need to use AT.
2929  // If it is not available we exit.
2930  unsigned ATReg = getATReg(IDLoc);
2931  if (!ATReg)
2932  return true;
2933  TmpReg = ATReg;
2934  }
2935 
2936  TOut.emitRRX(Mips::LW, TmpReg, ABI.GetGlobalPtr(),
2937  MCOperand::createExpr(GotExpr), IDLoc, STI);
2938 
2939  if (LoExpr)
2940  TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
2941  IDLoc, STI);
2942 
2943  if (UseSrcReg)
2944  TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
2945 
2946  return false;
2947  }
2948 
2949  if (inPicMode() && ABI.ArePtrs64bit()) {
2950  MCValue Res;
2951  if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
2952  Error(IDLoc, "expected relocatable expression");
2953  return true;
2954  }
2955  if (Res.getSymB() != nullptr) {
2956  Error(IDLoc, "expected relocatable expression with only one symbol");
2957  return true;
2958  }
2959 
2960  // The case where the result register is $25 is somewhat special. If the
2961  // symbol in the final relocation is external and not modified with a
2962  // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT_DISP.
2963  if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
2964  Res.getConstant() == 0 &&
2965  !(Res.getSymA()->getSymbol().isInSection() ||
2966  Res.getSymA()->getSymbol().isTemporary() ||
2967  (Res.getSymA()->getSymbol().isELF() &&
2968  cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
2969  ELF::STB_LOCAL))) {
2970  const MCExpr *CallExpr =
2971  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext());
2972  TOut.emitRRX(Mips::LD, DstReg, ABI.GetGlobalPtr(),
2973  MCOperand::createExpr(CallExpr), IDLoc, STI);
2974  return false;
2975  }
2976 
2977  // The remaining cases are:
2978  // Small offset: ld $tmp, %got_disp(symbol)($gp)
2979  // >daddiu $tmp, $tmp, offset
2980  // >daddu $rd, $tmp, $rs
2981  // The daddiu's marked with a '>' may be omitted if they are redundant. If
2982  // this happens then the last instruction must use $rd as the result
2983  // register.
2985  Res.getSymA(),
2986  getContext());
2987  const MCExpr *LoExpr = nullptr;
2988  if (Res.getConstant() != 0) {
2989  // Symbols fully resolve with just the %got_disp(symbol) but we
2990  // must still account for any offset to the symbol for
2991  // expressions like symbol+8.
2992  LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());
2993 
2994  // FIXME: Offsets greater than 16 bits are not yet implemented.
2995  // FIXME: The correct range is a 32-bit sign-extended number.
2996  if (Res.getConstant() < -0x8000 || Res.getConstant() > 0x7fff) {
2997  Error(IDLoc, "macro instruction uses large offset, which is not "
2998  "currently supported");
2999  return true;
3000  }
3001  }
3002 
3003  unsigned TmpReg = DstReg;
3004  if (UseSrcReg &&
3005  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
3006  SrcReg)) {
3007  // If $rs is the same as $rd, we need to use AT.
3008  // If it is not available we exit.
3009  unsigned ATReg = getATReg(IDLoc);
3010  if (!ATReg)
3011  return true;
3012  TmpReg = ATReg;
3013  }
3014 
3015  TOut.emitRRX(Mips::LD, TmpReg, ABI.GetGlobalPtr(),
3016  MCOperand::createExpr(GotExpr), IDLoc, STI);
3017 
3018  if (LoExpr)
3019  TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3020  IDLoc, STI);
3021 
3022  if (UseSrcReg)
3023  TOut.emitRRR(Mips::DADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3024 
3025  return false;
3026  }
3027 
3028  const MipsMCExpr *HiExpr =
3029  MipsMCExpr::create(MipsMCExpr::MEK_HI, SymExpr, getContext());
3030  const MipsMCExpr *LoExpr =
3031  MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());
3032 
3033  // This is the 64-bit symbol address expansion.
3034  if (ABI.ArePtrs64bit() && isGP64bit()) {
3035  // We need AT for the 64-bit expansion in the cases where the optional
3036  // source register is the destination register and for the superscalar
3037  // scheduled form.
3038  //
3039  // If it is not available we exit if the destination is the same as the
3040  // source register.
3041 
3042  const MipsMCExpr *HighestExpr =
3043  MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, SymExpr, getContext());
3044  const MipsMCExpr *HigherExpr =
3045  MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext());
3046 
3047  bool RdRegIsRsReg =
3048  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);
3049 
3050  if (canUseATReg() && UseSrcReg && RdRegIsRsReg) {
3051  unsigned ATReg = getATReg(IDLoc);
3052 
3053  // If $rs is the same as $rd:
3054  // (d)la $rd, sym($rd) => lui $at, %highest(sym)
3055  // daddiu $at, $at, %higher(sym)
3056  // dsll $at, $at, 16
3057  // daddiu $at, $at, %hi(sym)
3058  // dsll $at, $at, 16
3059  // daddiu $at, $at, %lo(sym)
3060  // daddu $rd, $at, $rd
3061  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3062  STI);
3063  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3064  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3065  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3066  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3067  IDLoc, STI);
3068  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3069  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3070  IDLoc, STI);
3071  TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
3072 
3073  return false;
3074  } else if (canUseATReg() && !RdRegIsRsReg) {
3075  unsigned ATReg = getATReg(IDLoc);
3076 
3077  // If the $rs is different from $rd or if $rs isn't specified and we
3078  // have $at available:
3079  // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym)
3080  // lui $at, %hi(sym)
3081  // daddiu $rd, $rd, %higher(sym)
3082  // daddiu $at, $at, %lo(sym)
3083  // dsll32 $rd, $rd, 0
3084  // daddu $rd, $rd, $at
3085  // (daddu $rd, $rd, $rs)
3086  //
3087  // Which is preferred for superscalar issue.
3088  TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3089  STI);
3090  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3091  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3092  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3093  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3094  IDLoc, STI);
3095  TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
3096  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
3097  if (UseSrcReg)
3098  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3099 
3100  return false;
3101  } else if (!canUseATReg() && !RdRegIsRsReg) {
3102  // Otherwise, synthesize the address in the destination register
3103  // serially:
3104  // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym)
3105  // daddiu $rd, $rd, %higher(sym)
3106  // dsll $rd, $rd, 16
3107  // daddiu $rd, $rd, %hi(sym)
3108  // dsll $rd, $rd, 16
3109  // daddiu $rd, $rd, %lo(sym)
3110  TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3111  STI);
3112  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3113  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3114  TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3115  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3116  MCOperand::createExpr(HiExpr), IDLoc, STI);
3117  TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3118  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3119  MCOperand::createExpr(LoExpr), IDLoc, STI);
3120  if (UseSrcReg)
3121  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3122 
3123  return false;
3124  } else {
3125  // We have a case where SrcReg == DstReg and we don't have $at
3126  // available. We can't expand this case, so error out appropriately.
3127  assert(SrcReg == DstReg && !canUseATReg() &&
3128  "Could have expanded dla but didn't?");
3129  reportParseError(IDLoc,
3130  "pseudo-instruction requires $at, which is not available");
3131  return true;
3132  }
3133  }
3134 
3135  // And now, the 32-bit symbol address expansion:
3136  // If $rs is the same as $rd:
3137  // (d)la $rd, sym($rd) => lui $at, %hi(sym)
3138  // ori $at, $at, %lo(sym)
3139  // addu $rd, $at, $rd
3140  // Otherwise, if the $rs is different from $rd or if $rs isn't specified:
3141  // (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym)
3142  // ori $rd, $rd, %lo(sym)
3143  // (addu $rd, $rd, $rs)
3144  unsigned TmpReg = DstReg;
3145  if (UseSrcReg &&
3146  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
3147  // If $rs is the same as $rd, we need to use AT.
3148  // If it is not available we exit.
3149  unsigned ATReg = getATReg(IDLoc);
3150  if (!ATReg)
3151  return true;
3152  TmpReg = ATReg;
3153  }
3154 
3155  TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3156  TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3157  IDLoc, STI);
3158 
3159  if (UseSrcReg)
3160  TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3161  else
3162  assert(
3163  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
3164 
3165  return false;
3166 }
3167 
3168 // Each double-precision register DO-D15 overlaps with two of the single
3169 // precision registers F0-F31. As an example, all of the following hold true:
3170 // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context.
3171 static unsigned nextReg(unsigned Reg) {
3172  if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
3173  return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
3174  switch (Reg) {
3175  default: llvm_unreachable("Unknown register in assembly macro expansion!");
3176  case Mips::ZERO: return Mips::AT;
3177  case Mips::AT: return Mips::V0;
3178  case Mips::V0: return Mips::V1;
3179  case Mips::V1: return Mips::A0;
3180  case Mips::A0: return Mips::A1;
3181  case Mips::A1: return Mips::A2;
3182  case Mips::A2: return Mips::A3;
3183  case Mips::A3: return Mips::T0;
3184  case Mips::T0: return Mips::T1;
3185  case Mips::T1: return Mips::T2;
3186  case Mips::T2: return Mips::T3;
3187  case Mips::T3: return Mips::T4;
3188  case Mips::T4: return Mips::T5;
3189  case Mips::T5: return Mips::T6;
3190  case Mips::T6: return Mips::T7;
3191  case Mips::T7: return Mips::S0;
3192  case Mips::S0: return Mips::S1;
3193  case Mips::S1: return Mips::S2;
3194  case Mips::S2: return Mips::S3;
3195  case Mips::S3: return Mips::S4;
3196  case Mips::S4: return Mips::S5;
3197  case Mips::S5: return Mips::S6;
3198  case Mips::S6: return Mips::S7;
3199  case Mips::S7: return Mips::T8;
3200  case Mips::T8: return Mips::T9;
3201  case Mips::T9: return Mips::K0;
3202  case Mips::K0: return Mips::K1;
3203  case Mips::K1: return Mips::GP;
3204  case Mips::GP: return Mips::SP;
3205  case Mips::SP: return Mips::FP;
3206  case Mips::FP: return Mips::RA;
3207  case Mips::RA: return Mips::ZERO;
3208  case Mips::D0: return Mips::F1;
3209  case Mips::D1: return Mips::F3;
3210  case Mips::D2: return Mips::F5;
3211  case Mips::D3: return Mips::F7;
3212  case Mips::D4: return Mips::F9;
3213  case Mips::D5: return Mips::F11;
3214  case Mips::D6: return Mips::F13;
3215  case Mips::D7: return Mips::F15;
3216  case Mips::D8: return Mips::F17;
3217  case Mips::D9: return Mips::F19;
3218  case Mips::D10: return Mips::F21;
3219  case Mips::D11: return Mips::F23;
3220  case Mips::D12: return Mips::F25;
3221  case Mips::D13: return Mips::F27;
3222  case Mips::D14: return Mips::F29;
3223  case Mips::D15: return Mips::F31;
3224  }
3225 }
3226 
3227 // FIXME: This method is too general. In principle we should compute the number
3228 // of instructions required to synthesize the immediate inline compared to
3229 // synthesizing the address inline and relying on non .text sections.
3230 // For static O32 and N32 this may yield a small benefit, for static N64 this is
3231 // likely to yield a much larger benefit as we have to synthesize a 64bit
3232 // address to load a 64 bit value.
3233 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
3234  MCSymbol *Sym) {
3235  unsigned ATReg = getATReg(IDLoc);
3236  if (!ATReg)
3237  return true;
3238 
3239  if(IsPicEnabled) {
3240  const MCExpr *GotSym =
3242  const MipsMCExpr *GotExpr =
3243  MipsMCExpr::create(MipsMCExpr::MEK_GOT, GotSym, getContext());
3244 
3245  if(isABI_O32() || isABI_N32()) {
3246  TOut.emitRRX(Mips::LW, ATReg, Mips::GP, MCOperand::createExpr(GotExpr),
3247  IDLoc, STI);
3248  } else { //isABI_N64()
3249  TOut.emitRRX(Mips::LD, ATReg, Mips::GP, MCOperand::createExpr(GotExpr),
3250  IDLoc, STI);
3251  }
3252  } else { //!IsPicEnabled
3253  const MCExpr *HiSym =
3255  const MipsMCExpr *HiExpr =
3256  MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext());
3257 
3258  // FIXME: This is technically correct but gives a different result to gas,
3259  // but gas is incomplete there (it has a fixme noting it doesn't work with
3260  // 64-bit addresses).
3261  // FIXME: With -msym32 option, the address expansion for N64 should probably
3262  // use the O32 / N32 case. It's safe to use the 64 address expansion as the
3263  // symbol's value is considered sign extended.
3264  if(isABI_O32() || isABI_N32()) {
3265  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3266  } else { //isABI_N64()
3267  const MCExpr *HighestSym =
3269  const MipsMCExpr *HighestExpr =
3270  MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, HighestSym, getContext());
3271  const MCExpr *HigherSym =
3273  const MipsMCExpr *HigherExpr =
3274  MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, HigherSym, getContext());
3275 
3276  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3277  STI);
3278  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3279  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3280  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3281  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3282  IDLoc, STI);
3283  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3284  }
3285  }
3286  return false;
3287 }
3288 
3289 bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR,
3290  bool Is64FPU, SMLoc IDLoc,
3291  MCStreamer &Out,
3292  const MCSubtargetInfo *STI) {
3293  MipsTargetStreamer &TOut = getTargetStreamer();
3294  assert(Inst.getNumOperands() == 2 && "Invalid operand count");
3295  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
3296  "Invalid instruction operand.");
3297 
3298  unsigned FirstReg = Inst.getOperand(0).getReg();
3299  uint64_t ImmOp64 = Inst.getOperand(1).getImm();
3300 
3301  uint32_t HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
3302  // If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
3303  // exponent field), convert it to double (e.g. 1 to 1.0)
3304  if ((HiImmOp64 & 0x7ff00000) == 0) {
3305  APFloat RealVal(APFloat::IEEEdouble(), ImmOp64);
3306  ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
3307  }
3308 
3309  uint32_t LoImmOp64 = ImmOp64 & 0xffffffff;
3310  HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
3311 
3312  if (IsSingle) {
3313  // Conversion of a double in an uint64_t to a float in a uint32_t,
3314  // retaining the bit pattern of a float.
3315  uint32_t ImmOp32;
3316  double doubleImm = BitsToDouble(ImmOp64);
3317  float tmp_float = static_cast<float>(doubleImm);
3318  ImmOp32 = FloatToBits(tmp_float);
3319 
3320  if (IsGPR) {
3321  if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,
3322  Out, STI))
3323  return true;
3324  return false;
3325  } else {
3326  unsigned ATReg = getATReg(IDLoc);
3327  if (!ATReg)
3328  return true;
3329  if (LoImmOp64 == 0) {
3330  if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc,
3331  Out, STI))
3332  return true;
3333  TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
3334  return false;
3335  }
3336 
3337  MCSection *CS = getStreamer().getCurrentSectionOnly();
3338  // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
3339  // where appropriate.
3340  MCSection *ReadOnlySection = getContext().getELFSection(
3341  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3342 
3343  MCSymbol *Sym = getContext().createTempSymbol();
3344  const MCExpr *LoSym =
3346  const MipsMCExpr *LoExpr =
3347  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3348 
3349  getStreamer().SwitchSection(ReadOnlySection);
3350  getStreamer().EmitLabel(Sym, IDLoc);
3351  getStreamer().EmitIntValue(ImmOp32, 4);
3352  getStreamer().SwitchSection(CS);
3353 
3354  if(emitPartialAddress(TOut, IDLoc, Sym))
3355  return true;
3356  TOut.emitRRX(Mips::LWC1, FirstReg, ATReg,
3357  MCOperand::createExpr(LoExpr), IDLoc, STI);
3358  }
3359  return false;
3360  }
3361 
3362  // if(!IsSingle)
3363  unsigned ATReg = getATReg(IDLoc);
3364  if (!ATReg)
3365  return true;
3366 
3367  if (IsGPR) {
3368  if (LoImmOp64 == 0) {
3369  if(isABI_N32() || isABI_N64()) {
3370  if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,
3371  IDLoc, Out, STI))
3372  return true;
3373  return false;
3374  } else {
3375  if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
3376  IDLoc, Out, STI))
3377  return true;
3378 
3379  if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true,
3380  IDLoc, Out, STI))
3381  return true;
3382  return false;
3383  }
3384  }
3385 
3386  MCSection *CS = getStreamer().getCurrentSectionOnly();
3387  MCSection *ReadOnlySection = getContext().getELFSection(
3388  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3389 
3390  MCSymbol *Sym = getContext().createTempSymbol();
3391  const MCExpr *LoSym =
3393  const MipsMCExpr *LoExpr =
3394  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3395 
3396  getStreamer().SwitchSection(ReadOnlySection);
3397  getStreamer().EmitLabel(Sym, IDLoc);
3398  getStreamer().EmitIntValue(HiImmOp64, 4);
3399  getStreamer().EmitIntValue(LoImmOp64, 4);
3400  getStreamer().SwitchSection(CS);
3401 
3402  if(emitPartialAddress(TOut, IDLoc, Sym))
3403  return true;
3404  if(isABI_N64())
3405  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3406  MCOperand::createExpr(LoExpr), IDLoc, STI);
3407  else
3408  TOut.emitRRX(Mips::ADDiu, ATReg, ATReg,
3409  MCOperand::createExpr(LoExpr), IDLoc, STI);
3410 
3411  if(isABI_N32() || isABI_N64())
3412  TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);
3413  else {
3414  TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);
3415  TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);
3416  }
3417  return false;
3418  } else { // if(!IsGPR && !IsSingle)
3419  if ((LoImmOp64 == 0) &&
3420  !((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
3421  // FIXME: In the case where the constant is zero, we can load the
3422  // register directly from the zero register.
3423  if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
3424  Out, STI))
3425  return true;
3426  if (isABI_N32() || isABI_N64())
3427  TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);
3428  else if (hasMips32r2()) {
3429  TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3430  TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
3431  } else {
3432  TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);
3433  TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3434  }
3435  return false;
3436  }
3437 
3438  MCSection *CS = getStreamer().getCurrentSectionOnly();
3439  // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
3440  // where appropriate.
3441  MCSection *ReadOnlySection = getContext().getELFSection(
3442  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3443 
3444  MCSymbol *Sym = getContext().createTempSymbol();
3445  const MCExpr *LoSym =
3447  const MipsMCExpr *LoExpr =
3448  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3449 
3450  getStreamer().SwitchSection(ReadOnlySection);
3451  getStreamer().EmitLabel(Sym, IDLoc);
3452  getStreamer().EmitIntValue(HiImmOp64, 4);
3453  getStreamer().EmitIntValue(LoImmOp64, 4);
3454  getStreamer().SwitchSection(CS);
3455 
3456  if(emitPartialAddress(TOut, IDLoc, Sym))
3457  return true;
3458  TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,
3459  MCOperand::createExpr(LoExpr), IDLoc, STI);
3460  }
3461  return false;
3462 }
3463 
3464 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
3465  MCStreamer &Out,
3466  const MCSubtargetInfo *STI) {
3467  MipsTargetStreamer &TOut = getTargetStreamer();
3468 
3469  assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
3470  "unexpected number of operands");
3471 
3472  MCOperand Offset = Inst.getOperand(0);
3473  if (Offset.isExpr()) {
3474  Inst.clear();
3475  Inst.setOpcode(Mips::BEQ_MM);
3476  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3477  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3478  Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
3479  } else {
3480  assert(Offset.isImm() && "expected immediate operand kind");
3481  if (isInt<11>(Offset.getImm())) {
3482  // If offset fits into 11 bits then this instruction becomes microMIPS
3483  // 16-bit unconditional branch instruction.
3484  if (inMicroMipsMode())
3485  Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
3486  } else {
3487  if (!isInt<17>(Offset.getImm()))
3488  return Error(IDLoc, "branch target out of range");
3489  if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
3490  return Error(IDLoc, "branch to misaligned address");
3491  Inst.clear();
3492  Inst.setOpcode(Mips::BEQ_MM);
3493  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3494  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3495  Inst.addOperand(MCOperand::createImm(Offset.getImm()));
3496  }
3497  }
3498  Out.EmitInstruction(Inst, *STI);
3499 
3500  // If .set reorder is active and branch instruction has a delay slot,
3501  // emit a NOP after it.
3502  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3503  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
3504  TOut.emitEmptyDelaySlot(true, IDLoc, STI);
3505 
3506  return false;
3507 }
3508 
3509 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3510  const MCSubtargetInfo *STI) {
3511  MipsTargetStreamer &TOut = getTargetStreamer();
3512  const MCOperand &DstRegOp = Inst.getOperand(0);
3513  assert(DstRegOp.isReg() && "expected register operand kind");
3514 
3515  const MCOperand &ImmOp = Inst.getOperand(1);
3516  assert(ImmOp.isImm() && "expected immediate operand kind");
3517 
3518  const MCOperand &MemOffsetOp = Inst.getOperand(2);
3519  assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) &&
3520  "expected immediate or expression operand");
3521 
3522  bool IsLikely = false;
3523 
3524  unsigned OpCode = 0;
3525  switch(Inst.getOpcode()) {
3526  case Mips::BneImm:
3527  OpCode = Mips::BNE;
3528  break;
3529  case Mips::BeqImm:
3530  OpCode = Mips::BEQ;
3531  break;
3532  case Mips::BEQLImmMacro:
3533  OpCode = Mips::BEQL;
3534  IsLikely = true;
3535  break;
3536  case Mips::BNELImmMacro:
3537  OpCode = Mips::BNEL;
3538  IsLikely = true;
3539  break;
3540  default:
3541  llvm_unreachable("Unknown immediate branch pseudo-instruction.");
3542  break;
3543  }
3544 
3545  int64_t ImmValue = ImmOp.getImm();
3546  if (ImmValue == 0) {
3547  if (IsLikely) {
3548  TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3549  MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3550  TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3551  } else
3552  TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3553  STI);
3554  } else {
3555  warnIfNoMacro(IDLoc);
3556 
3557  unsigned ATReg = getATReg(IDLoc);
3558  if (!ATReg)
3559  return true;
3560 
3561  if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
3562  IDLoc, Out, STI))
3563  return true;
3564 
3565  if (IsLikely) {
3566  TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
3567  MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3568  TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3569  } else
3570  TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
3571  }
3572  return false;
3573 }
3574 
3575 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3576  const MCSubtargetInfo *STI, bool IsLoad) {
3577  const MCOperand &DstRegOp = Inst.getOperand(0);
3578  assert(DstRegOp.isReg() && "expected register operand kind");
3579  const MCOperand &BaseRegOp = Inst.getOperand(1);
3580  assert(BaseRegOp.isReg() && "expected register operand kind");
3581  const MCOperand &OffsetOp = Inst.getOperand(2);
3582 
3583  MipsTargetStreamer &TOut = getTargetStreamer();
3584  unsigned DstReg = DstRegOp.getReg();
3585  unsigned BaseReg = BaseRegOp.getReg();
3586  unsigned TmpReg = DstReg;
3587 
3588  const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
3589  int16_t DstRegClass = Desc.OpInfo[0].RegClass;
3590  unsigned DstRegClassID =
3591  getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
3592  bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
3593  (DstRegClassID == Mips::GPR64RegClassID);
3594 
3595  if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
3596  // At this point we need AT to perform the expansions
3597  // and we exit if it is not available.
3598  TmpReg = getATReg(IDLoc);
3599  if (!TmpReg)
3600  return;
3601  }
3602 
3603  if (OffsetOp.isImm()) {
3604  int64_t LoOffset = OffsetOp.getImm() & 0xffff;
3605  int64_t HiOffset = OffsetOp.getImm() & ~0xffff;
3606 
3607  // If msb of LoOffset is 1(negative number) we must increment
3608  // HiOffset to account for the sign-extension of the low part.
3609  if (LoOffset & 0x8000)
3610  HiOffset += 0x10000;
3611 
3612  bool IsLargeOffset = HiOffset != 0;
3613 
3614  if (IsLargeOffset) {
3615  bool Is32BitImm = (HiOffset >> 32) == 0;
3616  if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
3617  IDLoc, Out, STI))
3618  return;
3619  }
3620 
3621  if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
3622  TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
3623  BaseReg, IDLoc, STI);
3624  TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
3625  } else {
3626  assert(OffsetOp.isExpr() && "expected expression operand kind");
3627  const MCExpr *ExprOffset = OffsetOp.getExpr();
3628  MCOperand LoOperand = MCOperand::createExpr(
3629  MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
3630  MCOperand HiOperand = MCOperand::createExpr(
3631  MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
3632 
3633  if (IsLoad)
3634  TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
3635  LoOperand, TmpReg, IDLoc, STI);
3636  else
3637  TOut.emitStoreWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
3638  LoOperand, TmpReg, IDLoc, STI);
3639  }
3640 }
3641 
3642 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
3643  MCStreamer &Out,
3644  const MCSubtargetInfo *STI) {
3645  unsigned OpNum = Inst.getNumOperands();
3646  unsigned Opcode = Inst.getOpcode();
3647  unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
3648 
3649  assert(Inst.getOperand(OpNum - 1).isImm() &&
3650  Inst.getOperand(OpNum - 2).isReg() &&
3651  Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.");
3652 
3653  if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
3654  Inst.getOperand(OpNum - 1).getImm() >= 0 &&
3655  (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
3656  Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
3657  (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
3658  Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
3659  // It can be implemented as SWM16 or LWM16 instruction.
3660  if (inMicroMipsMode() && hasMips32r6())
3661  NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
3662  else
3663  NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
3664  }
3665 
3666  Inst.setOpcode(NewOpcode);
3667  Out.EmitInstruction(Inst, *STI);
3668  return false;
3669 }
3670 
3671 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
3672  MCStreamer &Out,
3673  const MCSubtargetInfo *STI) {
3674  MipsTargetStreamer &TOut = getTargetStreamer();
3675  bool EmittedNoMacroWarning = false;
3676  unsigned PseudoOpcode = Inst.getOpcode();
3677  unsigned SrcReg = Inst.getOperand(0).getReg();
3678  const MCOperand &TrgOp = Inst.getOperand(1);
3679  const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
3680 
3681  unsigned ZeroSrcOpcode, ZeroTrgOpcode;
3682  bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
3683 
3684  unsigned TrgReg;
3685  if (TrgOp.isReg())
3686  TrgReg = TrgOp.getReg();
3687  else if (TrgOp.isImm()) {
3688  warnIfNoMacro(IDLoc);
3689  EmittedNoMacroWarning = true;
3690 
3691  TrgReg = getATReg(IDLoc);
3692  if (!TrgReg)
3693  return true;
3694 
3695  switch(PseudoOpcode) {
3696  default:
3697  llvm_unreachable("unknown opcode for branch pseudo-instruction");
3698  case Mips::BLTImmMacro:
3699  PseudoOpcode = Mips::BLT;
3700  break;
3701  case Mips::BLEImmMacro:
3702  PseudoOpcode = Mips::BLE;
3703  break;
3704  case Mips::BGEImmMacro:
3705  PseudoOpcode = Mips::BGE;
3706  break;
3707  case Mips::BGTImmMacro:
3708  PseudoOpcode = Mips::BGT;
3709  break;
3710  case Mips::BLTUImmMacro:
3711  PseudoOpcode = Mips::BLTU;
3712  break;
3713  case Mips::BLEUImmMacro:
3714  PseudoOpcode = Mips::BLEU;
3715  break;
3716  case Mips::BGEUImmMacro:
3717  PseudoOpcode = Mips::BGEU;
3718  break;
3719  case Mips::BGTUImmMacro:
3720  PseudoOpcode = Mips::BGTU;
3721  break;
3722  case Mips::BLTLImmMacro:
3723  PseudoOpcode = Mips::BLTL;
3724  break;
3725  case Mips::BLELImmMacro:
3726  PseudoOpcode = Mips::BLEL;
3727  break;
3728  case Mips::BGELImmMacro:
3729  PseudoOpcode = Mips::BGEL;
3730  break;
3731  case Mips::BGTLImmMacro:
3732  PseudoOpcode = Mips::BGTL;
3733  break;
3734  case Mips::BLTULImmMacro:
3735  PseudoOpcode = Mips::BLTUL;
3736  break;
3737  case Mips::BLEULImmMacro:
3738  PseudoOpcode = Mips::BLEUL;
3739  break;
3740  case Mips::BGEULImmMacro:
3741  PseudoOpcode = Mips::BGEUL;
3742  break;
3743  case Mips::BGTULImmMacro:
3744  PseudoOpcode = Mips::BGTUL;
3745  break;
3746  }
3747 
3748  if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
3749  false, IDLoc, Out, STI))
3750  return true;
3751  }
3752 
3753  switch (PseudoOpcode) {
3754  case Mips::BLT:
3755  case Mips::BLTU:
3756  case Mips::BLTL:
3757  case Mips::BLTUL:
3758  AcceptsEquality = false;
3759  ReverseOrderSLT = false;
3760  IsUnsigned =
3761  ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
3762  IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
3763  ZeroSrcOpcode = Mips::BGTZ;
3764  ZeroTrgOpcode = Mips::BLTZ;
3765  break;
3766  case Mips::BLE:
3767  case Mips::BLEU:
3768  case Mips::BLEL:
3769  case Mips::BLEUL:
3770  AcceptsEquality = true;
3771  ReverseOrderSLT = true;
3772  IsUnsigned =
3773  ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
3774  IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
3775  ZeroSrcOpcode = Mips::BGEZ;
3776  ZeroTrgOpcode = Mips::BLEZ;
3777  break;
3778  case Mips::BGE:
3779  case Mips::BGEU:
3780  case Mips::BGEL:
3781  case Mips::BGEUL:
3782  AcceptsEquality = true;
3783  ReverseOrderSLT = false;
3784  IsUnsigned =
3785  ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
3786  IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
3787  ZeroSrcOpcode = Mips::BLEZ;
3788  ZeroTrgOpcode = Mips::BGEZ;
3789  break;
3790  case Mips::BGT:
3791  case Mips::BGTU:
3792  case Mips::BGTL:
3793  case Mips::BGTUL:
3794  AcceptsEquality = false;
3795  ReverseOrderSLT = true;
3796  IsUnsigned =
3797  ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
3798  IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
3799  ZeroSrcOpcode = Mips::BLTZ;
3800  ZeroTrgOpcode = Mips::BGTZ;
3801  break;
3802  default:
3803  llvm_unreachable("unknown opcode for branch pseudo-instruction");
3804  }
3805 
3806  bool IsTrgRegZero = (TrgReg == Mips::ZERO);
3807  bool IsSrcRegZero = (SrcReg == Mips::ZERO);
3808  if (IsSrcRegZero && IsTrgRegZero) {
3809  // FIXME: All of these Opcode-specific if's are needed for compatibility
3810  // with GAS' behaviour. However, they may not generate the most efficient
3811  // code in some circumstances.
3812  if (PseudoOpcode == Mips::BLT) {
3813  TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3814  IDLoc, STI);
3815  return false;
3816  }
3817  if (PseudoOpcode == Mips::BLE) {
3818  TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3819  IDLoc, STI);
3820  Warning(IDLoc, "branch is always taken");
3821  return false;
3822  }
3823  if (PseudoOpcode == Mips::BGE) {
3824  TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3825  IDLoc, STI);
3826  Warning(IDLoc, "branch is always taken");
3827  return false;
3828  }
3829  if (PseudoOpcode == Mips::BGT) {
3830  TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3831  IDLoc, STI);
3832  return false;
3833  }
3834  if (PseudoOpcode == Mips::BGTU) {
3835  TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
3836  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3837  return false;
3838  }
3839  if (AcceptsEquality) {
3840  // If both registers are $0 and the pseudo-branch accepts equality, it
3841  // will always be taken, so we emit an unconditional branch.
3842  TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3843  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3844  Warning(IDLoc, "branch is always taken");
3845  return false;
3846  }
3847  // If both registers are $0 and the pseudo-branch does not accept
3848  // equality, it will never be taken, so we don't have to emit anything.
3849  return false;
3850  }
3851  if (IsSrcRegZero || IsTrgRegZero) {
3852  if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
3853  (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
3854  // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or
3855  // if the $rt is $0 and the pseudo-branch is BLTU (x < 0),
3856  // the pseudo-branch will never be taken, so we don't emit anything.
3857  // This only applies to unsigned pseudo-branches.
3858  return false;
3859  }
3860  if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
3861  (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
3862  // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or
3863  // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0),
3864  // the pseudo-branch will always be taken, so we emit an unconditional
3865  // branch.
3866  // This only applies to unsigned pseudo-branches.
3867  TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3868  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3869  Warning(IDLoc, "branch is always taken");
3870  return false;
3871  }
3872  if (IsUnsigned) {
3873  // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or
3874  // if the $rt is $0 and the pseudo-branch is BGTU (x > 0),
3875  // the pseudo-branch will be taken only when the non-zero register is
3876  // different from 0, so we emit a BNEZ.
3877  //
3878  // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or
3879  // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0),
3880  // the pseudo-branch will be taken only when the non-zero register is
3881  // equal to 0, so we emit a BEQZ.
3882  //
3883  // Because only BLEU and BGEU branch on equality, we can use the
3884  // AcceptsEquality variable to decide when to emit the BEQZ.
3885  TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
3886  IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
3887  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3888  return false;
3889  }
3890  // If we have a signed pseudo-branch and one of the registers is $0,
3891  // we can use an appropriate compare-to-zero branch. We select which one
3892  // to use in the switch statement above.
3893  TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
3894  IsSrcRegZero ? TrgReg : SrcReg,
3895  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3896  return false;
3897  }
3898 
3899  // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the
3900  // expansions. If it is not available, we return.
3901  unsigned ATRegNum = getATReg(IDLoc);
3902  if (!ATRegNum)
3903  return true;
3904 
3905  if (!EmittedNoMacroWarning)
3906  warnIfNoMacro(IDLoc);
3907 
3908  // SLT fits well with 2 of our 4 pseudo-branches:
3909  // BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
3910  // BGT, where $rs > $rt, translates into "slt $at, $rt, $rs".
3911  // If the result of the SLT is 1, we branch, and if it's 0, we don't.
3912  // This is accomplished by using a BNEZ with the result of the SLT.
3913  //
3914  // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
3915  // and BLE with BGT), so we change the BNEZ into a BEQZ.
3916  // Because only BGE and BLE branch on equality, we can use the
3917  // AcceptsEquality variable to decide when to emit the BEQZ.
3918  // Note that the order of the SLT arguments doesn't change between
3919  // opposites.
3920  //
3921  // The same applies to the unsigned variants, except that SLTu is used
3922  // instead of SLT.
3923  TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
3924  ReverseOrderSLT ? TrgReg : SrcReg,
3925  ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI);
3926 
3927  TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
3928  : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
3929  ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
3930  STI);
3931  return false;
3932 }
3933 
3934 // Expand a integer division macro.
3935 //
3936 // Notably we don't have to emit a warning when encountering $rt as the $zero
3937 // register, or 0 as an immediate. processInstruction() has already done that.
3938 //
3939 // The destination register can only be $zero when expanding (S)DivIMacro or
3940 // D(S)DivMacro.
3941 
3942 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3943  const MCSubtargetInfo *STI, const bool IsMips64,
3944  const bool Signed) {
3945  MipsTargetStreamer &TOut = getTargetStreamer();
3946 
3947  warnIfNoMacro(IDLoc);
3948 
3949  const MCOperand &RdRegOp = Inst.getOperand(0);
3950  assert(RdRegOp.isReg() && "expected register operand kind");
3951  unsigned RdReg = RdRegOp.getReg();
3952 
3953  const MCOperand &RsRegOp = Inst.getOperand(1);
3954  assert(RsRegOp.isReg() && "expected register operand kind");
3955  unsigned RsReg = RsRegOp.getReg();
3956 
3957  unsigned RtReg;
3958  int64_t ImmValue;
3959 
3960  const MCOperand &RtOp = Inst.getOperand(2);
3961  assert((RtOp.isReg() || RtOp.isImm()) &&
3962  "expected register or immediate operand kind");
3963  if (RtOp.isReg())
3964  RtReg = RtOp.getReg();
3965  else
3966  ImmValue = RtOp.getImm();
3967 
3968  unsigned DivOp;
3969  unsigned ZeroReg;
3970  unsigned SubOp;
3971 
3972  if (IsMips64) {
3973  DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
3974  ZeroReg = Mips::ZERO_64;
3975  SubOp = Mips::DSUB;
3976  } else {
3977  DivOp = Signed ? Mips::SDIV : Mips::UDIV;
3978  ZeroReg = Mips::ZERO;
3979  SubOp = Mips::SUB;
3980  }
3981 
3982  bool UseTraps = useTraps();
3983 
3984  unsigned Opcode = Inst.getOpcode();
3985  bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro ||
3986  Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro ||
3987  Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro ||
3988  Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro;
3989 
3990  bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro ||
3991  Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro ||
3992  Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro ||
3993  Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro;
3994 
3995  if (RtOp.isImm()) {
3996  unsigned ATReg = getATReg(IDLoc);
3997  if (!ATReg)
3998  return true;
3999 
4000  if (ImmValue == 0) {
4001  if (UseTraps)
4002  TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4003  else
4004  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4005  return false;
4006  }
4007 
4008  if (isRem && (ImmValue == 1 || (Signed && (ImmValue == -1)))) {
4009  TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
4010  return false;
4011  } else if (isDiv && ImmValue == 1) {
4012  TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4013  return false;
4014  } else if (isDiv && Signed && ImmValue == -1) {
4015  TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
4016  return false;
4017  } else {
4018  if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
4019  false, Inst.getLoc(), Out, STI))
4020  return true;
4021  TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);
4022  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4023  return false;
4024  }
4025  return true;
4026  }
4027 
4028  // If the macro expansion of (d)div(u) or (d)rem(u) would always trap or
4029  // break, insert the trap/break and exit. This gives a different result to
4030  // GAS. GAS has an inconsistency/missed optimization in that not all cases
4031  // are handled equivalently. As the observed behaviour is the same, we're ok.
4032  if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
4033  if (UseTraps) {
4034  TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4035  return false;
4036  }
4037  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4038  return false;
4039  }
4040 
4041  // (d)rem(u) $0, $X, $Y is a special case. Like div $zero, $X, $Y, it does
4042  // not expand to macro sequence.
4043  if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
4044  TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4045  return false;
4046  }
4047 
4048  // Temporary label for first branch traget
4050  MCSymbol *BrTarget;
4051  MCOperand LabelOp;
4052 
4053  if (UseTraps) {
4054  TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
4055  } else {
4056  // Branch to the li instruction.
4057  BrTarget = Context.createTempSymbol();
4058  LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4059  TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
4060  }
4061 
4062  TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4063 
4064  if (!UseTraps)
4065  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4066 
4067  if (!Signed) {
4068  if (!UseTraps)
4069  TOut.getStreamer().EmitLabel(BrTarget);
4070 
4071  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4072  return false;
4073  }
4074 
4075  unsigned ATReg = getATReg(IDLoc);
4076  if (!ATReg)
4077  return true;
4078 
4079  if (!UseTraps)
4080  TOut.getStreamer().EmitLabel(BrTarget);
4081 
4082  TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
4083 
4084  // Temporary label for the second branch target.
4085  MCSymbol *BrTargetEnd = Context.createTempSymbol();
4086  MCOperand LabelOpEnd =
4087  MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));
4088 
4089  // Branch to the mflo instruction.
4090  TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
4091 
4092  if (IsMips64) {
4093  TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
4094  TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
4095  } else {
4096  TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
4097  }
4098 
4099  if (UseTraps)
4100  TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
4101  else {
4102  // Branch to the mflo instruction.
4103  TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
4104  TOut.emitNop(IDLoc, STI);
4105  TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
4106  }
4107 
4108  TOut.getStreamer().EmitLabel(BrTargetEnd);
4109  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4110  return false;
4111 }
4112 
4113 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
4114  SMLoc IDLoc, MCStreamer &Out,
4115  const MCSubtargetInfo *STI) {
4116  MipsTargetStreamer &TOut = getTargetStreamer();
4117 
4118  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4119  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
4120  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
4121 
4122  unsigned FirstReg = Inst.getOperand(0).getReg();
4123  unsigned SecondReg = Inst.getOperand(1).getReg();
4124  unsigned ThirdReg = Inst.getOperand(2).getReg();
4125 
4126  if (hasMips1() && !hasMips2()) {
4127  unsigned ATReg = getATReg(IDLoc);
4128  if (!ATReg)
4129  return true;
4130  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4131  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4132  TOut.emitNop(IDLoc, STI);
4133  TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
4134  TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
4135  TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
4136  TOut.emitNop(IDLoc, STI);
4137  TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
4138  : Mips::CVT_W_S,
4139  FirstReg, SecondReg, IDLoc, STI);
4140  TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
4141  TOut.emitNop(IDLoc, STI);
4142  return false;
4143  }
4144 
4145  TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
4146  : Mips::TRUNC_W_S,
4147  FirstReg, SecondReg, IDLoc, STI);
4148 
4149  return false;
4150 }
4151 
4152 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
4153  MCStreamer &Out, const MCSubtargetInfo *STI) {
4154  if (hasMips32r6() || hasMips64r6()) {
4155  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4156  }
4157 
4158  const MCOperand &DstRegOp = Inst.getOperand(0);
4159  assert(DstRegOp.isReg() && "expected register operand kind");
4160  const MCOperand &SrcRegOp = Inst.getOperand(1);
4161  assert(SrcRegOp.isReg() && "expected register operand kind");
4162  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4163  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4164 
4165  MipsTargetStreamer &TOut = getTargetStreamer();
4166  unsigned DstReg = DstRegOp.getReg();
4167  unsigned SrcReg = SrcRegOp.getReg();
4168  int64_t OffsetValue = OffsetImmOp.getImm();
4169 
4170  // NOTE: We always need AT for ULHU, as it is always used as the source
4171  // register for one of the LBu's.
4172  warnIfNoMacro(IDLoc);
4173  unsigned ATReg = getATReg(IDLoc);
4174  if (!ATReg)
4175  return true;
4176 
4177  bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
4178  if (IsLargeOffset) {
4179  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
4180  IDLoc, Out, STI))
4181  return true;
4182  }
4183 
4184  int64_t FirstOffset = IsLargeOffset ? 0 : OffsetValue;
4185  int64_t SecondOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
4186  if (isLittle())
4187  std::swap(FirstOffset, SecondOffset);
4188 
4189  unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg;
4190  unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg;
4191 
4192  unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg;
4193  unsigned SllReg = IsLargeOffset ? DstReg : ATReg;
4194 
4195  TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
4196  FirstOffset, IDLoc, STI);
4197  TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI);
4198  TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
4199  TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4200 
4201  return false;
4202 }
4203 
4204 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4205  const MCSubtargetInfo *STI) {
4206  if (hasMips32r6() || hasMips64r6()) {
4207  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4208  }
4209 
4210  const MCOperand &DstRegOp = Inst.getOperand(0);
4211  assert(DstRegOp.isReg() && "expected register operand kind");
4212  const MCOperand &SrcRegOp = Inst.getOperand(1);
4213  assert(SrcRegOp.isReg() && "expected register operand kind");
4214  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4215  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4216 
4217  MipsTargetStreamer &TOut = getTargetStreamer();
4218  unsigned DstReg = DstRegOp.getReg();
4219  unsigned SrcReg = SrcRegOp.getReg();
4220  int64_t OffsetValue = OffsetImmOp.getImm();
4221 
4222  warnIfNoMacro(IDLoc);
4223  unsigned ATReg = getATReg(IDLoc);
4224  if (!ATReg)
4225  return true;
4226 
4227  bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
4228  if (IsLargeOffset) {
4229  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
4230  IDLoc, Out, STI))
4231  return true;
4232  }
4233 
4234  int64_t FirstOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
4235  int64_t SecondOffset = IsLargeOffset ? 0 : OffsetValue;
4236  if (isLittle())
4237  std::swap(FirstOffset, SecondOffset);
4238 
4239  if (IsLargeOffset) {
4240  TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI);
4241  TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI);
4242  TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI);
4243  TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI);
4244  TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
4245  TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4246  } else {
4247  TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI);
4248  TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI);
4249  TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI);
4250  }
4251 
4252  return false;
4253 }
4254 
4255 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4256  const MCSubtargetInfo *STI) {
4257  if (hasMips32r6() || hasMips64r6()) {
4258  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4259  }
4260 
4261  const MCOperand &DstRegOp = Inst.getOperand(0);
4262  assert(DstRegOp.isReg() && "expected register operand kind");
4263  const MCOperand &SrcRegOp = Inst.getOperand(1);
4264  assert(SrcRegOp.isReg() && "expected register operand kind");
4265  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4266  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4267 
4268  MipsTargetStreamer &TOut = getTargetStreamer();
4269  unsigned DstReg = DstRegOp.getReg();
4270  unsigned SrcReg = SrcRegOp.getReg();
4271  int64_t OffsetValue = OffsetImmOp.getImm();
4272 
4273  // Compute left/right load/store offsets.
4274  bool IsLargeOffset = !(isInt<16>(OffsetValue + 3) && isInt<16>(OffsetValue));
4275  int64_t LxlOffset = IsLargeOffset ? 0 : OffsetValue;
4276  int64_t LxrOffset = IsLargeOffset ? 3 : (OffsetValue + 3);
4277  if (isLittle())
4278  std::swap(LxlOffset, LxrOffset);
4279 
4280  bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
4281  bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset;
4282  unsigned TmpReg = SrcReg;
4283  if (IsLargeOffset || DoMove) {
4284  warnIfNoMacro(IDLoc);
4285  TmpReg = getATReg(IDLoc);
4286  if (!TmpReg)
4287  return true;
4288  }
4289 
4290  if (IsLargeOffset) {
4291  if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true,
4292  IDLoc, Out, STI))
4293  return true;
4294  }
4295 
4296  if (DoMove)
4297  std::swap(DstReg, TmpReg);
4298 
4299  unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL;
4300  unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR;
4301  TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI);
4302  TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
4303 
4304  if (DoMove)
4305  TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4306 
4307  return false;
4308 }
4309 
4310 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4311  const MCSubtargetInfo *STI) {
4312  MipsTargetStreamer &TOut = getTargetStreamer();
4313 
4314  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4315  assert(Inst.getOperand(0).isReg() &&
4316  Inst.getOperand(1).isReg() &&
4317  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
4318 
4319  unsigned DstReg = Inst.getOperand(0).getReg();
4320  unsigned SrcReg = Inst.getOperand(1).getReg();
4321  unsigned OpReg = Inst.getOperand(2).getReg();
4322  unsigned OpCode;
4323 
4324  warnIfNoMacro(IDLoc);
4325 
4326  switch (Inst.getOpcode()) {
4327  case Mips::SGE:
4328  OpCode = Mips::SLT;
4329  break;
4330  case Mips::SGEU:
4331  OpCode = Mips::SLTu;
4332  break;
4333  default:
4334  llvm_unreachable("unexpected 'sge' opcode");
4335  }
4336 
4337  // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
4338  TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4339  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4340 
4341  return false;
4342 }
4343 
4344 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4345  const MCSubtargetInfo *STI) {
4346  MipsTargetStreamer &TOut = getTargetStreamer();
4347 
4348  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4349  assert(Inst.getOperand(0).isReg() &&
4350  Inst.getOperand(1).isReg() &&
4351  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4352 
4353  unsigned DstReg = Inst.getOperand(0).getReg();
4354  unsigned SrcReg = Inst.getOperand(1).getReg();
4355  int64_t ImmValue = Inst.getOperand(2).getImm();
4356  unsigned OpRegCode, OpImmCode;
4357 
4358  warnIfNoMacro(IDLoc);
4359 
4360  switch (Inst.getOpcode()) {
4361  case Mips::SGEImm:
4362  case Mips::SGEImm64:
4363  OpRegCode = Mips::SLT;
4364  OpImmCode = Mips::SLTi;
4365  break;
4366  case Mips::SGEUImm:
4367  case Mips::SGEUImm64:
4368  OpRegCode = Mips::SLTu;
4369  OpImmCode = Mips::SLTiu;
4370  break;
4371  default:
4372  llvm_unreachable("unexpected 'sge' opcode with immediate");
4373  }
4374 
4375  // $SrcReg >= Imm is equal to (not ($SrcReg < Imm))
4376  if (isInt<16>(ImmValue)) {
4377  // Use immediate version of STL.
4378  TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
4379  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4380  } else {
4381  unsigned ImmReg = DstReg;
4382  if (DstReg == SrcReg) {
4383  unsigned ATReg = getATReg(Inst.getLoc());
4384  if (!ATReg)
4385  return true;
4386  ImmReg = ATReg;
4387  }
4388 
4389  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4390  false, IDLoc, Out, STI))
4391  return true;
4392 
4393  TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4394  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4395  }
4396 
4397  return false;
4398 }
4399 
4400 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4401  const MCSubtargetInfo *STI) {
4402  MipsTargetStreamer &TOut = getTargetStreamer();
4403 
4404  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4405  assert(Inst.getOperand(0).isReg() &&
4406  Inst.getOperand(1).isReg() &&
4407  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4408 
4409  unsigned DstReg = Inst.getOperand(0).getReg();
4410  unsigned SrcReg = Inst.getOperand(1).getReg();
4411  unsigned ImmReg = DstReg;
4412  int64_t ImmValue = Inst.getOperand(2).getImm();
4413  unsigned OpCode;
4414 
4415  warnIfNoMacro(IDLoc);
4416 
4417  switch (Inst.getOpcode()) {
4418  case Mips::SGTImm:
4419  case Mips::SGTImm64:
4420  OpCode = Mips::SLT;
4421  break;
4422  case Mips::SGTUImm:
4423  case Mips::SGTUImm64:
4424  OpCode = Mips::SLTu;
4425  break;
4426  default:
4427  llvm_unreachable("unexpected 'sgt' opcode with immediate");
4428  }
4429 
4430  if (DstReg == SrcReg) {
4431  unsigned ATReg = getATReg(Inst.getLoc());
4432  if (!ATReg)
4433  return true;
4434  ImmReg = ATReg;
4435  }
4436 
4437  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4438  false, IDLoc, Out, STI))
4439  return true;
4440 
4441  // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
4442  TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
4443 
4444  return false;
4445 }
4446 
4447 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
4448  MCStreamer &Out,
4449  const MCSubtargetInfo *STI) {
4450  MipsTargetStreamer &TOut = getTargetStreamer();
4451 
4452  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4453  assert(Inst.getOperand(0).isReg() &&
4454  Inst.getOperand(1).isReg() &&
4455  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4456 
4457  unsigned ATReg = Mips::NoRegister;
4458  unsigned FinalDstReg = Mips::NoRegister;
4459  unsigned DstReg = Inst.getOperand(0).getReg();
4460  unsigned SrcReg = Inst.getOperand(1).getReg();
4461  int64_t ImmValue = Inst.getOperand(2).getImm();
4462 
4463  bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue));
4464 
4465  unsigned FinalOpcode = Inst.getOpcode();
4466 
4467  if (DstReg == SrcReg) {
4468  ATReg = getATReg(Inst.getLoc());
4469  if (!ATReg)
4470  return true;
4471  FinalDstReg = DstReg;
4472  DstReg = ATReg;
4473  }
4474 
4475  if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false,
4476  Inst.getLoc(), Out, STI)) {
4477  switch (FinalOpcode) {
4478  default:
4479  llvm_unreachable("unimplemented expansion");
4480  case Mips::ADDi:
4481  FinalOpcode = Mips::ADD;
4482  break;
4483  case Mips::ADDiu:
4484  FinalOpcode = Mips::ADDu;
4485  break;
4486  case Mips::ANDi:
4487  FinalOpcode = Mips::AND;
4488  break;
4489  case Mips::NORImm:
4490  FinalOpcode = Mips::NOR;
4491  break;
4492  case Mips::ORi:
4493  FinalOpcode = Mips::OR;
4494  break;
4495  case Mips::SLTi:
4496  FinalOpcode = Mips::SLT;
4497  break;
4498  case Mips::SLTiu:
4499  FinalOpcode = Mips::SLTu;
4500  break;
4501  case Mips::XORi:
4502  FinalOpcode = Mips::XOR;
4503  break;
4504  case Mips::ADDi_MM:
4505  FinalOpcode = Mips::ADD_MM;
4506  break;
4507  case Mips::ADDiu_MM:
4508  FinalOpcode = Mips::ADDu_MM;
4509  break;
4510  case Mips::ANDi_MM:
4511  FinalOpcode = Mips::AND_MM;
4512  break;
4513  case Mips::ORi_MM:
4514  FinalOpcode = Mips::OR_MM;
4515  break;
4516  case Mips::SLTi_MM:
4517  FinalOpcode = Mips::SLT_MM;
4518  break;
4519  case Mips::SLTiu_MM:
4520  FinalOpcode = Mips::SLTu_MM;
4521  break;
4522  case Mips::XORi_MM:
4523  FinalOpcode = Mips::XOR_MM;
4524  break;
4525  case Mips::ANDi64:
4526  FinalOpcode = Mips::AND64;
4527  break;
4528  case Mips::NORImm64:
4529  FinalOpcode = Mips::NOR64;
4530  break;
4531  case Mips::ORi64:
4532  FinalOpcode = Mips::OR64;
4533  break;
4534  case Mips::SLTImm64:
4535  FinalOpcode = Mips::SLT64;
4536  break;
4537  case Mips::SLTUImm64:
4538  FinalOpcode = Mips::SLTu64;
4539  break;
4540  case Mips::XORi64:
4541  FinalOpcode = Mips::XOR64;
4542  break;
4543  }
4544 
4545  if (FinalDstReg == Mips::NoRegister)
4546  TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
4547  else
4548  TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
4549  return false;
4550  }
4551  return true;
4552 }
4553 
4554 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4555  const MCSubtargetInfo *STI) {
4556  MipsTargetStreamer &TOut = getTargetStreamer();
4557  unsigned ATReg = Mips::NoRegister;
4558  unsigned DReg = Inst.getOperand(0).getReg();
4559  unsigned SReg = Inst.getOperand(1).getReg();
4560  unsigned TReg = Inst.getOperand(2).getReg();
4561  unsigned TmpReg = DReg;
4562 
4563  unsigned FirstShift = Mips::NOP;
4564  unsigned SecondShift = Mips::NOP;
4565 
4566  if (hasMips32r2()) {
4567  if (DReg == SReg) {
4568  TmpReg = getATReg(Inst.getLoc());
4569  if (!TmpReg)
4570  return true;
4571  }
4572 
4573  if (Inst.getOpcode() == Mips::ROL) {
4574  TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4575  TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4576  return false;
4577  }
4578 
4579  if (Inst.getOpcode() == Mips::ROR) {
4580  TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4581  return false;
4582  }
4583 
4584  return true;
4585  }
4586 
4587  if (hasMips32()) {
4588  switch (Inst.getOpcode()) {
4589  default:
4590  llvm_unreachable("unexpected instruction opcode");
4591  case Mips::ROL:
4592  FirstShift = Mips::SRLV;
4593  SecondShift = Mips::SLLV;
4594  break;
4595  case Mips::ROR:
4596  FirstShift = Mips::SLLV;
4597  SecondShift = Mips::SRLV;
4598  break;
4599  }
4600 
4601  ATReg = getATReg(Inst.getLoc());
4602  if (!ATReg)
4603  return true;
4604 
4605  TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4606  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4607  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4608  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4609 
4610  return false;
4611  }
4612 
4613  return true;
4614 }
4615 
4616 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
4617  MCStreamer &Out,
4618  const MCSubtargetInfo *STI) {
4619  MipsTargetStreamer &TOut = getTargetStreamer();
4620  unsigned ATReg = Mips::NoRegister;
4621  unsigned DReg = Inst.getOperand(0).getReg();
4622  unsigned SReg = Inst.getOperand(1).getReg();
4623  int64_t ImmValue = Inst.getOperand(2).getImm();
4624 
4625  unsigned FirstShift = Mips::NOP;
4626  unsigned SecondShift = Mips::NOP;
4627 
4628  if (hasMips32r2()) {
4629  if (Inst.getOpcode() == Mips::ROLImm) {
4630  uint64_t MaxShift = 32;
4631  uint64_t ShiftValue = ImmValue;
4632  if (ImmValue != 0)
4633  ShiftValue = MaxShift - ImmValue;
4634  TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4635  return false;
4636  }
4637 
4638  if (Inst.getOpcode() == Mips::RORImm) {
4639  TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
4640  return false;
4641  }
4642 
4643  return true;
4644  }
4645 
4646  if (hasMips32()) {
4647  if (ImmValue == 0) {
4648  TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
4649  return false;
4650  }
4651 
4652  switch (Inst.getOpcode()) {
4653  default:
4654  llvm_unreachable("unexpected instruction opcode");
4655  case Mips::ROLImm:
4656  FirstShift = Mips::SLL;
4657  SecondShift = Mips::SRL;
4658  break;
4659  case Mips::RORImm:
4660  FirstShift = Mips::SRL;
4661  SecondShift = Mips::SLL;
4662  break;
4663  }
4664 
4665  ATReg = getATReg(Inst.getLoc());
4666  if (!ATReg)
4667  return true;
4668 
4669  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI);
4670  TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
4671  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4672 
4673  return false;
4674  }
4675 
4676  return true;
4677 }
4678 
4679 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4680  const MCSubtargetInfo *STI) {
4681  MipsTargetStreamer &TOut = getTargetStreamer();
4682  unsigned ATReg = Mips::NoRegister;
4683  unsigned DReg = Inst.getOperand(0).getReg();
4684  unsigned SReg = Inst.getOperand(1).getReg();
4685  unsigned TReg = Inst.getOperand(2).getReg();
4686  unsigned TmpReg = DReg;
4687 
4688  unsigned FirstShift = Mips::NOP;
4689  unsigned SecondShift = Mips::NOP;
4690 
4691  if (hasMips64r2()) {
4692  if (TmpReg == SReg) {
4693  TmpReg = getATReg(Inst.getLoc());
4694  if (!TmpReg)
4695  return true;
4696  }
4697 
4698  if (Inst.getOpcode() == Mips::DROL) {
4699  TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4700  TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4701  return false;
4702  }
4703 
4704  if (Inst.getOpcode() == Mips::DROR) {
4705  TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4706  return false;
4707  }
4708 
4709  return true;
4710  }
4711 
4712  if (hasMips64()) {
4713  switch (Inst.getOpcode()) {
4714  default:
4715  llvm_unreachable("unexpected instruction opcode");
4716  case Mips::DROL:
4717  FirstShift = Mips::DSRLV;
4718  SecondShift = Mips::DSLLV;
4719  break;
4720  case Mips::DROR:
4721  FirstShift = Mips::DSLLV;
4722  SecondShift = Mips::DSRLV;
4723  break;
4724  }
4725 
4726  ATReg = getATReg(Inst.getLoc());
4727  if (!ATReg)
4728  return true;
4729 
4730  TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4731  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4732  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4733  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4734 
4735  return false;
4736  }
4737 
4738  return true;
4739 }
4740 
4741 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
4742  MCStreamer &Out,
4743  const MCSubtargetInfo *STI) {
4744  MipsTargetStreamer &TOut = getTargetStreamer();
4745  unsigned ATReg = Mips::NoRegister;
4746  unsigned DReg = Inst.getOperand(0).getReg();
4747  unsigned SReg = Inst.getOperand(1).getReg();
4748  int64_t ImmValue = Inst.getOperand(2).getImm() % 64;
4749 
4750  unsigned FirstShift = Mips::NOP;
4751  unsigned SecondShift = Mips::NOP;
4752 
4753  MCInst TmpInst;
4754 
4755  if (hasMips64r2()) {
4756  unsigned FinalOpcode = Mips::NOP;
4757  if (ImmValue == 0)
4758  FinalOpcode = Mips::DROTR;
4759  else if (ImmValue % 32 == 0)
4760  FinalOpcode = Mips::DROTR32;
4761  else if ((ImmValue >= 1) && (ImmValue <= 32)) {
4762  if (Inst.getOpcode() == Mips::DROLImm)
4763  FinalOpcode = Mips::DROTR32;
4764  else
4765  FinalOpcode = Mips::DROTR;
4766  } else if (ImmValue >= 33) {
4767  if (Inst.getOpcode() == Mips::DROLImm)
4768  FinalOpcode = Mips::DROTR;
4769  else
4770  FinalOpcode = Mips::DROTR32;
4771  }
4772 
4773  uint64_t ShiftValue = ImmValue % 32;
4774  if (Inst.getOpcode() == Mips::DROLImm)
4775  ShiftValue = (32 - ImmValue % 32) % 32;
4776 
4777  TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4778 
4779  return false;
4780  }
4781 
4782  if (hasMips64()) {
4783  if (ImmValue == 0) {
4784  TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
4785  return false;
4786  }
4787 
4788  switch (Inst.getOpcode()) {
4789  default:
4790  llvm_unreachable("unexpected instruction opcode");
4791  case Mips::DROLImm:
4792  if ((ImmValue >= 1) && (ImmValue <= 31)) {
4793  FirstShift = Mips::DSLL;
4794  SecondShift = Mips::DSRL32;
4795  }
4796  if (ImmValue == 32) {
4797  FirstShift = Mips::DSLL32;
4798  SecondShift = Mips::DSRL32;
4799  }
4800  if ((ImmValue >= 33) && (ImmValue <= 63)) {
4801  FirstShift = Mips::DSLL32;
4802  SecondShift = Mips::DSRL;
4803  }
4804  break;
4805  case Mips::DRORImm:
4806  if ((ImmValue >= 1) && (ImmValue <= 31)) {
4807  FirstShift = Mips::DSRL;
4808  SecondShift = Mips::DSLL32;
4809  }
4810  if (ImmValue == 32) {
4811  FirstShift = Mips::DSRL32;
4812  SecondShift = Mips::DSLL32;
4813  }
4814  if ((ImmValue >= 33) && (ImmValue <= 63)) {
4815  FirstShift = Mips::DSRL32;
4816  SecondShift = Mips::DSLL;
4817  }
4818  break;
4819  }
4820 
4821  ATReg = getATReg(Inst.getLoc());
4822  if (!ATReg)
4823  return true;
4824 
4825  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI);
4826  TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
4827  Inst.getLoc(), STI);
4828  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4829 
4830  return false;
4831  }
4832 
4833  return true;
4834 }
4835 
4836 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4837  const MCSubtargetInfo *STI) {
4838  MipsTargetStreamer &TOut = getTargetStreamer();
4839  unsigned FirstRegOp = Inst.getOperand(0).getReg();
4840  unsigned SecondRegOp = Inst.getOperand(1).getReg();
4841 
4842  TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
4843  if (FirstRegOp != SecondRegOp)
4844  TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
4845  else
4846  TOut.emitEmptyDelaySlot(false, IDLoc, STI);
4847  TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
4848 
4849  return false;
4850 }
4851 
4852 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4853  const MCSubtargetInfo *STI) {
4854  MipsTargetStreamer &TOut = getTargetStreamer();
4855  unsigned ATReg = Mips::NoRegister;
4856  unsigned DstReg = Inst.getOperand(0).getReg();
4857  unsigned SrcReg = Inst.getOperand(1).getReg();
4858  int32_t ImmValue = Inst.getOperand(2).getImm();
4859 
4860  ATReg = getATReg(IDLoc);
4861  if (!ATReg)
4862  return true;
4863 
4864  loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
4865  STI);
4866 
4867  TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
4868  SrcReg, ATReg, IDLoc, STI);
4869 
4870  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4871 
4872  return false;
4873 }
4874 
4875 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4876  const MCSubtargetInfo *STI) {
4877  MipsTargetStreamer &TOut = getTargetStreamer();
4878  unsigned ATReg = Mips::NoRegister;
4879  unsigned DstReg = Inst.getOperand(0).getReg();
4880  unsigned SrcReg = Inst.getOperand(1).getReg();
4881  unsigned TmpReg = Inst.getOperand(2).getReg();
4882 
4883  ATReg = getATReg(Inst.getLoc());
4884  if (!ATReg)
4885  return true;
4886 
4887  TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
4888  SrcReg, TmpReg, IDLoc, STI);
4889 
4890  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4891 
4892  TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
4893  DstReg, DstReg, 0x1F, IDLoc, STI);
4894 
4895  TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
4896 
4897  if (useTraps()) {
4898  TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
4899  } else {
4900  MCContext & Context = TOut.getStreamer().getContext();
4901  MCSymbol * BrTarget = Context.createTempSymbol();
4902  MCOperand LabelOp =
4903  MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4904 
4905  TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
4906  if (AssemblerOptions.back()->isReorder())
4907  TOut.emitNop(IDLoc, STI);
4908  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
4909 
4910  TOut.getStreamer().EmitLabel(BrTarget);
4911  }
4912  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4913 
4914  return false;
4915 }
4916 
4917 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4918  const MCSubtargetInfo *STI) {
4919  MipsTargetStreamer &TOut = getTargetStreamer();
4920  unsigned ATReg = Mips::NoRegister;
4921  unsigned DstReg = Inst.getOperand(0).getReg();
4922  unsigned SrcReg = Inst.getOperand(1).getReg();
4923  unsigned TmpReg = Inst.getOperand(2).getReg();
4924 
4925  ATReg = getATReg(IDLoc);
4926  if (!ATReg)
4927  return true;
4928 
4929  TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
4930  SrcReg, TmpReg, IDLoc, STI);
4931 
4932  TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
4933  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4934  if (useTraps()) {
4935  TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
4936  } else {
4937  MCContext & Context = TOut.getStreamer().getContext();
4938  MCSymbol * BrTarget = Context.createTempSymbol();
4939  MCOperand LabelOp =
4940  MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4941 
4942  TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
4943  if (AssemblerOptions.back()->isReorder())
4944  TOut.emitNop(IDLoc, STI);
4945  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
4946 
4947  TOut.getStreamer().EmitLabel(BrTarget);
4948  }
4949 
4950  return false;
4951 }
4952 
4953 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4954  const MCSubtargetInfo *STI) {
4955  MipsTargetStreamer &TOut = getTargetStreamer();
4956  unsigned DstReg = Inst.getOperand(0).getReg();
4957  unsigned SrcReg = Inst.getOperand(1).getReg();
4958  unsigned TmpReg = Inst.getOperand(2).getReg();
4959 
4960  TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
4961  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4962 
4963  return false;
4964 }
4965 
4966 // Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2);
4967 // lw $<reg+1>>, offset+4($reg2)'
4968 // or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2);
4969 // sw $<reg+1>>, offset+4($reg2)'
4970 // for O32.
4971 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
4972  MCStreamer &Out,
4973  const MCSubtargetInfo *STI,
4974  bool IsLoad) {
4975  if (!isABI_O32())
4976  return true;
4977 
4978  warnIfNoMacro(IDLoc);
4979 
4980  MipsTargetStreamer &TOut = getTargetStreamer();
4981  unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
4982  unsigned FirstReg = Inst.getOperand(0).getReg();
4983  unsigned SecondReg = nextReg(FirstReg);
4984  unsigned BaseReg = Inst.getOperand(1).getReg();
4985  if (!SecondReg)
4986  return true;
4987 
4988  warnIfRegIndexIsAT(FirstReg, IDLoc);
4989 
4990  assert(Inst.getOperand(2).isImm() &&
4991  "Offset for load macro is not immediate!");
4992 
4993  MCOperand &FirstOffset = Inst.getOperand(2);
4994  signed NextOffset = FirstOffset.getImm() + 4;
4995  MCOperand SecondOffset = MCOperand::createImm(NextOffset);
4996 
4997  if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
4998  return true;
4999 
5000  // For loads, clobber the base register with the second load instead of the
5001  // first if the BaseReg == FirstReg.
5002  if (FirstReg != BaseReg || !IsLoad) {
5003  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5004  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5005  } else {
5006  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5007  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5008  }
5009 
5010  return false;
5011 }
5012 
5013 
5014 // Expand 's.d $<reg> offset($reg2)' to 'swc1 $<reg+1>, offset($reg2);
5015 // swc1 $<reg>, offset+4($reg2)'
5016 // or if little endian to 'swc1 $<reg>, offset($reg2);
5017 // swc1 $<reg+1>, offset+4($reg2)'
5018 // for Mips1.
5019 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
5020  MCStreamer &Out,
5021  const MCSubtargetInfo *STI) {
5022  if (!isABI_O32())
5023  return true;
5024 
5025  warnIfNoMacro(IDLoc);
5026 
5027  MipsTargetStreamer &TOut = getTargetStreamer();
5028  unsigned Opcode = Mips::SWC1;
5029  unsigned FirstReg = Inst.getOperand(0).getReg();
5030  unsigned SecondReg = nextReg(FirstReg);
5031  unsigned BaseReg = Inst.getOperand(1).getReg();
5032  if (!SecondReg)
5033  return true;
5034 
5035  warnIfRegIndexIsAT(FirstReg, IDLoc);
5036 
5037  assert(Inst.getOperand(2).isImm() &&
5038  "Offset for macro is not immediate!");
5039 
5040  MCOperand &FirstOffset = Inst.getOperand(2);
5041  signed NextOffset = FirstOffset.getImm() + 4;
5042  MCOperand SecondOffset = MCOperand::createImm(NextOffset);
5043 
5044  if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
5045  return true;
5046 
5047  if (!IsLittleEndian)
5048  std::swap(FirstReg, SecondReg);
5049 
5050  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5051  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5052 
5053  return false;
5054 }
5055 
5056 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5057  const MCSubtargetInfo *STI) {
5058  MipsTargetStreamer &TOut = getTargetStreamer();
5059 
5060  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
5061  assert(Inst.getOperand(0).isReg() &&
5062  Inst.getOperand(1).isReg() &&
5063  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
5064 
5065  unsigned DstReg = Inst.getOperand(0).getReg();
5066  unsigned SrcReg = Inst.getOperand(1).getReg();
5067  unsigned OpReg = Inst.getOperand(2).getReg();
5068 
5069  warnIfNoMacro(IDLoc);
5070 
5071  if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5072  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5073  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5074  return false;
5075  }
5076 
5077  unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
5078  TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
5079  return false;
5080 }
5081 
5082 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5083  const MCSubtargetInfo *STI) {
5084  MipsTargetStreamer &TOut = getTargetStreamer();
5085 
5086  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
5087  assert(Inst.getOperand(0).isReg() &&
5088  Inst.getOperand(1).isReg() &&
5089  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
5090 
5091  unsigned DstReg = Inst.getOperand(0).getReg();
5092  unsigned SrcReg = Inst.getOperand(1).getReg();
5093  int64_t Imm = Inst.getOperand(2).getImm();
5094 
5095  warnIfNoMacro(IDLoc);
5096 
5097  if (Imm == 0) {
5098  TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI);
5099  return false;
5100  }
5101 
5102  if (SrcReg == Mips::ZERO) {
5103  Warning(IDLoc, "comparison is always false");
5104  TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
5105  DstReg, SrcReg, SrcReg, IDLoc, STI);
5106  return false;
5107  }
5108 
5109  unsigned Opc;
5110  if (Imm > -0x8000 && Imm < 0) {
5111  Imm = -Imm;
5112  Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
5113  } else {
5114  Opc = Mips::XORi;
5115  }
5116 
5117  if (!isUInt<16>(Imm)) {
5118  unsigned ATReg = getATReg(IDLoc);
5119  if (!ATReg)
5120  return true;
5121 
5122  if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
5123  Out, STI))
5124  return true;
5125 
5126  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5127  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5128  return false;
5129  }
5130 
5131  TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI);
5132  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5133  return false;
5134 }
5135 
5136 // Map the DSP accumulator and control register to the corresponding gpr
5137 // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
5138 // do not map the DSP registers contigously to gpr registers.
5139 static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
5140  switch (Inst.getOpcode()) {
5141  case Mips::MFTLO:
5142  case Mips::MTTLO:
5143  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5144  case Mips::AC0:
5145  return Mips::ZERO;
5146  case Mips::AC1:
5147  return Mips::A0;
5148  case Mips::AC2:
5149  return Mips::T0;
5150  case Mips::AC3:
5151  return Mips::T4;
5152  default:
5153  llvm_unreachable("Unknown register for 'mttr' alias!");
5154  }
5155  case Mips::MFTHI:
5156  case Mips::MTTHI:
5157  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5158  case Mips::AC0:
5159  return Mips::AT;
5160  case Mips::AC1:
5161  return Mips::A1;
5162  case Mips::AC2:
5163  return Mips::T1;
5164  case Mips::AC3:
5165  return Mips::T5;
5166  default:
5167  llvm_unreachable("Unknown register for 'mttr' alias!");
5168  }
5169  case Mips::MFTACX:
5170  case Mips::MTTACX:
5171  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5172  case Mips::AC0:
5173  return Mips::V0;
5174  case Mips::AC1:
5175  return Mips::A2;
5176  case Mips::AC2:
5177  return Mips::T2;
5178  case Mips::AC3:
5179  return Mips::T6;
5180  default:
5181  llvm_unreachable("Unknown register for 'mttr' alias!");
5182  }
5183  case Mips::MFTDSP:
5184  case Mips::MTTDSP:
5185  return Mips::S0;
5186  default:
5187  llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
5188  }
5189 }
5190 
5191 // Map the floating point register operand to the corresponding register
5192 // operand.
5193 static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
5194  switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
5195  case Mips::F0: return Mips::ZERO;
5196  case Mips::F1: return Mips::AT;
5197  case Mips::F2: return Mips::V0;
5198  case Mips::F3: return Mips::V1;
5199  case Mips::F4: return Mips::A0;
5200  case Mips::F5: return Mips::A1;
5201  case Mips::F6: return Mips::A2;
5202  case Mips::F7: return Mips::A3;
5203  case Mips::F8: return Mips::T0;
5204  case Mips::F9: return Mips::T1;
5205  case Mips::F10: return Mips::T2;
5206  case Mips::F11: return Mips::T3;
5207  case Mips::F12: return Mips::T4;
5208  case Mips::F13: return Mips::T5;
5209  case Mips::F14: return Mips::T6;
5210  case Mips::F15: return Mips::T7;
5211  case Mips::F16: return Mips::S0;
5212  case Mips::F17: return Mips::S1;
5213  case Mips::F18: return Mips::S2;
5214  case Mips::F19: return Mips::S3;
5215  case Mips::F20: return Mips::S4;
5216  case Mips::F21: return Mips::S5;
5217  case Mips::F22: return Mips::S6;
5218  case Mips::F23: return Mips::S7;
5219  case Mips::F24: return Mips::T8;
5220  case Mips::F25: return Mips::T9;
5221  case Mips::F26: return Mips::K0;
5222  case Mips::F27: return Mips::K1;
5223  case Mips::F28: return Mips::GP;
5224  case Mips::F29: return Mips::SP;
5225  case Mips::F30: return Mips::FP;
5226  case Mips::F31: return Mips::RA;
5227  default: llvm_unreachable("Unknown register for mttc1 alias!");
5228  }
5229 }
5230 
5231 // Map the coprocessor operand the corresponding gpr register operand.
5232 static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
5233  switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
5234  case Mips::COP00: return Mips::ZERO;
5235  case Mips::COP01: return Mips::AT;
5236  case Mips::COP02: return Mips::V0;
5237  case Mips::COP03: return Mips::V1;
5238  case Mips::COP04: return Mips::A0;
5239  case Mips::COP05: return Mips::A1;
5240  case Mips::COP06: return Mips::A2;
5241  case Mips::COP07: return Mips::A3;
5242  case Mips::COP08: return Mips::T0;
5243  case Mips::COP09: return Mips::T1;
5244  case Mips::COP010: return Mips::T2;
5245  case Mips::COP011: return Mips::T3;
5246  case Mips::COP012: return Mips::T4;
5247  case Mips::COP013: return Mips::T5;
5248  case Mips::COP014: return Mips::T6;
5249  case Mips::COP015: return Mips::T7;
5250  case Mips::COP016: return Mips::S0;
5251  case Mips::COP017: return Mips::S1;
5252  case Mips::COP018: return Mips::S2;
5253  case Mips::COP019: return Mips::S3;
5254  case Mips::COP020: return Mips::S4;
5255  case Mips::COP021: return Mips::S5;
5256  case Mips::COP022: return Mips::S6;
5257  case Mips::COP023: return Mips::S7;
5258  case Mips::COP024: return Mips::T8;
5259  case Mips::COP025: return Mips::T9;
5260  case Mips::COP026: return Mips::K0;
5261  case Mips::COP027: return Mips::K1;
5262  case Mips::COP028: return Mips::GP;
5263  case Mips::COP029: return Mips::SP;
5264  case Mips::COP030: return Mips::FP;
5265  case Mips::COP031: return Mips::RA;
5266  default: llvm_unreachable("Unknown register for mttc0 alias!");
5267  }
5268 }
5269 
5270 /// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
5271 /// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
5272 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5273  const MCSubtargetInfo *STI) {
5274  MipsTargetStreamer &TOut = getTargetStreamer();
5275  unsigned rd = 0;
5276  unsigned u = 1;
5277  unsigned sel = 0;
5278  unsigned h = 0;
5279  bool IsMFTR = false;
5280  switch (Inst.getOpcode()) {
5281  case Mips::MFTC0:
5282  IsMFTR = true;
5284  case Mips::MTTC0:
5285  u = 0;
5286  rd = getRegisterForMxtrC0(Inst, IsMFTR);
5287  sel = Inst.getOperand(2).getImm();
5288  break;
5289  case Mips::MFTGPR:
5290  IsMFTR = true;
5292  case Mips::MTTGPR:
5293  rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
5294  break;
5295  case Mips::MFTLO:
5296  case Mips::MFTHI:
5297  case Mips::MFTACX:
5298  case Mips::MFTDSP:
5299  IsMFTR = true;
5301  case Mips::MTTLO:
5302  case Mips::MTTHI:
5303  case Mips::MTTACX:
5304  case Mips::MTTDSP:
5305  rd = getRegisterForMxtrDSP(Inst, IsMFTR);
5306  sel = 1;
5307  break;
5308  case Mips::MFTHC1:
5309  h = 1;
5311  case Mips::MFTC1:
5312  IsMFTR = true;
5313  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5314  sel = 2;
5315  break;
5316  case Mips::MTTHC1:
5317  h = 1;
5319  case Mips::MTTC1:
5320  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5321  sel = 2;
5322  break;
5323  case Mips::CFTC1:
5324  IsMFTR = true;
5326  case Mips::CTTC1:
5327  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5328  sel = 3;
5329  break;
5330  }
5331  unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
5332  unsigned Op1 =
5333  IsMFTR ? rd
5334  : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
5335  : Inst.getOperand(0).getReg());
5336 
5337  TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
5338  STI);
5339  return false;
5340 }
5341 
5342 unsigned
5343 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
5344  const OperandVector &Operands) {
5345  switch (Inst.getOpcode()) {
5346  default:
5347  return Match_Success;
5348  case Mips::DATI:
5349  case Mips::DAHI:
5350  if (static_cast<MipsOperand &>(*Operands[1])
5351  .isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
5352  return Match_Success;
5353  return Match_RequiresSameSrcAndDst;
5354  }
5355 }
5356 
5357 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5358  switch (Inst.getOpcode()) {
5359  // As described by the MIPSR6 spec, daui must not use the zero operand for
5360  // its source operand.
5361  case Mips::DAUI:
5362  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5363  Inst.getOperand(1).getReg() == Mips::ZERO_64)
5364  return Match_RequiresNoZeroRegister;
5365  return Match_Success;
5366  // As described by the Mips32r2 spec, the registers Rd and Rs for
5367  // jalr.hb must be different.
5368  // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
5369  // and registers Rd and Base for microMIPS lwp instruction
5370  case Mips::JALR_HB:
5371  case Mips::JALR_HB64:
5372  case Mips::JALRC_HB_MMR6:
5373  case Mips::JALRC_MMR6:
5374  if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
5375  return Match_RequiresDifferentSrcAndDst;
5376  return Match_Success;
5377  case Mips::LWP_MM:
5378  if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg())
5379  return Match_RequiresDifferentSrcAndDst;
5380  return Match_Success;
5381  case Mips::SYNC:
5382  if (Inst.getOperand(0).getImm() != 0 && !hasMips32())
5383  return Match_NonZeroOperandForSync;
5384  return Match_Success;
5385  case Mips::MFC0:
5386  case Mips::MTC0:
5387  case Mips::MTC2:
5388  case Mips::MFC2:
5389  if (Inst.getOperand(2).getImm() != 0 && !hasMips32())
5390  return Match_NonZeroOperandForMTCX;
5391  return Match_Success;
5392  // As described the MIPSR6 spec, the compact branches that compare registers
5393  // must:
5394  // a) Not use the zero register.
5395  // b) Not use the same register twice.
5396  // c) rs < rt for bnec, beqc.
5397  // NB: For this case, the encoding will swap the operands as their
5398  // ordering doesn't matter. GAS performs this transformation too.
5399  // Hence, that constraint does not have to be enforced.
5400  //
5401  // The compact branches that branch iff the signed addition of two registers
5402  // would overflow must have rs >= rt. That can be handled like beqc/bnec with
5403  // operand swapping. They do not have restriction of using the zero register.
5404  case Mips::BLEZC: case Mips::BLEZC_MMR6:
5405  case Mips::BGEZC: case Mips::BGEZC_MMR6:
5406  case Mips::BGTZC: case Mips::BGTZC_MMR6:
5407  case Mips::BLTZC: case Mips::BLTZC_MMR6:
5408  case Mips::BEQZC: case Mips::BEQZC_MMR6:
5409  case Mips::BNEZC: case Mips::BNEZC_MMR6:
5410  case Mips::BLEZC64:
5411  case Mips::BGEZC64:
5412  case Mips::BGTZC64:
5413  case Mips::BLTZC64:
5414  case Mips::BEQZC64:
5415  case Mips::BNEZC64:
5416  if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5417  Inst.getOperand(0).getReg() == Mips::ZERO_64)
5418  return Match_RequiresNoZeroRegister;
5419  return Match_Success;
5420  case Mips::BGEC: case Mips::BGEC_MMR6:
5421  case Mips::BLTC: case Mips::BLTC_MMR6:
5422  case Mips::BGEUC: case Mips::BGEUC_MMR6:
5423  case Mips::BLTUC: case Mips::BLTUC_MMR6:
5424  case Mips::BEQC: case Mips::BEQC_MMR6:
5425  case Mips::BNEC: case Mips::BNEC_MMR6:
5426  case Mips::BGEC64:
5427  case Mips::BLTC64:
5428  case Mips::BGEUC64:
5429  case Mips::BLTUC64:
5430  case Mips::BEQC64:
5431  case Mips::BNEC64:
5432  if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5433  Inst.getOperand(0).getReg() == Mips::ZERO_64)
5434  return Match_RequiresNoZeroRegister;
5435  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5436  Inst.getOperand(1).getReg() == Mips::ZERO_64)
5437  return Match_RequiresNoZeroRegister;
5438  if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
5439  return Match_RequiresDifferentOperands;
5440  return Match_Success;
5441  case Mips::DINS: {
5442  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5443  "Operands must be immediates for dins!");
5444  const signed Pos = Inst.getOperand(2).getImm();
5445  const signed Size = Inst.getOperand(3).getImm();
5446  if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
5447  return Match_RequiresPosSizeRange0_32;
5448  return Match_Success;
5449  }
5450  case Mips::DINSM:
5451  case Mips::DINSU: {
5452  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5453  "Operands must be immediates for dinsm/dinsu!");
5454  const signed Pos = Inst.getOperand(2).getImm();
5455  const signed Size = Inst.getOperand(3).getImm();
5456  if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
5457  return Match_RequiresPosSizeRange33_64;
5458  return Match_Success;
5459  }
5460  case Mips::DEXT: {
5461  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5462  "Operands must be immediates for DEXTM!");
5463  const signed Pos = Inst.getOperand(2).getImm();
5464  const signed Size = Inst.getOperand(3).getImm();
5465  if ((1 > (Pos + Size)) || ((Pos + Size) > 63))
5466  return Match_RequiresPosSizeUImm6;
5467  return Match_Success;
5468  }
5469  case Mips::DEXTM:
5470  case Mips::DEXTU: {
5471  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5472  "Operands must be immediates for dextm/dextu!");
5473  const signed Pos = Inst.getOperand(2).getImm();
5474  const signed Size = Inst.getOperand(3).getImm();
5475  if ((32 > (Pos + Size)) || ((Pos + Size) > 64))
5476  return Match_RequiresPosSizeRange33_64;
5477  return Match_Success;
5478  }
5479  case Mips::CRC32B: case Mips::CRC32CB:
5480  case Mips::CRC32H: case Mips::CRC32CH:
5481  case Mips::CRC32W: case Mips::CRC32CW:
5482  case Mips::CRC32D: case Mips::CRC32CD:
5483  if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg())
5484  return Match_RequiresSameSrcAndDst;
5485  return Match_Success;
5486  }
5487 
5488  uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
5489  if ((TSFlags & MipsII::HasFCCRegOperand) &&
5490  (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())
5491  return Match_NoFCCRegisterForCurrentISA;
5492 
5493  return Match_Success;
5494 
5495 }
5496 
5497 static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
5498  uint64_t ErrorInfo) {
5499  if (ErrorInfo != ~0ULL && ErrorInfo < Operands.size()) {
5500  SMLoc ErrorLoc = Operands[ErrorInfo]->getStartLoc();
5501  if (ErrorLoc == SMLoc())
5502  return Loc;
5503  return ErrorLoc;
5504  }
5505  return Loc;
5506 }
5507 
5508 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5509  OperandVector &Operands,
5510  MCStreamer &Out,
5511  uint64_t &ErrorInfo,
5512  bool MatchingInlineAsm) {
5513  MCInst Inst;
5514  unsigned MatchResult =
5515  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
5516 
5517  switch (MatchResult) {
5518  case Match_Success:
5519  if (processInstruction(Inst, IDLoc, Out, STI))
5520  return true;
5521  return false;
5522  case Match_MissingFeature:
5523  Error(IDLoc, "instruction requires a CPU feature not currently enabled");
5524  return true;
5525  case Match_InvalidOperand: {
5526  SMLoc ErrorLoc = IDLoc;
5527  if (ErrorInfo != ~0ULL) {
5528  if (ErrorInfo >= Operands.size())
5529  return Error(IDLoc, "too few operands for instruction");
5530 
5531  ErrorLoc = Operands[ErrorInfo]->getStartLoc();
5532  if (ErrorLoc == SMLoc())
5533  ErrorLoc = IDLoc;
5534  }
5535 
5536  return Error(ErrorLoc, "invalid operand for instruction");
5537  }
5538  case Match_NonZeroOperandForSync:
5539  return Error(IDLoc,
5540  "s-type must be zero or unspecified for pre-MIPS32 ISAs");
5541  case Match_NonZeroOperandForMTCX:
5542  return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs");
5543  case Match_MnemonicFail:
5544  return Error(IDLoc, "invalid instruction");
5545  case Match_RequiresDifferentSrcAndDst:
5546  return Error(IDLoc, "source and destination must be different");
5547  case Match_RequiresDifferentOperands:
5548  return Error(IDLoc, "registers must be different");
5549  case Match_RequiresNoZeroRegister:
5550  return Error(IDLoc, "invalid operand ($zero) for instruction");
5551  case Match_RequiresSameSrcAndDst:
5552  return Error(IDLoc, "source and destination must match");
5553  case Match_NoFCCRegisterForCurrentISA:
5554  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5555  "non-zero fcc register doesn't exist in current ISA level");
5556  case Match_Immz:
5557  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
5558  case Match_UImm1_0:
5559  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5560  "expected 1-bit unsigned immediate");
5561  case Match_UImm2_0:
5562  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5563  "expected 2-bit unsigned immediate");
5564  case Match_UImm2_1:
5565  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5566  "expected immediate in range 1 .. 4");
5567  case Match_UImm3_0:
5568  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5569  "expected 3-bit unsigned immediate");
5570  case Match_UImm4_0:
5571  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5572  "expected 4-bit unsigned immediate");
5573  case Match_SImm4_0:
5574  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5575  "expected 4-bit signed immediate");
5576  case Match_UImm5_0:
5577  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5578  "expected 5-bit unsigned immediate");
5579  case Match_SImm5_0:
5580  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5581  "expected 5-bit signed immediate");
5582  case Match_UImm5_1:
5583  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5584  "expected immediate in range 1 .. 32");
5585  case Match_UImm5_32:
5586  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5587  "expected immediate in range 32 .. 63");
5588  case Match_UImm5_33:
5589  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5590  "expected immediate in range 33 .. 64");
5591  case Match_UImm5_0_Report_UImm6:
5592  // This is used on UImm5 operands that have a corresponding UImm5_32
5593  // operand to avoid confusing the user.
5594  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5595  "expected 6-bit unsigned immediate");
5596  case Match_UImm5_Lsl2:
5597  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5598  "expected both 7-bit unsigned immediate and multiple of 4");
5599  case Match_UImmRange2_64:
5600  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5601  "expected immediate in range 2 .. 64");
5602  case Match_UImm6_0:
5603  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5604  "expected 6-bit unsigned immediate");
5605  case Match_UImm6_Lsl2:
5606  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5607  "expected both 8-bit unsigned immediate and multiple of 4");
5608  case Match_SImm6_0:
5609  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5610  "expected 6-bit signed immediate");
5611  case Match_UImm7_0:
5612  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5613  "expected 7-bit unsigned immediate");
5614  case Match_UImm7_N1:
5615  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5616  "expected immediate in range -1 .. 126");
5617  case Match_SImm7_Lsl2:
5618  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5619  "expected both 9-bit signed immediate and multiple of 4");
5620  case Match_UImm8_0:
5621  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5622  "expected 8-bit unsigned immediate");
5623  case Match_UImm10_0:
5624  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5625  "expected 10-bit unsigned immediate");
5626  case Match_SImm10_0:
5627  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5628  "expected 10-bit signed immediate");
5629  case Match_SImm11_0:
5630  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5631  "expected 11-bit signed immediate");
5632  case Match_UImm16:
5633  case Match_UImm16_Relaxed:
5634  case Match_UImm16_AltRelaxed:
5635  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5636  "expected 16-bit unsigned immediate");
5637  case Match_SImm16:
5638  case Match_SImm16_Relaxed:
5639  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5640  "expected 16-bit signed immediate");
5641  case Match_SImm19_Lsl2:
5642  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5643  "expected both 19-bit signed immediate and multiple of 4");
5644  case Match_UImm20_0:
5645  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5646  "expected 20-bit unsigned immediate");
5647  case Match_UImm26_0:
5648  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5649  "expected 26-bit unsigned immediate");
5650  case Match_SImm32:
5651  case Match_SImm32_Relaxed:
5652  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5653  "expected 32-bit signed immediate");
5654  case Match_UImm32_Coerced:
5655  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5656  "expected 32-bit immediate");
5657  case Match_MemSImm9:
5658  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5659  "expected memory with 9-bit signed offset");
5660  case Match_MemSImm10:
5661  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5662  "expected memory with 10-bit signed offset");
5663  case Match_MemSImm10Lsl1:
5664  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5665  "expected memory with 11-bit signed offset and multiple of 2");
5666  case Match_MemSImm10Lsl2:
5667  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5668  "expected memory with 12-bit signed offset and multiple of 4");
5669  case Match_MemSImm10Lsl3:
5670  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5671  "expected memory with 13-bit signed offset and multiple of 8");
5672  case Match_MemSImm11:
5673  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5674  "expected memory with 11-bit signed offset");
5675  case Match_MemSImm12:
5676  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5677  "expected memory with 12-bit signed offset");
5678  case Match_MemSImm16:
5679  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5680  "expected memory with 16-bit signed offset");
5681  case Match_MemSImmPtr:
5682  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5683  "expected memory with 32-bit signed offset");
5684  case Match_RequiresPosSizeRange0_32: {
5685  SMLoc ErrorStart = Operands[3]->getStartLoc();
5686  SMLoc ErrorEnd = Operands[4]->getEndLoc();
5687  return Error(ErrorStart, "size plus position are not in the range 0 .. 32",
5688  SMRange(ErrorStart, ErrorEnd));
5689  }
5690  case Match_RequiresPosSizeUImm6: {
5691  SMLoc ErrorStart = Operands[3]->getStartLoc();
5692  SMLoc ErrorEnd = Operands[4]->getEndLoc();
5693  return