LLVM 19.0.0git
AMDGPUMCKernelDescriptor.cpp
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1//===--- AMDHSAKernelDescriptor.h -----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "AMDGPUMCTargetDesc.h"
12#include "llvm/MC/MCContext.h"
13#include "llvm/MC/MCExpr.h"
16
17using namespace llvm;
18using namespace llvm::AMDGPU;
19
22 MCContext &Ctx) {
24
26 const MCExpr *ZeroMCExpr = MCConstantExpr::create(0, Ctx);
27 const MCExpr *OneMCExpr = MCConstantExpr::create(1, Ctx);
28
29 KD.group_segment_fixed_size = ZeroMCExpr;
30 KD.private_segment_fixed_size = ZeroMCExpr;
31 KD.compute_pgm_rsrc1 = ZeroMCExpr;
32 KD.compute_pgm_rsrc2 = ZeroMCExpr;
33 KD.compute_pgm_rsrc3 = ZeroMCExpr;
34 KD.kernarg_size = ZeroMCExpr;
35 KD.kernel_code_properties = ZeroMCExpr;
36 KD.kernarg_preload = ZeroMCExpr;
37
41 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
42 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Ctx);
43 if (Version.Major < 12) {
45 KD.compute_pgm_rsrc1, OneMCExpr,
46 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
47 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Ctx);
49 KD.compute_pgm_rsrc1, OneMCExpr,
50 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
51 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Ctx);
52 }
54 KD.compute_pgm_rsrc2, OneMCExpr,
55 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
56 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx);
57 if (Version.Major >= 10) {
58 if (STI->getFeatureBits().test(FeatureWavefrontSize32))
60 KD.kernel_code_properties, OneMCExpr,
61 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
62 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx);
63 if (!STI->getFeatureBits().test(FeatureCuMode))
65 KD.compute_pgm_rsrc1, OneMCExpr,
66 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
67 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Ctx);
68
70 KD.compute_pgm_rsrc1, OneMCExpr,
71 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
72 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Ctx);
73 }
74 if (AMDGPU::isGFX90A(*STI) && STI->getFeatureBits().test(FeatureTgSplit))
76 KD.compute_pgm_rsrc3, OneMCExpr,
77 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
78 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx);
79 return KD;
80}
81
83 uint32_t Shift, uint32_t Mask,
84 MCContext &Ctx) {
85 auto Sft = MCConstantExpr::create(Shift, Ctx);
86 auto Msk = MCConstantExpr::create(Mask, Ctx);
87 Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx);
89 Ctx);
90}
91
93 uint32_t Mask, MCContext &Ctx) {
94 auto Sft = MCConstantExpr::create(Shift, Ctx);
95 auto Msk = MCConstantExpr::create(Mask, Ctx);
96 return MCBinaryExpr::createLShr(MCBinaryExpr::createAnd(Src, Msk, Ctx), Sft,
97 Ctx);
98}
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
Provides AMDGPU specific target descriptions.
constexpr bool test(unsigned I) const
static const MCBinaryExpr * createLShr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:616
static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:541
static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:601
static const MCBinaryExpr * createShl(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:606
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:82
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef getCPU() const
static const MCUnaryExpr * createNot(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:466
LLVM Value Representation.
Definition: Value.h:74
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Instruction set architecture version.
Definition: TargetParser.h:127
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
static void bits_set(const MCExpr *&Dst, const MCExpr *Value, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
static MCKernelDescriptor getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI, MCContext &Ctx)