llvm::MCSubtargetInfo Class Reference

Generic base class for all target subtargets. More...

#include "llvm/MC/MCSubtargetInfo.h"

Inheritance diagram for llvm::MCSubtargetInfo:

Public Types
enum	HwModeType { HwMode_Default , HwMode_ValueType , HwMode_RegInfo , HwMode_EncodingInfo }
	HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specific IDs, such as the RegInfo HwMode ID, from the set as required. More...

Public Member Functions
	MCSubtargetInfo (const MCSubtargetInfo &)=default
	MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringTable PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, ArrayRef< SubtargetSubTypeAliasKV > PA, const MCSchedModel *PSM, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
	MCSubtargetInfo ()=delete
MCSubtargetInfo &	operator= (const MCSubtargetInfo &)=delete
MCSubtargetInfo &	operator= (MCSubtargetInfo &&)=delete
virtual	~MCSubtargetInfo ()=default
const Triple &	getTargetTriple () const
StringRef	getCPU () const
StringRef	getTuneCPU () const
const FeatureBitset &	getFeatureBits () const
void	setFeatureBits (const FeatureBitset &FeatureBits_)
StringRef	getFeatureString () const
bool	hasFeature (unsigned Feature) const
void	setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
	Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
const FeatureBitset &	ToggleFeature (uint64_t FB)
	Toggle a feature and return the re-computed feature bits.
const FeatureBitset &	ToggleFeature (const FeatureBitset &FB)
	Toggle a feature and return the re-computed feature bits.
const FeatureBitset &	ToggleFeature (StringRef FS)
	Toggle a set of features and return the re-computed feature bits.
const FeatureBitset &	ApplyFeatureFlag (StringRef FS)
	Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.
const FeatureBitset &	SetFeatureBitsTransitively (const FeatureBitset &FB)
	Set/clear additional feature bits, including all other bits they imply.
const FeatureBitset &	ClearFeatureBitsTransitively (const FeatureBitset &FB)
bool	checkFeatures (StringRef FS) const
	Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
bool	checkFeatureExpression (StringRef FeatureExpr) const
	Check whether the current subtarget satisfies a target feature expression.
const MCSchedModel &	getSchedModelForCPU (StringRef CPU) const
	Get the machine model of a CPU.
const MCSchedModel &	getSchedModel () const
	Get the machine model for this subtarget's CPU.
const MCWriteProcResEntry *	getWriteProcResBegin (const MCSchedClassDesc *SC) const
	Return an iterator at the first process resource consumed by the given scheduling class.
const MCWriteProcResEntry *	getWriteProcResEnd (const MCSchedClassDesc *SC) const
const MCWriteLatencyEntry *	getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
int	getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
ArrayRef< MCReadAdvanceEntry >	getReadAdvanceEntries (const MCSchedClassDesc &SC) const
	Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
InstrItineraryData	getInstrItineraryForCPU (StringRef CPU) const
	Get scheduling itinerary of a CPU.
void	initInstrItins (InstrItineraryData &InstrItins) const
	Initialize an InstrItineraryData instance.
virtual unsigned	resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
	Resolve a variant scheduling class for the given MCInst and CPU.
const SubtargetSubTypeKV *	resolveCPU (StringRef CPU) const
	Look up the processor entry for a CPU name, resolving aliases.
bool	isCPUStringValid (StringRef CPU) const
	Check whether the CPU string is valid.
ArrayRef< SubtargetSubTypeKV >	getAllProcessorDescriptions () const
	Return processor descriptions.
ArrayRef< SubtargetFeatureKV >	getAllProcessorFeatures () const
	Return processor features.
std::vector< const SubtargetFeatureKV * >	getEnabledProcessorFeatures () const
	Return the list of processor features currently enabled.
virtual unsigned	getHwModeSet () const
	Return a bit set containing all HwMode IDs of the current subtarget.
virtual unsigned	getHwMode (enum HwModeType type=HwMode_Default) const
	HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current subtarget.
virtual std::optional< unsigned >	getCacheSize (unsigned Level) const
	Return the cache size in bytes for the given level of cache.
virtual std::optional< unsigned >	getCacheAssociativity (unsigned Level) const
	Return the cache associatvity for the given level of cache.
virtual std::optional< unsigned >	getCacheLineSize (unsigned Level) const
	Return the target cache line size in bytes at a given level.
virtual unsigned	getCacheLineSize () const
	Return the target cache line size in bytes.
virtual unsigned	getPrefetchDistance () const
	Return the preferred prefetch distance in terms of instructions.
virtual unsigned	getMaxPrefetchIterationsAhead () const
	Return the maximum prefetch distance in terms of loop iterations.
virtual bool	enableWritePrefetching () const
virtual unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
	Return the minimum stride necessary to trigger software prefetching.
virtual bool	shouldPrefetchAddressSpace (unsigned AS) const

Protected Member Functions
void	InitMCProcessorInfo (StringRef CPU, StringRef TuneCPU, StringRef FS)
	Initialize the scheduling model and feature bits.

Detailed Description

Generic base class for all target subtargets.

Definition at line 141 of file MCSubtargetInfo.h.

Member Enumeration Documentation

HwModeType

enum llvm::MCSubtargetInfo::HwModeType

HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specific IDs, such as the RegInfo HwMode ID, from the set as required.

Using this approach, various types of HwMode IDs can be added to a subtarget to manage different attributes within that subtarget, significantly enhancing the scalability and usability of HwMode. Moreover, to ensure compatibility, this method also supports controlling multiple attributes with a single HwMode ID, just as was done previously.

Enumerator
HwMode_Default
HwMode_ValueType
HwMode_RegInfo
HwMode_EncodingInfo

Definition at line 330 of file MCSubtargetInfo.h.

Constructor & Destructor Documentation

MCSubtargetInfo() [1/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( const MCSubtargetInfo & )

default

References FP, MCSubtargetInfo(), and RA.

Referenced by MCSubtargetInfo(), operator=(), operator=(), and llvm::TargetSubtargetInfo::TargetSubtargetInfo().

MCSubtargetInfo() [2/3]

MCSubtargetInfo::MCSubtargetInfo	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringTable	PN,
		ArrayRef< SubtargetFeatureKV >	PF,
		ArrayRef< SubtargetSubTypeKV >	PD,
		ArrayRef< SubtargetSubTypeAliasKV >	PA,
		const MCSchedModel *	PSM,
		const MCWriteProcResEntry *	WPR,
		const MCWriteLatencyEntry *	WL,
		const MCReadAdvanceEntry *	RA,
		const InstrStage *	IS,
		const unsigned *	OC,
		const unsigned *	FP )

Definition at line 258 of file MCSubtargetInfo.cpp.

References C(), FP, InitMCProcessorInfo(), and RA.

MCSubtargetInfo() [3/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( )

delete

~MCSubtargetInfo()

virtual llvm::MCSubtargetInfo::~MCSubtargetInfo ( )

virtualdefault

Member Function Documentation

ApplyFeatureFlag()

const FeatureBitset & MCSubtargetInfo::ApplyFeatureFlag

(

StringRef

FS

)

Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.

Definition at line 324 of file MCSubtargetInfo.cpp.

References ApplyFeatureFlag().

Referenced by ApplyFeatureFlag().

checkFeatureExpression()

bool MCSubtargetInfo::checkFeatureExpression

(

StringRef

FeatureExpr

)

const

Check whether the current subtarget satisfies a target feature expression.

The expression uses feature names from the target's subtarget feature table. Comma means AND, | means OR, comma has higher precedence than |, and parentheses group expressions.

Definition at line 427 of file MCSubtargetInfo.cpp.

References llvm::StringRef::contains(), llvm::StringRef::empty(), and llvm::reportFatalInternalError().

Referenced by llvm::TargetSubtargetInfo::isIntrinsicSupported().

checkFeatures()

bool MCSubtargetInfo::checkFeatures

(

StringRef

FS

)

const

Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.

Definition at line 329 of file MCSubtargetInfo.cpp.

References llvm::all_of(), F, llvm::SubtargetFeatures::isEnabled(), and T.

ClearFeatureBitsTransitively()

const FeatureBitset & MCSubtargetInfo::ClearFeatureBitsTransitively

(

const FeatureBitset &

FB

)

Definition at line 289 of file MCSubtargetInfo.cpp.

References ClearImpliedBits(), I, and llvm::FeatureBitset::size().

enableWritePrefetching()

bool MCSubtargetInfo::enableWritePrefetching ( ) const

virtual

Returns

True if prefetching should also be done for writes.

Definition at line 508 of file MCSubtargetInfo.cpp.

getAllProcessorDescriptions()

ArrayRef< SubtargetSubTypeKV > llvm::MCSubtargetInfo::getAllProcessorDescriptions ( ) const

inline

Return processor descriptions.

Definition at line 310 of file MCSubtargetInfo.h.

getAllProcessorFeatures()

ArrayRef< SubtargetFeatureKV > llvm::MCSubtargetInfo::getAllProcessorFeatures ( ) const

inline

Return processor features.

Definition at line 315 of file MCSubtargetInfo.h.

Referenced by llvm::RISCVFeatures::parseFeatureBits().

getCacheAssociativity()

std::optional< unsigned > MCSubtargetInfo::getCacheAssociativity ( unsigned Level ) const

virtual

Return the cache associatvity for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 491 of file MCSubtargetInfo.cpp.

getCacheLineSize() [1/2]

virtual unsigned llvm::MCSubtargetInfo::getCacheLineSize ( ) const

inlinevirtual

Return the target cache line size in bytes.

By default, return the line size for the bottom-most level of cache. This provides a more convenient interface for the common case where all cache levels have the same line size. Return zero if there is no cache model.

Definition at line 371 of file MCSubtargetInfo.h.

References getCacheLineSize(), and Size.

getCacheLineSize() [2/2]

std::optional< unsigned > MCSubtargetInfo::getCacheLineSize ( unsigned Level ) const

virtual

Return the target cache line size in bytes at a given level.

Definition at line 496 of file MCSubtargetInfo.cpp.

Referenced by getCacheLineSize().

getCacheSize()

std::optional< unsigned > MCSubtargetInfo::getCacheSize ( unsigned Level ) const

virtual

Return the cache size in bytes for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 486 of file MCSubtargetInfo.cpp.

getCPU()

StringRef llvm::MCSubtargetInfo::getCPU ( ) const

inline

Definition at line 178 of file MCSubtargetInfo.h.

Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::MCSchedModel::computeInstrLatency(), llvm::AMDGPU::createAMDGPUTargetID(), llvm::createHexagonAsmBackend(), llvm::createMipsAsmBackend(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::ARMTargetStreamer::emitTargetAttributes(), llvm::CSKYTargetStreamer::emitTargetAttributes(), llvm::AMDGPU::DepCtr::encodeFieldHoldCnt(), getArchForCPU(), llvm::Hexagon_MC::getArchSubtarget(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::Hexagon_MC::GetELFFlags(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), llvm::AMDGPU::IsaInfo::isSGPROccupancyLimited(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

getEnabledProcessorFeatures()

std::vector< const SubtargetFeatureKV * > MCSubtargetInfo::getEnabledProcessorFeatures

(

)

const

Return the list of processor features currently enabled.

Definition at line 478 of file MCSubtargetInfo.cpp.

getFeatureBits()

const FeatureBitset & llvm::MCSubtargetInfo::getFeatureBits ( ) const

inline

Definition at line 181 of file MCSubtargetInfo.h.

Referenced by llvm::BasicTTIImplBase< BasicTTIImpl >::areInlineCompatible(), llvm::AVRELFStreamer::AVRELFStreamer(), cannotInsertTailCall(), llvm::RISCVABI::computeTargetABI(), createAMDGPUMCSubtargetInfo(), llvm::AMDGPU::createAMDGPUTargetID(), createSparcMCSubtargetInfo(), llvm::CSKYTargetELFStreamer::CSKYTargetELFStreamer(), DecodeCopMemInstruction(), DecodeCoprocessor(), DecodeForVMRSandVMSR(), DecodeGPRPairRegisterClass(), DecodeHINTInstruction(), DecodeMSRMask(), DecoderGPRRegisterClass(), DecodeSETPANInstruction(), DecodeSRRegisterClass(), DecodeSystemPStateImm0_15Instruction(), DecodeSystemPStateImm0_1Instruction(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodeThumbTableBranch(), DecodeURRegisterClass(), DecodeVCVTD(), DecodeVCVTQ(), DecodeVSTRVLDR_SYSREG(), llvm::HexagonTargetStreamer::emitTargetAttributes(), llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize(), llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs(), llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::MCInstrInfo::getDeprecatedInfo(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getInstCacheLineSize(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRTrapHandlerReserve(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), llvm::AMDGPU::IsaInfo::getVGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getWavefrontSize(), XtensaAsmParser::hasWindowed(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::ARM::isCDECoproc(), llvm::AMDGPU::isGFX12(), llvm::AMDGPU::isGFX1250(), llvm::AMDGPU::isGFX1250Plus(), llvm::AMDGPU::isGFX13(), isValidSysReg(), llvm::LoongArchTargetELFStreamer::LoongArchTargetELFStreamer(), matchAliasCondition(), llvm::RISCVFeatures::parseFeatureBits(), PermitsD32(), llvm::RISCVInstPrinter::printCSRSystemRegister(), llvm::ARMInstPrinter::printMSRMaskOperand(), llvm::AArch64InstPrinter::printPrefetchOp(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSyslAlias(), llvm::AArch64InstPrinter::printSyspAlias(), llvm::AArch64InstPrinter::printSystemPStateField(), llvm::WebAssemblyInstPrinter::printWebAssemblyMemOrderOperand(), and llvm::HexagonMCInstrInfo::requiresSlot().

getFeatureString()

StringRef llvm::MCSubtargetInfo::getFeatureString ( ) const

inline

Definition at line 186 of file MCSubtargetInfo.h.

Referenced by llvm::AMDGPUTargetStreamer::initializeTargetID().

getHwMode()

virtual unsigned llvm::MCSubtargetInfo::getHwMode ( enum HwModeType type = HwMode_Default ) const

inlinevirtual

HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current subtarget.

It’s important to note that if the current subtarget possesses two HwMode IDs and both control a single attribute (such as RegInfo), this interface will result in an error.

Definition at line 345 of file MCSubtargetInfo.h.

References HwMode_Default.

Referenced by llvm::SelectionDAGISel::initializeAnalysisResults(), llvm::SelectionDAGISel::initializeAnalysisResults(), matchAliasCondition(), and llvm::SDNodeInfo::verifyNode().

getHwModeSet()

virtual unsigned llvm::MCSubtargetInfo::getHwModeSet ( ) const

inlinevirtual

Return a bit set containing all HwMode IDs of the current subtarget.

Definition at line 339 of file MCSubtargetInfo.h.

getInstrItineraryForCPU()

InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU

(

StringRef

CPU

)

const

Get scheduling itinerary of a CPU.

Definition at line 467 of file MCSubtargetInfo.cpp.

References getSchedModelForCPU().

Referenced by llvm::MCSchedModel::computeInstrLatency().

getMaxPrefetchIterationsAhead()

unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead ( ) const

virtual

Return the maximum prefetch distance in terms of loop iterations.

Definition at line 504 of file MCSubtargetInfo.cpp.

getMinPrefetchStride()

unsigned MCSubtargetInfo::getMinPrefetchStride ( unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall ) const

virtual

Return the minimum stride necessary to trigger software prefetching.

Definition at line 512 of file MCSubtargetInfo.cpp.

getPrefetchDistance()

unsigned MCSubtargetInfo::getPrefetchDistance ( ) const

virtual

Return the preferred prefetch distance in terms of instructions.

Definition at line 500 of file MCSubtargetInfo.cpp.

getReadAdvanceCycles()

int llvm::MCSubtargetInfo::getReadAdvanceCycles ( const MCSchedClassDesc * SC, unsigned UseIdx, unsigned WriteResID ) const

inline

Definition at line 259 of file MCSubtargetInfo.h.

References E(), I, llvm::MCSchedClassDesc::NumReadAdvanceEntries, and llvm::MCSchedClassDesc::ReadAdvanceIdx.

Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), and llvm::mca::RegisterFile::collectWrites().

getReadAdvanceEntries()

ArrayRef< MCReadAdvanceEntry > llvm::MCSubtargetInfo::getReadAdvanceEntries ( const MCSchedClassDesc & SC ) const

inline

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

Definition at line 281 of file MCSubtargetInfo.h.

References llvm::MCSchedClassDesc::NumReadAdvanceEntries, and llvm::MCSchedClassDesc::ReadAdvanceIdx.

Referenced by llvm::MCSchedModel::getBypassDelayCycles().

getSchedModel()

const MCSchedModel & llvm::MCSubtargetInfo::getSchedModel ( ) const

inline

Get the machine model for this subtarget's CPU.

Definition at line 238 of file MCSubtargetInfo.h.

Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), llvm::mca::DispatchStage::DispatchStage(), emitComments(), emitLatency(), llvm::TargetSubtargetInfo::enablePostRAScheduler(), llvm::HexagonMCInstrInfo::getCVIResources(), llvm::TargetSubtargetInfo::getLoadLatency(), llvm::TargetSubtargetInfo::getMispredictionPenalty(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::HexagonMCInstrInfo::getUnits(), llvm::TargetSchedModel::init(), llvm::mca::initializeUsedResources(), and initInstrItins().

getSchedModelForCPU()

const MCSchedModel & MCSubtargetInfo::getSchedModelForCPU

(

StringRef

CPU

)

const

Get the machine model of a CPU.

Definition at line 449 of file MCSubtargetInfo.cpp.

References assert(), llvm::MCSchedModel::Default, llvm::errs(), llvm::is_sorted(), resolveCPU(), and llvm::SubtargetSubTypeKV::SchedModelIdx.

Referenced by getInstrItineraryForCPU(), and InitMCProcessorInfo().

getTargetTriple()

const Triple & llvm::MCSubtargetInfo::getTargetTriple ( ) const

inline

Definition at line 177 of file MCSubtargetInfo.h.

Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::ARMAsmBackend::adjustFixupValue(), llvm::RISCVABI::computeTargetABI(), llvm::createAArch64beAsmBackend(), llvm::createAArch64leAsmBackend(), llvm::createAArch64ObjectTargetStreamer(), llvm::createAMDGPUAsmBackend(), llvm::AMDGPU::createAMDGPUTargetID(), createARMAsmBackend(), llvm::createARMObjectTargetStreamer(), createAsmBackend(), llvm::createAVRAsmBackend(), createCSKYObjectTargetStreamer(), llvm::createHexagonAsmBackend(), llvm::createLanaiAsmBackend(), llvm::createLoongArchAsmBackend(), createLoongArchObjectTargetStreamer(), llvm::createM68kAsmBackend(), llvm::createMipsAsmBackend(), createMipsObjectTargetStreamer(), llvm::createMSP430ObjectTargetStreamer(), createObjectTargetStreamer(), llvm::createPPCAsmBackend(), llvm::createRISCVAsmBackend(), createRISCVObjectTargetStreamer(), llvm::createSparcAsmBackend(), llvm::createSystemZMCAsmBackend(), llvm::createVEAsmBackend(), llvm::createX86_32AsmBackend(), llvm::createX86_64AsmBackend(), llvm::createX86ObjectTargetStreamer(), llvm::createXtensaAsmBackend(), llvm::X86_MC::X86MCInstrAnalysis::findPltEntries(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::getMCReg(), llvm::PPCMCCodeEmitter::getTLSRegEncoding(), llvm::AMDGPU::isHsaAbi(), llvm::LoongArchTargetELFStreamer::LoongArchTargetELFStreamer(), lowerMSASplatZExt(), llvm::SparcInstPrinter::printCTILabel(), llvm::RISCVInstPrinter::printImm(), llvm::AMDGPUResourceUsageAnalysis::run(), and truncateVecElts().

getTuneCPU()

StringRef llvm::MCSubtargetInfo::getTuneCPU ( ) const

inline

Definition at line 179 of file MCSubtargetInfo.h.

getWriteLatencyEntry()

const MCWriteLatencyEntry * llvm::MCSubtargetInfo::getWriteLatencyEntry ( const MCSchedClassDesc * SC, unsigned DefIdx ) const

inline

Definition at line 251 of file MCSubtargetInfo.h.

References assert(), and llvm::MCSchedClassDesc::WriteLatencyIdx.

Referenced by llvm::MCSchedModel::computeInstrLatency(), and llvm::MCSchedModel::getBypassDelayCycles().

getWriteProcResBegin()

const MCWriteProcResEntry * llvm::MCSubtargetInfo::getWriteProcResBegin ( const MCSchedClassDesc * SC ) const

inline

Return an iterator at the first process resource consumed by the given scheduling class.

Definition at line 242 of file MCSubtargetInfo.h.

References llvm::MCSchedClassDesc::WriteProcResIdx.

Referenced by llvm::MCSchedModel::getReciprocalThroughput(), getWriteProcResEnd(), and llvm::mca::initializeUsedResources().

getWriteProcResEnd()

const MCWriteProcResEntry * llvm::MCSubtargetInfo::getWriteProcResEnd ( const MCSchedClassDesc * SC ) const

inline

Definition at line 246 of file MCSubtargetInfo.h.

References getWriteProcResBegin(), and llvm::MCSchedClassDesc::NumWriteProcResEntries.

Referenced by llvm::MCSchedModel::getReciprocalThroughput().

hasFeature()

bool llvm::MCSubtargetInfo::hasFeature ( unsigned Feature ) const

inline

Definition at line 188 of file MCSubtargetInfo.h.

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), adjust::adjustRelativeBranch(), checkFeature(), clearFeature(), createAMDGPUMCSubtargetInfo(), createSparcMCSubtargetInfo(), decodeFPUV3Instruction(), DecodeSimpleRegisterClass(), decodeUImm7EqXLenOperand(), decodeUImmLog2XLenOperand(), decodeZcmpRlist(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::ARMTargetStreamer::emitTargetAttributes(), llvm::CSKYTargetStreamer::emitTargetAttributes(), llvm::RISCVTargetStreamer::emitTargetAttributes(), llvm::RISCVMatInt::generateInstSeq(), generateInstSeqImpl(), generateInstSeqLeadingZeros(), llvm::RISCVMatInt::generateTwoRegInstSeq(), getArchForCPU(), getARMLoadDeprecationInfo(), getARMStoreDeprecationInfo(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), getEFlagsForFeatureSet(), llvm::RISCVMatInt::getIntMatCost(), getLit16Encoding(), getLit32Encoding(), getLit64Encoding(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), getMCRDeprecationInfo(), getMRCDeprecationInfo(), getRelaxedOpcode(), llvm::ARMAsmBackend::getRelaxedOpcode(), llvm::RISCVMCObjectFileInfo::getTextSectionAlignment(), llvm::AMDGPU::hasA16(), llvm::AMDGPU::hasArchitectedFlatScratch(), llvm::AMDGPU::hasDPPSrc1SGPR(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasGDS(), llvm::AMDGPU::hasGFX10_3Insts(), llvm::AMDGPU::hasKernargPreload(), llvm::AMDGPU::hasMAIInsts(), llvm::AMDGPU::hasMIMG_R128(), llvm::ARMAsmBackend::hasNOP(), llvm::AMDGPU::hasPackedD16(), hasParamSubqualifiers(), llvm::AMDGPU::hasPopsExitingWaveID(), llvm::AMDGPU::hasVOPD(), llvm::AMDGPU::hasXNACK(), llvm::ARMElfTargetObjectFile::Initialize(), llvm::X86_MC::is16BitMemOperand(), llvm::AMDGPU::isCI(), llvm::AMDGPU::isGCN3Encoding(), llvm::AMDGPU::isGFX10(), llvm::AMDGPU::isGFX10_BEncoding(), llvm::AMDGPU::isGFX11(), llvm::AMDGPU::isGFX9(), llvm::AMDGPU::isGFX90A(), llvm::AMDGPU::isGFX940(), isMicroMips(), isMips32r6(), llvm::AMDGPU::isSI(), isThumb(), isV8M(), llvm::SparcInstPrinter::isV9(), isValidInsnFormat(), llvm::AMDGPU::isVI(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::CSKYAsmBackend::mayNeedRelaxation(), llvm::MSP430TargetELFStreamer::MSP430TargetELFStreamer(), llvm::X86_MC::needsAddressSizeOverride(), llvm::HexagonMCInstrInfo::packetSizeSlots(), llvm::RISCVInstPrinter::printBranchOperand(), llvm::RISCVInstPrinter::printImm(), printImmediateBFloat16(), printImmediateFP16(), llvm::AArch64InstPrinter::printInst(), llvm::PPCInstPrinter::printInst(), llvm::X86ATTInstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::X86InstPrinterCommon::printInstFlags(), llvm::ARMInstPrinter::printMemBOption(), llvm::CSKYInstPrinter::printOperand(), llvm::RISCVInstPrinter::printStackAdj(), llvm::AArch64InstPrinter::printSysAlias(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVTargetStreamer::setFlagsFromFeatures(), llvm::RISCV::updateCZceFeatureImplications(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState(), llvm::AMDGPU::AMDGPUMCKernelCodeT::validate(), and llvm::ARMAsmBackend::writeNopData().

initInstrItins()

void MCSubtargetInfo::initInstrItins

(

InstrItineraryData &

InstrItins

)

const

Initialize an InstrItineraryData instance.

Definition at line 472 of file MCSubtargetInfo.cpp.

References getSchedModel().

InitMCProcessorInfo()

void MCSubtargetInfo::InitMCProcessorInfo ( StringRef CPU, StringRef TuneCPU, StringRef FS )

protected

Initialize the scheduling model and feature bits.

FIXME: Find a way to stick this in the constructor, since it should only be called during initialization.

Definition at line 239 of file MCSubtargetInfo.cpp.

References llvm::MCSchedModel::Default, getFeatures(), and getSchedModelForCPU().

Referenced by MCSubtargetInfo().

isCPUStringValid()

bool llvm::MCSubtargetInfo::isCPUStringValid ( StringRef CPU ) const

inline

Check whether the CPU string is valid.

Definition at line 307 of file MCSubtargetInfo.h.

References resolveCPU().

operator=() [1/2]

MCSubtargetInfo & llvm::MCSubtargetInfo::operator= ( const MCSubtargetInfo & )

delete

References MCSubtargetInfo().

operator=() [2/2]

MCSubtargetInfo & llvm::MCSubtargetInfo::operator= ( MCSubtargetInfo && )

delete

References MCSubtargetInfo().

resolveCPU()

const SubtargetSubTypeKV * MCSubtargetInfo::resolveCPU

(

StringRef

CPU

)

const

Look up the processor entry for a CPU name, resolving aliases.

Returns nullptr if the name matches neither a processor nor an alias.

Definition at line 438 of file MCSubtargetInfo.cpp.

References Find().

Referenced by getFeatures(), getSchedModelForCPU(), and isCPUStringValid().

resolveVariantSchedClass()

virtual unsigned llvm::MCSubtargetInfo::resolveVariantSchedClass ( unsigned SchedClass, const MCInst * MI, const MCInstrInfo * MCII, unsigned CPUID ) const

inlinevirtual

Resolve a variant scheduling class for the given MCInst and CPU.

Definition at line 295 of file MCSubtargetInfo.h.

References MI.

Referenced by llvm::MCSchedModel::computeInstrLatency(), and llvm::MCSchedModel::getReciprocalThroughput().

setDefaultFeatures()

void MCSubtargetInfo::setDefaultFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS )

Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.

Definition at line 251 of file MCSubtargetInfo.cpp.

References getFeatures().

setFeatureBits()

void llvm::MCSubtargetInfo::setFeatureBits ( const FeatureBitset & FeatureBits_ )

inline

Definition at line 182 of file MCSubtargetInfo.h.

Referenced by createSparcMCSubtargetInfo(), and llvm::CSKYAsmPrinter::runOnMachineFunction().

SetFeatureBitsTransitively()

const FeatureBitset & MCSubtargetInfo::SetFeatureBitsTransitively

(

const FeatureBitset &

FB

)

Set/clear additional feature bits, including all other bits they imply.

Definition at line 283 of file MCSubtargetInfo.cpp.

References SetImpliedBits().

shouldPrefetchAddressSpace()

bool MCSubtargetInfo::shouldPrefetchAddressSpace ( unsigned AS ) const

virtual

Returns

if target want to issue a prefetch in address space AS.

Definition at line 519 of file MCSubtargetInfo.cpp.

ToggleFeature() [1/3]

const FeatureBitset & MCSubtargetInfo::ToggleFeature

(

const FeatureBitset &

FB

)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 277 of file MCSubtargetInfo.cpp.

ToggleFeature() [2/3]

const FeatureBitset & MCSubtargetInfo::ToggleFeature

(

StringRef

FS

)

Toggle a set of features and return the re-computed feature bits.

This version will also change all implied bits.

Definition at line 299 of file MCSubtargetInfo.cpp.

References ClearImpliedBits(), llvm::errs(), Find(), llvm::FeatureBitArray::getAsBitset(), llvm::SubtargetFeatureKV::Implies, SetImpliedBits(), llvm::SubtargetFeatures::StripFlag(), and llvm::SubtargetFeatureKV::Value.

ToggleFeature() [3/3]

const FeatureBitset & MCSubtargetInfo::ToggleFeature

(

uint64_t

FB

)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 272 of file MCSubtargetInfo.cpp.

References llvm::FeatureBitset::flip().

Referenced by clearFeature(), createAMDGPUMCSubtargetInfo(), and llvm::RISCV::updateCZceFeatureImplications().

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The documentation for this class was generated from the following files:

• include/llvm/MC/MCSubtargetInfo.h
• lib/MC/MCSubtargetInfo.cpp