LLVM  13.0.0git
Public Member Functions | Protected Member Functions | List of all members
llvm::MCSubtargetInfo Class Reference

Generic base class for all target subtargets. More...

#include "llvm/MC/MCSubtargetInfo.h"

Inheritance diagram for llvm::MCSubtargetInfo:
Inheritance graph
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Public Member Functions

 MCSubtargetInfo (const MCSubtargetInfo &)=default
 
 MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
 MCSubtargetInfo ()=delete
 
MCSubtargetInfooperator= (const MCSubtargetInfo &)=delete
 
MCSubtargetInfooperator= (MCSubtargetInfo &&)=delete
 
virtual ~MCSubtargetInfo ()=default
 
const TriplegetTargetTriple () const
 
StringRef getCPU () const
 
StringRef getTuneCPU () const
 
const FeatureBitsetgetFeatureBits () const
 
void setFeatureBits (const FeatureBitset &FeatureBits_)
 
StringRef getFeatureString () const
 
bool hasFeature (unsigned Feature) const
 
void setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
 Set the features to the default for the given CPU and TuneCPU, with ano appended feature string. More...
 
FeatureBitset ToggleFeature (uint64_t FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (const FeatureBitset &FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (StringRef FS)
 Toggle a set of features and return the re-computed feature bits. More...
 
FeatureBitset ApplyFeatureFlag (StringRef FS)
 Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More...
 
FeatureBitset SetFeatureBitsTransitively (const FeatureBitset &FB)
 Set/clear additional feature bits, including all other bits they imply. More...
 
FeatureBitset ClearFeatureBitsTransitively (const FeatureBitset &FB)
 
bool checkFeatures (StringRef FS) const
 Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features. More...
 
const MCSchedModelgetSchedModelForCPU (StringRef CPU) const
 Get the machine model of a CPU. More...
 
const MCSchedModelgetSchedModel () const
 Get the machine model for this subtarget's CPU. More...
 
const MCWriteProcResEntrygetWriteProcResBegin (const MCSchedClassDesc *SC) const
 Return an iterator at the first process resource consumed by the given scheduling class. More...
 
const MCWriteProcResEntrygetWriteProcResEnd (const MCSchedClassDesc *SC) const
 
const MCWriteLatencyEntrygetWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
 
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
 
ArrayRef< MCReadAdvanceEntrygetReadAdvanceEntries (const MCSchedClassDesc &SC) const
 Return the set of ReadAdvance entries declared by the scheduling class descriptor in input. More...
 
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
 Get scheduling itinerary of a CPU. More...
 
void initInstrItins (InstrItineraryData &InstrItins) const
 Initialize an InstrItineraryData instance. More...
 
virtual unsigned resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
 Resolve a variant scheduling class for the given MCInst and CPU. More...
 
bool isCPUStringValid (StringRef CPU) const
 Check whether the CPU string is valid. More...
 
virtual unsigned getHwMode () const
 
virtual Optional< unsigned > getCacheSize (unsigned Level) const
 Return the cache size in bytes for the given level of cache. More...
 
virtual Optional< unsigned > getCacheAssociativity (unsigned Level) const
 Return the cache associatvity for the given level of cache. More...
 
virtual Optional< unsigned > getCacheLineSize (unsigned Level) const
 Return the target cache line size in bytes at a given level. More...
 
virtual unsigned getCacheLineSize () const
 Return the target cache line size in bytes. More...
 
virtual unsigned getPrefetchDistance () const
 Return the preferred prefetch distance in terms of instructions. More...
 
virtual unsigned getMaxPrefetchIterationsAhead () const
 Return the maximum prefetch distance in terms of loop iterations. More...
 
virtual bool enableWritePrefetching () const
 
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 Return the minimum stride necessary to trigger software prefetching. More...
 

Protected Member Functions

void InitMCProcessorInfo (StringRef CPU, StringRef TuneCPU, StringRef FS)
 Initialize the scheduling model and feature bits. More...
 

Detailed Description

Generic base class for all target subtargets.

Definition at line 75 of file MCSubtargetInfo.h.

Constructor & Destructor Documentation

◆ MCSubtargetInfo() [1/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( const MCSubtargetInfo )
default

◆ MCSubtargetInfo() [2/3]

MCSubtargetInfo::MCSubtargetInfo ( const Triple TT,
StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS,
ArrayRef< SubtargetFeatureKV PF,
ArrayRef< SubtargetSubTypeKV PD,
const MCWriteProcResEntry WPR,
const MCWriteLatencyEntry WL,
const MCReadAdvanceEntry RA,
const InstrStage IS,
const unsigned *  OC,
const unsigned *  FP 
)

Definition at line 225 of file MCSubtargetInfo.cpp.

References FP, llvm::X86AS::FS, InitMCProcessorInfo(), and string.

◆ MCSubtargetInfo() [3/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( )
delete

◆ ~MCSubtargetInfo()

virtual llvm::MCSubtargetInfo::~MCSubtargetInfo ( )
virtualdefault

Member Function Documentation

◆ ApplyFeatureFlag()

FeatureBitset MCSubtargetInfo::ApplyFeatureFlag ( StringRef  FS)

Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.

Definition at line 292 of file MCSubtargetInfo.cpp.

References llvm::X86AS::FS.

Referenced by checkFeatures().

◆ checkFeatures()

bool MCSubtargetInfo::checkFeatures ( StringRef  FS) const

Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.

Definition at line 297 of file MCSubtargetInfo.cpp.

References ApplyFeatureFlag(), F, llvm::X86AS::FS, and T.

◆ ClearFeatureBitsTransitively()

FeatureBitset MCSubtargetInfo::ClearFeatureBitsTransitively ( const FeatureBitset FB)

◆ enableWritePrefetching()

bool MCSubtargetInfo::enableWritePrefetching ( ) const
virtual
Returns
True if prefetching should also be done for writes.

Definition at line 359 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::enableWritePrefetching().

◆ getCacheAssociativity()

Optional< unsigned > MCSubtargetInfo::getCacheAssociativity ( unsigned  Level) const
virtual

Return the cache associatvity for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 343 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCacheAssociativity().

◆ getCacheLineSize() [1/2]

virtual unsigned llvm::MCSubtargetInfo::getCacheLineSize ( ) const
inlinevirtual

Return the target cache line size in bytes.

By default, return the line size for the bottom-most level of cache. This provides a more convenient interface for the common case where all cache levels have the same line size. Return zero if there is no cache model.

Definition at line 256 of file MCSubtargetInfo.h.

References llvm::Check::Size.

◆ getCacheLineSize() [2/2]

Optional< unsigned > MCSubtargetInfo::getCacheLineSize ( unsigned  Level) const
virtual

Return the target cache line size in bytes at a given level.

Definition at line 347 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCacheLineSize().

◆ getCacheSize()

Optional< unsigned > MCSubtargetInfo::getCacheSize ( unsigned  Level) const
virtual

Return the cache size in bytes for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 338 of file MCSubtargetInfo.cpp.

◆ getCPU()

StringRef llvm::MCSubtargetInfo::getCPU ( ) const
inline

◆ getFeatureBits()

const FeatureBitset& llvm::MCSubtargetInfo::getFeatureBits ( ) const
inline

Definition at line 111 of file MCSubtargetInfo.h.

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), llvm::AMDGPUDisassembler::AMDGPUDisassembler(), llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID(), llvm::AVRELFStreamer::AVRELFStreamer(), checkFeature(), clearFeature(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::decodeBoolReg(), DecodeHINTInstruction(), llvm::AMDGPUDisassembler::decodeSDWASrc(), llvm::AMDGPUDisassembler::decodeSDWAVopcDst(), DecodeSETPANInstruction(), DecodeSystemPStateInstruction(), llvm::HexagonMCCodeEmitter::encodeInstruction(), llvm::PPCMCCodeEmitter::encodeInstruction(), llvm::MipsTargetELFStreamer::finish(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs(), getARMLoadDeprecationInfo(), getARMStoreDeprecationInfo(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPUDisassembler::getInstruction(), getITDeprecationInfo(), getLit16Encoding(), getLit32Encoding(), getLit64Encoding(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), getMCRDeprecationInfo(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getMRCDeprecationInfo(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::ARMAsmBackend::getRelaxedOpcode(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), llvm::AMDGPU::IsaInfo::getVGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getWavefrontSize(), llvm::AMDGPUDisassembler::hasArchitectedFlatScratch(), llvm::AMDGPU::hasArchitectedFlatScratch(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasGFX10_3Insts(), llvm::AMDGPU::hasGFX10A16(), llvm::AMDGPU::hasMIMG_R128(), llvm::ARMAsmBackend::hasNOP(), llvm::AMDGPU::hasPackedD16(), llvm::AMDGPU::hasSRAMECC(), llvm::AMDGPU::hasXNACK(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::ARM::isCDECoproc(), llvm::AMDGPU::isCI(), isFullyRelaxed(), llvm::AMDGPU::isGCN3Encoding(), llvm::AMDGPU::isGFX10(), llvm::AMDGPU::isGFX10_BEncoding(), llvm::AMDGPU::isGFX9(), llvm::AMDGPUDisassembler::isGFX90A(), llvm::AMDGPU::isGFX90A(), isMicroMips(), llvm::AMDGPU::isSI(), isThumb(), llvm::SparcInstPrinter::isV9(), llvm::AMDGPUDisassembler::isVI(), llvm::AMDGPU::isVI(), llvm::RISCVTargetLowering::LowerFormalArguments(), matchAliasCondition(), llvm::MipsTargetELFStreamer::MipsTargetELFStreamer(), llvm::HexagonMCInstrInfo::packetSizeSlots(), llvm::RISCVInstPrinter::printCSRSystemRegister(), llvm::X86ATTInstPrinter::printInst(), llvm::AArch64InstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::PPCInstPrinter::printInst(), llvm::ARMInstPrinter::printMemBOption(), llvm::AArch64InstPrinter::printMRSSystemRegister(), llvm::ARMInstPrinter::printMSRMaskOperand(), llvm::AArch64InstPrinter::printMSRSystemRegister(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSystemPStateField(), llvm::HexagonMCInstrInfo::requiresSlot(), llvm::RISCVAsmBackend::RISCVAsmBackend(), llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer(), llvm::RISCVAsmBackend::shouldForceRelocation(), llvm::RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(), llvm::RISCVAsmBackend::shouldInsertFixupForCodeAlign(), llvm::RISCVAsmBackend::willForceRelocations(), and llvm::RISCVAsmBackend::writeNopData().

◆ getFeatureString()

StringRef llvm::MCSubtargetInfo::getFeatureString ( ) const
inline

Definition at line 116 of file MCSubtargetInfo.h.

◆ getHwMode()

virtual unsigned llvm::MCSubtargetInfo::getHwMode ( ) const
inlinevirtual

Definition at line 232 of file MCSubtargetInfo.h.

◆ getInstrItineraryForCPU()

InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU ( StringRef  CPU) const

Get scheduling itinerary of a CPU.

Definition at line 328 of file MCSubtargetInfo.cpp.

References getSchedModelForCPU().

Referenced by getItineraryLatency().

◆ getMaxPrefetchIterationsAhead()

unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead ( ) const
virtual

Return the maximum prefetch distance in terms of loop iterations.

Definition at line 355 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMaxPrefetchIterationsAhead().

◆ getMinPrefetchStride()

unsigned MCSubtargetInfo::getMinPrefetchStride ( unsigned  NumMemAccesses,
unsigned  NumStridedMemAccesses,
unsigned  NumPrefetches,
bool  HasCall 
) const
virtual

Return the minimum stride necessary to trigger software prefetching.

Definition at line 363 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMinPrefetchStride().

◆ getPrefetchDistance()

unsigned MCSubtargetInfo::getPrefetchDistance ( ) const
virtual

Return the preferred prefetch distance in terms of instructions.

Definition at line 351 of file MCSubtargetInfo.cpp.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getPrefetchDistance().

◆ getReadAdvanceCycles()

int llvm::MCSubtargetInfo::getReadAdvanceCycles ( const MCSchedClassDesc SC,
unsigned  UseIdx,
unsigned  WriteResID 
) const
inline

◆ getReadAdvanceEntries()

ArrayRef<MCReadAdvanceEntry> llvm::MCSubtargetInfo::getReadAdvanceEntries ( const MCSchedClassDesc SC) const
inline

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

Definition at line 205 of file MCSubtargetInfo.h.

References llvm::PPCISD::SC.

◆ getSchedModel()

const MCSchedModel& llvm::MCSubtargetInfo::getSchedModel ( ) const
inline

◆ getSchedModelForCPU()

const MCSchedModel & MCSubtargetInfo::getSchedModelForCPU ( StringRef  CPU) const

◆ getTargetTriple()

const Triple& llvm::MCSubtargetInfo::getTargetTriple ( ) const
inline

◆ getTuneCPU()

StringRef llvm::MCSubtargetInfo::getTuneCPU ( ) const
inline

Definition at line 109 of file MCSubtargetInfo.h.

◆ getWriteLatencyEntry()

const MCWriteLatencyEntry* llvm::MCSubtargetInfo::getWriteLatencyEntry ( const MCSchedClassDesc SC,
unsigned  DefIdx 
) const
inline

◆ getWriteProcResBegin()

const MCWriteProcResEntry* llvm::MCSubtargetInfo::getWriteProcResBegin ( const MCSchedClassDesc SC) const
inline

◆ getWriteProcResEnd()

const MCWriteProcResEntry* llvm::MCSubtargetInfo::getWriteProcResEnd ( const MCSchedClassDesc SC) const
inline

◆ hasFeature()

bool llvm::MCSubtargetInfo::hasFeature ( unsigned  Feature) const
inline

◆ initInstrItins()

void MCSubtargetInfo::initInstrItins ( InstrItineraryData InstrItins) const

Initialize an InstrItineraryData instance.

Definition at line 333 of file MCSubtargetInfo.cpp.

References getSchedModel().

Referenced by llvm::TargetSchedModel::init().

◆ InitMCProcessorInfo()

void MCSubtargetInfo::InitMCProcessorInfo ( StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS 
)
protected

Initialize the scheduling model and feature bits.

FIXME: Find a way to stick this in the constructor, since it should only be called during initialization.

Definition at line 208 of file MCSubtargetInfo.cpp.

References llvm::StringRef::empty(), llvm::X86AS::FS, llvm::MCSchedModel::GetDefaultSchedModel(), getFeatures(), and getSchedModelForCPU().

Referenced by MCSubtargetInfo().

◆ isCPUStringValid()

bool llvm::MCSubtargetInfo::isCPUStringValid ( StringRef  CPU) const
inline

Check whether the CPU string is valid.

Definition at line 227 of file MCSubtargetInfo.h.

References llvm::ArrayRef< T >::end(), and llvm::lower_bound().

◆ operator=() [1/2]

MCSubtargetInfo& llvm::MCSubtargetInfo::operator= ( const MCSubtargetInfo )
delete

◆ operator=() [2/2]

MCSubtargetInfo& llvm::MCSubtargetInfo::operator= ( MCSubtargetInfo &&  )
delete

◆ resolveVariantSchedClass()

virtual unsigned llvm::MCSubtargetInfo::resolveVariantSchedClass ( unsigned  SchedClass,
const MCInst MI,
const MCInstrInfo MCII,
unsigned  CPUID 
) const
inlinevirtual

Resolve a variant scheduling class for the given MCInst and CPU.

Definition at line 219 of file MCSubtargetInfo.h.

Referenced by llvm::MCSchedModel::computeInstrLatency(), and llvm::MCSchedModel::getReciprocalThroughput().

◆ setDefaultFeatures()

void MCSubtargetInfo::setDefaultFeatures ( StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS 
)

Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.

Definition at line 219 of file MCSubtargetInfo.cpp.

References llvm::X86AS::FS, and getFeatures().

◆ setFeatureBits()

void llvm::MCSubtargetInfo::setFeatureBits ( const FeatureBitset FeatureBits_)
inline

Definition at line 112 of file MCSubtargetInfo.h.

◆ SetFeatureBitsTransitively()

FeatureBitset MCSubtargetInfo::SetFeatureBitsTransitively ( const FeatureBitset FB)

Set/clear additional feature bits, including all other bits they imply.

Definition at line 250 of file MCSubtargetInfo.cpp.

References SetImpliedBits().

◆ ToggleFeature() [1/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( const FeatureBitset FB)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 245 of file MCSubtargetInfo.cpp.

◆ ToggleFeature() [2/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( StringRef  FS)

◆ ToggleFeature() [3/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( uint64_t  FB)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 240 of file MCSubtargetInfo.cpp.

References llvm::FeatureBitset::flip().

Referenced by clearFeature().


The documentation for this class was generated from the following files: