LLVM
15.0.0git
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Generic base class for all target subtargets. More...
#include "llvm/MC/MCSubtargetInfo.h"
Public Member Functions | |
MCSubtargetInfo (const MCSubtargetInfo &)=default | |
MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | |
MCSubtargetInfo ()=delete | |
MCSubtargetInfo & | operator= (const MCSubtargetInfo &)=delete |
MCSubtargetInfo & | operator= (MCSubtargetInfo &&)=delete |
virtual | ~MCSubtargetInfo ()=default |
const Triple & | getTargetTriple () const |
StringRef | getCPU () const |
StringRef | getTuneCPU () const |
const FeatureBitset & | getFeatureBits () const |
void | setFeatureBits (const FeatureBitset &FeatureBits_) |
StringRef | getFeatureString () const |
bool | hasFeature (unsigned Feature) const |
void | setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS) |
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string. More... | |
FeatureBitset | ToggleFeature (uint64_t FB) |
Toggle a feature and return the re-computed feature bits. More... | |
FeatureBitset | ToggleFeature (const FeatureBitset &FB) |
Toggle a feature and return the re-computed feature bits. More... | |
FeatureBitset | ToggleFeature (StringRef FS) |
Toggle a set of features and return the re-computed feature bits. More... | |
FeatureBitset | ApplyFeatureFlag (StringRef FS) |
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More... | |
FeatureBitset | SetFeatureBitsTransitively (const FeatureBitset &FB) |
Set/clear additional feature bits, including all other bits they imply. More... | |
FeatureBitset | ClearFeatureBitsTransitively (const FeatureBitset &FB) |
bool | checkFeatures (StringRef FS) const |
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features. More... | |
const MCSchedModel & | getSchedModelForCPU (StringRef CPU) const |
Get the machine model of a CPU. More... | |
const MCSchedModel & | getSchedModel () const |
Get the machine model for this subtarget's CPU. More... | |
const MCWriteProcResEntry * | getWriteProcResBegin (const MCSchedClassDesc *SC) const |
Return an iterator at the first process resource consumed by the given scheduling class. More... | |
const MCWriteProcResEntry * | getWriteProcResEnd (const MCSchedClassDesc *SC) const |
const MCWriteLatencyEntry * | getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const |
int | getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const |
ArrayRef< MCReadAdvanceEntry > | getReadAdvanceEntries (const MCSchedClassDesc &SC) const |
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input. More... | |
InstrItineraryData | getInstrItineraryForCPU (StringRef CPU) const |
Get scheduling itinerary of a CPU. More... | |
void | initInstrItins (InstrItineraryData &InstrItins) const |
Initialize an InstrItineraryData instance. More... | |
virtual unsigned | resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const |
Resolve a variant scheduling class for the given MCInst and CPU. More... | |
bool | isCPUStringValid (StringRef CPU) const |
Check whether the CPU string is valid. More... | |
virtual unsigned | getHwMode () const |
virtual Optional< unsigned > | getCacheSize (unsigned Level) const |
Return the cache size in bytes for the given level of cache. More... | |
virtual Optional< unsigned > | getCacheAssociativity (unsigned Level) const |
Return the cache associatvity for the given level of cache. More... | |
virtual Optional< unsigned > | getCacheLineSize (unsigned Level) const |
Return the target cache line size in bytes at a given level. More... | |
virtual unsigned | getCacheLineSize () const |
Return the target cache line size in bytes. More... | |
virtual unsigned | getPrefetchDistance () const |
Return the preferred prefetch distance in terms of instructions. More... | |
virtual unsigned | getMaxPrefetchIterationsAhead () const |
Return the maximum prefetch distance in terms of loop iterations. More... | |
virtual bool | enableWritePrefetching () const |
virtual unsigned | getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const |
Return the minimum stride necessary to trigger software prefetching. More... | |
Protected Member Functions | |
void | InitMCProcessorInfo (StringRef CPU, StringRef TuneCPU, StringRef FS) |
Initialize the scheduling model and feature bits. More... | |
Generic base class for all target subtargets.
Definition at line 76 of file MCSubtargetInfo.h.
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MCSubtargetInfo::MCSubtargetInfo | ( | const Triple & | TT, |
StringRef | CPU, | ||
StringRef | TuneCPU, | ||
StringRef | FS, | ||
ArrayRef< SubtargetFeatureKV > | PF, | ||
ArrayRef< SubtargetSubTypeKV > | PD, | ||
const MCWriteProcResEntry * | WPR, | ||
const MCWriteLatencyEntry * | WL, | ||
const MCReadAdvanceEntry * | RA, | ||
const InstrStage * | IS, | ||
const unsigned * | OC, | ||
const unsigned * | FP | ||
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Definition at line 225 of file MCSubtargetInfo.cpp.
References llvm::X86AS::FS, and InitMCProcessorInfo().
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FeatureBitset MCSubtargetInfo::ApplyFeatureFlag | ( | StringRef | FS | ) |
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.
Definition at line 292 of file MCSubtargetInfo.cpp.
References llvm::X86AS::FS.
Referenced by checkFeatures().
bool MCSubtargetInfo::checkFeatures | ( | StringRef | FS | ) | const |
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
Definition at line 297 of file MCSubtargetInfo.cpp.
References All, ApplyFeatureFlag(), F, llvm::X86AS::FS, and T.
FeatureBitset MCSubtargetInfo::ClearFeatureBitsTransitively | ( | const FeatureBitset & | FB | ) |
Definition at line 256 of file MCSubtargetInfo.cpp.
References ClearImpliedBits(), E, I, llvm::FeatureBitset::reset(), and llvm::FeatureBitset::size().
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Definition at line 359 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::enableWritePrefetching().
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Return the cache associatvity for the given level of cache.
Level is zero-based, so a value of zero means the first level of cache.
Definition at line 343 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCacheAssociativity().
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Return the target cache line size in bytes.
By default, return the line size for the bottom-most level of cache. This provides a more convenient interface for the common case where all cache levels have the same line size. Return zero if there is no cache model.
Definition at line 257 of file MCSubtargetInfo.h.
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Return the target cache line size in bytes at a given level.
Definition at line 347 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCacheLineSize().
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Return the cache size in bytes for the given level of cache.
Level is zero-based, so a value of zero means the first level of cache.
Definition at line 338 of file MCSubtargetInfo.cpp.
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Definition at line 109 of file MCSubtargetInfo.h.
Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::createHexagonAsmBackend(), llvm::createMipsAsmBackend(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::ARMTargetStreamer::emitTargetAttributes(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getArchForCPU(), llvm::Hexagon_MC::getArchSubtarget(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::Hexagon_MC::GetELFFlags(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), llvm::AMDGPUInstPrinter::printWaitFlag(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().
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Definition at line 112 of file MCSubtargetInfo.h.
Referenced by llvm::ARMAsmBackend::adjustFixupValue(), llvm::AMDGPUDisassembler::AMDGPUDisassembler(), llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID(), llvm::AVRELFStreamer::AVRELFStreamer(), checkFeature(), clearFeature(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::CSKYTargetELFStreamer::CSKYTargetELFStreamer(), llvm::AMDGPUDisassembler::decodeBoolReg(), decodeFPUV3Instruction(), DecodeGPRPairRegisterClass(), DecodeGPRRegisterClass(), DecodeHINTInstruction(), llvm::AMDGPUDisassembler::decodeSDWASrc(), llvm::AMDGPUDisassembler::decodeSDWAVopcDst(), DecodeSETPANInstruction(), DecodeSystemPStateInstruction(), llvm::RISCVTargetStreamer::emitTargetAttributes(), llvm::HexagonMCCodeEmitter::encodeInstruction(), llvm::PPCMCCodeEmitter::encodeInstruction(), llvm::CSKYMCCodeEmitter::expandJBTF(), llvm::RISCVTargetELFStreamer::finish(), llvm::MipsTargetELFStreamer::finish(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs(), getARMLoadDeprecationInfo(), getARMStoreDeprecationInfo(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPUDisassembler::getInstruction(), getLit16Encoding(), getLit32Encoding(), getLit64Encoding(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), getMCRDeprecationInfo(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getMRCDeprecationInfo(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::ARMAsmBackend::getRelaxedOpcode(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), llvm::AMDGPU::IsaInfo::getVGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getWavefrontSize(), llvm::AMDGPUDisassembler::hasArchitectedFlatScratch(), llvm::AMDGPU::hasArchitectedFlatScratch(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasGFX10_3Insts(), llvm::AMDGPU::hasGFX10A16(), llvm::AMDGPU::hasMAIInsts(), llvm::AMDGPU::hasMIMG_R128(), llvm::ARMAsmBackend::hasNOP(), llvm::AMDGPU::hasPackedD16(), llvm::AMDGPU::hasSRAMECC(), llvm::AMDGPU::hasVOPD(), llvm::AMDGPU::hasXNACK(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::ARM::isCDECoproc(), llvm::AMDGPU::isCI(), isFullyRelaxed(), llvm::AMDGPU::isGCN3Encoding(), llvm::AMDGPU::isGFX10(), llvm::AMDGPU::isGFX10_AEncoding(), llvm::AMDGPU::isGFX10_BEncoding(), llvm::AMDGPUDisassembler::isGFX11(), llvm::AMDGPU::isGFX11(), llvm::AMDGPU::isGFX9(), llvm::AMDGPUDisassembler::isGFX90A(), llvm::AMDGPU::isGFX90A(), llvm::AMDGPU::isGFX940(), isMicroMips(), isMips32r6(), llvm::AMDGPU::isSI(), isThumb(), llvm::SparcInstPrinter::isV9(), isValidSysReg(), llvm::AMDGPUDisassembler::isVI(), llvm::AMDGPU::isVI(), llvm::RISCVTargetLowering::LowerFormalArguments(), matchAliasCondition(), llvm::CSKYAsmBackend::mayNeedRelaxation(), llvm::MipsTargetELFStreamer::MipsTargetELFStreamer(), llvm::HexagonMCInstrInfo::packetSizeSlots(), llvm::RISCVInstPrinter::printCSRSystemRegister(), llvm::X86ATTInstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::AArch64InstPrinter::printInst(), llvm::PPCInstPrinter::printInst(), llvm::ARMInstPrinter::printMemBOption(), llvm::ARMInstPrinter::printMSRMaskOperand(), llvm::CSKYInstPrinter::printOperand(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSystemPStateField(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::HexagonMCInstrInfo::requiresSlot(), llvm::RISCVAsmBackend::RISCVAsmBackend(), llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer(), llvm::CSKYAsmPrinter::runOnMachineFunction(), llvm::RISCVAsmBackend::shouldForceRelocation(), llvm::RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(), llvm::RISCVAsmBackend::shouldInsertFixupForCodeAlign(), and llvm::RISCVAsmBackend::writeNopData().
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Definition at line 117 of file MCSubtargetInfo.h.
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Definition at line 233 of file MCSubtargetInfo.h.
InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU | ( | StringRef | CPU | ) | const |
Get scheduling itinerary of a CPU.
Definition at line 328 of file MCSubtargetInfo.cpp.
References getSchedModelForCPU().
Referenced by getItineraryLatency().
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Return the maximum prefetch distance in terms of loop iterations.
Definition at line 355 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMaxPrefetchIterationsAhead().
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Return the minimum stride necessary to trigger software prefetching.
Definition at line 363 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMinPrefetchStride().
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Return the preferred prefetch distance in terms of instructions.
Definition at line 351 of file MCSubtargetInfo.cpp.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getPrefetchDistance().
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Definition at line 184 of file MCSubtargetInfo.h.
References E, I, and llvm::PPCISD::SC.
Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), and llvm::TargetSchedModel::computeOperandLatency().
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Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
Definition at line 206 of file MCSubtargetInfo.h.
References llvm::PPCISD::SC.
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Get the machine model for this subtarget's CPU.
Definition at line 163 of file MCSubtargetInfo.h.
Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), llvm::mca::Context::createDefaultPipeline(), llvm::mca::Context::createInOrderPipeline(), llvm::mca::InstrBuilder::createInstruction(), llvm::mca::DispatchStage::DispatchStage(), llvm::TargetSubtargetInfo::enablePostRAScheduler(), llvm::HexagonMCInstrInfo::getCVIResources(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getInstructionLatency(), llvm::mca::InOrderIssueStage::getIssueWidth(), getLatency(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::HexagonMCInstrInfo::getUnits(), llvm::TargetSchedModel::init(), llvm::mca::initializeUsedResources(), initInstrItins(), and llvm::mca::InstrBuilder::InstrBuilder().
const MCSchedModel & MCSubtargetInfo::getSchedModelForCPU | ( | StringRef | CPU | ) | const |
Get the machine model of a CPU.
Definition at line 309 of file MCSubtargetInfo.cpp.
References assert(), llvm::errs(), Find(), llvm::MCSchedModel::GetDefaultSchedModel(), llvm::is_sorted(), and llvm::SubtargetSubTypeKV::SchedModel.
Referenced by getInstrItineraryForCPU(), and InitMCProcessorInfo().
Definition at line 108 of file MCSubtargetInfo.h.
Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::ARMAsmBackend::adjustFixupValue(), llvm::createAArch64beAsmBackend(), llvm::createAArch64leAsmBackend(), llvm::createAArch64ObjectTargetStreamer(), llvm::createAMDGPUAsmBackend(), createARMAsmBackend(), llvm::createARMObjectTargetStreamer(), createAsmBackend(), llvm::createAVRAsmBackend(), createCSKYObjectTargetStreamer(), llvm::createHexagonAsmBackend(), llvm::createLanaiAsmBackend(), llvm::createLoongArchAsmBackend(), llvm::createM68kAsmBackend(), llvm::createMipsAsmBackend(), llvm::createMSP430ObjectTargetStreamer(), createObjectTargetStreamer(), llvm::createPPCAsmBackend(), llvm::createRISCVAsmBackend(), createRISCVObjectTargetStreamer(), llvm::createSparcAsmBackend(), llvm::createSystemZMCAsmBackend(), llvm::createVEAsmBackend(), llvm::createX86_32AsmBackend(), llvm::createX86_64AsmBackend(), llvm::createX86ObjectTargetStreamer(), llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AsmPrinter::emitXRayTable(), llvm::RISCVAsmBackend::getFixupKind(), llvm::AMDGPU::getHsaAbiVersion(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::getMCReg(), llvm::PPCMCCodeEmitter::getTLSRegEncoding(), lowerMSASplatZExt(), llvm::MipsTargetELFStreamer::MipsTargetELFStreamer(), llvm::RISCVAsmBackend::RISCVAsmBackend(), llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer(), AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString(), truncateVecElts(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().
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Definition at line 110 of file MCSubtargetInfo.h.
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Definition at line 176 of file MCSubtargetInfo.h.
References assert(), and llvm::PPCISD::SC.
Referenced by llvm::MCSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeOperandLatency(), and getLatency().
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Return an iterator at the first process resource consumed by the given scheduling class.
Definition at line 167 of file MCSubtargetInfo.h.
References llvm::PPCISD::SC.
Referenced by llvm::ResourceManager::canReserveResources(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::TargetSchedModel::getWriteProcResBegin(), getWriteProcResEnd(), llvm::mca::initializeUsedResources(), and llvm::ResourceManager::reserveResources().
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Definition at line 171 of file MCSubtargetInfo.h.
References getWriteProcResBegin(), and llvm::PPCISD::SC.
Referenced by llvm::ResourceManager::canReserveResources(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::TargetSchedModel::getWriteProcResEnd(), and llvm::ResourceManager::reserveResources().
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Definition at line 119 of file MCSubtargetInfo.h.
Referenced by llvm::RISCVTargetStreamer::emitTargetAttributes(), llvm::ARMTargetStreamer::emitTargetAttributes(), getArchForCPU(), llvm::RISCVMCObjectFileInfo::getTextSectionAlignment(), llvm::ARMElfTargetObjectFile::Initialize(), llvm::X86_MC::is16BitMemOperand(), isV8M(), llvm::MSP430TargetELFStreamer::MSP430TargetELFStreamer(), llvm::X86_MC::needsAddressSizeOverride(), llvm::RISCVInstPrinter::printBranchOperand(), and llvm::X86InstPrinterCommon::printInstFlags().
void MCSubtargetInfo::initInstrItins | ( | InstrItineraryData & | InstrItins | ) | const |
Initialize an InstrItineraryData instance.
Definition at line 333 of file MCSubtargetInfo.cpp.
References getSchedModel().
Referenced by llvm::TargetSchedModel::init().
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Initialize the scheduling model and feature bits.
FIXME: Find a way to stick this in the constructor, since it should only be called during initialization.
Definition at line 208 of file MCSubtargetInfo.cpp.
References llvm::StringRef::empty(), llvm::X86AS::FS, llvm::MCSchedModel::GetDefaultSchedModel(), getFeatures(), and getSchedModelForCPU().
Referenced by MCSubtargetInfo().
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Check whether the CPU string is valid.
Definition at line 228 of file MCSubtargetInfo.h.
References llvm::ArrayRef< T >::end(), and llvm::lower_bound().
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Resolve a variant scheduling class for the given MCInst and CPU.
Definition at line 220 of file MCSubtargetInfo.h.
Referenced by llvm::MCSchedModel::computeInstrLatency(), and llvm::MCSchedModel::getReciprocalThroughput().
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
Definition at line 219 of file MCSubtargetInfo.cpp.
References llvm::X86AS::FS, and getFeatures().
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Definition at line 113 of file MCSubtargetInfo.h.
Referenced by llvm::CSKYAsmPrinter::runOnMachineFunction().
FeatureBitset MCSubtargetInfo::SetFeatureBitsTransitively | ( | const FeatureBitset & | FB | ) |
Set/clear additional feature bits, including all other bits they imply.
Definition at line 250 of file MCSubtargetInfo.cpp.
References SetImpliedBits().
FeatureBitset MCSubtargetInfo::ToggleFeature | ( | const FeatureBitset & | FB | ) |
Toggle a feature and return the re-computed feature bits.
This version does not change the implied bits.
Definition at line 245 of file MCSubtargetInfo.cpp.
FeatureBitset MCSubtargetInfo::ToggleFeature | ( | StringRef | FS | ) |
Toggle a set of features and return the re-computed feature bits.
This version will also change all implied bits.
Definition at line 267 of file MCSubtargetInfo.cpp.
References ClearImpliedBits(), llvm::errs(), Find(), llvm::FeatureBitArray::getAsBitset(), llvm::SubtargetFeatureKV::Implies, llvm::FeatureBitset::reset(), llvm::FeatureBitset::set(), SetImpliedBits(), llvm::SubtargetFeatures::StripFlag(), llvm::FeatureBitset::test(), and llvm::SubtargetFeatureKV::Value.
FeatureBitset MCSubtargetInfo::ToggleFeature | ( | uint64_t | FB | ) |
Toggle a feature and return the re-computed feature bits.
This version does not change the implied bits.
Definition at line 240 of file MCSubtargetInfo.cpp.
References llvm::FeatureBitset::flip().
Referenced by clearFeature().