LLVM  14.0.0git
Classes | Namespaces | Macros | Enumerations | Functions
AMDGPUBaseInfo.h File Reference
#include "SIDefines.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Support/Alignment.h"
#include "AMDGPUGenSearchableTables.inc"
Include dependency graph for AMDGPUBaseInfo.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  llvm::AMDGPU::GcnBufferFormatInfo
 
class  llvm::AMDGPU::IsaInfo::AMDGPUTargetID
 
struct  llvm::AMDGPU::MIMGBaseOpcodeInfo
 
struct  llvm::AMDGPU::MIMGDimInfo
 
struct  llvm::AMDGPU::MIMGLZMappingInfo
 
struct  llvm::AMDGPU::MIMGMIPMappingInfo
 
struct  llvm::AMDGPU::MIMGG16MappingInfo
 
struct  llvm::AMDGPU::MIMGInfo
 
struct  llvm::AMDGPU::Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction. More...
 
struct  llvm::AMDGPU::SIModeRegisterDefaults
 

Namespaces

 llvm
 ---------------------— PointerInfo ------------------------------------—
 
 llvm::amdhsa
 
 llvm::AMDGPU
 
 llvm::AMDGPU::IsaInfo
 
 llvm::AMDGPU::Hwreg
 
 llvm::AMDGPU::Exp
 
 llvm::AMDGPU::MTBUFFormat
 
 llvm::AMDGPU::SendMsg
 

Macros

#define GET_MIMGBaseOpcode_DECL
 
#define GET_MIMGDim_DECL
 
#define GET_MIMGEncoding_DECL
 
#define GET_MIMGLZMapping_DECL
 
#define GET_MIMGMIPMapping_DECL
 

Enumerations

enum  { llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG = 96, llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS = 16 }
 
enum  llvm::AMDGPU::IsaInfo::TargetIDSetting { llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported, llvm::AMDGPU::IsaInfo::TargetIDSetting::Any, llvm::AMDGPU::IsaInfo::TargetIDSetting::Off, llvm::AMDGPU::IsaInfo::TargetIDSetting::On }
 

Functions

Optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion2 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion4 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3Or4 (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
 
LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation (uint16_t Opcode)
 
const LLVM_READONLY MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
const LLVM_READONLY MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo (unsigned DimEnum)
 
const LLVM_READONLY MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding (uint8_t DimEnc)
 
const LLVM_READONLY MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
 
const LLVM_READONLY MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo (unsigned L)
 
const LLVM_READONLY MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo (unsigned MIP)
 
const LLVM_READONLY MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo (unsigned G)
 
int llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
int llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
unsigned llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
 
const LLVM_READONLY MIMGInfo * llvm::AMDGPU::getMIMGInfo (unsigned Opc)
 
int llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMTBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMUBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)
 
bool llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)
 
bool llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
 
int llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
int llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, intllvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
Waitcnt llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
int64_t llvm::AMDGPU::Hwreg::getHwregId (const StringRef Name)
 
bool llvm::AMDGPU::Hwreg::isValidHwreg (int64_t Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::Hwreg::isValidHwreg (int64_t Id)
 
bool llvm::AMDGPU::Hwreg::isValidHwregOffset (int64_t Offset)
 
bool llvm::AMDGPU::Hwreg::isValidHwregWidth (int64_t Width)
 
uint64_t llvm::AMDGPU::Hwreg::encodeHwreg (uint64_t Id, uint64_t Offset, uint64_t Width)
 
StringRef llvm::AMDGPU::Hwreg::getHwreg (unsigned Id, const MCSubtargetInfo &STI)
 
void llvm::AMDGPU::Hwreg::decodeHwreg (unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
 
bool llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)
 
unsigned llvm::AMDGPU::Exp::getTgtId (const StringRef Name)
 
bool llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)
 
void llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
 
int64_t llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)
 
StringRef llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)
 
int64_t llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)
 
StringRef llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name)
 
StringRef llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id)
 
bool llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id)
 
int64_t llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt)
 
bool llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)
 
unsigned llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::SendMsg::getMsgId (const StringRef Name)
 
int64_t llvm::AMDGPU::SendMsg::getMsgOpId (int64_t MsgId, const StringRef Name)
 
StringRef llvm::AMDGPU::SendMsg::getMsgName (int64_t MsgId)
 
StringRef llvm::AMDGPU::SendMsg::getMsgOpName (int64_t MsgId, int64_t OpId)
 
bool llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
 
bool llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
 
bool llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
 
bool llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId)
 
bool llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId)
 
void llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
 
uint64_t llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::getHasColorExport (const Function &F)
 
bool llvm::AMDGPU::getHasDepthExport (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isGraphics (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC)
 
LLVM_READNONE bool llvm::AMDGPU::isKernel (CallingConv::ID CC)
 
bool llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasGFX10A16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool llvm::AMDGPU::isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned llvm::AMDGPU::mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 
LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral (int64_t Literal)
 Is this literal inlinable, and not one of the values intended for floating point values. More...
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableIntLiteralV216 (int32_t Literal)
 
bool llvm::AMDGPU::isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
 
bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
 
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets. More...
 
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
 
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST, bool Signed)
 For FLAT segment the offset must be positive; MSB is ignored and forced to zero. More...
 
bool llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool llvm::AMDGPU::splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
 
LLVM_READNONE bool llvm::AMDGPU::isLegal64BitDPPControl (unsigned DC)
 
bool llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)
 
raw_ostream & llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)
 

Macro Definition Documentation

◆ GET_MIMGBaseOpcode_DECL

#define GET_MIMGBaseOpcode_DECL

Definition at line 62 of file AMDGPUBaseInfo.h.

◆ GET_MIMGDim_DECL

#define GET_MIMGDim_DECL

Definition at line 63 of file AMDGPUBaseInfo.h.

◆ GET_MIMGEncoding_DECL

#define GET_MIMGEncoding_DECL

Definition at line 64 of file AMDGPUBaseInfo.h.

◆ GET_MIMGLZMapping_DECL

#define GET_MIMGLZMapping_DECL

Definition at line 65 of file AMDGPUBaseInfo.h.

◆ GET_MIMGMIPMapping_DECL

#define GET_MIMGMIPMapping_DECL

Definition at line 66 of file AMDGPUBaseInfo.h.