LLVM 17.0.0git
MCSubtargetInfo.h
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1//===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the subtarget options of a Target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_MC_MCSUBTARGETINFO_H
14#define LLVM_MC_MCSUBTARGETINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/ADT/Triple.h"
21#include "llvm/MC/MCSchedule.h"
23#include <cassert>
24#include <cstdint>
25#include <optional>
26#include <string>
27
28namespace llvm {
29
30class MCInst;
31
32//===----------------------------------------------------------------------===//
33
34/// Used to provide key value pairs for feature and CPU bit flags.
36 const char *Key; ///< K-V key string
37 const char *Desc; ///< Help descriptor
38 unsigned Value; ///< K-V integer value
39 FeatureBitArray Implies; ///< K-V bit mask
40
41 /// Compare routine for std::lower_bound
42 bool operator<(StringRef S) const {
43 return StringRef(Key) < S;
44 }
45
46 /// Compare routine for std::is_sorted.
47 bool operator<(const SubtargetFeatureKV &Other) const {
48 return StringRef(Key) < StringRef(Other.Key);
49 }
50};
51
52//===----------------------------------------------------------------------===//
53
54/// Used to provide key value pairs for feature and CPU bit flags.
56 const char *Key; ///< K-V key string
57 FeatureBitArray Implies; ///< K-V bit mask
58 FeatureBitArray TuneImplies; ///< K-V bit mask
60
61 /// Compare routine for std::lower_bound
62 bool operator<(StringRef S) const {
63 return StringRef(Key) < S;
64 }
65
66 /// Compare routine for std::is_sorted.
67 bool operator<(const SubtargetSubTypeKV &Other) const {
68 return StringRef(Key) < StringRef(Other.Key);
69 }
70};
71
72//===----------------------------------------------------------------------===//
73///
74/// Generic base class for all target subtargets.
75///
77 Triple TargetTriple;
78 std::string CPU; // CPU being targeted.
79 std::string TuneCPU; // CPU being tuned for.
80 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
81 ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
82
83 // Scheduler machine model
84 const MCWriteProcResEntry *WriteProcResTable;
85 const MCWriteLatencyEntry *WriteLatencyTable;
86 const MCReadAdvanceEntry *ReadAdvanceTable;
87 const MCSchedModel *CPUSchedModel;
88
89 const InstrStage *Stages; // Instruction itinerary stages
90 const unsigned *OperandCycles; // Itinerary operand cycles
91 const unsigned *ForwardingPaths;
92 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
93 std::string FeatureString; // Feature string
94
95public:
96 MCSubtargetInfo(const MCSubtargetInfo &) = default;
97 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
100 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
101 const MCReadAdvanceEntry *RA, const InstrStage *IS,
102 const unsigned *OC, const unsigned *FP);
103 MCSubtargetInfo() = delete;
106 virtual ~MCSubtargetInfo() = default;
107
108 const Triple &getTargetTriple() const { return TargetTriple; }
109 StringRef getCPU() const { return CPU; }
110 StringRef getTuneCPU() const { return TuneCPU; }
111
112 const FeatureBitset& getFeatureBits() const { return FeatureBits; }
113 void setFeatureBits(const FeatureBitset &FeatureBits_) {
114 FeatureBits = FeatureBits_;
115 }
116
117 StringRef getFeatureString() const { return FeatureString; }
118
119 bool hasFeature(unsigned Feature) const {
120 return FeatureBits[Feature];
121 }
122
123protected:
124 /// Initialize the scheduling model and feature bits.
125 ///
126 /// FIXME: Find a way to stick this in the constructor, since it should only
127 /// be called during initialization.
128 void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
129
130public:
131 /// Set the features to the default for the given CPU and TuneCPU, with ano
132 /// appended feature string.
133 void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
134
135 /// Toggle a feature and return the re-computed feature bits.
136 /// This version does not change the implied bits.
138
139 /// Toggle a feature and return the re-computed feature bits.
140 /// This version does not change the implied bits.
142
143 /// Toggle a set of features and return the re-computed feature bits.
144 /// This version will also change all implied bits.
146
147 /// Apply a feature flag and return the re-computed feature bits, including
148 /// all feature bits implied by the flag.
150
151 /// Set/clear additional feature bits, including all other bits they imply.
154
155 /// Check whether the subtarget features are enabled/disabled as per
156 /// the provided string, ignoring all other features.
157 bool checkFeatures(StringRef FS) const;
158
159 /// Get the machine model of a CPU.
161
162 /// Get the machine model for this subtarget's CPU.
163 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
164
165 /// Return an iterator at the first process resource consumed by the given
166 /// scheduling class.
168 const MCSchedClassDesc *SC) const {
169 return &WriteProcResTable[SC->WriteProcResIdx];
170 }
172 const MCSchedClassDesc *SC) const {
173 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
174 }
175
177 unsigned DefIdx) const {
178 assert(DefIdx < SC->NumWriteLatencyEntries &&
179 "MachineModel does not specify a WriteResource for DefIdx");
180
181 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
182 }
183
184 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
185 unsigned WriteResID) const {
186 // TODO: The number of read advance entries in a class can be significant
187 // (~50). Consider compressing the WriteID into a dense ID of those that are
188 // used by ReadAdvance and representing them as a bitset.
189 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
190 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
191 if (I->UseIdx < UseIdx)
192 continue;
193 if (I->UseIdx > UseIdx)
194 break;
195 // Find the first WriteResIdx match, which has the highest cycle count.
196 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
197 return I->Cycles;
198 }
199 }
200 return 0;
201 }
202
203 /// Return the set of ReadAdvance entries declared by the scheduling class
204 /// descriptor in input.
207 if (!SC.NumReadAdvanceEntries)
209 return ArrayRef<MCReadAdvanceEntry>(&ReadAdvanceTable[SC.ReadAdvanceIdx],
210 SC.NumReadAdvanceEntries);
211 }
212
213 /// Get scheduling itinerary of a CPU.
215
216 /// Initialize an InstrItineraryData instance.
217 void initInstrItins(InstrItineraryData &InstrItins) const;
218
219 /// Resolve a variant scheduling class for the given MCInst and CPU.
220 virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
221 const MCInst *MI,
222 const MCInstrInfo *MCII,
223 unsigned CPUID) const {
224 return 0;
225 }
226
227 /// Check whether the CPU string is valid.
228 bool isCPUStringValid(StringRef CPU) const {
229 auto Found = llvm::lower_bound(ProcDesc, CPU);
230 return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
231 }
232
233 virtual unsigned getHwMode() const { return 0; }
234
235 /// Return the cache size in bytes for the given level of cache.
236 /// Level is zero-based, so a value of zero means the first level of
237 /// cache.
238 ///
239 virtual std::optional<unsigned> getCacheSize(unsigned Level) const;
240
241 /// Return the cache associatvity for the given level of cache.
242 /// Level is zero-based, so a value of zero means the first level of
243 /// cache.
244 ///
245 virtual std::optional<unsigned> getCacheAssociativity(unsigned Level) const;
246
247 /// Return the target cache line size in bytes at a given level.
248 ///
249 virtual std::optional<unsigned> getCacheLineSize(unsigned Level) const;
250
251 /// Return the target cache line size in bytes. By default, return
252 /// the line size for the bottom-most level of cache. This provides
253 /// a more convenient interface for the common case where all cache
254 /// levels have the same line size. Return zero if there is no
255 /// cache model.
256 ///
257 virtual unsigned getCacheLineSize() const {
258 std::optional<unsigned> Size = getCacheLineSize(0);
259 if (Size)
260 return *Size;
261
262 return 0;
263 }
264
265 /// Return the preferred prefetch distance in terms of instructions.
266 ///
267 virtual unsigned getPrefetchDistance() const;
268
269 /// Return the maximum prefetch distance in terms of loop
270 /// iterations.
271 ///
272 virtual unsigned getMaxPrefetchIterationsAhead() const;
273
274 /// \return True if prefetching should also be done for writes.
275 ///
276 virtual bool enableWritePrefetching() const;
277
278 /// Return the minimum stride necessary to trigger software
279 /// prefetching.
280 ///
281 virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
282 unsigned NumStridedMemAccesses,
283 unsigned NumPrefetches,
284 bool HasCall) const;
285
286 /// \return if target want to issue a prefetch in address space \p AS.
287 virtual bool shouldPrefetchAddressSpace(unsigned AS) const;
288};
289
290} // end namespace llvm
291
292#endif // LLVM_MC_MCSUBTARGETINFO_H
This header is deprecated in favour of llvm/TargetParser/Triple.h.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file contains some templates that are useful if you are working with the STL at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:152
Class used to store the subtarget bits in the tables created by tablegen.
Container class for subtarget features.
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Generic base class for all target subtargets.
virtual unsigned getCacheLineSize() const
Return the target cache line size in bytes.
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string,...
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
bool hasFeature(unsigned Feature) const
virtual unsigned getHwMode() const
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
StringRef getFeatureString() const
void setFeatureBits(const FeatureBitset &FeatureBits_)
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
virtual std::optional< unsigned > getCacheSize(unsigned Level) const
Return the cache size in bytes for the given level of cache.
const Triple & getTargetTriple() const
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
virtual bool shouldPrefetchAddressSpace(unsigned AS) const
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
MCSubtargetInfo & operator=(MCSubtargetInfo &&)=delete
const FeatureBitset & getFeatureBits() const
StringRef getCPU() const
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
virtual bool enableWritePrefetching() const
virtual unsigned getMaxPrefetchIterationsAhead() const
Return the maximum prefetch distance in terms of loop iterations.
virtual ~MCSubtargetInfo()=default
virtual unsigned getPrefetchDistance() const
Return the preferred prefetch distance in terms of instructions.
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
virtual std::optional< unsigned > getCacheAssociativity(unsigned Level) const
Return the cache associatvity for the given level of cache.
FeatureBitset SetFeatureBitsTransitively(const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
StringRef getTuneCPU() const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
MCSubtargetInfo(const MCSubtargetInfo &)=default
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB)
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1923
These values represent a non-pipelined step in the execution of an instruction.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
Used to provide key value pairs for feature and CPU bit flags.
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
bool operator<(const SubtargetFeatureKV &Other) const
Compare routine for std::is_sorted.
unsigned Value
K-V integer value.
const char * Key
K-V key string.
const char * Desc
Help descriptor.
FeatureBitArray Implies
K-V bit mask.
Used to provide key value pairs for feature and CPU bit flags.
const MCSchedModel * SchedModel
FeatureBitArray Implies
K-V bit mask.
const char * Key
K-V key string.
FeatureBitArray TuneImplies
K-V bit mask.
bool operator<(const SubtargetSubTypeKV &Other) const
Compare routine for std::is_sorted.
bool operator<(StringRef S) const
Compare routine for std::lower_bound.