LLVM  13.0.0git
MCSubtargetInfo.h
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1 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_MC_MCSUBTARGETINFO_H
14 #define LLVM_MC_MCSUBTARGETINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCSchedule.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 #include <string>
26 
27 namespace llvm {
28 
29 class MCInst;
30 
31 //===----------------------------------------------------------------------===//
32 
33 /// Used to provide key value pairs for feature and CPU bit flags.
35  const char *Key; ///< K-V key string
36  const char *Desc; ///< Help descriptor
37  unsigned Value; ///< K-V integer value
38  FeatureBitArray Implies; ///< K-V bit mask
39 
40  /// Compare routine for std::lower_bound
41  bool operator<(StringRef S) const {
42  return StringRef(Key) < S;
43  }
44 
45  /// Compare routine for std::is_sorted.
46  bool operator<(const SubtargetFeatureKV &Other) const {
47  return StringRef(Key) < StringRef(Other.Key);
48  }
49 };
50 
51 //===----------------------------------------------------------------------===//
52 
53 /// Used to provide key value pairs for feature and CPU bit flags.
55  const char *Key; ///< K-V key string
56  FeatureBitArray Implies; ///< K-V bit mask
57  FeatureBitArray TuneImplies; ///< K-V bit mask
59 
60  /// Compare routine for std::lower_bound
61  bool operator<(StringRef S) const {
62  return StringRef(Key) < S;
63  }
64 
65  /// Compare routine for std::is_sorted.
66  bool operator<(const SubtargetSubTypeKV &Other) const {
67  return StringRef(Key) < StringRef(Other.Key);
68  }
69 };
70 
71 //===----------------------------------------------------------------------===//
72 ///
73 /// Generic base class for all target subtargets.
74 ///
76  Triple TargetTriple;
77  std::string CPU; // CPU being targeted.
78  std::string TuneCPU; // CPU being tuned for.
79  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
80  ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
81 
82  // Scheduler machine model
83  const MCWriteProcResEntry *WriteProcResTable;
84  const MCWriteLatencyEntry *WriteLatencyTable;
85  const MCReadAdvanceEntry *ReadAdvanceTable;
86  const MCSchedModel *CPUSchedModel;
87 
88  const InstrStage *Stages; // Instruction itinerary stages
89  const unsigned *OperandCycles; // Itinerary operand cycles
90  const unsigned *ForwardingPaths;
91  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
92  std::string FeatureString; // Feature string
93 
94 public:
95  MCSubtargetInfo(const MCSubtargetInfo &) = default;
96  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
99  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
100  const MCReadAdvanceEntry *RA, const InstrStage *IS,
101  const unsigned *OC, const unsigned *FP);
102  MCSubtargetInfo() = delete;
103  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
105  virtual ~MCSubtargetInfo() = default;
106 
107  const Triple &getTargetTriple() const { return TargetTriple; }
108  StringRef getCPU() const { return CPU; }
109  StringRef getTuneCPU() const { return TuneCPU; }
110 
111  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
112  void setFeatureBits(const FeatureBitset &FeatureBits_) {
113  FeatureBits = FeatureBits_;
114  }
115 
116  StringRef getFeatureString() const { return FeatureString; }
117 
118  bool hasFeature(unsigned Feature) const {
119  return FeatureBits[Feature];
120  }
121 
122 protected:
123  /// Initialize the scheduling model and feature bits.
124  ///
125  /// FIXME: Find a way to stick this in the constructor, since it should only
126  /// be called during initialization.
127  void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
128 
129 public:
130  /// Set the features to the default for the given CPU and TuneCPU, with ano
131  /// appended feature string.
132  void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
133 
134  /// Toggle a feature and return the re-computed feature bits.
135  /// This version does not change the implied bits.
136  FeatureBitset ToggleFeature(uint64_t FB);
137 
138  /// Toggle a feature and return the re-computed feature bits.
139  /// This version does not change the implied bits.
141 
142  /// Toggle a set of features and return the re-computed feature bits.
143  /// This version will also change all implied bits.
145 
146  /// Apply a feature flag and return the re-computed feature bits, including
147  /// all feature bits implied by the flag.
149 
150  /// Set/clear additional feature bits, including all other bits they imply.
153 
154  /// Check whether the subtarget features are enabled/disabled as per
155  /// the provided string, ignoring all other features.
156  bool checkFeatures(StringRef FS) const;
157 
158  /// Get the machine model of a CPU.
159  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
160 
161  /// Get the machine model for this subtarget's CPU.
162  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
163 
164  /// Return an iterator at the first process resource consumed by the given
165  /// scheduling class.
167  const MCSchedClassDesc *SC) const {
168  return &WriteProcResTable[SC->WriteProcResIdx];
169  }
171  const MCSchedClassDesc *SC) const {
172  return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
173  }
174 
176  unsigned DefIdx) const {
177  assert(DefIdx < SC->NumWriteLatencyEntries &&
178  "MachineModel does not specify a WriteResource for DefIdx");
179 
180  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
181  }
182 
183  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
184  unsigned WriteResID) const {
185  // TODO: The number of read advance entries in a class can be significant
186  // (~50). Consider compressing the WriteID into a dense ID of those that are
187  // used by ReadAdvance and representing them as a bitset.
188  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
189  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
190  if (I->UseIdx < UseIdx)
191  continue;
192  if (I->UseIdx > UseIdx)
193  break;
194  // Find the first WriteResIdx match, which has the highest cycle count.
195  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
196  return I->Cycles;
197  }
198  }
199  return 0;
200  }
201 
202  /// Return the set of ReadAdvance entries declared by the scheduling class
203  /// descriptor in input.
206  if (!SC.NumReadAdvanceEntries)
208  return ArrayRef<MCReadAdvanceEntry>(&ReadAdvanceTable[SC.ReadAdvanceIdx],
209  SC.NumReadAdvanceEntries);
210  }
211 
212  /// Get scheduling itinerary of a CPU.
214 
215  /// Initialize an InstrItineraryData instance.
216  void initInstrItins(InstrItineraryData &InstrItins) const;
217 
218  /// Resolve a variant scheduling class for the given MCInst and CPU.
219  virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
220  const MCInst *MI,
221  const MCInstrInfo *MCII,
222  unsigned CPUID) const {
223  return 0;
224  }
225 
226  /// Check whether the CPU string is valid.
227  bool isCPUStringValid(StringRef CPU) const {
228  auto Found = llvm::lower_bound(ProcDesc, CPU);
229  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
230  }
231 
232  virtual unsigned getHwMode() const { return 0; }
233 
234  /// Return the cache size in bytes for the given level of cache.
235  /// Level is zero-based, so a value of zero means the first level of
236  /// cache.
237  ///
238  virtual Optional<unsigned> getCacheSize(unsigned Level) const;
239 
240  /// Return the cache associatvity for the given level of cache.
241  /// Level is zero-based, so a value of zero means the first level of
242  /// cache.
243  ///
244  virtual Optional<unsigned> getCacheAssociativity(unsigned Level) const;
245 
246  /// Return the target cache line size in bytes at a given level.
247  ///
248  virtual Optional<unsigned> getCacheLineSize(unsigned Level) const;
249 
250  /// Return the target cache line size in bytes. By default, return
251  /// the line size for the bottom-most level of cache. This provides
252  /// a more convenient interface for the common case where all cache
253  /// levels have the same line size. Return zero if there is no
254  /// cache model.
255  ///
256  virtual unsigned getCacheLineSize() const {
258  if (Size)
259  return *Size;
260 
261  return 0;
262  }
263 
264  /// Return the preferred prefetch distance in terms of instructions.
265  ///
266  virtual unsigned getPrefetchDistance() const;
267 
268  /// Return the maximum prefetch distance in terms of loop
269  /// iterations.
270  ///
271  virtual unsigned getMaxPrefetchIterationsAhead() const;
272 
273  /// \return True if prefetching should also be done for writes.
274  ///
275  virtual bool enableWritePrefetching() const;
276 
277  /// Return the minimum stride necessary to trigger software
278  /// prefetching.
279  ///
280  virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
281  unsigned NumStridedMemAccesses,
282  unsigned NumPrefetches,
283  bool HasCall) const;
284 };
285 
286 } // end namespace llvm
287 
288 #endif // LLVM_MC_MCSUBTARGETINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MCSubtargetInfo::enableWritePrefetching
virtual bool enableWritePrefetching() const
Definition: MCSubtargetInfo.cpp:359
llvm::MCSubtargetInfo::~MCSubtargetInfo
virtual ~MCSubtargetInfo()=default
llvm::MCSubtargetInfo::getWriteProcResEnd
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
Definition: MCSubtargetInfo.h:170
CmpMode::FP
@ FP
llvm::MCSubtargetInfo::getCacheSize
virtual Optional< unsigned > getCacheSize(unsigned Level) const
Return the cache size in bytes for the given level of cache.
Definition: MCSubtargetInfo.cpp:338
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::SubtargetFeatureKV::operator<
bool operator<(const SubtargetFeatureKV &Other) const
Compare routine for std::is_sorted.
Definition: MCSubtargetInfo.h:46
llvm::MCSubtargetInfo::getCacheLineSize
virtual unsigned getCacheLineSize() const
Return the target cache line size in bytes.
Definition: MCSubtargetInfo.h:256
llvm::SubtargetFeatureKV::Value
unsigned Value
K-V integer value.
Definition: MCSubtargetInfo.h:37
llvm::MCSubtargetInfo::MCSubtargetInfo
MCSubtargetInfo()=delete
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1592
StringRef.h
llvm::MCSubtargetInfo::getTuneCPU
StringRef getTuneCPU() const
Definition: MCSubtargetInfo.h:109
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::Optional< unsigned >
llvm::MCSubtargetInfo::getInstrItineraryForCPU
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Definition: MCSubtargetInfo.cpp:328
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCWriteProcResEntry
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:64
llvm::MCSubtargetInfo::setFeatureBits
void setFeatureBits(const FeatureBitset &FeatureBits_)
Definition: MCSubtargetInfo.h:112
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::MCSubtargetInfo::getHwMode
virtual unsigned getHwMode() const
Definition: MCSubtargetInfo.h:232
llvm::SubtargetSubTypeKV::SchedModel
const MCSchedModel * SchedModel
Definition: MCSubtargetInfo.h:58
llvm::SubtargetFeatureKV::Key
const char * Key
K-V key string.
Definition: MCSubtargetInfo.h:35
llvm::MCSubtargetInfo::getMaxPrefetchIterationsAhead
virtual unsigned getMaxPrefetchIterationsAhead() const
Return the maximum prefetch distance in terms of loop iterations.
Definition: MCSubtargetInfo.cpp:355
llvm::MCSubtargetInfo::resolveVariantSchedClass
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
Definition: MCSubtargetInfo.h:219
MCInstrItineraries.h
llvm::MCSubtargetInfo::getPrefetchDistance
virtual unsigned getPrefetchDistance() const
Return the preferred prefetch distance in terms of instructions.
Definition: MCSubtargetInfo.cpp:351
SubtargetFeature.h
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:410
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:118
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:110
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::MCSubtargetInfo::isCPUStringValid
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Definition: MCSubtargetInfo.h:227
llvm::MCSubtargetInfo::getWriteLatencyEntry
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
Definition: MCSubtargetInfo.h:175
llvm::MCSubtargetInfo::getSchedModelForCPU
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
Definition: MCSubtargetInfo.cpp:309
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:34
llvm::MCSubtargetInfo::ApplyFeatureFlag
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Definition: MCSubtargetInfo.cpp:292
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
MCSchedule.h
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:782
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SubtargetSubTypeKV::operator<
bool operator<(const SubtargetSubTypeKV &Other) const
Compare routine for std::is_sorted.
Definition: MCSubtargetInfo.h:66
ArrayRef.h
llvm::MCSubtargetInfo::operator=
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCSubtargetInfo::InitMCProcessorInfo
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.
Definition: MCSubtargetInfo.cpp:208
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:128
llvm::MCSubtargetInfo::ClearFeatureBitsTransitively
FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB)
Definition: MCSubtargetInfo.cpp:256
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::SubtargetSubTypeKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:54
llvm::SubtargetFeatureKV::Implies
FeatureBitArray Implies
K-V bit mask.
Definition: MCSubtargetInfo.h:38
llvm::MCSubtargetInfo::getMinPrefetchStride
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
Definition: MCSubtargetInfo.cpp:363
llvm::MCSubtargetInfo::initInstrItins
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
Definition: MCSubtargetInfo.cpp:333
Triple.h
llvm::MCSubtargetInfo::getFeatureString
StringRef getFeatureString() const
Definition: MCSubtargetInfo.h:116
llvm::SubtargetFeatureKV::Desc
const char * Desc
Help descriptor.
Definition: MCSubtargetInfo.h:36
llvm::MCSubtargetInfo::getWriteProcResBegin
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
Definition: MCSubtargetInfo.h:166
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::MCSubtargetInfo::SetFeatureBitsTransitively
FeatureBitset SetFeatureBitsTransitively(const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
Definition: MCSubtargetInfo.cpp:250
llvm::InstrStage
These values represent a non-pipelined step in the execution of an instruction.
Definition: MCInstrItineraries.h:58
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::MCReadAdvanceEntry
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:95
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:245
llvm::SubtargetSubTypeKV::Key
const char * Key
K-V key string.
Definition: MCSubtargetInfo.h:55
llvm::MCSubtargetInfo::checkFeatures
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string,...
Definition: MCSubtargetInfo.cpp:297
llvm::SubtargetSubTypeKV::Implies
FeatureBitArray Implies
K-V bit mask.
Definition: MCSubtargetInfo.h:56
llvm::MCSubtargetInfo::getReadAdvanceCycles
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
Definition: MCSubtargetInfo.h:183
llvm::SubtargetFeatureKV::operator<
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
Definition: MCSubtargetInfo.h:41
llvm::MCSubtargetInfo::getReadAdvanceEntries
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
Definition: MCSubtargetInfo.h:205
llvm::SubtargetSubTypeKV::TuneImplies
FeatureBitArray TuneImplies
K-V bit mask.
Definition: MCSubtargetInfo.h:57
llvm::MCSubtargetInfo::setDefaultFeatures
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
Definition: MCSubtargetInfo.cpp:219
llvm::SubtargetSubTypeKV::operator<
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
Definition: MCSubtargetInfo.h:61
llvm::MCSubtargetInfo::getCacheAssociativity
virtual Optional< unsigned > getCacheAssociativity(unsigned Level) const
Return the cache associatvity for the given level of cache.
Definition: MCSubtargetInfo.cpp:343
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1168
llvm::FeatureBitArray
Class used to store the subtarget bits in the tables created by tablegen.
Definition: SubtargetFeature.h:165