LLVM  15.0.0git
MCSubtargetInfo.h
Go to the documentation of this file.
1 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_MC_MCSUBTARGETINFO_H
14 #define LLVM_MC_MCSUBTARGETINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCSchedule.h"
24 #include <cassert>
25 #include <cstdint>
26 #include <string>
27 
28 namespace llvm {
29 
30 class MCInst;
31 
32 //===----------------------------------------------------------------------===//
33 
34 /// Used to provide key value pairs for feature and CPU bit flags.
36  const char *Key; ///< K-V key string
37  const char *Desc; ///< Help descriptor
38  unsigned Value; ///< K-V integer value
39  FeatureBitArray Implies; ///< K-V bit mask
40 
41  /// Compare routine for std::lower_bound
42  bool operator<(StringRef S) const {
43  return StringRef(Key) < S;
44  }
45 
46  /// Compare routine for std::is_sorted.
47  bool operator<(const SubtargetFeatureKV &Other) const {
48  return StringRef(Key) < StringRef(Other.Key);
49  }
50 };
51 
52 //===----------------------------------------------------------------------===//
53 
54 /// Used to provide key value pairs for feature and CPU bit flags.
56  const char *Key; ///< K-V key string
57  FeatureBitArray Implies; ///< K-V bit mask
58  FeatureBitArray TuneImplies; ///< K-V bit mask
60 
61  /// Compare routine for std::lower_bound
62  bool operator<(StringRef S) const {
63  return StringRef(Key) < S;
64  }
65 
66  /// Compare routine for std::is_sorted.
67  bool operator<(const SubtargetSubTypeKV &Other) const {
68  return StringRef(Key) < StringRef(Other.Key);
69  }
70 };
71 
72 //===----------------------------------------------------------------------===//
73 ///
74 /// Generic base class for all target subtargets.
75 ///
77  Triple TargetTriple;
78  std::string CPU; // CPU being targeted.
79  std::string TuneCPU; // CPU being tuned for.
80  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
81  ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
82 
83  // Scheduler machine model
84  const MCWriteProcResEntry *WriteProcResTable;
85  const MCWriteLatencyEntry *WriteLatencyTable;
86  const MCReadAdvanceEntry *ReadAdvanceTable;
87  const MCSchedModel *CPUSchedModel;
88 
89  const InstrStage *Stages; // Instruction itinerary stages
90  const unsigned *OperandCycles; // Itinerary operand cycles
91  const unsigned *ForwardingPaths;
92  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
93  std::string FeatureString; // Feature string
94 
95 public:
96  MCSubtargetInfo(const MCSubtargetInfo &) = default;
97  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
100  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
101  const MCReadAdvanceEntry *RA, const InstrStage *IS,
102  const unsigned *OC, const unsigned *FP);
103  MCSubtargetInfo() = delete;
104  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
106  virtual ~MCSubtargetInfo() = default;
107 
108  const Triple &getTargetTriple() const { return TargetTriple; }
109  StringRef getCPU() const { return CPU; }
110  StringRef getTuneCPU() const { return TuneCPU; }
111 
112  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
113  void setFeatureBits(const FeatureBitset &FeatureBits_) {
114  FeatureBits = FeatureBits_;
115  }
116 
117  StringRef getFeatureString() const { return FeatureString; }
118 
119  bool hasFeature(unsigned Feature) const {
120  return FeatureBits[Feature];
121  }
122 
123 protected:
124  /// Initialize the scheduling model and feature bits.
125  ///
126  /// FIXME: Find a way to stick this in the constructor, since it should only
127  /// be called during initialization.
128  void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
129 
130 public:
131  /// Set the features to the default for the given CPU and TuneCPU, with ano
132  /// appended feature string.
133  void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
134 
135  /// Toggle a feature and return the re-computed feature bits.
136  /// This version does not change the implied bits.
138 
139  /// Toggle a feature and return the re-computed feature bits.
140  /// This version does not change the implied bits.
142 
143  /// Toggle a set of features and return the re-computed feature bits.
144  /// This version will also change all implied bits.
146 
147  /// Apply a feature flag and return the re-computed feature bits, including
148  /// all feature bits implied by the flag.
150 
151  /// Set/clear additional feature bits, including all other bits they imply.
154 
155  /// Check whether the subtarget features are enabled/disabled as per
156  /// the provided string, ignoring all other features.
157  bool checkFeatures(StringRef FS) const;
158 
159  /// Get the machine model of a CPU.
160  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
161 
162  /// Get the machine model for this subtarget's CPU.
163  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
164 
165  /// Return an iterator at the first process resource consumed by the given
166  /// scheduling class.
168  const MCSchedClassDesc *SC) const {
169  return &WriteProcResTable[SC->WriteProcResIdx];
170  }
172  const MCSchedClassDesc *SC) const {
173  return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
174  }
175 
177  unsigned DefIdx) const {
178  assert(DefIdx < SC->NumWriteLatencyEntries &&
179  "MachineModel does not specify a WriteResource for DefIdx");
180 
181  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
182  }
183 
184  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
185  unsigned WriteResID) const {
186  // TODO: The number of read advance entries in a class can be significant
187  // (~50). Consider compressing the WriteID into a dense ID of those that are
188  // used by ReadAdvance and representing them as a bitset.
189  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
190  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
191  if (I->UseIdx < UseIdx)
192  continue;
193  if (I->UseIdx > UseIdx)
194  break;
195  // Find the first WriteResIdx match, which has the highest cycle count.
196  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
197  return I->Cycles;
198  }
199  }
200  return 0;
201  }
202 
203  /// Return the set of ReadAdvance entries declared by the scheduling class
204  /// descriptor in input.
207  if (!SC.NumReadAdvanceEntries)
209  return ArrayRef<MCReadAdvanceEntry>(&ReadAdvanceTable[SC.ReadAdvanceIdx],
210  SC.NumReadAdvanceEntries);
211  }
212 
213  /// Get scheduling itinerary of a CPU.
215 
216  /// Initialize an InstrItineraryData instance.
217  void initInstrItins(InstrItineraryData &InstrItins) const;
218 
219  /// Resolve a variant scheduling class for the given MCInst and CPU.
220  virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
221  const MCInst *MI,
222  const MCInstrInfo *MCII,
223  unsigned CPUID) const {
224  return 0;
225  }
226 
227  /// Check whether the CPU string is valid.
228  bool isCPUStringValid(StringRef CPU) const {
229  auto Found = llvm::lower_bound(ProcDesc, CPU);
230  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
231  }
232 
233  virtual unsigned getHwMode() const { return 0; }
234 
235  /// Return the cache size in bytes for the given level of cache.
236  /// Level is zero-based, so a value of zero means the first level of
237  /// cache.
238  ///
239  virtual Optional<unsigned> getCacheSize(unsigned Level) const;
240 
241  /// Return the cache associatvity for the given level of cache.
242  /// Level is zero-based, so a value of zero means the first level of
243  /// cache.
244  ///
245  virtual Optional<unsigned> getCacheAssociativity(unsigned Level) const;
246 
247  /// Return the target cache line size in bytes at a given level.
248  ///
249  virtual Optional<unsigned> getCacheLineSize(unsigned Level) const;
250 
251  /// Return the target cache line size in bytes. By default, return
252  /// the line size for the bottom-most level of cache. This provides
253  /// a more convenient interface for the common case where all cache
254  /// levels have the same line size. Return zero if there is no
255  /// cache model.
256  ///
257  virtual unsigned getCacheLineSize() const {
259  if (Size)
260  return *Size;
261 
262  return 0;
263  }
264 
265  /// Return the preferred prefetch distance in terms of instructions.
266  ///
267  virtual unsigned getPrefetchDistance() const;
268 
269  /// Return the maximum prefetch distance in terms of loop
270  /// iterations.
271  ///
272  virtual unsigned getMaxPrefetchIterationsAhead() const;
273 
274  /// \return True if prefetching should also be done for writes.
275  ///
276  virtual bool enableWritePrefetching() const;
277 
278  /// Return the minimum stride necessary to trigger software
279  /// prefetching.
280  ///
281  virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
282  unsigned NumStridedMemAccesses,
283  unsigned NumPrefetches,
284  bool HasCall) const;
285 };
286 
287 } // end namespace llvm
288 
289 #endif // LLVM_MC_MCSUBTARGETINFO_H
llvm::MCSubtargetInfo::enableWritePrefetching
virtual bool enableWritePrefetching() const
Definition: MCSubtargetInfo.cpp:359
llvm::MCSubtargetInfo::~MCSubtargetInfo
virtual ~MCSubtargetInfo()=default
llvm::MCSubtargetInfo::getWriteProcResEnd
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
Definition: MCSubtargetInfo.h:171
CmpMode::FP
@ FP
llvm::MCSubtargetInfo::getCacheSize
virtual Optional< unsigned > getCacheSize(unsigned Level) const
Return the cache size in bytes for the given level of cache.
Definition: MCSubtargetInfo.cpp:338
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SubtargetFeatureKV::operator<
bool operator<(const SubtargetFeatureKV &Other) const
Compare routine for std::is_sorted.
Definition: MCSubtargetInfo.h:47
llvm::MCSubtargetInfo::getCacheLineSize
virtual unsigned getCacheLineSize() const
Return the target cache line size in bytes.
Definition: MCSubtargetInfo.h:257
Optional.h
llvm::SubtargetFeatureKV::Value
unsigned Value
K-V integer value.
Definition: MCSubtargetInfo.h:38
llvm::MCSubtargetInfo::MCSubtargetInfo
MCSubtargetInfo()=delete
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:163
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1736
StringRef.h
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:787
llvm::MCSubtargetInfo::getTuneCPU
StringRef getTuneCPU() const
Definition: MCSubtargetInfo.h:110
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Optional< unsigned >
llvm::MCSubtargetInfo::getInstrItineraryForCPU
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Definition: MCSubtargetInfo.cpp:328
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCWriteProcResEntry
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
STLExtras.h
llvm::MCSubtargetInfo::setFeatureBits
void setFeatureBits(const FeatureBitset &FeatureBits_)
Definition: MCSubtargetInfo.h:113
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCSubtargetInfo::getHwMode
virtual unsigned getHwMode() const
Definition: MCSubtargetInfo.h:233
llvm::SubtargetSubTypeKV::SchedModel
const MCSchedModel * SchedModel
Definition: MCSubtargetInfo.h:59
llvm::SubtargetFeatureKV::Key
const char * Key
K-V key string.
Definition: MCSubtargetInfo.h:36
llvm::MCSubtargetInfo::getMaxPrefetchIterationsAhead
virtual unsigned getMaxPrefetchIterationsAhead() const
Return the maximum prefetch distance in terms of loop iterations.
Definition: MCSubtargetInfo.cpp:355
llvm::MCSubtargetInfo::resolveVariantSchedClass
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
Definition: MCSubtargetInfo.h:220
MCInstrItineraries.h
llvm::MCSubtargetInfo::getPrefetchDistance
virtual unsigned getPrefetchDistance() const
Return the preferred prefetch distance in terms of instructions.
Definition: MCSubtargetInfo.cpp:351
SubtargetFeature.h
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:418
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSubtargetInfo::isCPUStringValid
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Definition: MCSubtargetInfo.h:228
llvm::MCSubtargetInfo::getWriteLatencyEntry
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
Definition: MCSubtargetInfo.h:176
llvm::MCSubtargetInfo::getSchedModelForCPU
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
Definition: MCSubtargetInfo.cpp:309
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:35
llvm::MCSubtargetInfo::ApplyFeatureFlag
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Definition: MCSubtargetInfo.cpp:292
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
MCSchedule.h
uint64_t
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SubtargetSubTypeKV::operator<
bool operator<(const SubtargetSubTypeKV &Other) const
Compare routine for std::is_sorted.
Definition: MCSubtargetInfo.h:67
ArrayRef.h
llvm::MCSubtargetInfo::operator=
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCSubtargetInfo::InitMCProcessorInfo
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.
Definition: MCSubtargetInfo.cpp:208
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
llvm::MCSubtargetInfo::ClearFeatureBitsTransitively
FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB)
Definition: MCSubtargetInfo.cpp:256
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::SubtargetSubTypeKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:55
llvm::SubtargetFeatureKV::Implies
FeatureBitArray Implies
K-V bit mask.
Definition: MCSubtargetInfo.h:39
llvm::MCSubtargetInfo::getMinPrefetchStride
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
Definition: MCSubtargetInfo.cpp:363
llvm::MCSubtargetInfo::initInstrItins
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
Definition: MCSubtargetInfo.cpp:333
Triple.h
llvm::MCSubtargetInfo::getFeatureString
StringRef getFeatureString() const
Definition: MCSubtargetInfo.h:117
llvm::SubtargetFeatureKV::Desc
const char * Desc
Help descriptor.
Definition: MCSubtargetInfo.h:37
llvm::MCSubtargetInfo::getWriteProcResBegin
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
Definition: MCSubtargetInfo.h:167
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::MCSubtargetInfo::SetFeatureBitsTransitively
FeatureBitset SetFeatureBitsTransitively(const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
Definition: MCSubtargetInfo.cpp:250
llvm::InstrStage
These values represent a non-pipelined step in the execution of an instruction.
Definition: MCInstrItineraries.h:58
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCReadAdvanceEntry
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::SubtargetSubTypeKV::Key
const char * Key
K-V key string.
Definition: MCSubtargetInfo.h:56
llvm::MCSubtargetInfo::checkFeatures
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string,...
Definition: MCSubtargetInfo.cpp:297
llvm::SubtargetSubTypeKV::Implies
FeatureBitArray Implies
K-V bit mask.
Definition: MCSubtargetInfo.h:57
llvm::MCSubtargetInfo::getReadAdvanceCycles
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
Definition: MCSubtargetInfo.h:184
llvm::SubtargetFeatureKV::operator<
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
Definition: MCSubtargetInfo.h:42
llvm::MCSubtargetInfo::getReadAdvanceEntries
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
Definition: MCSubtargetInfo.h:206
llvm::SubtargetSubTypeKV::TuneImplies
FeatureBitArray TuneImplies
K-V bit mask.
Definition: MCSubtargetInfo.h:58
llvm::MCSubtargetInfo::setDefaultFeatures
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
Definition: MCSubtargetInfo.cpp:219
llvm::SubtargetSubTypeKV::operator<
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
Definition: MCSubtargetInfo.h:62
llvm::MCSubtargetInfo::getCacheAssociativity
virtual Optional< unsigned > getCacheAssociativity(unsigned Level) const
Return the cache associatvity for the given level of cache.
Definition: MCSubtargetInfo.cpp:343
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
llvm::FeatureBitArray
Class used to store the subtarget bits in the tables created by tablegen.
Definition: SubtargetFeature.h:165