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22 assert(!
D.isZero() &&
"Precondition violation.");
25 assert(
D.getBitWidth() >= 3 &&
"Does not work at smaller bitwidths.");
32 APInt T = SignedMin + (
D.lshr(
D.getBitWidth() - 1));
34 unsigned P =
D.getBitWidth() - 1;
57 }
while (Q1.
ult(Delta) || (Q1 == Delta && R1.
isZero()));
75 bool AllowEvenDivisorOptimization) {
76 assert(!
D.isZero() && !
D.isOne() &&
"Precondition violation.");
77 assert(
D.getBitWidth() > 1 &&
"Does not work at smaller bitwidths.");
87 APInt NC = AllOnes - (AllOnes + 1 -
D).urem(
D);
88 assert(
NC.urem(
D) ==
D - 1 &&
"Unexpected NC value");
89 unsigned P =
D.getBitWidth() - 1;
97 if (R1.
uge(
NC - R1)) {
108 if ((
R2 + 1).uge(
D -
R2)) {
109 if (Q2.
uge(SignedMax))
119 if (Q2.
uge(SignedMin))
131 }
while (
P <
D.getBitWidth() * 2 &&
132 (Q1.
ult(Delta) || (Q1 == Delta && R1.
isZero())));
134 if (Retval.
IsAdd && !
D[0] && AllowEvenDivisorOptimization) {
135 unsigned PreShift =
D.countTrailingZeros();
This is an optimization pass for GlobalISel generic memory operations.
static void udivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient, APInt &Remainder)
Dual division/remainder interface.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
static UnsignedDivisionByConstantInfo get(const APInt &D, unsigned LeadingZeros=0, bool AllowEvenDivisorOptimization=true)
Calculate the magic numbers required to implement an unsigned integer division by a constant as a seq...
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
unsigned PreShift
pre-shift amount
unsigned ShiftAmount
shift amount
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static SignedDivisionByConstantInfo get(const APInt &D)
Calculate the magic numbers required to implement a signed integer division by a constant as a sequen...
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
void negate()
Negate this APInt in place.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned PostShift
post-shift amount
Class for arbitrary precision integers.
Magic data for optimising unsigned division by a constant.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Magic data for optimising signed division by a constant.