15#ifndef LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H
16#define LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H
const HexagonInstrInfo * TII
Representation of each machine instruction.
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< ScheduleDAGMutation > createVOPDPairingMutation()
bool checkVOPDRegConstraints(const SIInstrInfo &TII, const MachineInstr &FirstMI, const MachineInstr &SecondMI, bool IsVOPD3, bool AllowSameVGPR)
std::optional< VOPDMatchInfo > tryMatchVOPDPair(const SIInstrInfo &TII, MachineInstr &FirstMI, MachineInstr &SecondMI)
Check whether FirstMI and SecondMI can be combined into a VOPD instruction.
Describes a matched VOPD pair: which instruction is the X component and which is the Y component,...