LLVM 19.0.0git
MachineInstr.h
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1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template <typename T> class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template <typename T> class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60//===----------------------------------------------------------------------===//
61/// Representation of each machine instruction.
62///
63/// This class isn't a POD type, but it must have a trivial destructor. When a
64/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65/// without having their destructor called.
66///
68 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69 ilist_sentinel_tracking<true>> {
70public:
72
73 /// Flags to specify different kinds of comments to output in
74 /// assembly code. These flags carry semantic information not
75 /// otherwise easily derivable from the IR text.
76 ///
78 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
80 TAsmComments = 0x4 // Target Asm comments should start from this value.
81 };
82
83 enum MIFlag {
85 FrameSetup = 1 << 0, // Instruction is used as a part of
86 // function frame setup code.
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
88 // function frame destruction code.
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
92 // math nan values.
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
94 // math infinity values.
95 FmNsz = 1 << 6, // Instruction is not required to retain
96 // signed zero values.
97 FmArcp = 1 << 7, // Instruction supports Fast math
98 // reciprocal approximations.
99 FmContract = 1 << 8, // Instruction supports Fast math
100 // contraction operations like fma.
101 FmAfn = 1 << 9, // Instruction may map to Fast math
102 // intrinsic approximation.
103 FmReassoc = 1 << 10, // Instruction supports Fast math
104 // reassociation of operand order.
105 NoUWrap = 1 << 11, // Instruction supports binary operator
106 // no unsigned wrap.
107 NoSWrap = 1 << 12, // Instruction supports binary operator
108 // no signed wrap.
109 IsExact = 1 << 13, // Instruction supports division is
110 // known to be exact.
111 NoFPExcept = 1 << 14, // Instruction does not raise
112 // floatint-point exceptions.
113 NoMerge = 1 << 15, // Passes that drop source location info
114 // (e.g. branch folding) should skip
115 // this instruction.
116 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117 NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118 NonNeg = 1 << 18, // The operand is non-negative.
119 Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120 NoUSWrap = 1 << 20, // Instruction supports geps
121 // no unsigned signed wrap.
122 };
123
124private:
125 const MCInstrDesc *MCID; // Instruction descriptor.
126 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
127
128 // Operands are allocated by an ArrayRecycler.
129 MachineOperand *Operands = nullptr; // Pointer to the first operand.
130
131#define LLVM_MI_NUMOPERANDS_BITS 24
132#define LLVM_MI_FLAGS_BITS 24
133#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
134
135 /// Number of operands on instruction.
137
138 // OperandCapacity has uint8_t size, so it should be next to NumOperands
139 // to properly pack.
140 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
141 OperandCapacity CapOperands; // Capacity of the Operands array.
142
143 /// Various bits of additional information about the machine instruction.
145
146 /// Various bits of information used by the AsmPrinter to emit helpful
147 /// comments. This is *not* semantic information. Do not use this for
148 /// anything other than to convey comment information to AsmPrinter.
149 uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
150
151 /// Internal implementation detail class that provides out-of-line storage for
152 /// extra info used by the machine instruction when this info cannot be stored
153 /// in-line within the instruction itself.
154 ///
155 /// This has to be defined eagerly due to the implementation constraints of
156 /// `PointerSumType` where it is used.
157 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
158 MCSymbol *, MDNode *, uint32_t> {
159 public:
160 static ExtraInfo *create(BumpPtrAllocator &Allocator,
161 ArrayRef<MachineMemOperand *> MMOs,
162 MCSymbol *PreInstrSymbol = nullptr,
163 MCSymbol *PostInstrSymbol = nullptr,
164 MDNode *HeapAllocMarker = nullptr,
165 MDNode *PCSections = nullptr, uint32_t CFIType = 0,
166 MDNode *MMRAs = nullptr) {
167 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
168 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
169 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
170 bool HasMMRAs = MMRAs != nullptr;
171 bool HasCFIType = CFIType != 0;
172 bool HasPCSections = PCSections != nullptr;
173 auto *Result = new (Allocator.Allocate(
174 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
175 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
176 HasHeapAllocMarker + HasPCSections + HasMMRAs, HasCFIType),
177 alignof(ExtraInfo)))
178 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
179 HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
180
181 // Copy the actual data into the trailing objects.
182 std::copy(MMOs.begin(), MMOs.end(),
183 Result->getTrailingObjects<MachineMemOperand *>());
184
185 unsigned MDNodeIdx = 0;
186
187 if (HasPreInstrSymbol)
188 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
189 if (HasPostInstrSymbol)
190 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
191 PostInstrSymbol;
192 if (HasHeapAllocMarker)
193 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
194 if (HasPCSections)
195 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
196 if (HasCFIType)
197 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
198 if (HasMMRAs)
199 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
200
201 return Result;
202 }
203
204 ArrayRef<MachineMemOperand *> getMMOs() const {
205 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
206 }
207
208 MCSymbol *getPreInstrSymbol() const {
209 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
210 }
211
212 MCSymbol *getPostInstrSymbol() const {
213 return HasPostInstrSymbol
214 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
215 : nullptr;
216 }
217
218 MDNode *getHeapAllocMarker() const {
219 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
220 }
221
222 MDNode *getPCSections() const {
223 return HasPCSections
224 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
225 : nullptr;
226 }
227
228 uint32_t getCFIType() const {
229 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
230 }
231
232 MDNode *getMMRAMetadata() const {
233 return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
234 HasPCSections]
235 : nullptr;
236 }
237
238 private:
239 friend TrailingObjects;
240
241 // Description of the extra info, used to interpret the actual optional
242 // data appended.
243 //
244 // Note that this is not terribly space optimized. This leaves a great deal
245 // of flexibility to fit more in here later.
246 const int NumMMOs;
247 const bool HasPreInstrSymbol;
248 const bool HasPostInstrSymbol;
249 const bool HasHeapAllocMarker;
250 const bool HasPCSections;
251 const bool HasCFIType;
252 const bool HasMMRAs;
253
254 // Implement the `TrailingObjects` internal API.
255 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
256 return NumMMOs;
257 }
258 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
259 return HasPreInstrSymbol + HasPostInstrSymbol;
260 }
261 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
262 return HasHeapAllocMarker + HasPCSections;
263 }
264 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
265 return HasCFIType;
266 }
267
268 // Just a boring constructor to allow us to initialize the sizes. Always use
269 // the `create` routine above.
270 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
271 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
272 bool HasMMRAs)
273 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
274 HasPostInstrSymbol(HasPostInstrSymbol),
275 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
276 HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
277 };
278
279 /// Enumeration of the kinds of inline extra info available. It is important
280 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
281 /// it accessible as an `ArrayRef`.
282 enum ExtraInfoInlineKinds {
283 EIIK_MMO = 0,
284 EIIK_PreInstrSymbol,
285 EIIK_PostInstrSymbol,
286 EIIK_OutOfLine
287 };
288
289 // We store extra information about the instruction here. The common case is
290 // expected to be nothing or a single pointer (typically a MMO or a symbol).
291 // We work to optimize this common case by storing it inline here rather than
292 // requiring a separate allocation, but we fall back to an allocation when
293 // multiple pointers are needed.
294 PointerSumType<ExtraInfoInlineKinds,
295 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
296 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
297 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
298 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
299 Info;
300
301 DebugLoc DbgLoc; // Source line information.
302
303 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
304 /// defined by this instruction.
305 unsigned DebugInstrNum;
306
307 // Intrusive list support
308 friend struct ilist_traits<MachineInstr>;
310 void setParent(MachineBasicBlock *P) { Parent = P; }
311
312 /// This constructor creates a copy of the given
313 /// MachineInstr in the given MachineFunction.
315
316 /// This constructor create a MachineInstr and add the implicit operands.
317 /// It reserves space for number of operands specified by
318 /// MCInstrDesc. An explicit DebugLoc is supplied.
320 bool NoImp = false);
321
322 // MachineInstrs are pool-allocated and owned by MachineFunction.
323 friend class MachineFunction;
324
325 void
326 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
327 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
328
329 static bool opIsRegDef(const MachineOperand &Op) {
330 return Op.isReg() && Op.isDef();
331 }
332
333 static bool opIsRegUse(const MachineOperand &Op) {
334 return Op.isReg() && Op.isUse();
335 }
336
337public:
338 MachineInstr(const MachineInstr &) = delete;
340 // Use MachineFunction::DeleteMachineInstr() instead.
341 ~MachineInstr() = delete;
342
343 const MachineBasicBlock* getParent() const { return Parent; }
344 MachineBasicBlock* getParent() { return Parent; }
345
346 /// Move the instruction before \p MovePos.
347 void moveBefore(MachineInstr *MovePos);
348
349 /// Return the function that contains the basic block that this instruction
350 /// belongs to.
351 ///
352 /// Note: this is undefined behaviour if the instruction does not have a
353 /// parent.
354 const MachineFunction *getMF() const;
356 return const_cast<MachineFunction *>(
357 static_cast<const MachineInstr *>(this)->getMF());
358 }
359
360 /// Return the asm printer flags bitvector.
361 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
362
363 /// Clear the AsmPrinter bitvector.
364 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
365
366 /// Return whether an AsmPrinter flag is set.
368 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
369 "Flag is out of range for the AsmPrinterFlags field");
370 return AsmPrinterFlags & Flag;
371 }
372
373 /// Set a flag for the AsmPrinter.
374 void setAsmPrinterFlag(uint8_t Flag) {
375 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
376 "Flag is out of range for the AsmPrinterFlags field");
377 AsmPrinterFlags |= Flag;
378 }
379
380 /// Clear specific AsmPrinter flags.
382 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
383 "Flag is out of range for the AsmPrinterFlags field");
384 AsmPrinterFlags &= ~Flag;
385 }
386
387 /// Return the MI flags bitvector.
389 return Flags;
390 }
391
392 /// Return whether an MI flag is set.
393 bool getFlag(MIFlag Flag) const {
394 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
395 "Flag is out of range for the Flags field");
396 return Flags & Flag;
397 }
398
399 /// Set a MI flag.
400 void setFlag(MIFlag Flag) {
401 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
402 "Flag is out of range for the Flags field");
403 Flags |= (uint32_t)Flag;
404 }
405
406 void setFlags(unsigned flags) {
407 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
408 "flags to be set are out of range for the Flags field");
409 // Filter out the automatically maintained flags.
410 unsigned Mask = BundledPred | BundledSucc;
411 Flags = (Flags & Mask) | (flags & ~Mask);
412 }
413
414 /// clearFlag - Clear a MI flag.
415 void clearFlag(MIFlag Flag) {
416 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
417 "Flag to clear is out of range for the Flags field");
418 Flags &= ~((uint32_t)Flag);
419 }
420
421 void clearFlags(unsigned flags) {
422 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
423 "flags to be cleared are out of range for the Flags field");
424 Flags &= ~flags;
425 }
426
427 /// Return true if MI is in a bundle (but not the first MI in a bundle).
428 ///
429 /// A bundle looks like this before it's finalized:
430 /// ----------------
431 /// | MI |
432 /// ----------------
433 /// |
434 /// ----------------
435 /// | MI * |
436 /// ----------------
437 /// |
438 /// ----------------
439 /// | MI * |
440 /// ----------------
441 /// In this case, the first MI starts a bundle but is not inside a bundle, the
442 /// next 2 MIs are considered "inside" the bundle.
443 ///
444 /// After a bundle is finalized, it looks like this:
445 /// ----------------
446 /// | Bundle |
447 /// ----------------
448 /// |
449 /// ----------------
450 /// | MI * |
451 /// ----------------
452 /// |
453 /// ----------------
454 /// | MI * |
455 /// ----------------
456 /// |
457 /// ----------------
458 /// | MI * |
459 /// ----------------
460 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
461 /// a bundle, but the next three MIs are.
462 bool isInsideBundle() const {
463 return getFlag(BundledPred);
464 }
465
466 /// Return true if this instruction part of a bundle. This is true
467 /// if either itself or its following instruction is marked "InsideBundle".
468 bool isBundled() const {
470 }
471
472 /// Return true if this instruction is part of a bundle, and it is not the
473 /// first instruction in the bundle.
474 bool isBundledWithPred() const { return getFlag(BundledPred); }
475
476 /// Return true if this instruction is part of a bundle, and it is not the
477 /// last instruction in the bundle.
478 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
479
480 /// Bundle this instruction with its predecessor. This can be an unbundled
481 /// instruction, or it can be the first instruction in a bundle.
482 void bundleWithPred();
483
484 /// Bundle this instruction with its successor. This can be an unbundled
485 /// instruction, or it can be the last instruction in a bundle.
486 void bundleWithSucc();
487
488 /// Break bundle above this instruction.
489 void unbundleFromPred();
490
491 /// Break bundle below this instruction.
492 void unbundleFromSucc();
493
494 /// Returns the debug location id of this MachineInstr.
495 const DebugLoc &getDebugLoc() const { return DbgLoc; }
496
497 /// Return the operand containing the offset to be used if this DBG_VALUE
498 /// instruction is indirect; will be an invalid register if this value is
499 /// not indirect, and an immediate with value 0 otherwise.
501 assert(isNonListDebugValue() && "not a DBG_VALUE");
502 return getOperand(1);
503 }
505 assert(isNonListDebugValue() && "not a DBG_VALUE");
506 return getOperand(1);
507 }
508
509 /// Return the operand for the debug variable referenced by
510 /// this DBG_VALUE instruction.
511 const MachineOperand &getDebugVariableOp() const;
513
514 /// Return the debug variable referenced by
515 /// this DBG_VALUE instruction.
516 const DILocalVariable *getDebugVariable() const;
517
518 /// Return the operand for the complex address expression referenced by
519 /// this DBG_VALUE instruction.
522
523 /// Return the complex address expression referenced by
524 /// this DBG_VALUE instruction.
525 const DIExpression *getDebugExpression() const;
526
527 /// Return the debug label referenced by
528 /// this DBG_LABEL instruction.
529 const DILabel *getDebugLabel() const;
530
531 /// Fetch the instruction number of this MachineInstr. If it does not have
532 /// one already, a new and unique number will be assigned.
533 unsigned getDebugInstrNum();
534
535 /// Fetch instruction number of this MachineInstr -- but before it's inserted
536 /// into \p MF. Needed for transformations that create an instruction but
537 /// don't immediately insert them.
538 unsigned getDebugInstrNum(MachineFunction &MF);
539
540 /// Examine the instruction number of this MachineInstr. May be zero if
541 /// it hasn't been assigned a number yet.
542 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
543
544 /// Set instruction number of this MachineInstr. Avoid using unless you're
545 /// deserializing this information.
546 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
547
548 /// Drop any variable location debugging information associated with this
549 /// instruction. Use when an instruction is modified in such a way that it no
550 /// longer defines the value it used to. Variable locations using that value
551 /// will be dropped.
552 void dropDebugNumber() { DebugInstrNum = 0; }
553
554 /// Emit an error referring to the source location of this instruction.
555 /// This should only be used for inline assembly that is somehow
556 /// impossible to compile. Other errors should have been handled much
557 /// earlier.
558 ///
559 /// If this method returns, the caller should try to recover from the error.
560 void emitError(StringRef Msg) const;
561
562 /// Returns the target instruction descriptor of this MachineInstr.
563 const MCInstrDesc &getDesc() const { return *MCID; }
564
565 /// Returns the opcode of this MachineInstr.
566 unsigned getOpcode() const { return MCID->Opcode; }
567
568 /// Retuns the total number of operands.
569 unsigned getNumOperands() const { return NumOperands; }
570
571 /// Returns the total number of operands which are debug locations.
572 unsigned getNumDebugOperands() const {
573 return std::distance(debug_operands().begin(), debug_operands().end());
574 }
575
576 const MachineOperand& getOperand(unsigned i) const {
577 assert(i < getNumOperands() && "getOperand() out of range!");
578 return Operands[i];
579 }
581 assert(i < getNumOperands() && "getOperand() out of range!");
582 return Operands[i];
583 }
584
586 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
587 return *(debug_operands().begin() + Index);
588 }
589 const MachineOperand &getDebugOperand(unsigned Index) const {
590 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
591 return *(debug_operands().begin() + Index);
592 }
593
594 /// Returns whether this debug value has at least one debug operand with the
595 /// register \p Reg.
597 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
598 return Op.isReg() && Op.getReg() == Reg;
599 });
600 }
601
602 /// Returns a range of all of the operands that correspond to a debug use of
603 /// \p Reg.
604 template <typename Operand, typename Instruction>
605 static iterator_range<
606 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
608 std::function<bool(Operand & Op)> OpUsesReg(
609 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
610 return make_filter_range(MI->debug_operands(), OpUsesReg);
611 }
613 std::function<bool(const MachineOperand &Op)>>>
616 const MachineInstr>(this, Reg);
617 }
619 std::function<bool(MachineOperand &Op)>>>
621 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
622 this, Reg);
623 }
624
625 bool isDebugOperand(const MachineOperand *Op) const {
626 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
627 }
628
629 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
630 assert(isDebugOperand(Op) && "Expected a debug operand.");
631 return std::distance(adl_begin(debug_operands()), Op);
632 }
633
634 /// Returns the total number of definitions.
635 unsigned getNumDefs() const {
636 return getNumExplicitDefs() + MCID->implicit_defs().size();
637 }
638
639 /// Returns true if the instruction has implicit definition.
640 bool hasImplicitDef() const {
641 for (const MachineOperand &MO : implicit_operands())
642 if (MO.isDef() && MO.isImplicit())
643 return true;
644 return false;
645 }
646
647 /// Returns the implicit operands number.
648 unsigned getNumImplicitOperands() const {
650 }
651
652 /// Return true if operand \p OpIdx is a subregister index.
653 bool isOperandSubregIdx(unsigned OpIdx) const {
654 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
655 if (isExtractSubreg() && OpIdx == 2)
656 return true;
657 if (isInsertSubreg() && OpIdx == 3)
658 return true;
659 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
660 return true;
661 if (isSubregToReg() && OpIdx == 3)
662 return true;
663 return false;
664 }
665
666 /// Returns the number of non-implicit operands.
667 unsigned getNumExplicitOperands() const;
668
669 /// Returns the number of non-implicit definitions.
670 unsigned getNumExplicitDefs() const;
671
672 /// iterator/begin/end - Iterate over all operands of a machine instruction.
675
677 mop_iterator operands_end() { return Operands + NumOperands; }
678
680 const_mop_iterator operands_end() const { return Operands + NumOperands; }
681
684 }
687 }
689 return make_range(operands_begin(),
691 }
693 return make_range(operands_begin(),
695 }
697 return make_range(explicit_operands().end(), operands_end());
698 }
700 return make_range(explicit_operands().end(), operands_end());
701 }
702 /// Returns a range over all operands that are used to determine the variable
703 /// location for this DBG_VALUE instruction.
705 assert((isDebugValueLike()) && "Must be a debug value instruction.");
706 return isNonListDebugValue()
709 }
710 /// \copydoc debug_operands()
712 assert((isDebugValueLike()) && "Must be a debug value instruction.");
713 return isNonListDebugValue()
716 }
717 /// Returns a range over all explicit operands that are register definitions.
718 /// Implicit definition are not included!
720 return make_range(operands_begin(),
722 }
723 /// \copydoc defs()
725 return make_range(operands_begin(),
727 }
728 /// Returns a range that includes all operands that are register uses.
729 /// This may include unrelated operands which are not register uses.
732 }
733 /// \copydoc uses()
736 }
740 }
744 }
745
750
751 /// Returns an iterator range over all operands that are (explicit or
752 /// implicit) register defs.
754 return make_filter_range(operands(), opIsRegDef);
755 }
756 /// \copydoc all_defs()
758 return make_filter_range(operands(), opIsRegDef);
759 }
760
761 /// Returns an iterator range over all operands that are (explicit or
762 /// implicit) register uses.
764 return make_filter_range(uses(), opIsRegUse);
765 }
766 /// \copydoc all_uses()
768 return make_filter_range(uses(), opIsRegUse);
769 }
770
771 /// Returns the number of the operand iterator \p I points to.
773 return I - operands_begin();
774 }
775
776 /// Access to memory operands of the instruction. If there are none, that does
777 /// not imply anything about whether the function accesses memory. Instead,
778 /// the caller must behave conservatively.
780 if (!Info)
781 return {};
782
783 if (Info.is<EIIK_MMO>())
784 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
785
786 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
787 return EI->getMMOs();
788
789 return {};
790 }
791
792 /// Access to memory operands of the instruction.
793 ///
794 /// If `memoperands_begin() == memoperands_end()`, that does not imply
795 /// anything about whether the function accesses memory. Instead, the caller
796 /// must behave conservatively.
797 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
798
799 /// Access to memory operands of the instruction.
800 ///
801 /// If `memoperands_begin() == memoperands_end()`, that does not imply
802 /// anything about whether the function accesses memory. Instead, the caller
803 /// must behave conservatively.
804 mmo_iterator memoperands_end() const { return memoperands().end(); }
805
806 /// Return true if we don't have any memory operands which described the
807 /// memory access done by this instruction. If this is true, calling code
808 /// must be conservative.
809 bool memoperands_empty() const { return memoperands().empty(); }
810
811 /// Return true if this instruction has exactly one MachineMemOperand.
812 bool hasOneMemOperand() const { return memoperands().size() == 1; }
813
814 /// Return the number of memory operands.
815 unsigned getNumMemOperands() const { return memoperands().size(); }
816
817 /// Helper to extract a pre-instruction symbol if one has been added.
819 if (!Info)
820 return nullptr;
821 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
822 return S;
823 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
824 return EI->getPreInstrSymbol();
825
826 return nullptr;
827 }
828
829 /// Helper to extract a post-instruction symbol if one has been added.
831 if (!Info)
832 return nullptr;
833 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
834 return S;
835 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
836 return EI->getPostInstrSymbol();
837
838 return nullptr;
839 }
840
841 /// Helper to extract a heap alloc marker if one has been added.
843 if (!Info)
844 return nullptr;
845 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
846 return EI->getHeapAllocMarker();
847
848 return nullptr;
849 }
850
851 /// Helper to extract PCSections metadata target sections.
853 if (!Info)
854 return nullptr;
855 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
856 return EI->getPCSections();
857
858 return nullptr;
859 }
860
861 /// Helper to extract mmra.op metadata.
863 if (!Info)
864 return nullptr;
865 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
866 return EI->getMMRAMetadata();
867 return nullptr;
868 }
869
870 /// Helper to extract a CFI type hash if one has been added.
872 if (!Info)
873 return 0;
874 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
875 return EI->getCFIType();
876
877 return 0;
878 }
879
880 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
881 /// queries but they are bundle aware.
882
884 IgnoreBundle, // Ignore bundles
885 AnyInBundle, // Return true if any instruction in bundle has property
886 AllInBundle // Return true if all instructions in bundle have property
887 };
888
889 /// Return true if the instruction (or in the case of a bundle,
890 /// the instructions inside the bundle) has the specified property.
891 /// The first argument is the property being queried.
892 /// The second argument indicates whether the query should look inside
893 /// instruction bundles.
894 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
895 assert(MCFlag < 64 &&
896 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
897 // Inline the fast path for unbundled or bundle-internal instructions.
899 return getDesc().getFlags() & (1ULL << MCFlag);
900
901 // If this is the first instruction in a bundle, take the slow path.
902 return hasPropertyInBundle(1ULL << MCFlag, Type);
903 }
904
905 /// Return true if this is an instruction that should go through the usual
906 /// legalization steps.
909 }
910
911 /// Return true if this instruction can have a variable number of operands.
912 /// In this case, the variable operands will be after the normal
913 /// operands but before the implicit definitions and uses (if any are
914 /// present).
917 }
918
919 /// Set if this instruction has an optional definition, e.g.
920 /// ARM instructions which can set condition code if 's' bit is set.
923 }
924
925 /// Return true if this is a pseudo instruction that doesn't
926 /// correspond to a real machine instruction.
929 }
930
931 /// Return true if this instruction doesn't produce any output in the form of
932 /// executable instructions.
934 return hasProperty(MCID::Meta, Type);
935 }
936
939 }
940
941 /// Return true if this is an instruction that marks the end of an EH scope,
942 /// i.e., a catchpad or a cleanuppad instruction.
945 }
946
948 return hasProperty(MCID::Call, Type);
949 }
950
951 /// Return true if this is a call instruction that may have an associated
952 /// call site entry in the debug info.
954 /// Return true if copying, moving, or erasing this instruction requires
955 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
956 /// \ref eraseCallSiteInfo).
957 bool shouldUpdateCallSiteInfo() const;
958
959 /// Returns true if the specified instruction stops control flow
960 /// from executing the instruction immediately following it. Examples include
961 /// unconditional branches and return instructions.
964 }
965
966 /// Returns true if this instruction part of the terminator for a basic block.
967 /// Typically this is things like return and branch instructions.
968 ///
969 /// Various passes use this to insert code into the bottom of a basic block,
970 /// but before control flow occurs.
973 }
974
975 /// Returns true if this is a conditional, unconditional, or indirect branch.
976 /// Predicates below can be used to discriminate between
977 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
978 /// get more information.
981 }
982
983 /// Return true if this is an indirect branch, such as a
984 /// branch through a register.
987 }
988
989 /// Return true if this is a branch which may fall
990 /// through to the next instruction or may transfer control flow to some other
991 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
992 /// information about this branch.
995 }
996
997 /// Return true if this is a branch which always
998 /// transfers control flow to some other block. The
999 /// TargetInstrInfo::analyzeBranch method can be used to get more information
1000 /// about this branch.
1003 }
1004
1005 /// Return true if this instruction has a predicate operand that
1006 /// controls execution. It may be set to 'always', or may be set to other
1007 /// values. There are various methods in TargetInstrInfo that can be used to
1008 /// control and modify the predicate in this instruction.
1010 // If it's a bundle than all bundled instructions must be predicable for this
1011 // to return true.
1013 }
1014
1015 /// Return true if this instruction is a comparison.
1018 }
1019
1020 /// Return true if this instruction is a move immediate
1021 /// (including conditional moves) instruction.
1024 }
1025
1026 /// Return true if this instruction is a register move.
1027 /// (including moving values from subreg to reg)
1030 }
1031
1032 /// Return true if this instruction is a bitcast instruction.
1035 }
1036
1037 /// Return true if this instruction is a select instruction.
1039 return hasProperty(MCID::Select, Type);
1040 }
1041
1042 /// Return true if this instruction cannot be safely duplicated.
1043 /// For example, if the instruction has a unique labels attached
1044 /// to it, duplicating it would cause multiple definition errors.
1047 return true;
1049 }
1050
1051 /// Return true if this instruction is convergent.
1052 /// Convergent instructions can not be made control-dependent on any
1053 /// additional values.
1055 if (isInlineAsm()) {
1056 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1057 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1058 return true;
1059 }
1060 if (getFlag(NoConvergent))
1061 return false;
1063 }
1064
1065 /// Returns true if the specified instruction has a delay slot
1066 /// which must be filled by the code generator.
1069 }
1070
1071 /// Return true for instructions that can be folded as
1072 /// memory operands in other instructions. The most common use for this
1073 /// is instructions that are simple loads from memory that don't modify
1074 /// the loaded value in any way, but it can also be used for instructions
1075 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1076 /// on x86, to allow them to be folded when it is beneficial.
1077 /// This should only be set on instructions that return a value in their
1078 /// only virtual register definition.
1081 }
1082
1083 /// Return true if this instruction behaves
1084 /// the same way as the generic REG_SEQUENCE instructions.
1085 /// E.g., on ARM,
1086 /// dX VMOVDRR rY, rZ
1087 /// is equivalent to
1088 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1089 ///
1090 /// Note that for the optimizers to be able to take advantage of
1091 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1092 /// override accordingly.
1095 }
1096
1097 /// Return true if this instruction behaves
1098 /// the same way as the generic EXTRACT_SUBREG instructions.
1099 /// E.g., on ARM,
1100 /// rX, rY VMOVRRD dZ
1101 /// is equivalent to two EXTRACT_SUBREG:
1102 /// rX = EXTRACT_SUBREG dZ, ssub_0
1103 /// rY = EXTRACT_SUBREG dZ, ssub_1
1104 ///
1105 /// Note that for the optimizers to be able to take advantage of
1106 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1107 /// override accordingly.
1110 }
1111
1112 /// Return true if this instruction behaves
1113 /// the same way as the generic INSERT_SUBREG instructions.
1114 /// E.g., on ARM,
1115 /// dX = VSETLNi32 dY, rZ, Imm
1116 /// is equivalent to a INSERT_SUBREG:
1117 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1118 ///
1119 /// Note that for the optimizers to be able to take advantage of
1120 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1121 /// override accordingly.
1124 }
1125
1126 //===--------------------------------------------------------------------===//
1127 // Side Effect Analysis
1128 //===--------------------------------------------------------------------===//
1129
1130 /// Return true if this instruction could possibly read memory.
1131 /// Instructions with this flag set are not necessarily simple load
1132 /// instructions, they may load a value and modify it, for example.
1134 if (isInlineAsm()) {
1135 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1136 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1137 return true;
1138 }
1140 }
1141
1142 /// Return true if this instruction could possibly modify memory.
1143 /// Instructions with this flag set are not necessarily simple store
1144 /// instructions, they may store a modified value based on their operands, or
1145 /// may not actually modify anything, for example.
1147 if (isInlineAsm()) {
1148 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1149 if (ExtraInfo & InlineAsm::Extra_MayStore)
1150 return true;
1151 }
1153 }
1154
1155 /// Return true if this instruction could possibly read or modify memory.
1157 return mayLoad(Type) || mayStore(Type);
1158 }
1159
1160 /// Return true if this instruction could possibly raise a floating-point
1161 /// exception. This is the case if the instruction is a floating-point
1162 /// instruction that can in principle raise an exception, as indicated
1163 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1164 /// the instruction is used in a context where we expect floating-point
1165 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1166 bool mayRaiseFPException() const {
1169 }
1170
1171 //===--------------------------------------------------------------------===//
1172 // Flags that indicate whether an instruction can be modified by a method.
1173 //===--------------------------------------------------------------------===//
1174
1175 /// Return true if this may be a 2- or 3-address
1176 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1177 /// result if Y and Z are exchanged. If this flag is set, then the
1178 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1179 /// instruction.
1180 ///
1181 /// Note that this flag may be set on instructions that are only commutable
1182 /// sometimes. In these cases, the call to commuteInstruction will fail.
1183 /// Also note that some instructions require non-trivial modification to
1184 /// commute them.
1187 }
1188
1189 /// Return true if this is a 2-address instruction
1190 /// which can be changed into a 3-address instruction if needed. Doing this
1191 /// transformation can be profitable in the register allocator, because it
1192 /// means that the instruction can use a 2-address form if possible, but
1193 /// degrade into a less efficient form if the source and dest register cannot
1194 /// be assigned to the same register. For example, this allows the x86
1195 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1196 /// is the same speed as the shift but has bigger code size.
1197 ///
1198 /// If this returns true, then the target must implement the
1199 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1200 /// is allowed to fail if the transformation isn't valid for this specific
1201 /// instruction (e.g. shl reg, 4 on x86).
1202 ///
1205 }
1206
1207 /// Return true if this instruction requires
1208 /// custom insertion support when the DAG scheduler is inserting it into a
1209 /// machine basic block. If this is true for the instruction, it basically
1210 /// means that it is a pseudo instruction used at SelectionDAG time that is
1211 /// expanded out into magic code by the target when MachineInstrs are formed.
1212 ///
1213 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1214 /// is used to insert this into the MachineBasicBlock.
1217 }
1218
1219 /// Return true if this instruction requires *adjustment*
1220 /// after instruction selection by calling a target hook. For example, this
1221 /// can be used to fill in ARM 's' optional operand depending on whether
1222 /// the conditional flag register is used.
1225 }
1226
1227 /// Returns true if this instruction is a candidate for remat.
1228 /// This flag is deprecated, please don't use it anymore. If this
1229 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1230 /// verify the instruction is really rematerializable.
1232 // It's only possible to re-mat a bundle if all bundled instructions are
1233 // re-materializable.
1235 }
1236
1237 /// Returns true if this instruction has the same cost (or less) than a move
1238 /// instruction. This is useful during certain types of optimizations
1239 /// (e.g., remat during two-address conversion or machine licm)
1240 /// where we would like to remat or hoist the instruction, but not if it costs
1241 /// more than moving the instruction into the appropriate register. Note, we
1242 /// are not marking copies from and to the same register class with this flag.
1244 // Only returns true for a bundle if all bundled instructions are cheap.
1246 }
1247
1248 /// Returns true if this instruction source operands
1249 /// have special register allocation requirements that are not captured by the
1250 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1251 /// even / odd pair, ARM::STM registers have to be in ascending order.
1252 /// Post-register allocation passes should not attempt to change allocations
1253 /// for sources of instructions with this flag.
1256 }
1257
1258 /// Returns true if this instruction def operands
1259 /// have special register allocation requirements that are not captured by the
1260 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1261 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1262 /// Post-register allocation passes should not attempt to change allocations
1263 /// for definitions of instructions with this flag.
1266 }
1267
1269 CheckDefs, // Check all operands for equality
1270 CheckKillDead, // Check all operands including kill / dead markers
1271 IgnoreDefs, // Ignore all definitions
1272 IgnoreVRegDefs // Ignore virtual register definitions
1274
1275 /// Return true if this instruction is identical to \p Other.
1276 /// Two instructions are identical if they have the same opcode and all their
1277 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1278 /// Note that this means liveness related flags (dead, undef, kill) do not
1279 /// affect the notion of identical.
1280 bool isIdenticalTo(const MachineInstr &Other,
1281 MICheckType Check = CheckDefs) const;
1282
1283 /// Returns true if this instruction is a debug instruction that represents an
1284 /// identical debug value to \p Other.
1285 /// This function considers these debug instructions equivalent if they have
1286 /// identical variables, debug locations, and debug operands, and if the
1287 /// DIExpressions combined with the directness flags are equivalent.
1288 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1289
1290 /// Unlink 'this' from the containing basic block, and return it without
1291 /// deleting it.
1292 ///
1293 /// This function can not be used on bundled instructions, use
1294 /// removeFromBundle() to remove individual instructions from a bundle.
1296
1297 /// Unlink this instruction from its basic block and return it without
1298 /// deleting it.
1299 ///
1300 /// If the instruction is part of a bundle, the other instructions in the
1301 /// bundle remain bundled.
1303
1304 /// Unlink 'this' from the containing basic block and delete it.
1305 ///
1306 /// If this instruction is the header of a bundle, the whole bundle is erased.
1307 /// This function can not be used for instructions inside a bundle, use
1308 /// eraseFromBundle() to erase individual bundled instructions.
1309 void eraseFromParent();
1310
1311 /// Unlink 'this' from its basic block and delete it.
1312 ///
1313 /// If the instruction is part of a bundle, the other instructions in the
1314 /// bundle remain bundled.
1315 void eraseFromBundle();
1316
1317 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1318 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1319 bool isAnnotationLabel() const {
1320 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1321 }
1322
1323 /// Returns true if the MachineInstr represents a label.
1324 bool isLabel() const {
1325 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1326 }
1327
1328 bool isCFIInstruction() const {
1329 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1330 }
1331
1332 bool isPseudoProbe() const {
1333 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1334 }
1335
1336 // True if the instruction represents a position in the function.
1337 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1338
1339 bool isNonListDebugValue() const {
1340 return getOpcode() == TargetOpcode::DBG_VALUE;
1341 }
1342 bool isDebugValueList() const {
1343 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1344 }
1345 bool isDebugValue() const {
1347 }
1348 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1349 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1350 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1351 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1352 bool isDebugInstr() const {
1353 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1354 }
1356 return isDebugInstr() || isPseudoProbe();
1357 }
1358
1359 bool isDebugOffsetImm() const {
1361 }
1362
1363 /// A DBG_VALUE is indirect iff the location operand is a register and
1364 /// the offset operand is an immediate.
1366 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1367 }
1368
1369 /// A DBG_VALUE is an entry value iff its debug expression contains the
1370 /// DW_OP_LLVM_entry_value operation.
1371 bool isDebugEntryValue() const;
1372
1373 /// Return true if the instruction is a debug value which describes a part of
1374 /// a variable as unavailable.
1375 bool isUndefDebugValue() const {
1376 if (!isDebugValue())
1377 return false;
1378 // If any $noreg locations are given, this DV is undef.
1379 for (const MachineOperand &Op : debug_operands())
1380 if (Op.isReg() && !Op.getReg().isValid())
1381 return true;
1382 return false;
1383 }
1384
1386 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1387 }
1388
1389 bool isPHI() const {
1390 return getOpcode() == TargetOpcode::PHI ||
1391 getOpcode() == TargetOpcode::G_PHI;
1392 }
1393 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1394 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1395 bool isInlineAsm() const {
1396 return getOpcode() == TargetOpcode::INLINEASM ||
1397 getOpcode() == TargetOpcode::INLINEASM_BR;
1398 }
1399 /// Returns true if the register operand can be folded with a load or store
1400 /// into a frame index. Does so by checking the InlineAsm::Flag immediate
1401 /// operand at OpId - 1.
1402 bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1403
1404 bool isStackAligningInlineAsm() const;
1406
1407 bool isInsertSubreg() const {
1408 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1409 }
1410
1411 bool isSubregToReg() const {
1412 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1413 }
1414
1415 bool isRegSequence() const {
1416 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1417 }
1418
1419 bool isBundle() const {
1420 return getOpcode() == TargetOpcode::BUNDLE;
1421 }
1422
1423 bool isCopy() const {
1424 return getOpcode() == TargetOpcode::COPY;
1425 }
1426
1427 bool isFullCopy() const {
1428 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1429 }
1430
1431 bool isExtractSubreg() const {
1432 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1433 }
1434
1435 /// Return true if the instruction behaves like a copy.
1436 /// This does not include native copy instructions.
1437 bool isCopyLike() const {
1438 return isCopy() || isSubregToReg();
1439 }
1440
1441 /// Return true is the instruction is an identity copy.
1442 bool isIdentityCopy() const {
1443 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1445 }
1446
1447 /// Return true if this is a transient instruction that is either very likely
1448 /// to be eliminated during register allocation (such as copy-like
1449 /// instructions), or if this instruction doesn't have an execution-time cost.
1450 bool isTransient() const {
1451 switch (getOpcode()) {
1452 default:
1453 return isMetaInstruction();
1454 // Copy-like instructions are usually eliminated during register allocation.
1455 case TargetOpcode::PHI:
1456 case TargetOpcode::G_PHI:
1457 case TargetOpcode::COPY:
1458 case TargetOpcode::INSERT_SUBREG:
1459 case TargetOpcode::SUBREG_TO_REG:
1460 case TargetOpcode::REG_SEQUENCE:
1461 return true;
1462 }
1463 }
1464
1465 /// Return the number of instructions inside the MI bundle, excluding the
1466 /// bundle header.
1467 ///
1468 /// This is the number of instructions that MachineBasicBlock::iterator
1469 /// skips, 0 for unbundled instructions.
1470 unsigned getBundleSize() const;
1471
1472 /// Return true if the MachineInstr reads the specified register.
1473 /// If TargetRegisterInfo is non-null, then it also checks if there
1474 /// is a read of a super-register.
1475 /// This does not count partial redefines of virtual registers as reads:
1476 /// %reg1024:6 = OP.
1478 return findRegisterUseOperandIdx(Reg, TRI, false) != -1;
1479 }
1480
1481 /// Return true if the MachineInstr reads the specified virtual register.
1482 /// Take into account that a partial define is a
1483 /// read-modify-write operation.
1485 return readsWritesVirtualRegister(Reg).first;
1486 }
1487
1488 /// Return a pair of bools (reads, writes) indicating if this instruction
1489 /// reads or writes Reg. This also considers partial defines.
1490 /// If Ops is not null, all operand indices for Reg are added.
1491 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1492 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1493
1494 /// Return true if the MachineInstr kills the specified register.
1495 /// If TargetRegisterInfo is non-null, then it also checks if there is
1496 /// a kill of a super-register.
1498 return findRegisterUseOperandIdx(Reg, TRI, true) != -1;
1499 }
1500
1501 /// Return true if the MachineInstr fully defines the specified register.
1502 /// If TargetRegisterInfo is non-null, then it also checks
1503 /// if there is a def of a super-register.
1504 /// NOTE: It's ignoring subreg indices on virtual registers.
1506 return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
1507 }
1508
1509 /// Return true if the MachineInstr modifies (fully define or partially
1510 /// define) the specified register.
1511 /// NOTE: It's ignoring subreg indices on virtual registers.
1513 return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
1514 }
1515
1516 /// Returns true if the register is dead in this machine instruction.
1517 /// If TargetRegisterInfo is non-null, then it also checks
1518 /// if there is a dead def of a super-register.
1520 return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
1521 }
1522
1523 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1524 /// the given register (not considering sub/super-registers).
1526
1527 /// Returns the operand index that is a use of the specific register or -1
1528 /// if it is not found. It further tightens the search criteria to a use
1529 /// that kills the register if isKill is true.
1531 bool isKill = false) const;
1532
1533 /// Wrapper for findRegisterUseOperandIdx, it returns
1534 /// a pointer to the MachineOperand rather than an index.
1536 const TargetRegisterInfo *TRI,
1537 bool isKill = false) {
1539 return (Idx == -1) ? nullptr : &getOperand(Idx);
1540 }
1541
1543 const TargetRegisterInfo *TRI,
1544 bool isKill = false) const {
1545 return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1546 isKill);
1547 }
1548
1549 /// Returns the operand index that is a def of the specified register or
1550 /// -1 if it is not found. If isDead is true, defs that are not dead are
1551 /// skipped. If Overlap is true, then it also looks for defs that merely
1552 /// overlap the specified register. If TargetRegisterInfo is non-null,
1553 /// then it also checks if there is a def of a super-register.
1554 /// This may also return a register mask operand when Overlap is true.
1556 bool isDead = false,
1557 bool Overlap = false) const;
1558
1559 /// Wrapper for findRegisterDefOperandIdx, it returns
1560 /// a pointer to the MachineOperand rather than an index.
1562 const TargetRegisterInfo *TRI,
1563 bool isDead = false,
1564 bool Overlap = false) {
1565 int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1566 return (Idx == -1) ? nullptr : &getOperand(Idx);
1567 }
1568
1570 const TargetRegisterInfo *TRI,
1571 bool isDead = false,
1572 bool Overlap = false) const {
1573 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1574 Reg, TRI, isDead, Overlap);
1575 }
1576
1577 /// Find the index of the first operand in the
1578 /// operand list that is used to represent the predicate. It returns -1 if
1579 /// none is found.
1580 int findFirstPredOperandIdx() const;
1581
1582 /// Find the index of the flag word operand that
1583 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1584 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1585 ///
1586 /// If GroupNo is not NULL, it will receive the number of the operand group
1587 /// containing OpIdx.
1588 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1589
1590 /// Compute the static register class constraint for operand OpIdx.
1591 /// For normal instructions, this is derived from the MCInstrDesc.
1592 /// For inline assembly it is derived from the flag words.
1593 ///
1594 /// Returns NULL if the static register class constraint cannot be
1595 /// determined.
1596 const TargetRegisterClass*
1597 getRegClassConstraint(unsigned OpIdx,
1598 const TargetInstrInfo *TII,
1599 const TargetRegisterInfo *TRI) const;
1600
1601 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1602 /// the given \p CurRC.
1603 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1604 /// instructions inside the bundle will be taken into account. In other words,
1605 /// this method accumulates all the constraints of the operand of this MI and
1606 /// the related bundle if MI is a bundle or inside a bundle.
1607 ///
1608 /// Returns the register class that satisfies both \p CurRC and the
1609 /// constraints set by MI. Returns NULL if such a register class does not
1610 /// exist.
1611 ///
1612 /// \pre CurRC must not be NULL.
1614 Register Reg, const TargetRegisterClass *CurRC,
1616 bool ExploreBundle = false) const;
1617
1618 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1619 /// to the given \p CurRC.
1620 ///
1621 /// Returns the register class that satisfies both \p CurRC and the
1622 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1623 /// does not exist.
1624 ///
1625 /// \pre CurRC must not be NULL.
1626 /// \pre The operand at \p OpIdx must be a register.
1627 const TargetRegisterClass *
1628 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1629 const TargetInstrInfo *TII,
1630 const TargetRegisterInfo *TRI) const;
1631
1632 /// Add a tie between the register operands at DefIdx and UseIdx.
1633 /// The tie will cause the register allocator to ensure that the two
1634 /// operands are assigned the same physical register.
1635 ///
1636 /// Tied operands are managed automatically for explicit operands in the
1637 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1638 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1639
1640 /// Given the index of a tied register operand, find the
1641 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1642 /// index of the tied operand which must exist.
1643 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1644
1645 /// Given the index of a register def operand,
1646 /// check if the register def is tied to a source operand, due to either
1647 /// two-address elimination or inline assembly constraints. Returns the
1648 /// first tied use operand index by reference if UseOpIdx is not null.
1649 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1650 unsigned *UseOpIdx = nullptr) const {
1651 const MachineOperand &MO = getOperand(DefOpIdx);
1652 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1653 return false;
1654 if (UseOpIdx)
1655 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1656 return true;
1657 }
1658
1659 /// Return true if the use operand of the specified index is tied to a def
1660 /// operand. It also returns the def operand index by reference if DefOpIdx
1661 /// is not null.
1662 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1663 unsigned *DefOpIdx = nullptr) const {
1664 const MachineOperand &MO = getOperand(UseOpIdx);
1665 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1666 return false;
1667 if (DefOpIdx)
1668 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1669 return true;
1670 }
1671
1672 /// Clears kill flags on all operands.
1673 void clearKillInfo();
1674
1675 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1676 /// properly composing subreg indices where necessary.
1677 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1679
1680 /// We have determined MI kills a register. Look for the
1681 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1682 /// add a implicit operand if it's not found. Returns true if the operand
1683 /// exists / is added.
1684 bool addRegisterKilled(Register IncomingReg,
1686 bool AddIfNotFound = false);
1687
1688 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1689 /// all aliasing registers.
1691
1692 /// We have determined MI defined a register without a use.
1693 /// Look for the operand that defines it and mark it as IsDead. If
1694 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1695 /// true if the operand exists / is added.
1697 bool AddIfNotFound = false);
1698
1699 /// Clear all dead flags on operands defining register @p Reg.
1701
1702 /// Mark all subregister defs of register @p Reg with the undef flag.
1703 /// This function is used when we determined to have a subregister def in an
1704 /// otherwise undefined super register.
1705 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1706
1707 /// We have determined MI defines a register. Make sure there is an operand
1708 /// defining Reg.
1710 const TargetRegisterInfo *RegInfo = nullptr);
1711
1712 /// Mark every physreg used by this instruction as
1713 /// dead except those in the UsedRegs list.
1714 ///
1715 /// On instructions with register mask operands, also add implicit-def
1716 /// operands for all registers in UsedRegs.
1718 const TargetRegisterInfo &TRI);
1719
1720 /// Return true if it is safe to move this instruction. If
1721 /// SawStore is set to true, it means that there is a store (or call) between
1722 /// the instruction's location and its intended destination.
1723 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1724
1725 /// Returns true if this instruction's memory access aliases the memory
1726 /// access of Other.
1727 //
1728 /// Assumes any physical registers used to compute addresses
1729 /// have the same value for both instructions. Returns false if neither
1730 /// instruction writes to memory.
1731 ///
1732 /// @param AA Optional alias analysis, used to compare memory operands.
1733 /// @param Other MachineInstr to check aliasing against.
1734 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1735 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1736
1737 /// Return true if this instruction may have an ordered
1738 /// or volatile memory reference, or if the information describing the memory
1739 /// reference is not available. Return false if it is known to have no
1740 /// ordered or volatile memory references.
1741 bool hasOrderedMemoryRef() const;
1742
1743 /// Return true if this load instruction never traps and points to a memory
1744 /// location whose value doesn't change during the execution of this function.
1745 ///
1746 /// Examples include loading a value from the constant pool or from the
1747 /// argument area of a function (if it does not change). If the instruction
1748 /// does multiple loads, this returns true only if all of the loads are
1749 /// dereferenceable and invariant.
1750 bool isDereferenceableInvariantLoad() const;
1751
1752 /// If the specified instruction is a PHI that always merges together the
1753 /// same virtual register, return the register, otherwise return 0.
1754 unsigned isConstantValuePHI() const;
1755
1756 /// Return true if this instruction has side effects that are not modeled
1757 /// by mayLoad / mayStore, etc.
1758 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1759 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1760 /// INLINEASM instruction, in which case the side effect property is encoded
1761 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1762 ///
1763 bool hasUnmodeledSideEffects() const;
1764
1765 /// Returns true if it is illegal to fold a load across this instruction.
1766 bool isLoadFoldBarrier() const;
1767
1768 /// Return true if all the defs of this instruction are dead.
1769 bool allDefsAreDead() const;
1770
1771 /// Return true if all the implicit defs of this instruction are dead.
1772 bool allImplicitDefsAreDead() const;
1773
1774 /// Return a valid size if the instruction is a spill instruction.
1775 std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1776
1777 /// Return a valid size if the instruction is a folded spill instruction.
1778 std::optional<LocationSize>
1780
1781 /// Return a valid size if the instruction is a restore instruction.
1782 std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1783
1784 /// Return a valid size if the instruction is a folded restore instruction.
1785 std::optional<LocationSize>
1787
1788 /// Copy implicit register operands from specified
1789 /// instruction to this instruction.
1791
1792 /// Debugging support
1793 /// @{
1794 /// Determine the generic type to be printed (if needed) on uses and defs.
1795 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1796 const MachineRegisterInfo &MRI) const;
1797
1798 /// Return true when an instruction has tied register that can't be determined
1799 /// by the instruction's descriptor. This is useful for MIR printing, to
1800 /// determine whether we need to print the ties or not.
1801 bool hasComplexRegisterTies() const;
1802
1803 /// Print this MI to \p OS.
1804 /// Don't print information that can be inferred from other instructions if
1805 /// \p IsStandalone is false. It is usually true when only a fragment of the
1806 /// function is printed.
1807 /// Only print the defs and the opcode if \p SkipOpers is true.
1808 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1809 /// Otherwise, also print the debug loc, with a terminating newline.
1810 /// \p TII is used to print the opcode name. If it's not present, but the
1811 /// MI is in a function, the opcode will be printed using the function's TII.
1812 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1813 bool SkipDebugLoc = false, bool AddNewLine = true,
1814 const TargetInstrInfo *TII = nullptr) const;
1815 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1816 bool SkipOpers = false, bool SkipDebugLoc = false,
1817 bool AddNewLine = true,
1818 const TargetInstrInfo *TII = nullptr) const;
1819 void dump() const;
1820 /// Print on dbgs() the current instruction and the instructions defining its
1821 /// operands and so on until we reach \p MaxDepth.
1822 void dumpr(const MachineRegisterInfo &MRI,
1823 unsigned MaxDepth = UINT_MAX) const;
1824 /// @}
1825
1826 //===--------------------------------------------------------------------===//
1827 // Accessors used to build up machine instructions.
1828
1829 /// Add the specified operand to the instruction. If it is an implicit
1830 /// operand, it is added to the end of the operand list. If it is an
1831 /// explicit operand it is added at the end of the explicit operand list
1832 /// (before the first implicit operand).
1833 ///
1834 /// MF must be the machine function that was used to allocate this
1835 /// instruction.
1836 ///
1837 /// MachineInstrBuilder provides a more convenient interface for creating
1838 /// instructions and adding operands.
1839 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1840
1841 /// Add an operand without providing an MF reference. This only works for
1842 /// instructions that are inserted in a basic block.
1843 ///
1844 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1845 /// preferred.
1846 void addOperand(const MachineOperand &Op);
1847
1848 /// Inserts Ops BEFORE It. Can untie/retie tied operands.
1849 void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1850
1851 /// Replace the instruction descriptor (thus opcode) of
1852 /// the current instruction with a new one.
1853 void setDesc(const MCInstrDesc &TID);
1854
1855 /// Replace current source information with new such.
1856 /// Avoid using this, the constructor argument is preferable.
1858 DbgLoc = std::move(DL);
1859 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1860 }
1861
1862 /// Erase an operand from an instruction, leaving it with one
1863 /// fewer operand than it started with.
1864 void removeOperand(unsigned OpNo);
1865
1866 /// Clear this MachineInstr's memory reference descriptor list. This resets
1867 /// the memrefs to their most conservative state. This should be used only
1868 /// as a last resort since it greatly pessimizes our knowledge of the memory
1869 /// access performed by the instruction.
1870 void dropMemRefs(MachineFunction &MF);
1871
1872 /// Assign this MachineInstr's memory reference descriptor list.
1873 ///
1874 /// Unlike other methods, this *will* allocate them into a new array
1875 /// associated with the provided `MachineFunction`.
1877
1878 /// Add a MachineMemOperand to the machine instruction.
1879 /// This function should be used only occasionally. The setMemRefs function
1880 /// is the primary method for setting up a MachineInstr's MemRefs list.
1882
1883 /// Clone another MachineInstr's memory reference descriptor list and replace
1884 /// ours with it.
1885 ///
1886 /// Note that `*this` may be the incoming MI!
1887 ///
1888 /// Prefer this API whenever possible as it can avoid allocations in common
1889 /// cases.
1890 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1891
1892 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1893 /// list and replace ours with it.
1894 ///
1895 /// Note that `*this` may be one of the incoming MIs!
1896 ///
1897 /// Prefer this API whenever possible as it can avoid allocations in common
1898 /// cases.
1901
1902 /// Set a symbol that will be emitted just prior to the instruction itself.
1903 ///
1904 /// Setting this to a null pointer will remove any such symbol.
1905 ///
1906 /// FIXME: This is not fully implemented yet.
1907 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1908
1909 /// Set a symbol that will be emitted just after the instruction itself.
1910 ///
1911 /// Setting this to a null pointer will remove any such symbol.
1912 ///
1913 /// FIXME: This is not fully implemented yet.
1914 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1915
1916 /// Clone another MachineInstr's pre- and post- instruction symbols and
1917 /// replace ours with it.
1919
1920 /// Set a marker on instructions that denotes where we should create and emit
1921 /// heap alloc site labels. This waits until after instruction selection and
1922 /// optimizations to create the label, so it should still work if the
1923 /// instruction is removed or duplicated.
1925
1926 // Set metadata on instructions that say which sections to emit instruction
1927 // addresses into.
1928 void setPCSections(MachineFunction &MF, MDNode *MD);
1929
1930 void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1931
1932 /// Set the CFI type for the instruction.
1934
1935 /// Return the MIFlags which represent both MachineInstrs. This
1936 /// should be used when merging two MachineInstrs into one. This routine does
1937 /// not modify the MIFlags of this MachineInstr.
1939
1941
1942 /// Copy all flags to MachineInst MIFlags
1943 void copyIRFlags(const Instruction &I);
1944
1945 /// Break any tie involving OpIdx.
1946 void untieRegOperand(unsigned OpIdx) {
1947 MachineOperand &MO = getOperand(OpIdx);
1948 if (MO.isReg() && MO.isTied()) {
1949 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1950 MO.TiedTo = 0;
1951 }
1952 }
1953
1954 /// Add all implicit def and use operands to this instruction.
1956
1957 /// Scan instructions immediately following MI and collect any matching
1958 /// DBG_VALUEs.
1960
1961 /// Find all DBG_VALUEs that point to the register def in this instruction
1962 /// and point them to \p Reg instead.
1964
1965 /// Sets all register debug operands in this debug value instruction to be
1966 /// undef.
1968 assert(isDebugValue() && "Must be a debug value instruction.");
1969 for (MachineOperand &MO : debug_operands()) {
1970 if (MO.isReg()) {
1971 MO.setReg(0);
1972 MO.setSubReg(0);
1973 }
1974 }
1975 }
1976
1977 std::tuple<Register, Register> getFirst2Regs() const {
1978 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg());
1979 }
1980
1981 std::tuple<Register, Register, Register> getFirst3Regs() const {
1982 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1983 getOperand(2).getReg());
1984 }
1985
1986 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1987 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1988 getOperand(2).getReg(), getOperand(3).getReg());
1989 }
1990
1991 std::tuple<Register, Register, Register, Register, Register>
1993 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1995 getOperand(4).getReg());
1996 }
1997
1998 std::tuple<LLT, LLT> getFirst2LLTs() const;
1999 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
2000 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
2001 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2002
2003 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2004 std::tuple<Register, LLT, Register, LLT, Register, LLT>
2005 getFirst3RegLLTs() const;
2006 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2007 getFirst4RegLLTs() const;
2008 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
2009 Register, LLT>
2010 getFirst5RegLLTs() const;
2011
2012private:
2013 /// If this instruction is embedded into a MachineFunction, return the
2014 /// MachineRegisterInfo object for the current function, otherwise
2015 /// return null.
2016 MachineRegisterInfo *getRegInfo();
2017 const MachineRegisterInfo *getRegInfo() const;
2018
2019 /// Unlink all of the register operands in this instruction from their
2020 /// respective use lists. This requires that the operands already be on their
2021 /// use lists.
2022 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2023
2024 /// Add all of the register operands in this instruction from their
2025 /// respective use lists. This requires that the operands not be on their
2026 /// use lists yet.
2027 void addRegOperandsToUseLists(MachineRegisterInfo&);
2028
2029 /// Slow path for hasProperty when we're dealing with a bundle.
2030 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2031
2032 /// Implements the logic of getRegClassConstraintEffectForVReg for the
2033 /// this MI and the given operand index \p OpIdx.
2034 /// If the related operand does not constrained Reg, this returns CurRC.
2035 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2036 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2037 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2038
2039 /// Stores extra instruction information inline or allocates as ExtraInfo
2040 /// based on the number of pointers.
2041 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2042 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2043 MDNode *HeapAllocMarker, MDNode *PCSections,
2044 uint32_t CFIType, MDNode *MMRAs);
2045};
2046
2047/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2048/// instruction rather than by pointer value.
2049/// The hashing and equality testing functions ignore definitions so this is
2050/// useful for CSE, etc.
2052 static inline MachineInstr *getEmptyKey() {
2053 return nullptr;
2054 }
2055
2057 return reinterpret_cast<MachineInstr*>(-1);
2058 }
2059
2060 static unsigned getHashValue(const MachineInstr* const &MI);
2061
2062 static bool isEqual(const MachineInstr* const &LHS,
2063 const MachineInstr* const &RHS) {
2064 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2065 LHS == getEmptyKey() || LHS == getTombstoneKey())
2066 return LHS == RHS;
2067 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
2068 }
2069};
2070
2071//===----------------------------------------------------------------------===//
2072// Debugging Support
2073
2075 MI.print(OS);
2076 return OS;
2077}
2078
2079} // end namespace llvm
2080
2081#endif // LLVM_CODEGEN_MACHINEINSTR_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
#define LLVM_MI_ASMPRINTERFLAGS_BITS
Definition: MachineInstr.h:133
#define LLVM_MI_FLAGS_BITS
Definition: MachineInstr.h:132
#define LLVM_MI_NUMOPERANDS_BITS
Definition: MachineInstr.h:131
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:110
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define P(N)
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This header defines support for implementing classes that have some trailing object (or arrays of obj...
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
DWARF expression.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:251
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
unsigned short Opcode
Definition: MCInstrDesc.h:205
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
Representation of each machine instruction.
Definition: MachineInstr.h:69
mop_iterator operands_begin()
Definition: MachineInstr.h:676
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:566
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:648
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:937
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:607
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:596
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:737
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:77
bool isPosition() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:971
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:734
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopy() const
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:364
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:704
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:343
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:552
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
Definition: MachineInstr.h:862
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:871
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:894
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:406
MachineFunction * getMF()
Definition: MachineInstr.h:355
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:883
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:962
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:344
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:947
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:393
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:381
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:730
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:741
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:763
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:572
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:569
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:546
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:692
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:674
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:367
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:809
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:804
bool isDebugRef() const
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:504
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:688
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:542
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:724
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:772
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:640
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:979
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:474
bool isDebugPHI() const
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:580
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:680
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:374
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
Definition: MachineInstr.h:677
bool isFullCopy() const
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:852
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:563
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void clearFlags(unsigned flags)
Definition: MachineInstr.h:421
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:767
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:993
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:711
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr kills the specified register.
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:815
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:415
bool isGCLabel() const
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:361
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:653
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:679
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
const MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
bool isJumpTableDebugInfo() const
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:812
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:682
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:757
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:620
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:719
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:797
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:462
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:685
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:779
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:673
MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:400
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:495
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:907
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:943
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:927
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:699
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:818
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:921
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:629
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:500
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:585
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:696
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:478
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:842
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:625
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:576
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:388
bool isEHLabel() const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:830
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:753
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:589
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:635
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
bool isKill() const
const MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:933
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:614
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:985
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:915
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:468
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
std::tuple< Register, Register > getFirst2Regs() const
~MachineInstr()=delete
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:497
An ilist node that can access its parent list.
Definition: ilist_node.h:321
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:181
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:175
@ MayRaiseFPException
Definition: MCInstrDesc.h:170
@ Rematerializable
Definition: MCInstrDesc.h:178
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:180
@ UsesCustomInserter
Definition: MCInstrDesc.h:176
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
Definition: ADL.h:78
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
Definition: ADL.h:86
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:572
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition: Allocator.h:380
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:50
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
Template traits for intrusive list.
Definition: ilist.h:90