LLVM  13.0.0git
MachineInstr.h
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1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/ilist.h"
22 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/PseudoProbe.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <utility>
38 
39 namespace llvm {
40 
41 class AAResults;
42 template <typename T> class ArrayRef;
43 class DIExpression;
44 class DILocalVariable;
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineRegisterInfo;
48 class ModuleSlotTracker;
49 class raw_ostream;
50 template <typename T> class SmallVectorImpl;
51 class SmallBitVector;
52 class StringRef;
53 class TargetInstrInfo;
54 class TargetRegisterClass;
55 class TargetRegisterInfo;
56 
57 //===----------------------------------------------------------------------===//
58 /// Representation of each machine instruction.
59 ///
60 /// This class isn't a POD type, but it must have a trivial destructor. When a
61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62 /// without having their destructor called.
63 ///
65  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66  ilist_sentinel_tracking<true>> {
67 public:
69 
70  /// Flags to specify different kinds of comments to output in
71  /// assembly code. These flags carry semantic information not
72  /// otherwise easily derivable from the IR text.
73  ///
74  enum CommentFlag {
75  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
77  TAsmComments = 0x4 // Target Asm comments should start from this value.
78  };
79 
80  enum MIFlag {
81  NoFlags = 0,
82  FrameSetup = 1 << 0, // Instruction is used as a part of
83  // function frame setup code.
84  FrameDestroy = 1 << 1, // Instruction is used as a part of
85  // function frame destruction code.
86  BundledPred = 1 << 2, // Instruction has bundled predecessors.
87  BundledSucc = 1 << 3, // Instruction has bundled successors.
88  FmNoNans = 1 << 4, // Instruction does not support Fast
89  // math nan values.
90  FmNoInfs = 1 << 5, // Instruction does not support Fast
91  // math infinity values.
92  FmNsz = 1 << 6, // Instruction is not required to retain
93  // signed zero values.
94  FmArcp = 1 << 7, // Instruction supports Fast math
95  // reciprocal approximations.
96  FmContract = 1 << 8, // Instruction supports Fast math
97  // contraction operations like fma.
98  FmAfn = 1 << 9, // Instruction may map to Fast math
99  // instrinsic approximation.
100  FmReassoc = 1 << 10, // Instruction supports Fast math
101  // reassociation of operand order.
102  NoUWrap = 1 << 11, // Instruction supports binary operator
103  // no unsigned wrap.
104  NoSWrap = 1 << 12, // Instruction supports binary operator
105  // no signed wrap.
106  IsExact = 1 << 13, // Instruction supports division is
107  // known to be exact.
108  NoFPExcept = 1 << 14, // Instruction does not raise
109  // floatint-point exceptions.
110  NoMerge = 1 << 15, // Passes that drop source location info
111  // (e.g. branch folding) should skip
112  // this instruction.
113  };
114 
115 private:
116  const MCInstrDesc *MCID; // Instruction descriptor.
117  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
118 
119  // Operands are allocated by an ArrayRecycler.
120  MachineOperand *Operands = nullptr; // Pointer to the first operand.
121  unsigned NumOperands = 0; // Number of operands on instruction.
122 
123  uint16_t Flags = 0; // Various bits of additional
124  // information about machine
125  // instruction.
126 
127  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
128  // the AsmPrinter to emit helpful
129  // comments. This is *not* semantic
130  // information. Do not use this for
131  // anything other than to convey comment
132  // information to AsmPrinter.
133 
134  // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
135  // to properly pack.
136  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
137  OperandCapacity CapOperands; // Capacity of the Operands array.
138 
139  /// Internal implementation detail class that provides out-of-line storage for
140  /// extra info used by the machine instruction when this info cannot be stored
141  /// in-line within the instruction itself.
142  ///
143  /// This has to be defined eagerly due to the implementation constraints of
144  /// `PointerSumType` where it is used.
145  class ExtraInfo final
146  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
147  public:
148  static ExtraInfo *create(BumpPtrAllocator &Allocator,
150  MCSymbol *PreInstrSymbol = nullptr,
151  MCSymbol *PostInstrSymbol = nullptr,
152  MDNode *HeapAllocMarker = nullptr) {
153  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
154  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
155  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
156  auto *Result = new (Allocator.Allocate(
157  totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
158  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
159  HasHeapAllocMarker),
160  alignof(ExtraInfo)))
161  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
162  HasHeapAllocMarker);
163 
164  // Copy the actual data into the trailing objects.
165  std::copy(MMOs.begin(), MMOs.end(),
166  Result->getTrailingObjects<MachineMemOperand *>());
167 
168  if (HasPreInstrSymbol)
169  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
170  if (HasPostInstrSymbol)
171  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
172  PostInstrSymbol;
173  if (HasHeapAllocMarker)
174  Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
175 
176  return Result;
177  }
178 
179  ArrayRef<MachineMemOperand *> getMMOs() const {
180  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
181  }
182 
183  MCSymbol *getPreInstrSymbol() const {
184  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
185  }
186 
187  MCSymbol *getPostInstrSymbol() const {
188  return HasPostInstrSymbol
189  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
190  : nullptr;
191  }
192 
193  MDNode *getHeapAllocMarker() const {
194  return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
195  }
196 
197  private:
198  friend TrailingObjects;
199 
200  // Description of the extra info, used to interpret the actual optional
201  // data appended.
202  //
203  // Note that this is not terribly space optimized. This leaves a great deal
204  // of flexibility to fit more in here later.
205  const int NumMMOs;
206  const bool HasPreInstrSymbol;
207  const bool HasPostInstrSymbol;
208  const bool HasHeapAllocMarker;
209 
210  // Implement the `TrailingObjects` internal API.
211  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
212  return NumMMOs;
213  }
214  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
215  return HasPreInstrSymbol + HasPostInstrSymbol;
216  }
217  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
218  return HasHeapAllocMarker;
219  }
220 
221  // Just a boring constructor to allow us to initialize the sizes. Always use
222  // the `create` routine above.
223  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
224  bool HasHeapAllocMarker)
225  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
226  HasPostInstrSymbol(HasPostInstrSymbol),
227  HasHeapAllocMarker(HasHeapAllocMarker) {}
228  };
229 
230  /// Enumeration of the kinds of inline extra info available. It is important
231  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
232  /// it accessible as an `ArrayRef`.
233  enum ExtraInfoInlineKinds {
234  EIIK_MMO = 0,
235  EIIK_PreInstrSymbol,
236  EIIK_PostInstrSymbol,
237  EIIK_OutOfLine
238  };
239 
240  // We store extra information about the instruction here. The common case is
241  // expected to be nothing or a single pointer (typically a MMO or a symbol).
242  // We work to optimize this common case by storing it inline here rather than
243  // requiring a separate allocation, but we fall back to an allocation when
244  // multiple pointers are needed.
245  PointerSumType<ExtraInfoInlineKinds,
246  PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
247  PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
248  PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
249  PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
250  Info;
251 
252  DebugLoc debugLoc; // Source line information.
253 
254  /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
255  /// defined by this instruction.
256  unsigned DebugInstrNum;
257 
258  // Intrusive list support
259  friend struct ilist_traits<MachineInstr>;
261  void setParent(MachineBasicBlock *P) { Parent = P; }
262 
263  /// This constructor creates a copy of the given
264  /// MachineInstr in the given MachineFunction.
266 
267  /// This constructor create a MachineInstr and add the implicit operands.
268  /// It reserves space for number of operands specified by
269  /// MCInstrDesc. An explicit DebugLoc is supplied.
271  bool NoImp = false);
272 
273  // MachineInstrs are pool-allocated and owned by MachineFunction.
274  friend class MachineFunction;
275 
276  void
277  dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
278  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
279 
280 public:
281  MachineInstr(const MachineInstr &) = delete;
282  MachineInstr &operator=(const MachineInstr &) = delete;
283  // Use MachineFunction::DeleteMachineInstr() instead.
284  ~MachineInstr() = delete;
285 
286  const MachineBasicBlock* getParent() const { return Parent; }
287  MachineBasicBlock* getParent() { return Parent; }
288 
289  /// Move the instruction before \p MovePos.
290  void moveBefore(MachineInstr *MovePos);
291 
292  /// Return the function that contains the basic block that this instruction
293  /// belongs to.
294  ///
295  /// Note: this is undefined behaviour if the instruction does not have a
296  /// parent.
297  const MachineFunction *getMF() const;
299  return const_cast<MachineFunction *>(
300  static_cast<const MachineInstr *>(this)->getMF());
301  }
302 
303  /// Return the asm printer flags bitvector.
304  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
305 
306  /// Clear the AsmPrinter bitvector.
307  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
308 
309  /// Return whether an AsmPrinter flag is set.
311  return AsmPrinterFlags & Flag;
312  }
313 
314  /// Set a flag for the AsmPrinter.
315  void setAsmPrinterFlag(uint8_t Flag) {
316  AsmPrinterFlags |= Flag;
317  }
318 
319  /// Clear specific AsmPrinter flags.
321  AsmPrinterFlags &= ~Flag;
322  }
323 
324  /// Return the MI flags bitvector.
325  uint16_t getFlags() const {
326  return Flags;
327  }
328 
329  /// Return whether an MI flag is set.
330  bool getFlag(MIFlag Flag) const {
331  return Flags & Flag;
332  }
333 
334  /// Set a MI flag.
336  Flags |= (uint16_t)Flag;
337  }
338 
339  void setFlags(unsigned flags) {
340  // Filter out the automatically maintained flags.
341  unsigned Mask = BundledPred | BundledSucc;
342  Flags = (Flags & Mask) | (flags & ~Mask);
343  }
344 
345  /// clearFlag - Clear a MI flag.
347  Flags &= ~((uint16_t)Flag);
348  }
349 
350  /// Return true if MI is in a bundle (but not the first MI in a bundle).
351  ///
352  /// A bundle looks like this before it's finalized:
353  /// ----------------
354  /// | MI |
355  /// ----------------
356  /// |
357  /// ----------------
358  /// | MI * |
359  /// ----------------
360  /// |
361  /// ----------------
362  /// | MI * |
363  /// ----------------
364  /// In this case, the first MI starts a bundle but is not inside a bundle, the
365  /// next 2 MIs are considered "inside" the bundle.
366  ///
367  /// After a bundle is finalized, it looks like this:
368  /// ----------------
369  /// | Bundle |
370  /// ----------------
371  /// |
372  /// ----------------
373  /// | MI * |
374  /// ----------------
375  /// |
376  /// ----------------
377  /// | MI * |
378  /// ----------------
379  /// |
380  /// ----------------
381  /// | MI * |
382  /// ----------------
383  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
384  /// a bundle, but the next three MIs are.
385  bool isInsideBundle() const {
386  return getFlag(BundledPred);
387  }
388 
389  /// Return true if this instruction part of a bundle. This is true
390  /// if either itself or its following instruction is marked "InsideBundle".
391  bool isBundled() const {
392  return isBundledWithPred() || isBundledWithSucc();
393  }
394 
395  /// Return true if this instruction is part of a bundle, and it is not the
396  /// first instruction in the bundle.
397  bool isBundledWithPred() const { return getFlag(BundledPred); }
398 
399  /// Return true if this instruction is part of a bundle, and it is not the
400  /// last instruction in the bundle.
401  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
402 
403  /// Bundle this instruction with its predecessor. This can be an unbundled
404  /// instruction, or it can be the first instruction in a bundle.
405  void bundleWithPred();
406 
407  /// Bundle this instruction with its successor. This can be an unbundled
408  /// instruction, or it can be the last instruction in a bundle.
409  void bundleWithSucc();
410 
411  /// Break bundle above this instruction.
412  void unbundleFromPred();
413 
414  /// Break bundle below this instruction.
415  void unbundleFromSucc();
416 
417  /// Returns the debug location id of this MachineInstr.
418  const DebugLoc &getDebugLoc() const { return debugLoc; }
419 
420  /// Return the operand containing the offset to be used if this DBG_VALUE
421  /// instruction is indirect; will be an invalid register if this value is
422  /// not indirect, and an immediate with value 0 otherwise.
424  assert(isNonListDebugValue() && "not a DBG_VALUE");
425  return getOperand(1);
426  }
428  assert(isNonListDebugValue() && "not a DBG_VALUE");
429  return getOperand(1);
430  }
431 
432  /// Return the operand for the debug variable referenced by
433  /// this DBG_VALUE instruction.
434  const MachineOperand &getDebugVariableOp() const;
436 
437  /// Return the debug variable referenced by
438  /// this DBG_VALUE instruction.
439  const DILocalVariable *getDebugVariable() const;
440 
441  /// Return the operand for the complex address expression referenced by
442  /// this DBG_VALUE instruction.
443  const MachineOperand &getDebugExpressionOp() const;
445 
446  /// Return the complex address expression referenced by
447  /// this DBG_VALUE instruction.
448  const DIExpression *getDebugExpression() const;
449 
450  /// Return the debug label referenced by
451  /// this DBG_LABEL instruction.
452  const DILabel *getDebugLabel() const;
453 
454  /// Fetch the instruction number of this MachineInstr. If it does not have
455  /// one already, a new and unique number will be assigned.
456  unsigned getDebugInstrNum();
457 
458  /// Examine the instruction number of this MachineInstr. May be zero if
459  /// it hasn't been assigned a number yet.
460  unsigned peekDebugInstrNum() const { return DebugInstrNum; }
461 
462  /// Set instruction number of this MachineInstr. Avoid using unless you're
463  /// deserializing this information.
464  void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
465 
466  /// Emit an error referring to the source location of this instruction.
467  /// This should only be used for inline assembly that is somehow
468  /// impossible to compile. Other errors should have been handled much
469  /// earlier.
470  ///
471  /// If this method returns, the caller should try to recover from the error.
472  void emitError(StringRef Msg) const;
473 
474  /// Returns the target instruction descriptor of this MachineInstr.
475  const MCInstrDesc &getDesc() const { return *MCID; }
476 
477  /// Returns the opcode of this MachineInstr.
478  unsigned getOpcode() const { return MCID->Opcode; }
479 
480  /// Retuns the total number of operands.
481  unsigned getNumOperands() const { return NumOperands; }
482 
483  /// Returns the total number of operands which are debug locations.
484  unsigned getNumDebugOperands() const {
485  return std::distance(debug_operands().begin(), debug_operands().end());
486  }
487 
488  const MachineOperand& getOperand(unsigned i) const {
489  assert(i < getNumOperands() && "getOperand() out of range!");
490  return Operands[i];
491  }
493  assert(i < getNumOperands() && "getOperand() out of range!");
494  return Operands[i];
495  }
496 
498  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
499  return *(debug_operands().begin() + Index);
500  }
501  const MachineOperand &getDebugOperand(unsigned Index) const {
502  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
503  return *(debug_operands().begin() + Index);
504  }
505 
507  assert(isDebugValue() && "not a DBG_VALUE*");
508  SmallSet<Register, 4> UsedRegs;
509  for (auto MO : debug_operands())
510  if (MO.isReg() && MO.getReg())
511  UsedRegs.insert(MO.getReg());
512  return UsedRegs;
513  }
514 
515  /// Returns whether this debug value has at least one debug operand with the
516  /// register \p Reg.
518  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
519  return Op.isReg() && Op.getReg() == Reg;
520  });
521  }
522 
523  /// Returns a range of all of the operands that correspond to a debug use of
524  /// \p Reg.
525  template <typename Operand, typename Instruction>
526  static iterator_range<
527  filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
529  std::function<bool(Operand & Op)> OpUsesReg(
530  [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
531  return make_filter_range(MI->debug_operands(), OpUsesReg);
532  }
534  std::function<bool(const MachineOperand &Op)>>>
537  const MachineInstr>(this, Reg);
538  }
542  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
543  this, Reg);
544  }
545 
546  bool isDebugOperand(const MachineOperand *Op) const {
547  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
548  }
549 
550  unsigned getDebugOperandIndex(const MachineOperand *Op) const {
551  assert(isDebugOperand(Op) && "Expected a debug operand.");
552  return std::distance(adl_begin(debug_operands()), Op);
553  }
554 
555  /// Returns the total number of definitions.
556  unsigned getNumDefs() const {
557  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
558  }
559 
560  /// Returns true if the instruction has implicit definition.
561  bool hasImplicitDef() const {
562  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
563  I != E; ++I) {
564  const MachineOperand &MO = getOperand(I);
565  if (MO.isDef() && MO.isImplicit())
566  return true;
567  }
568  return false;
569  }
570 
571  /// Returns the implicit operands number.
572  unsigned getNumImplicitOperands() const {
574  }
575 
576  /// Return true if operand \p OpIdx is a subregister index.
577  bool isOperandSubregIdx(unsigned OpIdx) const {
579  "Expected MO_Immediate operand type.");
580  if (isExtractSubreg() && OpIdx == 2)
581  return true;
582  if (isInsertSubreg() && OpIdx == 3)
583  return true;
584  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
585  return true;
586  if (isSubregToReg() && OpIdx == 3)
587  return true;
588  return false;
589  }
590 
591  /// Returns the number of non-implicit operands.
592  unsigned getNumExplicitOperands() const;
593 
594  /// Returns the number of non-implicit definitions.
595  unsigned getNumExplicitDefs() const;
596 
597  /// iterator/begin/end - Iterate over all operands of a machine instruction.
600 
602  mop_iterator operands_end() { return Operands + NumOperands; }
603 
605  const_mop_iterator operands_end() const { return Operands + NumOperands; }
606 
609  }
612  }
614  return make_range(operands_begin(),
616  }
618  return make_range(operands_begin(),
620  }
623  }
626  }
627  /// Returns a range over all operands that are used to determine the variable
628  /// location for this DBG_VALUE instruction.
630  assert(isDebugValue() && "Must be a debug value instruction.");
631  return isDebugValueList()
634  }
635  /// \copydoc debug_operands()
637  assert(isDebugValue() && "Must be a debug value instruction.");
638  return isDebugValueList()
641  }
642  /// Returns a range over all explicit operands that are register definitions.
643  /// Implicit definition are not included!
645  return make_range(operands_begin(),
647  }
648  /// \copydoc defs()
650  return make_range(operands_begin(),
652  }
653  /// Returns a range that includes all operands that are register uses.
654  /// This may include unrelated operands which are not register uses.
657  }
658  /// \copydoc uses()
661  }
665  }
669  }
670 
671  /// Returns the number of the operand iterator \p I points to.
673  return I - operands_begin();
674  }
675 
676  /// Access to memory operands of the instruction. If there are none, that does
677  /// not imply anything about whether the function accesses memory. Instead,
678  /// the caller must behave conservatively.
680  if (!Info)
681  return {};
682 
683  if (Info.is<EIIK_MMO>())
684  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
685 
686  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
687  return EI->getMMOs();
688 
689  return {};
690  }
691 
692  /// Access to memory operands of the instruction.
693  ///
694  /// If `memoperands_begin() == memoperands_end()`, that does not imply
695  /// anything about whether the function accesses memory. Instead, the caller
696  /// must behave conservatively.
697  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
698 
699  /// Access to memory operands of the instruction.
700  ///
701  /// If `memoperands_begin() == memoperands_end()`, that does not imply
702  /// anything about whether the function accesses memory. Instead, the caller
703  /// must behave conservatively.
704  mmo_iterator memoperands_end() const { return memoperands().end(); }
705 
706  /// Return true if we don't have any memory operands which described the
707  /// memory access done by this instruction. If this is true, calling code
708  /// must be conservative.
709  bool memoperands_empty() const { return memoperands().empty(); }
710 
711  /// Return true if this instruction has exactly one MachineMemOperand.
712  bool hasOneMemOperand() const { return memoperands().size() == 1; }
713 
714  /// Return the number of memory operands.
715  unsigned getNumMemOperands() const { return memoperands().size(); }
716 
717  /// Helper to extract a pre-instruction symbol if one has been added.
719  if (!Info)
720  return nullptr;
721  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
722  return S;
723  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
724  return EI->getPreInstrSymbol();
725 
726  return nullptr;
727  }
728 
729  /// Helper to extract a post-instruction symbol if one has been added.
731  if (!Info)
732  return nullptr;
733  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
734  return S;
735  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
736  return EI->getPostInstrSymbol();
737 
738  return nullptr;
739  }
740 
741  /// Helper to extract a heap alloc marker if one has been added.
743  if (!Info)
744  return nullptr;
745  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
746  return EI->getHeapAllocMarker();
747 
748  return nullptr;
749  }
750 
751  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
752  /// queries but they are bundle aware.
753 
754  enum QueryType {
755  IgnoreBundle, // Ignore bundles
756  AnyInBundle, // Return true if any instruction in bundle has property
757  AllInBundle // Return true if all instructions in bundle have property
758  };
759 
760  /// Return true if the instruction (or in the case of a bundle,
761  /// the instructions inside the bundle) has the specified property.
762  /// The first argument is the property being queried.
763  /// The second argument indicates whether the query should look inside
764  /// instruction bundles.
765  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
766  assert(MCFlag < 64 &&
767  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
768  // Inline the fast path for unbundled or bundle-internal instructions.
769  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
770  return getDesc().getFlags() & (1ULL << MCFlag);
771 
772  // If this is the first instruction in a bundle, take the slow path.
773  return hasPropertyInBundle(1ULL << MCFlag, Type);
774  }
775 
776  /// Return true if this is an instruction that should go through the usual
777  /// legalization steps.
780  }
781 
782  /// Return true if this instruction can have a variable number of operands.
783  /// In this case, the variable operands will be after the normal
784  /// operands but before the implicit definitions and uses (if any are
785  /// present).
788  }
789 
790  /// Set if this instruction has an optional definition, e.g.
791  /// ARM instructions which can set condition code if 's' bit is set.
794  }
795 
796  /// Return true if this is a pseudo instruction that doesn't
797  /// correspond to a real machine instruction.
799  return hasProperty(MCID::Pseudo, Type);
800  }
801 
803  return hasProperty(MCID::Return, Type);
804  }
805 
806  /// Return true if this is an instruction that marks the end of an EH scope,
807  /// i.e., a catchpad or a cleanuppad instruction.
810  }
811 
813  return hasProperty(MCID::Call, Type);
814  }
815 
816  /// Return true if this is a call instruction that may have an associated
817  /// call site entry in the debug info.
819  /// Return true if copying, moving, or erasing this instruction requires
820  /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
821  /// \ref eraseCallSiteInfo).
822  bool shouldUpdateCallSiteInfo() const;
823 
824  /// Returns true if the specified instruction stops control flow
825  /// from executing the instruction immediately following it. Examples include
826  /// unconditional branches and return instructions.
828  return hasProperty(MCID::Barrier, Type);
829  }
830 
831  /// Returns true if this instruction part of the terminator for a basic block.
832  /// Typically this is things like return and branch instructions.
833  ///
834  /// Various passes use this to insert code into the bottom of a basic block,
835  /// but before control flow occurs.
838  }
839 
840  /// Returns true if this is a conditional, unconditional, or indirect branch.
841  /// Predicates below can be used to discriminate between
842  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
843  /// get more information.
845  return hasProperty(MCID::Branch, Type);
846  }
847 
848  /// Return true if this is an indirect branch, such as a
849  /// branch through a register.
852  }
853 
854  /// Return true if this is a branch which may fall
855  /// through to the next instruction or may transfer control flow to some other
856  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
857  /// information about this branch.
859  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
860  }
861 
862  /// Return true if this is a branch which always
863  /// transfers control flow to some other block. The
864  /// TargetInstrInfo::analyzeBranch method can be used to get more information
865  /// about this branch.
867  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
868  }
869 
870  /// Return true if this instruction has a predicate operand that
871  /// controls execution. It may be set to 'always', or may be set to other
872  /// values. There are various methods in TargetInstrInfo that can be used to
873  /// control and modify the predicate in this instruction.
875  // If it's a bundle than all bundled instructions must be predicable for this
876  // to return true.
878  }
879 
880  /// Return true if this instruction is a comparison.
882  return hasProperty(MCID::Compare, Type);
883  }
884 
885  /// Return true if this instruction is a move immediate
886  /// (including conditional moves) instruction.
888  return hasProperty(MCID::MoveImm, Type);
889  }
890 
891  /// Return true if this instruction is a register move.
892  /// (including moving values from subreg to reg)
894  return hasProperty(MCID::MoveReg, Type);
895  }
896 
897  /// Return true if this instruction is a bitcast instruction.
899  return hasProperty(MCID::Bitcast, Type);
900  }
901 
902  /// Return true if this instruction is a select instruction.
904  return hasProperty(MCID::Select, Type);
905  }
906 
907  /// Return true if this instruction cannot be safely duplicated.
908  /// For example, if the instruction has a unique labels attached
909  /// to it, duplicating it would cause multiple definition errors.
912  }
913 
914  /// Return true if this instruction is convergent.
915  /// Convergent instructions can not be made control-dependent on any
916  /// additional values.
918  if (isInlineAsm()) {
919  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
920  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
921  return true;
922  }
924  }
925 
926  /// Returns true if the specified instruction has a delay slot
927  /// which must be filled by the code generator.
930  }
931 
932  /// Return true for instructions that can be folded as
933  /// memory operands in other instructions. The most common use for this
934  /// is instructions that are simple loads from memory that don't modify
935  /// the loaded value in any way, but it can also be used for instructions
936  /// that can be expressed as constant-pool loads, such as V_SETALLONES
937  /// on x86, to allow them to be folded when it is beneficial.
938  /// This should only be set on instructions that return a value in their
939  /// only virtual register definition.
942  }
943 
944  /// Return true if this instruction behaves
945  /// the same way as the generic REG_SEQUENCE instructions.
946  /// E.g., on ARM,
947  /// dX VMOVDRR rY, rZ
948  /// is equivalent to
949  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
950  ///
951  /// Note that for the optimizers to be able to take advantage of
952  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
953  /// override accordingly.
956  }
957 
958  /// Return true if this instruction behaves
959  /// the same way as the generic EXTRACT_SUBREG instructions.
960  /// E.g., on ARM,
961  /// rX, rY VMOVRRD dZ
962  /// is equivalent to two EXTRACT_SUBREG:
963  /// rX = EXTRACT_SUBREG dZ, ssub_0
964  /// rY = EXTRACT_SUBREG dZ, ssub_1
965  ///
966  /// Note that for the optimizers to be able to take advantage of
967  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
968  /// override accordingly.
971  }
972 
973  /// Return true if this instruction behaves
974  /// the same way as the generic INSERT_SUBREG instructions.
975  /// E.g., on ARM,
976  /// dX = VSETLNi32 dY, rZ, Imm
977  /// is equivalent to a INSERT_SUBREG:
978  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
979  ///
980  /// Note that for the optimizers to be able to take advantage of
981  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
982  /// override accordingly.
985  }
986 
987  //===--------------------------------------------------------------------===//
988  // Side Effect Analysis
989  //===--------------------------------------------------------------------===//
990 
991  /// Return true if this instruction could possibly read memory.
992  /// Instructions with this flag set are not necessarily simple load
993  /// instructions, they may load a value and modify it, for example.
995  if (isInlineAsm()) {
996  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
997  if (ExtraInfo & InlineAsm::Extra_MayLoad)
998  return true;
999  }
1000  return hasProperty(MCID::MayLoad, Type);
1001  }
1002 
1003  /// Return true if this instruction could possibly modify memory.
1004  /// Instructions with this flag set are not necessarily simple store
1005  /// instructions, they may store a modified value based on their operands, or
1006  /// may not actually modify anything, for example.
1008  if (isInlineAsm()) {
1009  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1010  if (ExtraInfo & InlineAsm::Extra_MayStore)
1011  return true;
1012  }
1013  return hasProperty(MCID::MayStore, Type);
1014  }
1015 
1016  /// Return true if this instruction could possibly read or modify memory.
1018  return mayLoad(Type) || mayStore(Type);
1019  }
1020 
1021  /// Return true if this instruction could possibly raise a floating-point
1022  /// exception. This is the case if the instruction is a floating-point
1023  /// instruction that can in principle raise an exception, as indicated
1024  /// by the MCID::MayRaiseFPException property, *and* at the same time,
1025  /// the instruction is used in a context where we expect floating-point
1026  /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1027  bool mayRaiseFPException() const {
1029  !getFlag(MachineInstr::MIFlag::NoFPExcept);
1030  }
1031 
1032  //===--------------------------------------------------------------------===//
1033  // Flags that indicate whether an instruction can be modified by a method.
1034  //===--------------------------------------------------------------------===//
1035 
1036  /// Return true if this may be a 2- or 3-address
1037  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1038  /// result if Y and Z are exchanged. If this flag is set, then the
1039  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1040  /// instruction.
1041  ///
1042  /// Note that this flag may be set on instructions that are only commutable
1043  /// sometimes. In these cases, the call to commuteInstruction will fail.
1044  /// Also note that some instructions require non-trivial modification to
1045  /// commute them.
1048  }
1049 
1050  /// Return true if this is a 2-address instruction
1051  /// which can be changed into a 3-address instruction if needed. Doing this
1052  /// transformation can be profitable in the register allocator, because it
1053  /// means that the instruction can use a 2-address form if possible, but
1054  /// degrade into a less efficient form if the source and dest register cannot
1055  /// be assigned to the same register. For example, this allows the x86
1056  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1057  /// is the same speed as the shift but has bigger code size.
1058  ///
1059  /// If this returns true, then the target must implement the
1060  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1061  /// is allowed to fail if the transformation isn't valid for this specific
1062  /// instruction (e.g. shl reg, 4 on x86).
1063  ///
1066  }
1067 
1068  /// Return true if this instruction requires
1069  /// custom insertion support when the DAG scheduler is inserting it into a
1070  /// machine basic block. If this is true for the instruction, it basically
1071  /// means that it is a pseudo instruction used at SelectionDAG time that is
1072  /// expanded out into magic code by the target when MachineInstrs are formed.
1073  ///
1074  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1075  /// is used to insert this into the MachineBasicBlock.
1078  }
1079 
1080  /// Return true if this instruction requires *adjustment*
1081  /// after instruction selection by calling a target hook. For example, this
1082  /// can be used to fill in ARM 's' optional operand depending on whether
1083  /// the conditional flag register is used.
1086  }
1087 
1088  /// Returns true if this instruction is a candidate for remat.
1089  /// This flag is deprecated, please don't use it anymore. If this
1090  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1091  /// verify the instruction is really rematable.
1093  // It's only possible to re-mat a bundle if all bundled instructions are
1094  // re-materializable.
1096  }
1097 
1098  /// Returns true if this instruction has the same cost (or less) than a move
1099  /// instruction. This is useful during certain types of optimizations
1100  /// (e.g., remat during two-address conversion or machine licm)
1101  /// where we would like to remat or hoist the instruction, but not if it costs
1102  /// more than moving the instruction into the appropriate register. Note, we
1103  /// are not marking copies from and to the same register class with this flag.
1105  // Only returns true for a bundle if all bundled instructions are cheap.
1107  }
1108 
1109  /// Returns true if this instruction source operands
1110  /// have special register allocation requirements that are not captured by the
1111  /// operand register classes. e.g. ARM::STRD's two source registers must be an
1112  /// even / odd pair, ARM::STM registers have to be in ascending order.
1113  /// Post-register allocation passes should not attempt to change allocations
1114  /// for sources of instructions with this flag.
1117  }
1118 
1119  /// Returns true if this instruction def operands
1120  /// have special register allocation requirements that are not captured by the
1121  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1122  /// even / odd pair, ARM::LDM registers have to be in ascending order.
1123  /// Post-register allocation passes should not attempt to change allocations
1124  /// for definitions of instructions with this flag.
1127  }
1128 
1130  CheckDefs, // Check all operands for equality
1131  CheckKillDead, // Check all operands including kill / dead markers
1132  IgnoreDefs, // Ignore all definitions
1133  IgnoreVRegDefs // Ignore virtual register definitions
1134  };
1135 
1136  /// Return true if this instruction is identical to \p Other.
1137  /// Two instructions are identical if they have the same opcode and all their
1138  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1139  /// Note that this means liveness related flags (dead, undef, kill) do not
1140  /// affect the notion of identical.
1141  bool isIdenticalTo(const MachineInstr &Other,
1142  MICheckType Check = CheckDefs) const;
1143 
1144  /// Unlink 'this' from the containing basic block, and return it without
1145  /// deleting it.
1146  ///
1147  /// This function can not be used on bundled instructions, use
1148  /// removeFromBundle() to remove individual instructions from a bundle.
1150 
1151  /// Unlink this instruction from its basic block and return it without
1152  /// deleting it.
1153  ///
1154  /// If the instruction is part of a bundle, the other instructions in the
1155  /// bundle remain bundled.
1157 
1158  /// Unlink 'this' from the containing basic block and delete it.
1159  ///
1160  /// If this instruction is the header of a bundle, the whole bundle is erased.
1161  /// This function can not be used for instructions inside a bundle, use
1162  /// eraseFromBundle() to erase individual bundled instructions.
1163  void eraseFromParent();
1164 
1165  /// Unlink 'this' from the containing basic block and delete it.
1166  ///
1167  /// For all definitions mark their uses in DBG_VALUE nodes
1168  /// as undefined. Otherwise like eraseFromParent().
1170 
1171  /// Unlink 'this' form its basic block and delete it.
1172  ///
1173  /// If the instruction is part of a bundle, the other instructions in the
1174  /// bundle remain bundled.
1175  void eraseFromBundle();
1176 
1177  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1178  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1179  bool isAnnotationLabel() const {
1181  }
1182 
1183  /// Returns true if the MachineInstr represents a label.
1184  bool isLabel() const {
1185  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1186  }
1187 
1188  bool isCFIInstruction() const {
1189  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1190  }
1191 
1192  bool isPseudoProbe() const {
1194  }
1195 
1196  // True if the instruction represents a position in the function.
1197  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1198 
1199  bool isNonListDebugValue() const {
1200  return getOpcode() == TargetOpcode::DBG_VALUE;
1201  }
1202  bool isDebugValueList() const {
1203  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1204  }
1205  bool isDebugValue() const {
1206  return isNonListDebugValue() || isDebugValueList();
1207  }
1208  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1209  bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1210  bool isDebugInstr() const {
1211  return isDebugValue() || isDebugLabel() || isDebugRef();
1212  }
1213  bool isDebugOrPseudoInstr() const {
1214  return isDebugInstr() || isPseudoProbe();
1215  }
1216 
1217  bool isDebugOffsetImm() const {
1218  return isNonListDebugValue() && getDebugOffset().isImm();
1219  }
1220 
1221  /// A DBG_VALUE is indirect iff the location operand is a register and
1222  /// the offset operand is an immediate.
1223  bool isIndirectDebugValue() const {
1224  return isDebugOffsetImm() && getDebugOperand(0).isReg();
1225  }
1226 
1227  /// A DBG_VALUE is an entry value iff its debug expression contains the
1228  /// DW_OP_LLVM_entry_value operation.
1229  bool isDebugEntryValue() const;
1230 
1231  /// Return true if the instruction is a debug value which describes a part of
1232  /// a variable as unavailable.
1233  bool isUndefDebugValue() const {
1234  if (!isDebugValue())
1235  return false;
1236  // If any $noreg locations are given, this DV is undef.
1237  for (const MachineOperand &Op : debug_operands())
1238  if (Op.isReg() && !Op.getReg().isValid())
1239  return true;
1240  return false;
1241  }
1242 
1243  bool isPHI() const {
1244  return getOpcode() == TargetOpcode::PHI ||
1245  getOpcode() == TargetOpcode::G_PHI;
1246  }
1247  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1248  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1249  bool isInlineAsm() const {
1250  return getOpcode() == TargetOpcode::INLINEASM ||
1252  }
1253 
1254  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1255  /// specific, be attached to a generic MachineInstr.
1256  bool isMSInlineAsm() const {
1258  }
1259 
1260  bool isStackAligningInlineAsm() const;
1262 
1263  bool isInsertSubreg() const {
1264  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1265  }
1266 
1267  bool isSubregToReg() const {
1268  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1269  }
1270 
1271  bool isRegSequence() const {
1272  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1273  }
1274 
1275  bool isBundle() const {
1276  return getOpcode() == TargetOpcode::BUNDLE;
1277  }
1278 
1279  bool isCopy() const {
1280  return getOpcode() == TargetOpcode::COPY;
1281  }
1282 
1283  bool isFullCopy() const {
1284  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1285  }
1286 
1287  bool isExtractSubreg() const {
1288  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1289  }
1290 
1291  /// Return true if the instruction behaves like a copy.
1292  /// This does not include native copy instructions.
1293  bool isCopyLike() const {
1294  return isCopy() || isSubregToReg();
1295  }
1296 
1297  /// Return true is the instruction is an identity copy.
1298  bool isIdentityCopy() const {
1299  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1301  }
1302 
1303  /// Return true if this instruction doesn't produce any output in the form of
1304  /// executable instructions.
1305  bool isMetaInstruction() const {
1306  switch (getOpcode()) {
1307  default:
1308  return false;
1309  case TargetOpcode::IMPLICIT_DEF:
1310  case TargetOpcode::KILL:
1311  case TargetOpcode::CFI_INSTRUCTION:
1313  case TargetOpcode::GC_LABEL:
1314  case TargetOpcode::DBG_VALUE:
1315  case TargetOpcode::DBG_VALUE_LIST:
1316  case TargetOpcode::DBG_INSTR_REF:
1317  case TargetOpcode::DBG_LABEL:
1321  return true;
1322  }
1323  }
1324 
1325  /// Return true if this is a transient instruction that is either very likely
1326  /// to be eliminated during register allocation (such as copy-like
1327  /// instructions), or if this instruction doesn't have an execution-time cost.
1328  bool isTransient() const {
1329  switch (getOpcode()) {
1330  default:
1331  return isMetaInstruction();
1332  // Copy-like instructions are usually eliminated during register allocation.
1333  case TargetOpcode::PHI:
1334  case TargetOpcode::G_PHI:
1335  case TargetOpcode::COPY:
1336  case TargetOpcode::INSERT_SUBREG:
1337  case TargetOpcode::SUBREG_TO_REG:
1338  case TargetOpcode::REG_SEQUENCE:
1339  return true;
1340  }
1341  }
1342 
1343  /// Return the number of instructions inside the MI bundle, excluding the
1344  /// bundle header.
1345  ///
1346  /// This is the number of instructions that MachineBasicBlock::iterator
1347  /// skips, 0 for unbundled instructions.
1348  unsigned getBundleSize() const;
1349 
1350  /// Return true if the MachineInstr reads the specified register.
1351  /// If TargetRegisterInfo is passed, then it also checks if there
1352  /// is a read of a super-register.
1353  /// This does not count partial redefines of virtual registers as reads:
1354  /// %reg1024:6 = OP.
1356  const TargetRegisterInfo *TRI = nullptr) const {
1357  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1358  }
1359 
1360  /// Return true if the MachineInstr reads the specified virtual register.
1361  /// Take into account that a partial define is a
1362  /// read-modify-write operation.
1364  return readsWritesVirtualRegister(Reg).first;
1365  }
1366 
1367  /// Return a pair of bools (reads, writes) indicating if this instruction
1368  /// reads or writes Reg. This also considers partial defines.
1369  /// If Ops is not null, all operand indices for Reg are added.
1370  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1371  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1372 
1373  /// Return true if the MachineInstr kills the specified register.
1374  /// If TargetRegisterInfo is passed, then it also checks if there is
1375  /// a kill of a super-register.
1377  const TargetRegisterInfo *TRI = nullptr) const {
1378  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1379  }
1380 
1381  /// Return true if the MachineInstr fully defines the specified register.
1382  /// If TargetRegisterInfo is passed, then it also checks
1383  /// if there is a def of a super-register.
1384  /// NOTE: It's ignoring subreg indices on virtual registers.
1386  const TargetRegisterInfo *TRI = nullptr) const {
1387  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1388  }
1389 
1390  /// Return true if the MachineInstr modifies (fully define or partially
1391  /// define) the specified register.
1392  /// NOTE: It's ignoring subreg indices on virtual registers.
1394  const TargetRegisterInfo *TRI = nullptr) const {
1395  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1396  }
1397 
1398  /// Returns true if the register is dead in this machine instruction.
1399  /// If TargetRegisterInfo is passed, then it also checks
1400  /// if there is a dead def of a super-register.
1402  const TargetRegisterInfo *TRI = nullptr) const {
1403  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1404  }
1405 
1406  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1407  /// the given register (not considering sub/super-registers).
1409 
1410  /// Returns the operand index that is a use of the specific register or -1
1411  /// if it is not found. It further tightens the search criteria to a use
1412  /// that kills the register if isKill is true.
1413  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1414  const TargetRegisterInfo *TRI = nullptr) const;
1415 
1416  /// Wrapper for findRegisterUseOperandIdx, it returns
1417  /// a pointer to the MachineOperand rather than an index.
1419  const TargetRegisterInfo *TRI = nullptr) {
1420  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1421  return (Idx == -1) ? nullptr : &getOperand(Idx);
1422  }
1423 
1425  Register Reg, bool isKill = false,
1426  const TargetRegisterInfo *TRI = nullptr) const {
1427  return const_cast<MachineInstr *>(this)->
1429  }
1430 
1431  /// Returns the operand index that is a def of the specified register or
1432  /// -1 if it is not found. If isDead is true, defs that are not dead are
1433  /// skipped. If Overlap is true, then it also looks for defs that merely
1434  /// overlap the specified register. If TargetRegisterInfo is non-null,
1435  /// then it also checks if there is a def of a super-register.
1436  /// This may also return a register mask operand when Overlap is true.
1438  bool isDead = false, bool Overlap = false,
1439  const TargetRegisterInfo *TRI = nullptr) const;
1440 
1441  /// Wrapper for findRegisterDefOperandIdx, it returns
1442  /// a pointer to the MachineOperand rather than an index.
1443  MachineOperand *
1444  findRegisterDefOperand(Register Reg, bool isDead = false,
1445  bool Overlap = false,
1446  const TargetRegisterInfo *TRI = nullptr) {
1447  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1448  return (Idx == -1) ? nullptr : &getOperand(Idx);
1449  }
1450 
1451  const MachineOperand *
1452  findRegisterDefOperand(Register Reg, bool isDead = false,
1453  bool Overlap = false,
1454  const TargetRegisterInfo *TRI = nullptr) const {
1455  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1456  Reg, isDead, Overlap, TRI);
1457  }
1458 
1459  /// Find the index of the first operand in the
1460  /// operand list that is used to represent the predicate. It returns -1 if
1461  /// none is found.
1462  int findFirstPredOperandIdx() const;
1463 
1464  /// Find the index of the flag word operand that
1465  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1466  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1467  ///
1468  /// If GroupNo is not NULL, it will receive the number of the operand group
1469  /// containing OpIdx.
1470  ///
1471  /// The flag operand is an immediate that can be decoded with methods like
1472  /// InlineAsm::hasRegClassConstraint().
1473  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1474 
1475  /// Compute the static register class constraint for operand OpIdx.
1476  /// For normal instructions, this is derived from the MCInstrDesc.
1477  /// For inline assembly it is derived from the flag words.
1478  ///
1479  /// Returns NULL if the static register class constraint cannot be
1480  /// determined.
1481  const TargetRegisterClass*
1482  getRegClassConstraint(unsigned OpIdx,
1483  const TargetInstrInfo *TII,
1484  const TargetRegisterInfo *TRI) const;
1485 
1486  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1487  /// the given \p CurRC.
1488  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1489  /// instructions inside the bundle will be taken into account. In other words,
1490  /// this method accumulates all the constraints of the operand of this MI and
1491  /// the related bundle if MI is a bundle or inside a bundle.
1492  ///
1493  /// Returns the register class that satisfies both \p CurRC and the
1494  /// constraints set by MI. Returns NULL if such a register class does not
1495  /// exist.
1496  ///
1497  /// \pre CurRC must not be NULL.
1499  Register Reg, const TargetRegisterClass *CurRC,
1500  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1501  bool ExploreBundle = false) const;
1502 
1503  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1504  /// to the given \p CurRC.
1505  ///
1506  /// Returns the register class that satisfies both \p CurRC and the
1507  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1508  /// does not exist.
1509  ///
1510  /// \pre CurRC must not be NULL.
1511  /// \pre The operand at \p OpIdx must be a register.
1512  const TargetRegisterClass *
1513  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1514  const TargetInstrInfo *TII,
1515  const TargetRegisterInfo *TRI) const;
1516 
1517  /// Add a tie between the register operands at DefIdx and UseIdx.
1518  /// The tie will cause the register allocator to ensure that the two
1519  /// operands are assigned the same physical register.
1520  ///
1521  /// Tied operands are managed automatically for explicit operands in the
1522  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1523  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1524 
1525  /// Given the index of a tied register operand, find the
1526  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1527  /// index of the tied operand which must exist.
1528  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1529 
1530  /// Given the index of a register def operand,
1531  /// check if the register def is tied to a source operand, due to either
1532  /// two-address elimination or inline assembly constraints. Returns the
1533  /// first tied use operand index by reference if UseOpIdx is not null.
1534  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1535  unsigned *UseOpIdx = nullptr) const {
1536  const MachineOperand &MO = getOperand(DefOpIdx);
1537  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1538  return false;
1539  if (UseOpIdx)
1540  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1541  return true;
1542  }
1543 
1544  /// Return true if the use operand of the specified index is tied to a def
1545  /// operand. It also returns the def operand index by reference if DefOpIdx
1546  /// is not null.
1547  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1548  unsigned *DefOpIdx = nullptr) const {
1549  const MachineOperand &MO = getOperand(UseOpIdx);
1550  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1551  return false;
1552  if (DefOpIdx)
1553  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1554  return true;
1555  }
1556 
1557  /// Clears kill flags on all operands.
1558  void clearKillInfo();
1559 
1560  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1561  /// properly composing subreg indices where necessary.
1562  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1563  const TargetRegisterInfo &RegInfo);
1564 
1565  /// We have determined MI kills a register. Look for the
1566  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1567  /// add a implicit operand if it's not found. Returns true if the operand
1568  /// exists / is added.
1569  bool addRegisterKilled(Register IncomingReg,
1570  const TargetRegisterInfo *RegInfo,
1571  bool AddIfNotFound = false);
1572 
1573  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1574  /// all aliasing registers.
1576 
1577  /// We have determined MI defined a register without a use.
1578  /// Look for the operand that defines it and mark it as IsDead. If
1579  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1580  /// true if the operand exists / is added.
1582  bool AddIfNotFound = false);
1583 
1584  /// Clear all dead flags on operands defining register @p Reg.
1586 
1587  /// Mark all subregister defs of register @p Reg with the undef flag.
1588  /// This function is used when we determined to have a subregister def in an
1589  /// otherwise undefined super register.
1590  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1591 
1592  /// We have determined MI defines a register. Make sure there is an operand
1593  /// defining Reg.
1595  const TargetRegisterInfo *RegInfo = nullptr);
1596 
1597  /// Mark every physreg used by this instruction as
1598  /// dead except those in the UsedRegs list.
1599  ///
1600  /// On instructions with register mask operands, also add implicit-def
1601  /// operands for all registers in UsedRegs.
1603  const TargetRegisterInfo &TRI);
1604 
1605  /// Return true if it is safe to move this instruction. If
1606  /// SawStore is set to true, it means that there is a store (or call) between
1607  /// the instruction's location and its intended destination.
1608  bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1609 
1610  /// Returns true if this instruction's memory access aliases the memory
1611  /// access of Other.
1612  //
1613  /// Assumes any physical registers used to compute addresses
1614  /// have the same value for both instructions. Returns false if neither
1615  /// instruction writes to memory.
1616  ///
1617  /// @param AA Optional alias analysis, used to compare memory operands.
1618  /// @param Other MachineInstr to check aliasing against.
1619  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1620  bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1621 
1622  /// Return true if this instruction may have an ordered
1623  /// or volatile memory reference, or if the information describing the memory
1624  /// reference is not available. Return false if it is known to have no
1625  /// ordered or volatile memory references.
1626  bool hasOrderedMemoryRef() const;
1627 
1628  /// Return true if this load instruction never traps and points to a memory
1629  /// location whose value doesn't change during the execution of this function.
1630  ///
1631  /// Examples include loading a value from the constant pool or from the
1632  /// argument area of a function (if it does not change). If the instruction
1633  /// does multiple loads, this returns true only if all of the loads are
1634  /// dereferenceable and invariant.
1635  bool isDereferenceableInvariantLoad(AAResults *AA) const;
1636 
1637  /// If the specified instruction is a PHI that always merges together the
1638  /// same virtual register, return the register, otherwise return 0.
1639  unsigned isConstantValuePHI() const;
1640 
1641  /// Return true if this instruction has side effects that are not modeled
1642  /// by mayLoad / mayStore, etc.
1643  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1644  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1645  /// INLINEASM instruction, in which case the side effect property is encoded
1646  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1647  ///
1648  bool hasUnmodeledSideEffects() const;
1649 
1650  /// Returns true if it is illegal to fold a load across this instruction.
1651  bool isLoadFoldBarrier() const;
1652 
1653  /// Return true if all the defs of this instruction are dead.
1654  bool allDefsAreDead() const;
1655 
1656  /// Return a valid size if the instruction is a spill instruction.
1658 
1659  /// Return a valid size if the instruction is a folded spill instruction.
1661 
1662  /// Return a valid size if the instruction is a restore instruction.
1664 
1665  /// Return a valid size if the instruction is a folded restore instruction.
1668 
1669  /// Copy implicit register operands from specified
1670  /// instruction to this instruction.
1671  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1672 
1673  /// Debugging support
1674  /// @{
1675  /// Determine the generic type to be printed (if needed) on uses and defs.
1676  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1677  const MachineRegisterInfo &MRI) const;
1678 
1679  /// Return true when an instruction has tied register that can't be determined
1680  /// by the instruction's descriptor. This is useful for MIR printing, to
1681  /// determine whether we need to print the ties or not.
1682  bool hasComplexRegisterTies() const;
1683 
1684  /// Print this MI to \p OS.
1685  /// Don't print information that can be inferred from other instructions if
1686  /// \p IsStandalone is false. It is usually true when only a fragment of the
1687  /// function is printed.
1688  /// Only print the defs and the opcode if \p SkipOpers is true.
1689  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1690  /// Otherwise, also print the debug loc, with a terminating newline.
1691  /// \p TII is used to print the opcode name. If it's not present, but the
1692  /// MI is in a function, the opcode will be printed using the function's TII.
1693  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1694  bool SkipDebugLoc = false, bool AddNewLine = true,
1695  const TargetInstrInfo *TII = nullptr) const;
1696  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1697  bool SkipOpers = false, bool SkipDebugLoc = false,
1698  bool AddNewLine = true,
1699  const TargetInstrInfo *TII = nullptr) const;
1700  void dump() const;
1701  /// Print on dbgs() the current instruction and the instructions defining its
1702  /// operands and so on until we reach \p MaxDepth.
1703  void dumpr(const MachineRegisterInfo &MRI,
1704  unsigned MaxDepth = UINT_MAX) const;
1705  /// @}
1706 
1707  //===--------------------------------------------------------------------===//
1708  // Accessors used to build up machine instructions.
1709 
1710  /// Add the specified operand to the instruction. If it is an implicit
1711  /// operand, it is added to the end of the operand list. If it is an
1712  /// explicit operand it is added at the end of the explicit operand list
1713  /// (before the first implicit operand).
1714  ///
1715  /// MF must be the machine function that was used to allocate this
1716  /// instruction.
1717  ///
1718  /// MachineInstrBuilder provides a more convenient interface for creating
1719  /// instructions and adding operands.
1720  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1721 
1722  /// Add an operand without providing an MF reference. This only works for
1723  /// instructions that are inserted in a basic block.
1724  ///
1725  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1726  /// preferred.
1727  void addOperand(const MachineOperand &Op);
1728 
1729  /// Replace the instruction descriptor (thus opcode) of
1730  /// the current instruction with a new one.
1731  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1732 
1733  /// Replace current source information with new such.
1734  /// Avoid using this, the constructor argument is preferable.
1736  debugLoc = std::move(dl);
1737  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1738  }
1739 
1740  /// Erase an operand from an instruction, leaving it with one
1741  /// fewer operand than it started with.
1742  void RemoveOperand(unsigned OpNo);
1743 
1744  /// Clear this MachineInstr's memory reference descriptor list. This resets
1745  /// the memrefs to their most conservative state. This should be used only
1746  /// as a last resort since it greatly pessimizes our knowledge of the memory
1747  /// access performed by the instruction.
1748  void dropMemRefs(MachineFunction &MF);
1749 
1750  /// Assign this MachineInstr's memory reference descriptor list.
1751  ///
1752  /// Unlike other methods, this *will* allocate them into a new array
1753  /// associated with the provided `MachineFunction`.
1755 
1756  /// Add a MachineMemOperand to the machine instruction.
1757  /// This function should be used only occasionally. The setMemRefs function
1758  /// is the primary method for setting up a MachineInstr's MemRefs list.
1760 
1761  /// Clone another MachineInstr's memory reference descriptor list and replace
1762  /// ours with it.
1763  ///
1764  /// Note that `*this` may be the incoming MI!
1765  ///
1766  /// Prefer this API whenever possible as it can avoid allocations in common
1767  /// cases.
1768  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1769 
1770  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1771  /// list and replace ours with it.
1772  ///
1773  /// Note that `*this` may be one of the incoming MIs!
1774  ///
1775  /// Prefer this API whenever possible as it can avoid allocations in common
1776  /// cases.
1779 
1780  /// Set a symbol that will be emitted just prior to the instruction itself.
1781  ///
1782  /// Setting this to a null pointer will remove any such symbol.
1783  ///
1784  /// FIXME: This is not fully implemented yet.
1786 
1787  /// Set a symbol that will be emitted just after the instruction itself.
1788  ///
1789  /// Setting this to a null pointer will remove any such symbol.
1790  ///
1791  /// FIXME: This is not fully implemented yet.
1793 
1794  /// Clone another MachineInstr's pre- and post- instruction symbols and
1795  /// replace ours with it.
1797 
1798  /// Set a marker on instructions that denotes where we should create and emit
1799  /// heap alloc site labels. This waits until after instruction selection and
1800  /// optimizations to create the label, so it should still work if the
1801  /// instruction is removed or duplicated.
1802  void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1803 
1804  /// Return the MIFlags which represent both MachineInstrs. This
1805  /// should be used when merging two MachineInstrs into one. This routine does
1806  /// not modify the MIFlags of this MachineInstr.
1807  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1808 
1810 
1811  /// Copy all flags to MachineInst MIFlags
1812  void copyIRFlags(const Instruction &I);
1813 
1814  /// Break any tie involving OpIdx.
1815  void untieRegOperand(unsigned OpIdx) {
1816  MachineOperand &MO = getOperand(OpIdx);
1817  if (MO.isReg() && MO.isTied()) {
1818  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1819  MO.TiedTo = 0;
1820  }
1821  }
1822 
1823  /// Add all implicit def and use operands to this instruction.
1825 
1826  /// Scan instructions immediately following MI and collect any matching
1827  /// DBG_VALUEs.
1829 
1830  /// Find all DBG_VALUEs that point to the register def in this instruction
1831  /// and point them to \p Reg instead.
1833 
1834  /// Returns the Intrinsic::ID for this instruction.
1835  /// \pre Must have an intrinsic ID operand.
1836  unsigned getIntrinsicID() const {
1838  }
1839 
1840  /// Sets all register debug operands in this debug value instruction to be
1841  /// undef.
1843  assert(isDebugValue() && "Must be a debug value instruction.");
1844  for (MachineOperand &MO : debug_operands()) {
1845  if (MO.isReg()) {
1846  MO.setReg(0);
1847  MO.setSubReg(0);
1848  }
1849  }
1850  }
1851 
1853  assert(isPseudoProbe() && "Must be a pseudo probe instruction");
1855  }
1856 
1858  assert(isPseudoProbe() && "Must be a pseudo probe instruction");
1859  MachineOperand &AttrOperand = getOperand(3);
1860  AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr);
1861  }
1862 
1863 private:
1864  /// If this instruction is embedded into a MachineFunction, return the
1865  /// MachineRegisterInfo object for the current function, otherwise
1866  /// return null.
1867  MachineRegisterInfo *getRegInfo();
1868 
1869  /// Unlink all of the register operands in this instruction from their
1870  /// respective use lists. This requires that the operands already be on their
1871  /// use lists.
1872  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1873 
1874  /// Add all of the register operands in this instruction from their
1875  /// respective use lists. This requires that the operands not be on their
1876  /// use lists yet.
1877  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1878 
1879  /// Slow path for hasProperty when we're dealing with a bundle.
1880  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1881 
1882  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1883  /// this MI and the given operand index \p OpIdx.
1884  /// If the related operand does not constrained Reg, this returns CurRC.
1885  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1886  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1887  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1888 
1889  /// Stores extra instruction information inline or allocates as ExtraInfo
1890  /// based on the number of pointers.
1891  void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1892  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1893  MDNode *HeapAllocMarker);
1894 };
1895 
1896 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1897 /// instruction rather than by pointer value.
1898 /// The hashing and equality testing functions ignore definitions so this is
1899 /// useful for CSE, etc.
1901  static inline MachineInstr *getEmptyKey() {
1902  return nullptr;
1903  }
1904 
1905  static inline MachineInstr *getTombstoneKey() {
1906  return reinterpret_cast<MachineInstr*>(-1);
1907  }
1908 
1909  static unsigned getHashValue(const MachineInstr* const &MI);
1910 
1911  static bool isEqual(const MachineInstr* const &LHS,
1912  const MachineInstr* const &RHS) {
1913  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1914  LHS == getEmptyKey() || LHS == getTombstoneKey())
1915  return LHS == RHS;
1916  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1917  }
1918 };
1919 
1920 //===----------------------------------------------------------------------===//
1921 // Debugging Support
1922 
1924  MI.print(OS);
1925  return OS;
1926 }
1927 
1928 } // end namespace llvm
1929 
1930 #endif // LLVM_CODEGEN_MACHINEINSTR_H
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1205
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:768
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:859
llvm::MachineInstr::getNumDebugOperands
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:484
llvm::MachineInstr::isBranch
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:844
llvm::MachineInstr::setDebugValueUndef
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
Definition: MachineInstr.h:1842
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:152
TrailingObjects.h
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2010
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2044
llvm::MachineInstr::isUndefDebugValue
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
Definition: MachineInstr.h:1233
llvm::MachineInstr::isExtractSubregLike
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MachineInstr.h:969
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2372
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:655
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1957
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:158
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:672
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:163
llvm
Definition: AllocatorList.h:23
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1248
llvm::MachineInstr::getDebugOperandIndex
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:550
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:850
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2070
llvm::MachineInstr::usesCustomInsertionHook
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:1076
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1164
llvm::TrailingObjects< ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode * >::TrailingObjects
TrailingObjects(const TrailingObjects &)=delete
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:77
llvm::MachineInstr::explicit_operands
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:613
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:910
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1232
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:629
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1017
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:164
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:726
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:697
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1163
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:730
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:534
llvm::MachineInstr::isCompare
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:881
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:303
llvm::MachineInstr::isEHScopeReturn
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:808
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:672
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:169
llvm::MachineInstr::isRegSequenceLike
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:954
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:994
llvm::ArrayRef::iterator
const_pointer iterator
Definition: ArrayRef.h:48
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1223
llvm::MachineInstr::implicit_operands
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:621
ilist.h
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1131
InlineAsm.h
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:171
llvm::ilist_node_with_parent
An ilist node that can access its parent list.
Definition: ilist_node.h:256
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MachineInstr::clearAsmPrinterFlags
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:307
llvm::MachineInstr::isMoveImmediate
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:887
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:978
llvm::MachineInstr::addPseudoProbeAttribute
void addPseudoProbeAttribute(PseudoProbeAttributes Attr)
Definition: MachineInstr.h:1857
llvm::MachineInstr::isInsertSubregLike
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MachineInstr.h:983
llvm::MachineInstr::isDebugOffsetImm
bool isDebugOffsetImm() const
Definition: MachineInstr.h:1217
llvm::MachineInstr::NoSchedComment
@ NoSchedComment
Definition: MachineInstr.h:76
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:759
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1192
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2026
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1476
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1444
llvm::MachineInstr::isEHLabel
bool isEHLabel() const
Definition: MachineInstr.h:1177
llvm::ilist_callback_traits
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:64
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:644
llvm::MachineInstr::hasPostISelHook
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:1084
llvm::MachineInstr::isBundled
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:391
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineInstr::operands_begin
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:604
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:475
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::PseudoProbeAttributes
PseudoProbeAttributes
Definition: PseudoProbe.h:30
llvm::filter_iterator_impl
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:412
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:98
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::findRegisterUseOperand
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1418
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:980
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::Optional< unsigned >
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1279
llvm::MachineInstr::peekDebugInstrNum
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:460
llvm::MachineInstr::setDebugLoc
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
Definition: MachineInstr.h:1735
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:182
llvm::MachineInstr::operands_end
mop_iterator operands_end()
Definition: MachineInstr.h:602
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:786
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2559
llvm::MachineInstr::uses
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:659
llvm::MachineInstr::hasDebugOperandForReg
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:517
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:535
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineInstr::getMF
MachineFunction * getMF()
Definition: MachineInstr.h:298
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:712
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:838
llvm::MachineInstr::isPreISelOpcode
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:778
llvm::MachineInstrExpressionTrait::getTombstoneKey
static MachineInstr * getTombstoneKey()
Definition: MachineInstr.h:1905
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1376
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1547
llvm::MachineInstr::isInsertSubreg
bool isInsertSubreg() const
Definition: MachineInstr.h:1263
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:556
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:970
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1183
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1126
llvm::MachineInstr::readsVirtualRegister
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:1363
llvm::MachineInstr::getParent
MachineBasicBlock * getParent()
Definition: MachineInstr.h:287
llvm::MachineInstrExpressionTrait::isEqual
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Definition: MachineInstr.h:1911
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:325
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:528
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:866
llvm::MachineInstr::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:1115
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:153
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1274
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::MachineInstr::isLabel
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:1184
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:812
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineInstr::isGCLabel
bool isGCLabel() const
Definition: MachineInstr.h:1178
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:505
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::MachineInstr::isPredicable
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:874
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3041
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:371
llvm::adl_end
decltype(auto) adl_end(ContainerTy &&container)
Definition: STLExtras.h:242
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2346
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1202
llvm::MachineInstr::implicit_operands
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:624
llvm::MachineInstr::isInsideBundle
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:385
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1129
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:168
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:217
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:424
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1328
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::isIdentityCopy
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:1298
MCSymbol.h
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:667
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:786
llvm::MachineInstr::isDebugOrPseudoInstr
bool isDebugOrPseudoInstr() const
Definition: MachineInstr.h:1213
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:104
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1210
llvm::MachineInstr::CommentFlag
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:74
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1878
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:90
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:151
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::isPseudo
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:798
llvm::MachineInstr::getAsmPrinterFlags
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:304
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:346
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1209
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:720
llvm::MachineInstr::getIntrinsicID
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
Definition: MachineInstr.h:1836
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:968
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineInstr::isConvertibleTo3Addr
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:1064
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:197
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:795
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:475
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:592
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:765
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:104
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1469
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1385
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:226
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1570
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:179
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:92
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1376
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1199
llvm::MachineInstrExpressionTrait
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
Definition: MachineInstr.h:1900
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:166
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:756
llvm::MachineInstr::isConvergent
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:917
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:165
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:167
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:89
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:572
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:177
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:230
llvm::MachineInstr::~MachineInstr
~MachineInstr()=delete
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:150
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1515
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:423
llvm::MachineInstr::getDebugOperand
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:497
llvm::MachineInstr::clearAsmPrinterFlag
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:320
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:157
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2084
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:871
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:715
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:75
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:154
llvm::MachineInstr::findRegisterDefOperand
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1452
llvm::MachineInstr::isCommutable
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MachineInstr.h:1046
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:843
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:390
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:100
llvm::MachineInstr::getNumImplicitOperands
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:572
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:67
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2018
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineInstr::operands_begin
mop_iterator operands_begin()
Definition: MachineInstr.h:601
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:225
llvm::MachineInstr::isAsCheapAsAMove
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:1104
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:757
llvm::MachineInstr::getDebugOffset
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:427
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:175
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:68
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2281
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:339
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:161
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:777
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1944
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1012
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:176
llvm::MachineInstr::isMoveReg
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:893
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:704
iterator_range.h
llvm::MachineInstr::operator=
MachineInstr & operator=(const MachineInstr &)=delete
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1243
llvm::MachineInstr::hasDelaySlot
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:928
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:804
llvm::MachineInstr::isMetaInstruction
bool isMetaInstruction() const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:1305
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1398
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:802
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:577
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1355
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1133
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1540
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:984
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:702
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:855
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:106
llvm::MachineInstr::isRegTiedToUseOperand
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
Definition: MachineInstr.h:1534
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:810
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:561
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:174
llvm::MachineInstr::getUsedDebugRegs
SmallSet< Register, 4 > getUsedDebugRegs() const
Definition: MachineInstr.h:506
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:246
RegInfo
Definition: AMDGPUAsmParser.cpp:2355
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1489
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineInstr::getPseudoProbeAttribute
PseudoProbeAttributes getPseudoProbeAttribute() const
Definition: MachineInstr.h:1852
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1249
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1815
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:742
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2365
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:173
llvm::MachineInstr::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:1125
uint32_t
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1069
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:110
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1577
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:836
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1208
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:718
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:159
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:224
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1197
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::MachineInstr::findRegisterUseOperand
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1424
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:880
llvm::make_filter_range
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:486
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1188
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:853
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::ArrayRecycler
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
llvm::MachineInstr::isExtractSubreg
bool isExtractSubreg() const
Definition: MachineInstr.h:1287
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:148
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:180
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:948
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1393
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:940
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1271
llvm::MachineInstr::operands_end
const_mop_iterator operands_end() const
Definition: MachineInstr.h:605
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:528
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1293
uint16_t
llvm::MachineInstr::explicit_uses
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:666
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:514
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:315
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1007
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1457
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:156
llvm::MachineInstr::getOperand
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:492
llvm::adl_begin
decltype(auto) adl_begin(ContainerTy &&container)
Definition: STLExtras.h:237
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:973
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:875
llvm::MachineInstr::explicit_operands
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:617
llvm::TrailingObjects
See the file comment for details on the usage of the TrailingObjects type.
Definition: TrailingObjects.h:212
PseudoProbe.h
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:707
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:96
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:160
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:397
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:709
llvm::MachineInstr::getDebugOperand
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:501
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1275
llvm::MachineInstr::getAsmPrinterFlag
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:310
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:682
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1209
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:755
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:149
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:541
llvm::MachineInstr::explicit_uses
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:662
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1041
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:102
ArrayRecycler.h
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:146
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:401
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::MachineInstr::isMSInlineAsm
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific,...
Definition: MachineInstr.h:1256
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::MachineInstr::CheckDefs
@ CheckDefs
Definition: MachineInstr.h:1130
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::MachineInstr::debug_operands
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:636
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:363
llvm::MachineInstr::isTransient
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:1328
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:147
llvm::MachineInstr::isDebugOperand
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:546
ilist_node.h
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:94
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:679
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1498
llvm::SmallVectorImpl< unsigned >
MachineOperand.h
DenseMapInfo.h
llvm::MachineInstr::isConditionalBranch
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:858
llvm::MachineInstr::isBitcast
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:898
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1731
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:172
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstrExpressionTrait::getEmptyKey
static MachineInstr * getEmptyKey()
Definition: MachineInstr.h:1901
llvm::MachineInstr::isSelect
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:903
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2354
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:919
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1132
llvm::MachineInstr::isAnnotationLabel
bool isAnnotationLabel() const
Definition: MachineInstr.h:1179
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3121
llvm::MachineInstr::operands
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:610
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1247
llvm::MachineInstr::setDebugInstrNum
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:464
llvm::MachineInstr::isSubregToReg
bool isSubregToReg() const
Definition: MachineInstr.h:1267
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstr::isRematerializable
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:1092
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1283
PointerSumType.h
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:178
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1027
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1401
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1202
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1444
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstr::hasOptionalDef
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:792
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:827
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:754
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:607
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:155
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:992
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:181
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:490
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2335
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:745
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:165
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:335
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1167
llvm::MachineInstr::defs
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:649
SmallSet.h
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2297
llvm::LLT
Definition: LowLevelTypeImpl.h:40