LLVM  15.0.0git
MachineInstr.h
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1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/ilist.h"
22 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSymbol.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <utility>
37 
38 namespace llvm {
39 
40 class DILabel;
41 class Instruction;
42 class MDNode;
43 class AAResults;
44 template <typename T> class ArrayRef;
45 class DIExpression;
46 class DILocalVariable;
47 class MachineBasicBlock;
48 class MachineFunction;
49 class MachineRegisterInfo;
50 class ModuleSlotTracker;
51 class raw_ostream;
52 template <typename T> class SmallVectorImpl;
53 class SmallBitVector;
54 class StringRef;
55 class TargetInstrInfo;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 
59 //===----------------------------------------------------------------------===//
60 /// Representation of each machine instruction.
61 ///
62 /// This class isn't a POD type, but it must have a trivial destructor. When a
63 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
64 /// without having their destructor called.
65 ///
67  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
68  ilist_sentinel_tracking<true>> {
69 public:
71 
72  /// Flags to specify different kinds of comments to output in
73  /// assembly code. These flags carry semantic information not
74  /// otherwise easily derivable from the IR text.
75  ///
76  enum CommentFlag {
77  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
79  TAsmComments = 0x4 // Target Asm comments should start from this value.
80  };
81 
82  enum MIFlag {
83  NoFlags = 0,
84  FrameSetup = 1 << 0, // Instruction is used as a part of
85  // function frame setup code.
86  FrameDestroy = 1 << 1, // Instruction is used as a part of
87  // function frame destruction code.
88  BundledPred = 1 << 2, // Instruction has bundled predecessors.
89  BundledSucc = 1 << 3, // Instruction has bundled successors.
90  FmNoNans = 1 << 4, // Instruction does not support Fast
91  // math nan values.
92  FmNoInfs = 1 << 5, // Instruction does not support Fast
93  // math infinity values.
94  FmNsz = 1 << 6, // Instruction is not required to retain
95  // signed zero values.
96  FmArcp = 1 << 7, // Instruction supports Fast math
97  // reciprocal approximations.
98  FmContract = 1 << 8, // Instruction supports Fast math
99  // contraction operations like fma.
100  FmAfn = 1 << 9, // Instruction may map to Fast math
101  // intrinsic approximation.
102  FmReassoc = 1 << 10, // Instruction supports Fast math
103  // reassociation of operand order.
104  NoUWrap = 1 << 11, // Instruction supports binary operator
105  // no unsigned wrap.
106  NoSWrap = 1 << 12, // Instruction supports binary operator
107  // no signed wrap.
108  IsExact = 1 << 13, // Instruction supports division is
109  // known to be exact.
110  NoFPExcept = 1 << 14, // Instruction does not raise
111  // floatint-point exceptions.
112  NoMerge = 1 << 15, // Passes that drop source location info
113  // (e.g. branch folding) should skip
114  // this instruction.
115  };
116 
117 private:
118  const MCInstrDesc *MCID; // Instruction descriptor.
119  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
120 
121  // Operands are allocated by an ArrayRecycler.
122  MachineOperand *Operands = nullptr; // Pointer to the first operand.
123  unsigned NumOperands = 0; // Number of operands on instruction.
124 
125  uint16_t Flags = 0; // Various bits of additional
126  // information about machine
127  // instruction.
128 
129  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
130  // the AsmPrinter to emit helpful
131  // comments. This is *not* semantic
132  // information. Do not use this for
133  // anything other than to convey comment
134  // information to AsmPrinter.
135 
136  // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
137  // to properly pack.
138  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
139  OperandCapacity CapOperands; // Capacity of the Operands array.
140 
141  /// Internal implementation detail class that provides out-of-line storage for
142  /// extra info used by the machine instruction when this info cannot be stored
143  /// in-line within the instruction itself.
144  ///
145  /// This has to be defined eagerly due to the implementation constraints of
146  /// `PointerSumType` where it is used.
147  class ExtraInfo final
148  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
149  public:
150  static ExtraInfo *create(BumpPtrAllocator &Allocator,
152  MCSymbol *PreInstrSymbol = nullptr,
153  MCSymbol *PostInstrSymbol = nullptr,
154  MDNode *HeapAllocMarker = nullptr) {
155  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
156  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
157  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
158  auto *Result = new (Allocator.Allocate(
159  totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
160  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
161  HasHeapAllocMarker),
162  alignof(ExtraInfo)))
163  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
164  HasHeapAllocMarker);
165 
166  // Copy the actual data into the trailing objects.
167  std::copy(MMOs.begin(), MMOs.end(),
168  Result->getTrailingObjects<MachineMemOperand *>());
169 
170  if (HasPreInstrSymbol)
171  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
172  if (HasPostInstrSymbol)
173  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
174  PostInstrSymbol;
175  if (HasHeapAllocMarker)
176  Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
177 
178  return Result;
179  }
180 
181  ArrayRef<MachineMemOperand *> getMMOs() const {
182  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
183  }
184 
185  MCSymbol *getPreInstrSymbol() const {
186  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
187  }
188 
189  MCSymbol *getPostInstrSymbol() const {
190  return HasPostInstrSymbol
191  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
192  : nullptr;
193  }
194 
195  MDNode *getHeapAllocMarker() const {
196  return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
197  }
198 
199  private:
200  friend TrailingObjects;
201 
202  // Description of the extra info, used to interpret the actual optional
203  // data appended.
204  //
205  // Note that this is not terribly space optimized. This leaves a great deal
206  // of flexibility to fit more in here later.
207  const int NumMMOs;
208  const bool HasPreInstrSymbol;
209  const bool HasPostInstrSymbol;
210  const bool HasHeapAllocMarker;
211 
212  // Implement the `TrailingObjects` internal API.
213  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
214  return NumMMOs;
215  }
216  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
217  return HasPreInstrSymbol + HasPostInstrSymbol;
218  }
219  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
220  return HasHeapAllocMarker;
221  }
222 
223  // Just a boring constructor to allow us to initialize the sizes. Always use
224  // the `create` routine above.
225  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
226  bool HasHeapAllocMarker)
227  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
228  HasPostInstrSymbol(HasPostInstrSymbol),
229  HasHeapAllocMarker(HasHeapAllocMarker) {}
230  };
231 
232  /// Enumeration of the kinds of inline extra info available. It is important
233  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
234  /// it accessible as an `ArrayRef`.
235  enum ExtraInfoInlineKinds {
236  EIIK_MMO = 0,
237  EIIK_PreInstrSymbol,
238  EIIK_PostInstrSymbol,
239  EIIK_OutOfLine
240  };
241 
242  // We store extra information about the instruction here. The common case is
243  // expected to be nothing or a single pointer (typically a MMO or a symbol).
244  // We work to optimize this common case by storing it inline here rather than
245  // requiring a separate allocation, but we fall back to an allocation when
246  // multiple pointers are needed.
247  PointerSumType<ExtraInfoInlineKinds,
248  PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
249  PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
250  PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
251  PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
252  Info;
253 
254  DebugLoc DbgLoc; // Source line information.
255 
256  /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
257  /// defined by this instruction.
258  unsigned DebugInstrNum;
259 
260  // Intrusive list support
261  friend struct ilist_traits<MachineInstr>;
263  void setParent(MachineBasicBlock *P) { Parent = P; }
264 
265  /// This constructor creates a copy of the given
266  /// MachineInstr in the given MachineFunction.
268 
269  /// This constructor create a MachineInstr and add the implicit operands.
270  /// It reserves space for number of operands specified by
271  /// MCInstrDesc. An explicit DebugLoc is supplied.
273  bool NoImp = false);
274 
275  // MachineInstrs are pool-allocated and owned by MachineFunction.
276  friend class MachineFunction;
277 
278  void
279  dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
280  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
281 
282 public:
283  MachineInstr(const MachineInstr &) = delete;
284  MachineInstr &operator=(const MachineInstr &) = delete;
285  // Use MachineFunction::DeleteMachineInstr() instead.
286  ~MachineInstr() = delete;
287 
288  const MachineBasicBlock* getParent() const { return Parent; }
289  MachineBasicBlock* getParent() { return Parent; }
290 
291  /// Move the instruction before \p MovePos.
292  void moveBefore(MachineInstr *MovePos);
293 
294  /// Return the function that contains the basic block that this instruction
295  /// belongs to.
296  ///
297  /// Note: this is undefined behaviour if the instruction does not have a
298  /// parent.
299  const MachineFunction *getMF() const;
301  return const_cast<MachineFunction *>(
302  static_cast<const MachineInstr *>(this)->getMF());
303  }
304 
305  /// Return the asm printer flags bitvector.
306  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
307 
308  /// Clear the AsmPrinter bitvector.
309  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
310 
311  /// Return whether an AsmPrinter flag is set.
313  return AsmPrinterFlags & Flag;
314  }
315 
316  /// Set a flag for the AsmPrinter.
317  void setAsmPrinterFlag(uint8_t Flag) {
318  AsmPrinterFlags |= Flag;
319  }
320 
321  /// Clear specific AsmPrinter flags.
323  AsmPrinterFlags &= ~Flag;
324  }
325 
326  /// Return the MI flags bitvector.
327  uint16_t getFlags() const {
328  return Flags;
329  }
330 
331  /// Return whether an MI flag is set.
332  bool getFlag(MIFlag Flag) const {
333  return Flags & Flag;
334  }
335 
336  /// Set a MI flag.
338  Flags |= (uint16_t)Flag;
339  }
340 
341  void setFlags(unsigned flags) {
342  // Filter out the automatically maintained flags.
343  unsigned Mask = BundledPred | BundledSucc;
344  Flags = (Flags & Mask) | (flags & ~Mask);
345  }
346 
347  /// clearFlag - Clear a MI flag.
349  Flags &= ~((uint16_t)Flag);
350  }
351 
352  /// Return true if MI is in a bundle (but not the first MI in a bundle).
353  ///
354  /// A bundle looks like this before it's finalized:
355  /// ----------------
356  /// | MI |
357  /// ----------------
358  /// |
359  /// ----------------
360  /// | MI * |
361  /// ----------------
362  /// |
363  /// ----------------
364  /// | MI * |
365  /// ----------------
366  /// In this case, the first MI starts a bundle but is not inside a bundle, the
367  /// next 2 MIs are considered "inside" the bundle.
368  ///
369  /// After a bundle is finalized, it looks like this:
370  /// ----------------
371  /// | Bundle |
372  /// ----------------
373  /// |
374  /// ----------------
375  /// | MI * |
376  /// ----------------
377  /// |
378  /// ----------------
379  /// | MI * |
380  /// ----------------
381  /// |
382  /// ----------------
383  /// | MI * |
384  /// ----------------
385  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
386  /// a bundle, but the next three MIs are.
387  bool isInsideBundle() const {
388  return getFlag(BundledPred);
389  }
390 
391  /// Return true if this instruction part of a bundle. This is true
392  /// if either itself or its following instruction is marked "InsideBundle".
393  bool isBundled() const {
394  return isBundledWithPred() || isBundledWithSucc();
395  }
396 
397  /// Return true if this instruction is part of a bundle, and it is not the
398  /// first instruction in the bundle.
399  bool isBundledWithPred() const { return getFlag(BundledPred); }
400 
401  /// Return true if this instruction is part of a bundle, and it is not the
402  /// last instruction in the bundle.
403  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
404 
405  /// Bundle this instruction with its predecessor. This can be an unbundled
406  /// instruction, or it can be the first instruction in a bundle.
407  void bundleWithPred();
408 
409  /// Bundle this instruction with its successor. This can be an unbundled
410  /// instruction, or it can be the last instruction in a bundle.
411  void bundleWithSucc();
412 
413  /// Break bundle above this instruction.
414  void unbundleFromPred();
415 
416  /// Break bundle below this instruction.
417  void unbundleFromSucc();
418 
419  /// Returns the debug location id of this MachineInstr.
420  const DebugLoc &getDebugLoc() const { return DbgLoc; }
421 
422  /// Return the operand containing the offset to be used if this DBG_VALUE
423  /// instruction is indirect; will be an invalid register if this value is
424  /// not indirect, and an immediate with value 0 otherwise.
426  assert(isNonListDebugValue() && "not a DBG_VALUE");
427  return getOperand(1);
428  }
430  assert(isNonListDebugValue() && "not a DBG_VALUE");
431  return getOperand(1);
432  }
433 
434  /// Return the operand for the debug variable referenced by
435  /// this DBG_VALUE instruction.
436  const MachineOperand &getDebugVariableOp() const;
438 
439  /// Return the debug variable referenced by
440  /// this DBG_VALUE instruction.
441  const DILocalVariable *getDebugVariable() const;
442 
443  /// Return the operand for the complex address expression referenced by
444  /// this DBG_VALUE instruction.
445  const MachineOperand &getDebugExpressionOp() const;
447 
448  /// Return the complex address expression referenced by
449  /// this DBG_VALUE instruction.
450  const DIExpression *getDebugExpression() const;
451 
452  /// Return the debug label referenced by
453  /// this DBG_LABEL instruction.
454  const DILabel *getDebugLabel() const;
455 
456  /// Fetch the instruction number of this MachineInstr. If it does not have
457  /// one already, a new and unique number will be assigned.
458  unsigned getDebugInstrNum();
459 
460  /// Fetch instruction number of this MachineInstr -- but before it's inserted
461  /// into \p MF. Needed for transformations that create an instruction but
462  /// don't immediately insert them.
463  unsigned getDebugInstrNum(MachineFunction &MF);
464 
465  /// Examine the instruction number of this MachineInstr. May be zero if
466  /// it hasn't been assigned a number yet.
467  unsigned peekDebugInstrNum() const { return DebugInstrNum; }
468 
469  /// Set instruction number of this MachineInstr. Avoid using unless you're
470  /// deserializing this information.
471  void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
472 
473  /// Drop any variable location debugging information associated with this
474  /// instruction. Use when an instruction is modified in such a way that it no
475  /// longer defines the value it used to. Variable locations using that value
476  /// will be dropped.
477  void dropDebugNumber() { DebugInstrNum = 0; }
478 
479  /// Emit an error referring to the source location of this instruction.
480  /// This should only be used for inline assembly that is somehow
481  /// impossible to compile. Other errors should have been handled much
482  /// earlier.
483  ///
484  /// If this method returns, the caller should try to recover from the error.
485  void emitError(StringRef Msg) const;
486 
487  /// Returns the target instruction descriptor of this MachineInstr.
488  const MCInstrDesc &getDesc() const { return *MCID; }
489 
490  /// Returns the opcode of this MachineInstr.
491  unsigned getOpcode() const { return MCID->Opcode; }
492 
493  /// Retuns the total number of operands.
494  unsigned getNumOperands() const { return NumOperands; }
495 
496  /// Returns the total number of operands which are debug locations.
497  unsigned getNumDebugOperands() const {
498  return std::distance(debug_operands().begin(), debug_operands().end());
499  }
500 
501  const MachineOperand& getOperand(unsigned i) const {
502  assert(i < getNumOperands() && "getOperand() out of range!");
503  return Operands[i];
504  }
506  assert(i < getNumOperands() && "getOperand() out of range!");
507  return Operands[i];
508  }
509 
511  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
512  return *(debug_operands().begin() + Index);
513  }
514  const MachineOperand &getDebugOperand(unsigned Index) const {
515  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
516  return *(debug_operands().begin() + Index);
517  }
518 
520  assert(isDebugValue() && "not a DBG_VALUE*");
521  SmallSet<Register, 4> UsedRegs;
522  for (const auto &MO : debug_operands())
523  if (MO.isReg() && MO.getReg())
524  UsedRegs.insert(MO.getReg());
525  return UsedRegs;
526  }
527 
528  /// Returns whether this debug value has at least one debug operand with the
529  /// register \p Reg.
531  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
532  return Op.isReg() && Op.getReg() == Reg;
533  });
534  }
535 
536  /// Returns a range of all of the operands that correspond to a debug use of
537  /// \p Reg.
538  template <typename Operand, typename Instruction>
539  static iterator_range<
540  filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
542  std::function<bool(Operand & Op)> OpUsesReg(
543  [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
544  return make_filter_range(MI->debug_operands(), OpUsesReg);
545  }
547  std::function<bool(const MachineOperand &Op)>>>
550  const MachineInstr>(this, Reg);
551  }
555  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
556  this, Reg);
557  }
558 
559  bool isDebugOperand(const MachineOperand *Op) const {
560  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
561  }
562 
563  unsigned getDebugOperandIndex(const MachineOperand *Op) const {
564  assert(isDebugOperand(Op) && "Expected a debug operand.");
565  return std::distance(adl_begin(debug_operands()), Op);
566  }
567 
568  /// Returns the total number of definitions.
569  unsigned getNumDefs() const {
570  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
571  }
572 
573  /// Returns true if the instruction has implicit definition.
574  bool hasImplicitDef() const {
575  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
576  I != E; ++I) {
577  const MachineOperand &MO = getOperand(I);
578  if (MO.isDef() && MO.isImplicit())
579  return true;
580  }
581  return false;
582  }
583 
584  /// Returns the implicit operands number.
585  unsigned getNumImplicitOperands() const {
587  }
588 
589  /// Return true if operand \p OpIdx is a subregister index.
590  bool isOperandSubregIdx(unsigned OpIdx) const {
591  assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
592  if (isExtractSubreg() && OpIdx == 2)
593  return true;
594  if (isInsertSubreg() && OpIdx == 3)
595  return true;
596  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
597  return true;
598  if (isSubregToReg() && OpIdx == 3)
599  return true;
600  return false;
601  }
602 
603  /// Returns the number of non-implicit operands.
604  unsigned getNumExplicitOperands() const;
605 
606  /// Returns the number of non-implicit definitions.
607  unsigned getNumExplicitDefs() const;
608 
609  /// iterator/begin/end - Iterate over all operands of a machine instruction.
612 
614  mop_iterator operands_end() { return Operands + NumOperands; }
615 
617  const_mop_iterator operands_end() const { return Operands + NumOperands; }
618 
621  }
624  }
626  return make_range(operands_begin(),
628  }
630  return make_range(operands_begin(),
632  }
635  }
638  }
639  /// Returns a range over all operands that are used to determine the variable
640  /// location for this DBG_VALUE instruction.
642  assert(isDebugValue() && "Must be a debug value instruction.");
643  return isDebugValueList()
646  }
647  /// \copydoc debug_operands()
649  assert(isDebugValue() && "Must be a debug value instruction.");
650  return isDebugValueList()
653  }
654  /// Returns a range over all explicit operands that are register definitions.
655  /// Implicit definition are not included!
657  return make_range(operands_begin(),
659  }
660  /// \copydoc defs()
662  return make_range(operands_begin(),
664  }
665  /// Returns a range that includes all operands that are register uses.
666  /// This may include unrelated operands which are not register uses.
669  }
670  /// \copydoc uses()
673  }
677  }
681  }
682 
683  /// Returns the number of the operand iterator \p I points to.
685  return I - operands_begin();
686  }
687 
688  /// Access to memory operands of the instruction. If there are none, that does
689  /// not imply anything about whether the function accesses memory. Instead,
690  /// the caller must behave conservatively.
692  if (!Info)
693  return {};
694 
695  if (Info.is<EIIK_MMO>())
696  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
697 
698  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
699  return EI->getMMOs();
700 
701  return {};
702  }
703 
704  /// Access to memory operands of the instruction.
705  ///
706  /// If `memoperands_begin() == memoperands_end()`, that does not imply
707  /// anything about whether the function accesses memory. Instead, the caller
708  /// must behave conservatively.
709  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
710 
711  /// Access to memory operands of the instruction.
712  ///
713  /// If `memoperands_begin() == memoperands_end()`, that does not imply
714  /// anything about whether the function accesses memory. Instead, the caller
715  /// must behave conservatively.
716  mmo_iterator memoperands_end() const { return memoperands().end(); }
717 
718  /// Return true if we don't have any memory operands which described the
719  /// memory access done by this instruction. If this is true, calling code
720  /// must be conservative.
721  bool memoperands_empty() const { return memoperands().empty(); }
722 
723  /// Return true if this instruction has exactly one MachineMemOperand.
724  bool hasOneMemOperand() const { return memoperands().size() == 1; }
725 
726  /// Return the number of memory operands.
727  unsigned getNumMemOperands() const { return memoperands().size(); }
728 
729  /// Helper to extract a pre-instruction symbol if one has been added.
731  if (!Info)
732  return nullptr;
733  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
734  return S;
735  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
736  return EI->getPreInstrSymbol();
737 
738  return nullptr;
739  }
740 
741  /// Helper to extract a post-instruction symbol if one has been added.
743  if (!Info)
744  return nullptr;
745  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
746  return S;
747  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
748  return EI->getPostInstrSymbol();
749 
750  return nullptr;
751  }
752 
753  /// Helper to extract a heap alloc marker if one has been added.
755  if (!Info)
756  return nullptr;
757  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
758  return EI->getHeapAllocMarker();
759 
760  return nullptr;
761  }
762 
763  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
764  /// queries but they are bundle aware.
765 
766  enum QueryType {
767  IgnoreBundle, // Ignore bundles
768  AnyInBundle, // Return true if any instruction in bundle has property
769  AllInBundle // Return true if all instructions in bundle have property
770  };
771 
772  /// Return true if the instruction (or in the case of a bundle,
773  /// the instructions inside the bundle) has the specified property.
774  /// The first argument is the property being queried.
775  /// The second argument indicates whether the query should look inside
776  /// instruction bundles.
777  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
778  assert(MCFlag < 64 &&
779  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
780  // Inline the fast path for unbundled or bundle-internal instructions.
781  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
782  return getDesc().getFlags() & (1ULL << MCFlag);
783 
784  // If this is the first instruction in a bundle, take the slow path.
785  return hasPropertyInBundle(1ULL << MCFlag, Type);
786  }
787 
788  /// Return true if this is an instruction that should go through the usual
789  /// legalization steps.
792  }
793 
794  /// Return true if this instruction can have a variable number of operands.
795  /// In this case, the variable operands will be after the normal
796  /// operands but before the implicit definitions and uses (if any are
797  /// present).
800  }
801 
802  /// Set if this instruction has an optional definition, e.g.
803  /// ARM instructions which can set condition code if 's' bit is set.
806  }
807 
808  /// Return true if this is a pseudo instruction that doesn't
809  /// correspond to a real machine instruction.
811  return hasProperty(MCID::Pseudo, Type);
812  }
813 
814  /// Return true if this instruction doesn't produce any output in the form of
815  /// executable instructions.
817  return hasProperty(MCID::Meta, Type);
818  }
819 
821  return hasProperty(MCID::Return, Type);
822  }
823 
824  /// Return true if this is an instruction that marks the end of an EH scope,
825  /// i.e., a catchpad or a cleanuppad instruction.
828  }
829 
831  return hasProperty(MCID::Call, Type);
832  }
833 
834  /// Return true if this is a call instruction that may have an associated
835  /// call site entry in the debug info.
837  /// Return true if copying, moving, or erasing this instruction requires
838  /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
839  /// \ref eraseCallSiteInfo).
840  bool shouldUpdateCallSiteInfo() const;
841 
842  /// Returns true if the specified instruction stops control flow
843  /// from executing the instruction immediately following it. Examples include
844  /// unconditional branches and return instructions.
846  return hasProperty(MCID::Barrier, Type);
847  }
848 
849  /// Returns true if this instruction part of the terminator for a basic block.
850  /// Typically this is things like return and branch instructions.
851  ///
852  /// Various passes use this to insert code into the bottom of a basic block,
853  /// but before control flow occurs.
856  }
857 
858  /// Returns true if this is a conditional, unconditional, or indirect branch.
859  /// Predicates below can be used to discriminate between
860  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
861  /// get more information.
863  return hasProperty(MCID::Branch, Type);
864  }
865 
866  /// Return true if this is an indirect branch, such as a
867  /// branch through a register.
870  }
871 
872  /// Return true if this is a branch which may fall
873  /// through to the next instruction or may transfer control flow to some other
874  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
875  /// information about this branch.
877  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
878  }
879 
880  /// Return true if this is a branch which always
881  /// transfers control flow to some other block. The
882  /// TargetInstrInfo::analyzeBranch method can be used to get more information
883  /// about this branch.
885  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
886  }
887 
888  /// Return true if this instruction has a predicate operand that
889  /// controls execution. It may be set to 'always', or may be set to other
890  /// values. There are various methods in TargetInstrInfo that can be used to
891  /// control and modify the predicate in this instruction.
893  // If it's a bundle than all bundled instructions must be predicable for this
894  // to return true.
896  }
897 
898  /// Return true if this instruction is a comparison.
900  return hasProperty(MCID::Compare, Type);
901  }
902 
903  /// Return true if this instruction is a move immediate
904  /// (including conditional moves) instruction.
906  return hasProperty(MCID::MoveImm, Type);
907  }
908 
909  /// Return true if this instruction is a register move.
910  /// (including moving values from subreg to reg)
912  return hasProperty(MCID::MoveReg, Type);
913  }
914 
915  /// Return true if this instruction is a bitcast instruction.
917  return hasProperty(MCID::Bitcast, Type);
918  }
919 
920  /// Return true if this instruction is a select instruction.
922  return hasProperty(MCID::Select, Type);
923  }
924 
925  /// Return true if this instruction cannot be safely duplicated.
926  /// For example, if the instruction has a unique labels attached
927  /// to it, duplicating it would cause multiple definition errors.
930  }
931 
932  /// Return true if this instruction is convergent.
933  /// Convergent instructions can not be made control-dependent on any
934  /// additional values.
936  if (isInlineAsm()) {
937  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
938  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
939  return true;
940  }
942  }
943 
944  /// Returns true if the specified instruction has a delay slot
945  /// which must be filled by the code generator.
948  }
949 
950  /// Return true for instructions that can be folded as
951  /// memory operands in other instructions. The most common use for this
952  /// is instructions that are simple loads from memory that don't modify
953  /// the loaded value in any way, but it can also be used for instructions
954  /// that can be expressed as constant-pool loads, such as V_SETALLONES
955  /// on x86, to allow them to be folded when it is beneficial.
956  /// This should only be set on instructions that return a value in their
957  /// only virtual register definition.
960  }
961 
962  /// Return true if this instruction behaves
963  /// the same way as the generic REG_SEQUENCE instructions.
964  /// E.g., on ARM,
965  /// dX VMOVDRR rY, rZ
966  /// is equivalent to
967  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
968  ///
969  /// Note that for the optimizers to be able to take advantage of
970  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
971  /// override accordingly.
974  }
975 
976  /// Return true if this instruction behaves
977  /// the same way as the generic EXTRACT_SUBREG instructions.
978  /// E.g., on ARM,
979  /// rX, rY VMOVRRD dZ
980  /// is equivalent to two EXTRACT_SUBREG:
981  /// rX = EXTRACT_SUBREG dZ, ssub_0
982  /// rY = EXTRACT_SUBREG dZ, ssub_1
983  ///
984  /// Note that for the optimizers to be able to take advantage of
985  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
986  /// override accordingly.
989  }
990 
991  /// Return true if this instruction behaves
992  /// the same way as the generic INSERT_SUBREG instructions.
993  /// E.g., on ARM,
994  /// dX = VSETLNi32 dY, rZ, Imm
995  /// is equivalent to a INSERT_SUBREG:
996  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
997  ///
998  /// Note that for the optimizers to be able to take advantage of
999  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1000  /// override accordingly.
1003  }
1004 
1005  //===--------------------------------------------------------------------===//
1006  // Side Effect Analysis
1007  //===--------------------------------------------------------------------===//
1008 
1009  /// Return true if this instruction could possibly read memory.
1010  /// Instructions with this flag set are not necessarily simple load
1011  /// instructions, they may load a value and modify it, for example.
1013  if (isInlineAsm()) {
1014  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1015  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1016  return true;
1017  }
1018  return hasProperty(MCID::MayLoad, Type);
1019  }
1020 
1021  /// Return true if this instruction could possibly modify memory.
1022  /// Instructions with this flag set are not necessarily simple store
1023  /// instructions, they may store a modified value based on their operands, or
1024  /// may not actually modify anything, for example.
1026  if (isInlineAsm()) {
1027  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1028  if (ExtraInfo & InlineAsm::Extra_MayStore)
1029  return true;
1030  }
1031  return hasProperty(MCID::MayStore, Type);
1032  }
1033 
1034  /// Return true if this instruction could possibly read or modify memory.
1036  return mayLoad(Type) || mayStore(Type);
1037  }
1038 
1039  /// Return true if this instruction could possibly raise a floating-point
1040  /// exception. This is the case if the instruction is a floating-point
1041  /// instruction that can in principle raise an exception, as indicated
1042  /// by the MCID::MayRaiseFPException property, *and* at the same time,
1043  /// the instruction is used in a context where we expect floating-point
1044  /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1045  bool mayRaiseFPException() const {
1047  !getFlag(MachineInstr::MIFlag::NoFPExcept);
1048  }
1049 
1050  //===--------------------------------------------------------------------===//
1051  // Flags that indicate whether an instruction can be modified by a method.
1052  //===--------------------------------------------------------------------===//
1053 
1054  /// Return true if this may be a 2- or 3-address
1055  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1056  /// result if Y and Z are exchanged. If this flag is set, then the
1057  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1058  /// instruction.
1059  ///
1060  /// Note that this flag may be set on instructions that are only commutable
1061  /// sometimes. In these cases, the call to commuteInstruction will fail.
1062  /// Also note that some instructions require non-trivial modification to
1063  /// commute them.
1066  }
1067 
1068  /// Return true if this is a 2-address instruction
1069  /// which can be changed into a 3-address instruction if needed. Doing this
1070  /// transformation can be profitable in the register allocator, because it
1071  /// means that the instruction can use a 2-address form if possible, but
1072  /// degrade into a less efficient form if the source and dest register cannot
1073  /// be assigned to the same register. For example, this allows the x86
1074  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1075  /// is the same speed as the shift but has bigger code size.
1076  ///
1077  /// If this returns true, then the target must implement the
1078  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1079  /// is allowed to fail if the transformation isn't valid for this specific
1080  /// instruction (e.g. shl reg, 4 on x86).
1081  ///
1084  }
1085 
1086  /// Return true if this instruction requires
1087  /// custom insertion support when the DAG scheduler is inserting it into a
1088  /// machine basic block. If this is true for the instruction, it basically
1089  /// means that it is a pseudo instruction used at SelectionDAG time that is
1090  /// expanded out into magic code by the target when MachineInstrs are formed.
1091  ///
1092  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1093  /// is used to insert this into the MachineBasicBlock.
1096  }
1097 
1098  /// Return true if this instruction requires *adjustment*
1099  /// after instruction selection by calling a target hook. For example, this
1100  /// can be used to fill in ARM 's' optional operand depending on whether
1101  /// the conditional flag register is used.
1104  }
1105 
1106  /// Returns true if this instruction is a candidate for remat.
1107  /// This flag is deprecated, please don't use it anymore. If this
1108  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1109  /// verify the instruction is really rematable.
1111  // It's only possible to re-mat a bundle if all bundled instructions are
1112  // re-materializable.
1114  }
1115 
1116  /// Returns true if this instruction has the same cost (or less) than a move
1117  /// instruction. This is useful during certain types of optimizations
1118  /// (e.g., remat during two-address conversion or machine licm)
1119  /// where we would like to remat or hoist the instruction, but not if it costs
1120  /// more than moving the instruction into the appropriate register. Note, we
1121  /// are not marking copies from and to the same register class with this flag.
1123  // Only returns true for a bundle if all bundled instructions are cheap.
1125  }
1126 
1127  /// Returns true if this instruction source operands
1128  /// have special register allocation requirements that are not captured by the
1129  /// operand register classes. e.g. ARM::STRD's two source registers must be an
1130  /// even / odd pair, ARM::STM registers have to be in ascending order.
1131  /// Post-register allocation passes should not attempt to change allocations
1132  /// for sources of instructions with this flag.
1135  }
1136 
1137  /// Returns true if this instruction def operands
1138  /// have special register allocation requirements that are not captured by the
1139  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1140  /// even / odd pair, ARM::LDM registers have to be in ascending order.
1141  /// Post-register allocation passes should not attempt to change allocations
1142  /// for definitions of instructions with this flag.
1145  }
1146 
1148  CheckDefs, // Check all operands for equality
1149  CheckKillDead, // Check all operands including kill / dead markers
1150  IgnoreDefs, // Ignore all definitions
1151  IgnoreVRegDefs // Ignore virtual register definitions
1152  };
1153 
1154  /// Return true if this instruction is identical to \p Other.
1155  /// Two instructions are identical if they have the same opcode and all their
1156  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1157  /// Note that this means liveness related flags (dead, undef, kill) do not
1158  /// affect the notion of identical.
1159  bool isIdenticalTo(const MachineInstr &Other,
1160  MICheckType Check = CheckDefs) const;
1161 
1162  /// Unlink 'this' from the containing basic block, and return it without
1163  /// deleting it.
1164  ///
1165  /// This function can not be used on bundled instructions, use
1166  /// removeFromBundle() to remove individual instructions from a bundle.
1168 
1169  /// Unlink this instruction from its basic block and return it without
1170  /// deleting it.
1171  ///
1172  /// If the instruction is part of a bundle, the other instructions in the
1173  /// bundle remain bundled.
1175 
1176  /// Unlink 'this' from the containing basic block and delete it.
1177  ///
1178  /// If this instruction is the header of a bundle, the whole bundle is erased.
1179  /// This function can not be used for instructions inside a bundle, use
1180  /// eraseFromBundle() to erase individual bundled instructions.
1181  void eraseFromParent();
1182 
1183  /// Unlink 'this' form its basic block and delete it.
1184  ///
1185  /// If the instruction is part of a bundle, the other instructions in the
1186  /// bundle remain bundled.
1187  void eraseFromBundle();
1188 
1189  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1190  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1191  bool isAnnotationLabel() const {
1193  }
1194 
1195  /// Returns true if the MachineInstr represents a label.
1196  bool isLabel() const {
1197  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1198  }
1199 
1200  bool isCFIInstruction() const {
1201  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1202  }
1203 
1204  bool isPseudoProbe() const {
1206  }
1207 
1208  // True if the instruction represents a position in the function.
1209  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1210 
1211  bool isNonListDebugValue() const {
1212  return getOpcode() == TargetOpcode::DBG_VALUE;
1213  }
1214  bool isDebugValueList() const {
1215  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1216  }
1217  bool isDebugValue() const {
1218  return isNonListDebugValue() || isDebugValueList();
1219  }
1220  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1221  bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1222  bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1223  bool isDebugInstr() const {
1224  return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1225  }
1226  bool isDebugOrPseudoInstr() const {
1227  return isDebugInstr() || isPseudoProbe();
1228  }
1229 
1230  bool isDebugOffsetImm() const {
1231  return isNonListDebugValue() && getDebugOffset().isImm();
1232  }
1233 
1234  /// A DBG_VALUE is indirect iff the location operand is a register and
1235  /// the offset operand is an immediate.
1236  bool isIndirectDebugValue() const {
1237  return isDebugOffsetImm() && getDebugOperand(0).isReg();
1238  }
1239 
1240  /// A DBG_VALUE is an entry value iff its debug expression contains the
1241  /// DW_OP_LLVM_entry_value operation.
1242  bool isDebugEntryValue() const;
1243 
1244  /// Return true if the instruction is a debug value which describes a part of
1245  /// a variable as unavailable.
1246  bool isUndefDebugValue() const {
1247  if (!isDebugValue())
1248  return false;
1249  // If any $noreg locations are given, this DV is undef.
1250  for (const MachineOperand &Op : debug_operands())
1251  if (Op.isReg() && !Op.getReg().isValid())
1252  return true;
1253  return false;
1254  }
1255 
1256  bool isPHI() const {
1257  return getOpcode() == TargetOpcode::PHI ||
1258  getOpcode() == TargetOpcode::G_PHI;
1259  }
1260  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1261  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1262  bool isInlineAsm() const {
1263  return getOpcode() == TargetOpcode::INLINEASM ||
1265  }
1266 
1267  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1268  /// specific, be attached to a generic MachineInstr.
1269  bool isMSInlineAsm() const {
1271  }
1272 
1273  bool isStackAligningInlineAsm() const;
1275 
1276  bool isInsertSubreg() const {
1277  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1278  }
1279 
1280  bool isSubregToReg() const {
1281  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1282  }
1283 
1284  bool isRegSequence() const {
1285  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1286  }
1287 
1288  bool isBundle() const {
1289  return getOpcode() == TargetOpcode::BUNDLE;
1290  }
1291 
1292  bool isCopy() const {
1293  return getOpcode() == TargetOpcode::COPY;
1294  }
1295 
1296  bool isFullCopy() const {
1297  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1298  }
1299 
1300  bool isExtractSubreg() const {
1301  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1302  }
1303 
1304  /// Return true if the instruction behaves like a copy.
1305  /// This does not include native copy instructions.
1306  bool isCopyLike() const {
1307  return isCopy() || isSubregToReg();
1308  }
1309 
1310  /// Return true is the instruction is an identity copy.
1311  bool isIdentityCopy() const {
1312  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1314  }
1315 
1316  /// Return true if this is a transient instruction that is either very likely
1317  /// to be eliminated during register allocation (such as copy-like
1318  /// instructions), or if this instruction doesn't have an execution-time cost.
1319  bool isTransient() const {
1320  switch (getOpcode()) {
1321  default:
1322  return isMetaInstruction();
1323  // Copy-like instructions are usually eliminated during register allocation.
1324  case TargetOpcode::PHI:
1325  case TargetOpcode::G_PHI:
1326  case TargetOpcode::COPY:
1327  case TargetOpcode::INSERT_SUBREG:
1328  case TargetOpcode::SUBREG_TO_REG:
1329  case TargetOpcode::REG_SEQUENCE:
1330  return true;
1331  }
1332  }
1333 
1334  /// Return the number of instructions inside the MI bundle, excluding the
1335  /// bundle header.
1336  ///
1337  /// This is the number of instructions that MachineBasicBlock::iterator
1338  /// skips, 0 for unbundled instructions.
1339  unsigned getBundleSize() const;
1340 
1341  /// Return true if the MachineInstr reads the specified register.
1342  /// If TargetRegisterInfo is passed, then it also checks if there
1343  /// is a read of a super-register.
1344  /// This does not count partial redefines of virtual registers as reads:
1345  /// %reg1024:6 = OP.
1347  const TargetRegisterInfo *TRI = nullptr) const {
1348  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1349  }
1350 
1351  /// Return true if the MachineInstr reads the specified virtual register.
1352  /// Take into account that a partial define is a
1353  /// read-modify-write operation.
1355  return readsWritesVirtualRegister(Reg).first;
1356  }
1357 
1358  /// Return a pair of bools (reads, writes) indicating if this instruction
1359  /// reads or writes Reg. This also considers partial defines.
1360  /// If Ops is not null, all operand indices for Reg are added.
1361  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1362  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1363 
1364  /// Return true if the MachineInstr kills the specified register.
1365  /// If TargetRegisterInfo is passed, then it also checks if there is
1366  /// a kill of a super-register.
1368  const TargetRegisterInfo *TRI = nullptr) const {
1369  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1370  }
1371 
1372  /// Return true if the MachineInstr fully defines the specified register.
1373  /// If TargetRegisterInfo is passed, then it also checks
1374  /// if there is a def of a super-register.
1375  /// NOTE: It's ignoring subreg indices on virtual registers.
1377  const TargetRegisterInfo *TRI = nullptr) const {
1378  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1379  }
1380 
1381  /// Return true if the MachineInstr modifies (fully define or partially
1382  /// define) the specified register.
1383  /// NOTE: It's ignoring subreg indices on virtual registers.
1385  const TargetRegisterInfo *TRI = nullptr) const {
1386  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1387  }
1388 
1389  /// Returns true if the register is dead in this machine instruction.
1390  /// If TargetRegisterInfo is passed, then it also checks
1391  /// if there is a dead def of a super-register.
1393  const TargetRegisterInfo *TRI = nullptr) const {
1394  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1395  }
1396 
1397  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1398  /// the given register (not considering sub/super-registers).
1400 
1401  /// Returns the operand index that is a use of the specific register or -1
1402  /// if it is not found. It further tightens the search criteria to a use
1403  /// that kills the register if isKill is true.
1404  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1405  const TargetRegisterInfo *TRI = nullptr) const;
1406 
1407  /// Wrapper for findRegisterUseOperandIdx, it returns
1408  /// a pointer to the MachineOperand rather than an index.
1410  const TargetRegisterInfo *TRI = nullptr) {
1411  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1412  return (Idx == -1) ? nullptr : &getOperand(Idx);
1413  }
1414 
1416  Register Reg, bool isKill = false,
1417  const TargetRegisterInfo *TRI = nullptr) const {
1418  return const_cast<MachineInstr *>(this)->
1420  }
1421 
1422  /// Returns the operand index that is a def of the specified register or
1423  /// -1 if it is not found. If isDead is true, defs that are not dead are
1424  /// skipped. If Overlap is true, then it also looks for defs that merely
1425  /// overlap the specified register. If TargetRegisterInfo is non-null,
1426  /// then it also checks if there is a def of a super-register.
1427  /// This may also return a register mask operand when Overlap is true.
1429  bool isDead = false, bool Overlap = false,
1430  const TargetRegisterInfo *TRI = nullptr) const;
1431 
1432  /// Wrapper for findRegisterDefOperandIdx, it returns
1433  /// a pointer to the MachineOperand rather than an index.
1434  MachineOperand *
1435  findRegisterDefOperand(Register Reg, bool isDead = false,
1436  bool Overlap = false,
1437  const TargetRegisterInfo *TRI = nullptr) {
1438  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1439  return (Idx == -1) ? nullptr : &getOperand(Idx);
1440  }
1441 
1442  const MachineOperand *
1443  findRegisterDefOperand(Register Reg, bool isDead = false,
1444  bool Overlap = false,
1445  const TargetRegisterInfo *TRI = nullptr) const {
1446  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1447  Reg, isDead, Overlap, TRI);
1448  }
1449 
1450  /// Find the index of the first operand in the
1451  /// operand list that is used to represent the predicate. It returns -1 if
1452  /// none is found.
1453  int findFirstPredOperandIdx() const;
1454 
1455  /// Find the index of the flag word operand that
1456  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1457  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1458  ///
1459  /// If GroupNo is not NULL, it will receive the number of the operand group
1460  /// containing OpIdx.
1461  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1462 
1463  /// Compute the static register class constraint for operand OpIdx.
1464  /// For normal instructions, this is derived from the MCInstrDesc.
1465  /// For inline assembly it is derived from the flag words.
1466  ///
1467  /// Returns NULL if the static register class constraint cannot be
1468  /// determined.
1469  const TargetRegisterClass*
1470  getRegClassConstraint(unsigned OpIdx,
1471  const TargetInstrInfo *TII,
1472  const TargetRegisterInfo *TRI) const;
1473 
1474  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1475  /// the given \p CurRC.
1476  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1477  /// instructions inside the bundle will be taken into account. In other words,
1478  /// this method accumulates all the constraints of the operand of this MI and
1479  /// the related bundle if MI is a bundle or inside a bundle.
1480  ///
1481  /// Returns the register class that satisfies both \p CurRC and the
1482  /// constraints set by MI. Returns NULL if such a register class does not
1483  /// exist.
1484  ///
1485  /// \pre CurRC must not be NULL.
1487  Register Reg, const TargetRegisterClass *CurRC,
1488  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1489  bool ExploreBundle = false) const;
1490 
1491  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1492  /// to the given \p CurRC.
1493  ///
1494  /// Returns the register class that satisfies both \p CurRC and the
1495  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1496  /// does not exist.
1497  ///
1498  /// \pre CurRC must not be NULL.
1499  /// \pre The operand at \p OpIdx must be a register.
1500  const TargetRegisterClass *
1501  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1502  const TargetInstrInfo *TII,
1503  const TargetRegisterInfo *TRI) const;
1504 
1505  /// Add a tie between the register operands at DefIdx and UseIdx.
1506  /// The tie will cause the register allocator to ensure that the two
1507  /// operands are assigned the same physical register.
1508  ///
1509  /// Tied operands are managed automatically for explicit operands in the
1510  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1511  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1512 
1513  /// Given the index of a tied register operand, find the
1514  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1515  /// index of the tied operand which must exist.
1516  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1517 
1518  /// Given the index of a register def operand,
1519  /// check if the register def is tied to a source operand, due to either
1520  /// two-address elimination or inline assembly constraints. Returns the
1521  /// first tied use operand index by reference if UseOpIdx is not null.
1522  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1523  unsigned *UseOpIdx = nullptr) const {
1524  const MachineOperand &MO = getOperand(DefOpIdx);
1525  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1526  return false;
1527  if (UseOpIdx)
1528  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1529  return true;
1530  }
1531 
1532  /// Return true if the use operand of the specified index is tied to a def
1533  /// operand. It also returns the def operand index by reference if DefOpIdx
1534  /// is not null.
1535  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1536  unsigned *DefOpIdx = nullptr) const {
1537  const MachineOperand &MO = getOperand(UseOpIdx);
1538  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1539  return false;
1540  if (DefOpIdx)
1541  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1542  return true;
1543  }
1544 
1545  /// Clears kill flags on all operands.
1546  void clearKillInfo();
1547 
1548  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1549  /// properly composing subreg indices where necessary.
1550  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1551  const TargetRegisterInfo &RegInfo);
1552 
1553  /// We have determined MI kills a register. Look for the
1554  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1555  /// add a implicit operand if it's not found. Returns true if the operand
1556  /// exists / is added.
1557  bool addRegisterKilled(Register IncomingReg,
1558  const TargetRegisterInfo *RegInfo,
1559  bool AddIfNotFound = false);
1560 
1561  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1562  /// all aliasing registers.
1564 
1565  /// We have determined MI defined a register without a use.
1566  /// Look for the operand that defines it and mark it as IsDead. If
1567  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1568  /// true if the operand exists / is added.
1570  bool AddIfNotFound = false);
1571 
1572  /// Clear all dead flags on operands defining register @p Reg.
1574 
1575  /// Mark all subregister defs of register @p Reg with the undef flag.
1576  /// This function is used when we determined to have a subregister def in an
1577  /// otherwise undefined super register.
1578  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1579 
1580  /// We have determined MI defines a register. Make sure there is an operand
1581  /// defining Reg.
1583  const TargetRegisterInfo *RegInfo = nullptr);
1584 
1585  /// Mark every physreg used by this instruction as
1586  /// dead except those in the UsedRegs list.
1587  ///
1588  /// On instructions with register mask operands, also add implicit-def
1589  /// operands for all registers in UsedRegs.
1591  const TargetRegisterInfo &TRI);
1592 
1593  /// Return true if it is safe to move this instruction. If
1594  /// SawStore is set to true, it means that there is a store (or call) between
1595  /// the instruction's location and its intended destination.
1596  bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1597 
1598  /// Returns true if this instruction's memory access aliases the memory
1599  /// access of Other.
1600  //
1601  /// Assumes any physical registers used to compute addresses
1602  /// have the same value for both instructions. Returns false if neither
1603  /// instruction writes to memory.
1604  ///
1605  /// @param AA Optional alias analysis, used to compare memory operands.
1606  /// @param Other MachineInstr to check aliasing against.
1607  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1608  bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1609 
1610  /// Return true if this instruction may have an ordered
1611  /// or volatile memory reference, or if the information describing the memory
1612  /// reference is not available. Return false if it is known to have no
1613  /// ordered or volatile memory references.
1614  bool hasOrderedMemoryRef() const;
1615 
1616  /// Return true if this load instruction never traps and points to a memory
1617  /// location whose value doesn't change during the execution of this function.
1618  ///
1619  /// Examples include loading a value from the constant pool or from the
1620  /// argument area of a function (if it does not change). If the instruction
1621  /// does multiple loads, this returns true only if all of the loads are
1622  /// dereferenceable and invariant.
1624 
1625  /// If the specified instruction is a PHI that always merges together the
1626  /// same virtual register, return the register, otherwise return 0.
1627  unsigned isConstantValuePHI() const;
1628 
1629  /// Return true if this instruction has side effects that are not modeled
1630  /// by mayLoad / mayStore, etc.
1631  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1632  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1633  /// INLINEASM instruction, in which case the side effect property is encoded
1634  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1635  ///
1636  bool hasUnmodeledSideEffects() const;
1637 
1638  /// Returns true if it is illegal to fold a load across this instruction.
1639  bool isLoadFoldBarrier() const;
1640 
1641  /// Return true if all the defs of this instruction are dead.
1642  bool allDefsAreDead() const;
1643 
1644  /// Return a valid size if the instruction is a spill instruction.
1646 
1647  /// Return a valid size if the instruction is a folded spill instruction.
1649 
1650  /// Return a valid size if the instruction is a restore instruction.
1652 
1653  /// Return a valid size if the instruction is a folded restore instruction.
1656 
1657  /// Copy implicit register operands from specified
1658  /// instruction to this instruction.
1659  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1660 
1661  /// Debugging support
1662  /// @{
1663  /// Determine the generic type to be printed (if needed) on uses and defs.
1664  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1665  const MachineRegisterInfo &MRI) const;
1666 
1667  /// Return true when an instruction has tied register that can't be determined
1668  /// by the instruction's descriptor. This is useful for MIR printing, to
1669  /// determine whether we need to print the ties or not.
1670  bool hasComplexRegisterTies() const;
1671 
1672  /// Print this MI to \p OS.
1673  /// Don't print information that can be inferred from other instructions if
1674  /// \p IsStandalone is false. It is usually true when only a fragment of the
1675  /// function is printed.
1676  /// Only print the defs and the opcode if \p SkipOpers is true.
1677  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1678  /// Otherwise, also print the debug loc, with a terminating newline.
1679  /// \p TII is used to print the opcode name. If it's not present, but the
1680  /// MI is in a function, the opcode will be printed using the function's TII.
1681  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1682  bool SkipDebugLoc = false, bool AddNewLine = true,
1683  const TargetInstrInfo *TII = nullptr) const;
1684  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1685  bool SkipOpers = false, bool SkipDebugLoc = false,
1686  bool AddNewLine = true,
1687  const TargetInstrInfo *TII = nullptr) const;
1688  void dump() const;
1689  /// Print on dbgs() the current instruction and the instructions defining its
1690  /// operands and so on until we reach \p MaxDepth.
1691  void dumpr(const MachineRegisterInfo &MRI,
1692  unsigned MaxDepth = UINT_MAX) const;
1693  /// @}
1694 
1695  //===--------------------------------------------------------------------===//
1696  // Accessors used to build up machine instructions.
1697 
1698  /// Add the specified operand to the instruction. If it is an implicit
1699  /// operand, it is added to the end of the operand list. If it is an
1700  /// explicit operand it is added at the end of the explicit operand list
1701  /// (before the first implicit operand).
1702  ///
1703  /// MF must be the machine function that was used to allocate this
1704  /// instruction.
1705  ///
1706  /// MachineInstrBuilder provides a more convenient interface for creating
1707  /// instructions and adding operands.
1708  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1709 
1710  /// Add an operand without providing an MF reference. This only works for
1711  /// instructions that are inserted in a basic block.
1712  ///
1713  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1714  /// preferred.
1715  void addOperand(const MachineOperand &Op);
1716 
1717  /// Replace the instruction descriptor (thus opcode) of
1718  /// the current instruction with a new one.
1719  void setDesc(const MCInstrDesc &TID) { MCID = &TID; }
1720 
1721  /// Replace current source information with new such.
1722  /// Avoid using this, the constructor argument is preferable.
1724  DbgLoc = std::move(DL);
1725  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1726  }
1727 
1728  /// Erase an operand from an instruction, leaving it with one
1729  /// fewer operand than it started with.
1730  void removeOperand(unsigned OpNo);
1731 
1732  /// Clear this MachineInstr's memory reference descriptor list. This resets
1733  /// the memrefs to their most conservative state. This should be used only
1734  /// as a last resort since it greatly pessimizes our knowledge of the memory
1735  /// access performed by the instruction.
1736  void dropMemRefs(MachineFunction &MF);
1737 
1738  /// Assign this MachineInstr's memory reference descriptor list.
1739  ///
1740  /// Unlike other methods, this *will* allocate them into a new array
1741  /// associated with the provided `MachineFunction`.
1743 
1744  /// Add a MachineMemOperand to the machine instruction.
1745  /// This function should be used only occasionally. The setMemRefs function
1746  /// is the primary method for setting up a MachineInstr's MemRefs list.
1748 
1749  /// Clone another MachineInstr's memory reference descriptor list and replace
1750  /// ours with it.
1751  ///
1752  /// Note that `*this` may be the incoming MI!
1753  ///
1754  /// Prefer this API whenever possible as it can avoid allocations in common
1755  /// cases.
1756  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1757 
1758  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1759  /// list and replace ours with it.
1760  ///
1761  /// Note that `*this` may be one of the incoming MIs!
1762  ///
1763  /// Prefer this API whenever possible as it can avoid allocations in common
1764  /// cases.
1767 
1768  /// Set a symbol that will be emitted just prior to the instruction itself.
1769  ///
1770  /// Setting this to a null pointer will remove any such symbol.
1771  ///
1772  /// FIXME: This is not fully implemented yet.
1774 
1775  /// Set a symbol that will be emitted just after the instruction itself.
1776  ///
1777  /// Setting this to a null pointer will remove any such symbol.
1778  ///
1779  /// FIXME: This is not fully implemented yet.
1781 
1782  /// Clone another MachineInstr's pre- and post- instruction symbols and
1783  /// replace ours with it.
1785 
1786  /// Set a marker on instructions that denotes where we should create and emit
1787  /// heap alloc site labels. This waits until after instruction selection and
1788  /// optimizations to create the label, so it should still work if the
1789  /// instruction is removed or duplicated.
1790  void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1791 
1792  /// Return the MIFlags which represent both MachineInstrs. This
1793  /// should be used when merging two MachineInstrs into one. This routine does
1794  /// not modify the MIFlags of this MachineInstr.
1795  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1796 
1798 
1799  /// Copy all flags to MachineInst MIFlags
1800  void copyIRFlags(const Instruction &I);
1801 
1802  /// Break any tie involving OpIdx.
1803  void untieRegOperand(unsigned OpIdx) {
1804  MachineOperand &MO = getOperand(OpIdx);
1805  if (MO.isReg() && MO.isTied()) {
1806  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1807  MO.TiedTo = 0;
1808  }
1809  }
1810 
1811  /// Add all implicit def and use operands to this instruction.
1813 
1814  /// Scan instructions immediately following MI and collect any matching
1815  /// DBG_VALUEs.
1817 
1818  /// Find all DBG_VALUEs that point to the register def in this instruction
1819  /// and point them to \p Reg instead.
1821 
1822  /// Returns the Intrinsic::ID for this instruction.
1823  /// \pre Must have an intrinsic ID operand.
1824  unsigned getIntrinsicID() const {
1826  }
1827 
1828  /// Sets all register debug operands in this debug value instruction to be
1829  /// undef.
1831  assert(isDebugValue() && "Must be a debug value instruction.");
1832  for (MachineOperand &MO : debug_operands()) {
1833  if (MO.isReg()) {
1834  MO.setReg(0);
1835  MO.setSubReg(0);
1836  }
1837  }
1838  }
1839 
1840 private:
1841  /// If this instruction is embedded into a MachineFunction, return the
1842  /// MachineRegisterInfo object for the current function, otherwise
1843  /// return null.
1844  MachineRegisterInfo *getRegInfo();
1845 
1846  /// Unlink all of the register operands in this instruction from their
1847  /// respective use lists. This requires that the operands already be on their
1848  /// use lists.
1849  void removeRegOperandsFromUseLists(MachineRegisterInfo&);
1850 
1851  /// Add all of the register operands in this instruction from their
1852  /// respective use lists. This requires that the operands not be on their
1853  /// use lists yet.
1854  void addRegOperandsToUseLists(MachineRegisterInfo&);
1855 
1856  /// Slow path for hasProperty when we're dealing with a bundle.
1857  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1858 
1859  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1860  /// this MI and the given operand index \p OpIdx.
1861  /// If the related operand does not constrained Reg, this returns CurRC.
1862  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1863  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1864  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1865 
1866  /// Stores extra instruction information inline or allocates as ExtraInfo
1867  /// based on the number of pointers.
1868  void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1869  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1870  MDNode *HeapAllocMarker);
1871 };
1872 
1873 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1874 /// instruction rather than by pointer value.
1875 /// The hashing and equality testing functions ignore definitions so this is
1876 /// useful for CSE, etc.
1878  static inline MachineInstr *getEmptyKey() {
1879  return nullptr;
1880  }
1881 
1882  static inline MachineInstr *getTombstoneKey() {
1883  return reinterpret_cast<MachineInstr*>(-1);
1884  }
1885 
1886  static unsigned getHashValue(const MachineInstr* const &MI);
1887 
1888  static bool isEqual(const MachineInstr* const &LHS,
1889  const MachineInstr* const &RHS) {
1890  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1891  LHS == getEmptyKey() || LHS == getTombstoneKey())
1892  return LHS == RHS;
1893  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1894  }
1895 };
1896 
1897 //===----------------------------------------------------------------------===//
1898 // Debugging Support
1899 
1901  MI.print(OS);
1902  return OS;
1903 }
1904 
1905 } // end namespace llvm
1906 
1907 #endif // LLVM_CODEGEN_MACHINEINSTR_H
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1217
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:721
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:812
llvm::MachineInstr::getNumDebugOperands
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:497
llvm::MachineInstr::isBranch
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:862
llvm::MachineInstr::setDebugValueUndef
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
Definition: MachineInstr.h:1830
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:154
TrailingObjects.h
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:1960
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:1994
llvm::MachineInstr::isUndefDebugValue
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
Definition: MachineInstr.h:1246
llvm::MachineInstr::isExtractSubregLike
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MachineInstr.h:987
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2322
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:667
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1907
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:160
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:684
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1261
llvm::MachineInstr::getDebugOperandIndex
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:563
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:868
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2020
llvm::MachineInstr::usesCustomInsertionHook
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:1094
llvm::TrailingObjects< ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode * >::TrailingObjects
TrailingObjects(const TrailingObjects &)=delete
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:79
llvm::MachineInstr::explicit_operands
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:625
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:928
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1185
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:641
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1035
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:166
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:679
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:709
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:742
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:507
llvm::MachineInstr::isCompare
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:899
llvm::MachineInstr::isEHScopeReturn
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:826
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:645
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:171
llvm::MachineInstr::isRegSequenceLike
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:972
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1012
llvm::ArrayRef::iterator
const_pointer iterator
Definition: ArrayRef.h:49
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1236
llvm::MachineInstr::implicit_operands
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:633
ilist.h
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1149
InlineAsm.h
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:173
llvm::ilist_node_with_parent
An ilist node that can access its parent list.
Definition: ilist_node.h:257
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineInstr::clearAsmPrinterFlags
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:309
llvm::MachineInstr::isMoveImmediate
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:905
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::MachineInstr::isInsertSubregLike
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MachineInstr.h:1001
llvm::MachineInstr::isDebugOffsetImm
bool isDebugOffsetImm() const
Definition: MachineInstr.h:1230
llvm::MachineInstr::NoSchedComment
@ NoSchedComment
Definition: MachineInstr.h:78
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:712
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1204
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:1976
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1428
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1396
llvm::MachineInstr::isEHLabel
bool isEHLabel() const
Definition: MachineInstr.h:1189
llvm::ilist_callback_traits
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:656
llvm::MachineInstr::hasPostISelHook
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:1102
llvm::MachineInstr::isBundled
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:393
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MachineInstr::operands_begin
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:616
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:488
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::filter_iterator_impl
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:462
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:100
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::findRegisterUseOperand
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1409
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:933
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:636
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:233
llvm::Optional< unsigned >
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1292
llvm::MachineInstr::peekDebugInstrNum
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:467
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:184
llvm::MachineInstr::operands_end
mop_iterator operands_end()
Definition: MachineInstr.h:614
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:798
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachineInstr::uses
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:671
llvm::MachineInstr::hasDebugOperandForReg
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:530
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:548
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineInstr::getMF
MachineFunction * getMF()
Definition: MachineInstr.h:300
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:724
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:355
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:791
llvm::MachineInstr::isPreISelOpcode
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:790
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:982
llvm::MachineInstrExpressionTrait::getTombstoneKey
static MachineInstr * getTombstoneKey()
Definition: MachineInstr.h:1882
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1329
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1535
llvm::MachineInstr::isInsertSubreg
bool isInsertSubreg() const
Definition: MachineInstr.h:1276
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:569
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1242
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1079
llvm::MachineInstr::readsVirtualRegister
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:1354
llvm::MachineInstr::getParent
MachineBasicBlock * getParent()
Definition: MachineInstr.h:289
llvm::MachineInstrExpressionTrait::isEqual
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Definition: MachineInstr.h:1888
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:327
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:541
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:884
llvm::MachineInstr::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:1133
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:136
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:232
llvm::MachineInstr::isLabel
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:1196
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:830
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineInstr::isGCLabel
bool isGCLabel() const
Definition: MachineInstr.h:1190
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:478
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::MachineInstr::isPredicable
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:892
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3058
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1440
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:344
llvm::adl_end
decltype(auto) adl_end(ContainerTy &&container)
Definition: STLExtras.h:256
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2296
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1155
llvm::MachineInstr::implicit_operands
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:636
llvm::MachineInstr::isInsideBundle
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:387
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1147
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:170
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:397
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1281
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::MachineInstr::isIdentityCopy
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:1311
MCSymbol.h
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:640
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:739
llvm::MachineInstr::isDebugOrPseudoInstr
bool isDebugOrPseudoInstr() const
Definition: MachineInstr.h:1226
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:87
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1223
llvm::MachineInstr::CommentFlag
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:76
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1828
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:92
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:153
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:224
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineInstr::isPseudo
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:810
llvm::MachineInstr::getAsmPrinterFlags
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:306
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:348
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1162
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:673
llvm::MachineInstr::getIntrinsicID
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
Definition: MachineInstr.h:1824
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:921
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineInstr::isConvertibleTo3Addr
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:1082
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:199
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:748
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:448
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:565
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:777
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1421
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1376
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1520
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:181
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:94
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1367
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1211
llvm::MachineInstrExpressionTrait
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
Definition: MachineInstr.h:1877
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:168
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:129
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:768
llvm::MachineInstr::isConvergent
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:935
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:167
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:169
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:90
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:545
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:179
llvm::MachineInstr::~MachineInstr
~MachineInstr()=delete
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:151
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1465
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:425
llvm::MachineInstr::getDebugOperand
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:510
llvm::MachineInstr::clearAsmPrinterFlag
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:322
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:159
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2034
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:824
Index
uint32_t Index
Definition: ELFObjHandler.cpp:82
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:727
uint64_t
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:77
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:332
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:156
llvm::MachineInstr::findRegisterDefOperand
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1443
llvm::MachineInstr::isCommutable
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MachineInstr.h:1064
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:796
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:363
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:102
llvm::MachineInstr::isMetaInstruction
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:816
llvm::MachineInstr::getNumImplicitOperands
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:585
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:1968
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineInstr::operands_begin
mop_iterator operands_begin()
Definition: MachineInstr.h:613
llvm::MachineInstr::isAsCheapAsAMove
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:1122
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:769
llvm::MachineInstr::getDebugOffset
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:429
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:177
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:70
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2231
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:341
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:163
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:730
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1894
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:965
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:178
llvm::MachineInstr::isMoveReg
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:911
llvm::MachineInstr::isDebugPHI
bool isDebugPHI() const
Definition: MachineInstr.h:1222
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:716
iterator_range.h
llvm::MachineInstr::operator=
MachineInstr & operator=(const MachineInstr &)=delete
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1256
llvm::MachineInstr::hasDelaySlot
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:946
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:757
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1351
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MDNode
Metadata node.
Definition: Metadata.h:937
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:820
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:590
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1346
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1151
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1490
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1039
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:655
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:808
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:108
llvm::MachineInstr::isRegTiedToUseOperand
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
Definition: MachineInstr.h:1522
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:763
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:574
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:176
llvm::MachineInstr::getUsedDebugRegs
SmallSet< Register, 4 > getUsedDebugRegs() const
Definition: MachineInstr.h:519
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:248
RegInfo
Definition: AMDGPUAsmParser.cpp:2542
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1262
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1803
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:754
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2315
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:175
llvm::MachineInstr::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:1143
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1022
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:112
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1527
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:854
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1220
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:730
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:161
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1209
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
llvm::MachineInstr::findRegisterUseOperand
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1415
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:833
llvm::make_filter_range
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:534
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1200
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:918
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::ArrayRecycler
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::MachineInstr::isExtractSubreg
bool isExtractSubreg() const
Definition: MachineInstr.h:1300
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:149
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:182
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:901
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1384
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:958
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1284
llvm::MachineInstr::operands_end
const_mop_iterator operands_end() const
Definition: MachineInstr.h:617
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:501
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1306
uint16_t
llvm::MachineInstr::explicit_uses
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:678
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:487
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:317
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1025
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1409
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:158
llvm::MachineInstr::getOperand
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:505
llvm::adl_begin
decltype(auto) adl_begin(ContainerTy &&container)
Definition: STLExtras.h:251
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:828
llvm::MachineInstr::explicit_operands
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:629
llvm::TrailingObjects
See the file comment for details on the usage of the TrailingObjects type.
Definition: TrailingObjects.h:212
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:90
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:660
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:98
llvm::MachineInstr::setDebugLoc
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
Definition: MachineInstr.h:1723
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:162
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:399
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:721
llvm::MachineInstr::getDebugOperand
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:514
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1288
llvm::MachineInstr::getAsmPrinterFlag
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:312
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1719
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:276
AA
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1221
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:767
llvm::MachineInstr::dropDebugNumber
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:477
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:150
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:554
llvm::MachineInstr::explicit_uses
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:674
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:994
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:104
ArrayRecycler.h
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:142
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:403
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::MachineInstr::isMSInlineAsm
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific,...
Definition: MachineInstr.h:1269
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:184
llvm::MachineInstr::CheckDefs
@ CheckDefs
Definition: MachineInstr.h:1148
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:89
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineInstr::debug_operands
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:648
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:336
llvm::MachineInstr::isTransient
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:1319
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:148
llvm::MachineInstr::isDebugOperand
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:559
ilist_node.h
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:96
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:691
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1448
llvm::SmallVectorImpl< unsigned >
MachineOperand.h
DenseMapInfo.h
llvm::MachineInstr::isConditionalBranch
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:876
llvm::MachineInstr::isBitcast
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:916
llvm::MCID::Meta
@ Meta
Definition: MCInstrDesc.h:152
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:174
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstrExpressionTrait::getEmptyKey
static MachineInstr * getEmptyKey()
Definition: MachineInstr.h:1878
llvm::MachineInstr::isSelect
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:921
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2304
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:872
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1150
llvm::MachineInstr::isAnnotationLabel
bool isAnnotationLabel() const
Definition: MachineInstr.h:1191
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3148
llvm::MachineInstr::operands
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:622
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1260
llvm::MachineInstr::setDebugInstrNum
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:471
llvm::MachineInstr::isSubregToReg
bool isSubregToReg() const
Definition: MachineInstr.h:1280
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstr::isRematerializable
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:1110
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1296
PointerSumType.h
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:180
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1052
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1045
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:88
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1392
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1214
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1435
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:650
llvm::MachineInstr::hasOptionalDef
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:804
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:845
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:766
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:619
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:157
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:945
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:231
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:183
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:463
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2285
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:698
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:337
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
llvm::MachineInstr::defs
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:661
SmallSet.h
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2247
llvm::LLT
Definition: LowLevelTypeImpl.h:39