LLVM  14.0.0git
MachineInstr.h
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1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/ilist.h"
22 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/PseudoProbe.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <utility>
38 
39 namespace llvm {
40 
41 class AAResults;
42 template <typename T> class ArrayRef;
43 class DIExpression;
44 class DILocalVariable;
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineRegisterInfo;
48 class ModuleSlotTracker;
49 class raw_ostream;
50 template <typename T> class SmallVectorImpl;
51 class SmallBitVector;
52 class StringRef;
53 class TargetInstrInfo;
54 class TargetRegisterClass;
55 class TargetRegisterInfo;
56 
57 //===----------------------------------------------------------------------===//
58 /// Representation of each machine instruction.
59 ///
60 /// This class isn't a POD type, but it must have a trivial destructor. When a
61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62 /// without having their destructor called.
63 ///
65  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66  ilist_sentinel_tracking<true>> {
67 public:
69 
70  /// Flags to specify different kinds of comments to output in
71  /// assembly code. These flags carry semantic information not
72  /// otherwise easily derivable from the IR text.
73  ///
74  enum CommentFlag {
75  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
77  TAsmComments = 0x4 // Target Asm comments should start from this value.
78  };
79 
80  enum MIFlag {
81  NoFlags = 0,
82  FrameSetup = 1 << 0, // Instruction is used as a part of
83  // function frame setup code.
84  FrameDestroy = 1 << 1, // Instruction is used as a part of
85  // function frame destruction code.
86  BundledPred = 1 << 2, // Instruction has bundled predecessors.
87  BundledSucc = 1 << 3, // Instruction has bundled successors.
88  FmNoNans = 1 << 4, // Instruction does not support Fast
89  // math nan values.
90  FmNoInfs = 1 << 5, // Instruction does not support Fast
91  // math infinity values.
92  FmNsz = 1 << 6, // Instruction is not required to retain
93  // signed zero values.
94  FmArcp = 1 << 7, // Instruction supports Fast math
95  // reciprocal approximations.
96  FmContract = 1 << 8, // Instruction supports Fast math
97  // contraction operations like fma.
98  FmAfn = 1 << 9, // Instruction may map to Fast math
99  // instrinsic approximation.
100  FmReassoc = 1 << 10, // Instruction supports Fast math
101  // reassociation of operand order.
102  NoUWrap = 1 << 11, // Instruction supports binary operator
103  // no unsigned wrap.
104  NoSWrap = 1 << 12, // Instruction supports binary operator
105  // no signed wrap.
106  IsExact = 1 << 13, // Instruction supports division is
107  // known to be exact.
108  NoFPExcept = 1 << 14, // Instruction does not raise
109  // floatint-point exceptions.
110  NoMerge = 1 << 15, // Passes that drop source location info
111  // (e.g. branch folding) should skip
112  // this instruction.
113  };
114 
115 private:
116  const MCInstrDesc *MCID; // Instruction descriptor.
117  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
118 
119  // Operands are allocated by an ArrayRecycler.
120  MachineOperand *Operands = nullptr; // Pointer to the first operand.
121  unsigned NumOperands = 0; // Number of operands on instruction.
122 
123  uint16_t Flags = 0; // Various bits of additional
124  // information about machine
125  // instruction.
126 
127  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
128  // the AsmPrinter to emit helpful
129  // comments. This is *not* semantic
130  // information. Do not use this for
131  // anything other than to convey comment
132  // information to AsmPrinter.
133 
134  // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
135  // to properly pack.
136  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
137  OperandCapacity CapOperands; // Capacity of the Operands array.
138 
139  /// Internal implementation detail class that provides out-of-line storage for
140  /// extra info used by the machine instruction when this info cannot be stored
141  /// in-line within the instruction itself.
142  ///
143  /// This has to be defined eagerly due to the implementation constraints of
144  /// `PointerSumType` where it is used.
145  class ExtraInfo final
146  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
147  public:
148  static ExtraInfo *create(BumpPtrAllocator &Allocator,
150  MCSymbol *PreInstrSymbol = nullptr,
151  MCSymbol *PostInstrSymbol = nullptr,
152  MDNode *HeapAllocMarker = nullptr) {
153  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
154  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
155  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
156  auto *Result = new (Allocator.Allocate(
157  totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
158  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
159  HasHeapAllocMarker),
160  alignof(ExtraInfo)))
161  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
162  HasHeapAllocMarker);
163 
164  // Copy the actual data into the trailing objects.
165  std::copy(MMOs.begin(), MMOs.end(),
166  Result->getTrailingObjects<MachineMemOperand *>());
167 
168  if (HasPreInstrSymbol)
169  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
170  if (HasPostInstrSymbol)
171  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
172  PostInstrSymbol;
173  if (HasHeapAllocMarker)
174  Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
175 
176  return Result;
177  }
178 
179  ArrayRef<MachineMemOperand *> getMMOs() const {
180  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
181  }
182 
183  MCSymbol *getPreInstrSymbol() const {
184  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
185  }
186 
187  MCSymbol *getPostInstrSymbol() const {
188  return HasPostInstrSymbol
189  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
190  : nullptr;
191  }
192 
193  MDNode *getHeapAllocMarker() const {
194  return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
195  }
196 
197  private:
198  friend TrailingObjects;
199 
200  // Description of the extra info, used to interpret the actual optional
201  // data appended.
202  //
203  // Note that this is not terribly space optimized. This leaves a great deal
204  // of flexibility to fit more in here later.
205  const int NumMMOs;
206  const bool HasPreInstrSymbol;
207  const bool HasPostInstrSymbol;
208  const bool HasHeapAllocMarker;
209 
210  // Implement the `TrailingObjects` internal API.
211  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
212  return NumMMOs;
213  }
214  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
215  return HasPreInstrSymbol + HasPostInstrSymbol;
216  }
217  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
218  return HasHeapAllocMarker;
219  }
220 
221  // Just a boring constructor to allow us to initialize the sizes. Always use
222  // the `create` routine above.
223  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
224  bool HasHeapAllocMarker)
225  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
226  HasPostInstrSymbol(HasPostInstrSymbol),
227  HasHeapAllocMarker(HasHeapAllocMarker) {}
228  };
229 
230  /// Enumeration of the kinds of inline extra info available. It is important
231  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
232  /// it accessible as an `ArrayRef`.
233  enum ExtraInfoInlineKinds {
234  EIIK_MMO = 0,
235  EIIK_PreInstrSymbol,
236  EIIK_PostInstrSymbol,
237  EIIK_OutOfLine
238  };
239 
240  // We store extra information about the instruction here. The common case is
241  // expected to be nothing or a single pointer (typically a MMO or a symbol).
242  // We work to optimize this common case by storing it inline here rather than
243  // requiring a separate allocation, but we fall back to an allocation when
244  // multiple pointers are needed.
245  PointerSumType<ExtraInfoInlineKinds,
246  PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
247  PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
248  PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
249  PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
250  Info;
251 
252  DebugLoc debugLoc; // Source line information.
253 
254  /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
255  /// defined by this instruction.
256  unsigned DebugInstrNum;
257 
258  // Intrusive list support
259  friend struct ilist_traits<MachineInstr>;
261  void setParent(MachineBasicBlock *P) { Parent = P; }
262 
263  /// This constructor creates a copy of the given
264  /// MachineInstr in the given MachineFunction.
266 
267  /// This constructor create a MachineInstr and add the implicit operands.
268  /// It reserves space for number of operands specified by
269  /// MCInstrDesc. An explicit DebugLoc is supplied.
271  bool NoImp = false);
272 
273  // MachineInstrs are pool-allocated and owned by MachineFunction.
274  friend class MachineFunction;
275 
276  void
277  dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
278  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
279 
280 public:
281  MachineInstr(const MachineInstr &) = delete;
282  MachineInstr &operator=(const MachineInstr &) = delete;
283  // Use MachineFunction::DeleteMachineInstr() instead.
284  ~MachineInstr() = delete;
285 
286  const MachineBasicBlock* getParent() const { return Parent; }
287  MachineBasicBlock* getParent() { return Parent; }
288 
289  /// Move the instruction before \p MovePos.
290  void moveBefore(MachineInstr *MovePos);
291 
292  /// Return the function that contains the basic block that this instruction
293  /// belongs to.
294  ///
295  /// Note: this is undefined behaviour if the instruction does not have a
296  /// parent.
297  const MachineFunction *getMF() const;
299  return const_cast<MachineFunction *>(
300  static_cast<const MachineInstr *>(this)->getMF());
301  }
302 
303  /// Return the asm printer flags bitvector.
304  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
305 
306  /// Clear the AsmPrinter bitvector.
307  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
308 
309  /// Return whether an AsmPrinter flag is set.
311  return AsmPrinterFlags & Flag;
312  }
313 
314  /// Set a flag for the AsmPrinter.
315  void setAsmPrinterFlag(uint8_t Flag) {
316  AsmPrinterFlags |= Flag;
317  }
318 
319  /// Clear specific AsmPrinter flags.
321  AsmPrinterFlags &= ~Flag;
322  }
323 
324  /// Return the MI flags bitvector.
325  uint16_t getFlags() const {
326  return Flags;
327  }
328 
329  /// Return whether an MI flag is set.
330  bool getFlag(MIFlag Flag) const {
331  return Flags & Flag;
332  }
333 
334  /// Set a MI flag.
336  Flags |= (uint16_t)Flag;
337  }
338 
339  void setFlags(unsigned flags) {
340  // Filter out the automatically maintained flags.
341  unsigned Mask = BundledPred | BundledSucc;
342  Flags = (Flags & Mask) | (flags & ~Mask);
343  }
344 
345  /// clearFlag - Clear a MI flag.
347  Flags &= ~((uint16_t)Flag);
348  }
349 
350  /// Return true if MI is in a bundle (but not the first MI in a bundle).
351  ///
352  /// A bundle looks like this before it's finalized:
353  /// ----------------
354  /// | MI |
355  /// ----------------
356  /// |
357  /// ----------------
358  /// | MI * |
359  /// ----------------
360  /// |
361  /// ----------------
362  /// | MI * |
363  /// ----------------
364  /// In this case, the first MI starts a bundle but is not inside a bundle, the
365  /// next 2 MIs are considered "inside" the bundle.
366  ///
367  /// After a bundle is finalized, it looks like this:
368  /// ----------------
369  /// | Bundle |
370  /// ----------------
371  /// |
372  /// ----------------
373  /// | MI * |
374  /// ----------------
375  /// |
376  /// ----------------
377  /// | MI * |
378  /// ----------------
379  /// |
380  /// ----------------
381  /// | MI * |
382  /// ----------------
383  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
384  /// a bundle, but the next three MIs are.
385  bool isInsideBundle() const {
386  return getFlag(BundledPred);
387  }
388 
389  /// Return true if this instruction part of a bundle. This is true
390  /// if either itself or its following instruction is marked "InsideBundle".
391  bool isBundled() const {
392  return isBundledWithPred() || isBundledWithSucc();
393  }
394 
395  /// Return true if this instruction is part of a bundle, and it is not the
396  /// first instruction in the bundle.
397  bool isBundledWithPred() const { return getFlag(BundledPred); }
398 
399  /// Return true if this instruction is part of a bundle, and it is not the
400  /// last instruction in the bundle.
401  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
402 
403  /// Bundle this instruction with its predecessor. This can be an unbundled
404  /// instruction, or it can be the first instruction in a bundle.
405  void bundleWithPred();
406 
407  /// Bundle this instruction with its successor. This can be an unbundled
408  /// instruction, or it can be the last instruction in a bundle.
409  void bundleWithSucc();
410 
411  /// Break bundle above this instruction.
412  void unbundleFromPred();
413 
414  /// Break bundle below this instruction.
415  void unbundleFromSucc();
416 
417  /// Returns the debug location id of this MachineInstr.
418  const DebugLoc &getDebugLoc() const { return debugLoc; }
419 
420  /// Return the operand containing the offset to be used if this DBG_VALUE
421  /// instruction is indirect; will be an invalid register if this value is
422  /// not indirect, and an immediate with value 0 otherwise.
424  assert(isNonListDebugValue() && "not a DBG_VALUE");
425  return getOperand(1);
426  }
428  assert(isNonListDebugValue() && "not a DBG_VALUE");
429  return getOperand(1);
430  }
431 
432  /// Return the operand for the debug variable referenced by
433  /// this DBG_VALUE instruction.
434  const MachineOperand &getDebugVariableOp() const;
436 
437  /// Return the debug variable referenced by
438  /// this DBG_VALUE instruction.
439  const DILocalVariable *getDebugVariable() const;
440 
441  /// Return the operand for the complex address expression referenced by
442  /// this DBG_VALUE instruction.
443  const MachineOperand &getDebugExpressionOp() const;
445 
446  /// Return the complex address expression referenced by
447  /// this DBG_VALUE instruction.
448  const DIExpression *getDebugExpression() const;
449 
450  /// Return the debug label referenced by
451  /// this DBG_LABEL instruction.
452  const DILabel *getDebugLabel() const;
453 
454  /// Fetch the instruction number of this MachineInstr. If it does not have
455  /// one already, a new and unique number will be assigned.
456  unsigned getDebugInstrNum();
457 
458  /// Fetch instruction number of this MachineInstr -- but before it's inserted
459  /// into \p MF. Needed for transformations that create an instruction but
460  /// don't immediately insert them.
461  unsigned getDebugInstrNum(MachineFunction &MF);
462 
463  /// Examine the instruction number of this MachineInstr. May be zero if
464  /// it hasn't been assigned a number yet.
465  unsigned peekDebugInstrNum() const { return DebugInstrNum; }
466 
467  /// Set instruction number of this MachineInstr. Avoid using unless you're
468  /// deserializing this information.
469  void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
470 
471  /// Drop any variable location debugging information associated with this
472  /// instruction. Use when an instruction is modified in such a way that it no
473  /// longer defines the value it used to. Variable locations using that value
474  /// will be dropped.
475  void dropDebugNumber() { DebugInstrNum = 0; }
476 
477  /// Emit an error referring to the source location of this instruction.
478  /// This should only be used for inline assembly that is somehow
479  /// impossible to compile. Other errors should have been handled much
480  /// earlier.
481  ///
482  /// If this method returns, the caller should try to recover from the error.
483  void emitError(StringRef Msg) const;
484 
485  /// Returns the target instruction descriptor of this MachineInstr.
486  const MCInstrDesc &getDesc() const { return *MCID; }
487 
488  /// Returns the opcode of this MachineInstr.
489  unsigned getOpcode() const { return MCID->Opcode; }
490 
491  /// Retuns the total number of operands.
492  unsigned getNumOperands() const { return NumOperands; }
493 
494  /// Returns the total number of operands which are debug locations.
495  unsigned getNumDebugOperands() const {
496  return std::distance(debug_operands().begin(), debug_operands().end());
497  }
498 
499  const MachineOperand& getOperand(unsigned i) const {
500  assert(i < getNumOperands() && "getOperand() out of range!");
501  return Operands[i];
502  }
504  assert(i < getNumOperands() && "getOperand() out of range!");
505  return Operands[i];
506  }
507 
509  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
510  return *(debug_operands().begin() + Index);
511  }
512  const MachineOperand &getDebugOperand(unsigned Index) const {
513  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
514  return *(debug_operands().begin() + Index);
515  }
516 
518  assert(isDebugValue() && "not a DBG_VALUE*");
519  SmallSet<Register, 4> UsedRegs;
520  for (auto MO : debug_operands())
521  if (MO.isReg() && MO.getReg())
522  UsedRegs.insert(MO.getReg());
523  return UsedRegs;
524  }
525 
526  /// Returns whether this debug value has at least one debug operand with the
527  /// register \p Reg.
529  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
530  return Op.isReg() && Op.getReg() == Reg;
531  });
532  }
533 
534  /// Returns a range of all of the operands that correspond to a debug use of
535  /// \p Reg.
536  template <typename Operand, typename Instruction>
537  static iterator_range<
538  filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
540  std::function<bool(Operand & Op)> OpUsesReg(
541  [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
542  return make_filter_range(MI->debug_operands(), OpUsesReg);
543  }
545  std::function<bool(const MachineOperand &Op)>>>
548  const MachineInstr>(this, Reg);
549  }
553  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
554  this, Reg);
555  }
556 
557  bool isDebugOperand(const MachineOperand *Op) const {
558  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
559  }
560 
561  unsigned getDebugOperandIndex(const MachineOperand *Op) const {
562  assert(isDebugOperand(Op) && "Expected a debug operand.");
563  return std::distance(adl_begin(debug_operands()), Op);
564  }
565 
566  /// Returns the total number of definitions.
567  unsigned getNumDefs() const {
568  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
569  }
570 
571  /// Returns true if the instruction has implicit definition.
572  bool hasImplicitDef() const {
573  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
574  I != E; ++I) {
575  const MachineOperand &MO = getOperand(I);
576  if (MO.isDef() && MO.isImplicit())
577  return true;
578  }
579  return false;
580  }
581 
582  /// Returns the implicit operands number.
583  unsigned getNumImplicitOperands() const {
585  }
586 
587  /// Return true if operand \p OpIdx is a subregister index.
588  bool isOperandSubregIdx(unsigned OpIdx) const {
590  "Expected MO_Immediate operand type.");
591  if (isExtractSubreg() && OpIdx == 2)
592  return true;
593  if (isInsertSubreg() && OpIdx == 3)
594  return true;
595  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
596  return true;
597  if (isSubregToReg() && OpIdx == 3)
598  return true;
599  return false;
600  }
601 
602  /// Returns the number of non-implicit operands.
603  unsigned getNumExplicitOperands() const;
604 
605  /// Returns the number of non-implicit definitions.
606  unsigned getNumExplicitDefs() const;
607 
608  /// iterator/begin/end - Iterate over all operands of a machine instruction.
611 
613  mop_iterator operands_end() { return Operands + NumOperands; }
614 
616  const_mop_iterator operands_end() const { return Operands + NumOperands; }
617 
620  }
623  }
625  return make_range(operands_begin(),
627  }
629  return make_range(operands_begin(),
631  }
634  }
637  }
638  /// Returns a range over all operands that are used to determine the variable
639  /// location for this DBG_VALUE instruction.
641  assert(isDebugValue() && "Must be a debug value instruction.");
642  return isDebugValueList()
645  }
646  /// \copydoc debug_operands()
648  assert(isDebugValue() && "Must be a debug value instruction.");
649  return isDebugValueList()
652  }
653  /// Returns a range over all explicit operands that are register definitions.
654  /// Implicit definition are not included!
656  return make_range(operands_begin(),
658  }
659  /// \copydoc defs()
661  return make_range(operands_begin(),
663  }
664  /// Returns a range that includes all operands that are register uses.
665  /// This may include unrelated operands which are not register uses.
668  }
669  /// \copydoc uses()
672  }
676  }
680  }
681 
682  /// Returns the number of the operand iterator \p I points to.
684  return I - operands_begin();
685  }
686 
687  /// Access to memory operands of the instruction. If there are none, that does
688  /// not imply anything about whether the function accesses memory. Instead,
689  /// the caller must behave conservatively.
691  if (!Info)
692  return {};
693 
694  if (Info.is<EIIK_MMO>())
695  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
696 
697  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
698  return EI->getMMOs();
699 
700  return {};
701  }
702 
703  /// Access to memory operands of the instruction.
704  ///
705  /// If `memoperands_begin() == memoperands_end()`, that does not imply
706  /// anything about whether the function accesses memory. Instead, the caller
707  /// must behave conservatively.
708  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
709 
710  /// Access to memory operands of the instruction.
711  ///
712  /// If `memoperands_begin() == memoperands_end()`, that does not imply
713  /// anything about whether the function accesses memory. Instead, the caller
714  /// must behave conservatively.
715  mmo_iterator memoperands_end() const { return memoperands().end(); }
716 
717  /// Return true if we don't have any memory operands which described the
718  /// memory access done by this instruction. If this is true, calling code
719  /// must be conservative.
720  bool memoperands_empty() const { return memoperands().empty(); }
721 
722  /// Return true if this instruction has exactly one MachineMemOperand.
723  bool hasOneMemOperand() const { return memoperands().size() == 1; }
724 
725  /// Return the number of memory operands.
726  unsigned getNumMemOperands() const { return memoperands().size(); }
727 
728  /// Helper to extract a pre-instruction symbol if one has been added.
730  if (!Info)
731  return nullptr;
732  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
733  return S;
734  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
735  return EI->getPreInstrSymbol();
736 
737  return nullptr;
738  }
739 
740  /// Helper to extract a post-instruction symbol if one has been added.
742  if (!Info)
743  return nullptr;
744  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
745  return S;
746  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
747  return EI->getPostInstrSymbol();
748 
749  return nullptr;
750  }
751 
752  /// Helper to extract a heap alloc marker if one has been added.
754  if (!Info)
755  return nullptr;
756  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
757  return EI->getHeapAllocMarker();
758 
759  return nullptr;
760  }
761 
762  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
763  /// queries but they are bundle aware.
764 
765  enum QueryType {
766  IgnoreBundle, // Ignore bundles
767  AnyInBundle, // Return true if any instruction in bundle has property
768  AllInBundle // Return true if all instructions in bundle have property
769  };
770 
771  /// Return true if the instruction (or in the case of a bundle,
772  /// the instructions inside the bundle) has the specified property.
773  /// The first argument is the property being queried.
774  /// The second argument indicates whether the query should look inside
775  /// instruction bundles.
776  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
777  assert(MCFlag < 64 &&
778  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
779  // Inline the fast path for unbundled or bundle-internal instructions.
780  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
781  return getDesc().getFlags() & (1ULL << MCFlag);
782 
783  // If this is the first instruction in a bundle, take the slow path.
784  return hasPropertyInBundle(1ULL << MCFlag, Type);
785  }
786 
787  /// Return true if this is an instruction that should go through the usual
788  /// legalization steps.
791  }
792 
793  /// Return true if this instruction can have a variable number of operands.
794  /// In this case, the variable operands will be after the normal
795  /// operands but before the implicit definitions and uses (if any are
796  /// present).
799  }
800 
801  /// Set if this instruction has an optional definition, e.g.
802  /// ARM instructions which can set condition code if 's' bit is set.
805  }
806 
807  /// Return true if this is a pseudo instruction that doesn't
808  /// correspond to a real machine instruction.
810  return hasProperty(MCID::Pseudo, Type);
811  }
812 
814  return hasProperty(MCID::Return, Type);
815  }
816 
817  /// Return true if this is an instruction that marks the end of an EH scope,
818  /// i.e., a catchpad or a cleanuppad instruction.
821  }
822 
824  return hasProperty(MCID::Call, Type);
825  }
826 
827  /// Return true if this is a call instruction that may have an associated
828  /// call site entry in the debug info.
830  /// Return true if copying, moving, or erasing this instruction requires
831  /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
832  /// \ref eraseCallSiteInfo).
833  bool shouldUpdateCallSiteInfo() const;
834 
835  /// Returns true if the specified instruction stops control flow
836  /// from executing the instruction immediately following it. Examples include
837  /// unconditional branches and return instructions.
839  return hasProperty(MCID::Barrier, Type);
840  }
841 
842  /// Returns true if this instruction part of the terminator for a basic block.
843  /// Typically this is things like return and branch instructions.
844  ///
845  /// Various passes use this to insert code into the bottom of a basic block,
846  /// but before control flow occurs.
849  }
850 
851  /// Returns true if this is a conditional, unconditional, or indirect branch.
852  /// Predicates below can be used to discriminate between
853  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
854  /// get more information.
856  return hasProperty(MCID::Branch, Type);
857  }
858 
859  /// Return true if this is an indirect branch, such as a
860  /// branch through a register.
863  }
864 
865  /// Return true if this is a branch which may fall
866  /// through to the next instruction or may transfer control flow to some other
867  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
868  /// information about this branch.
870  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
871  }
872 
873  /// Return true if this is a branch which always
874  /// transfers control flow to some other block. The
875  /// TargetInstrInfo::analyzeBranch method can be used to get more information
876  /// about this branch.
878  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
879  }
880 
881  /// Return true if this instruction has a predicate operand that
882  /// controls execution. It may be set to 'always', or may be set to other
883  /// values. There are various methods in TargetInstrInfo that can be used to
884  /// control and modify the predicate in this instruction.
886  // If it's a bundle than all bundled instructions must be predicable for this
887  // to return true.
889  }
890 
891  /// Return true if this instruction is a comparison.
893  return hasProperty(MCID::Compare, Type);
894  }
895 
896  /// Return true if this instruction is a move immediate
897  /// (including conditional moves) instruction.
899  return hasProperty(MCID::MoveImm, Type);
900  }
901 
902  /// Return true if this instruction is a register move.
903  /// (including moving values from subreg to reg)
905  return hasProperty(MCID::MoveReg, Type);
906  }
907 
908  /// Return true if this instruction is a bitcast instruction.
910  return hasProperty(MCID::Bitcast, Type);
911  }
912 
913  /// Return true if this instruction is a select instruction.
915  return hasProperty(MCID::Select, Type);
916  }
917 
918  /// Return true if this instruction cannot be safely duplicated.
919  /// For example, if the instruction has a unique labels attached
920  /// to it, duplicating it would cause multiple definition errors.
923  }
924 
925  /// Return true if this instruction is convergent.
926  /// Convergent instructions can not be made control-dependent on any
927  /// additional values.
929  if (isInlineAsm()) {
930  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
931  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
932  return true;
933  }
935  }
936 
937  /// Returns true if the specified instruction has a delay slot
938  /// which must be filled by the code generator.
941  }
942 
943  /// Return true for instructions that can be folded as
944  /// memory operands in other instructions. The most common use for this
945  /// is instructions that are simple loads from memory that don't modify
946  /// the loaded value in any way, but it can also be used for instructions
947  /// that can be expressed as constant-pool loads, such as V_SETALLONES
948  /// on x86, to allow them to be folded when it is beneficial.
949  /// This should only be set on instructions that return a value in their
950  /// only virtual register definition.
953  }
954 
955  /// Return true if this instruction behaves
956  /// the same way as the generic REG_SEQUENCE instructions.
957  /// E.g., on ARM,
958  /// dX VMOVDRR rY, rZ
959  /// is equivalent to
960  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
961  ///
962  /// Note that for the optimizers to be able to take advantage of
963  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
964  /// override accordingly.
967  }
968 
969  /// Return true if this instruction behaves
970  /// the same way as the generic EXTRACT_SUBREG instructions.
971  /// E.g., on ARM,
972  /// rX, rY VMOVRRD dZ
973  /// is equivalent to two EXTRACT_SUBREG:
974  /// rX = EXTRACT_SUBREG dZ, ssub_0
975  /// rY = EXTRACT_SUBREG dZ, ssub_1
976  ///
977  /// Note that for the optimizers to be able to take advantage of
978  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
979  /// override accordingly.
982  }
983 
984  /// Return true if this instruction behaves
985  /// the same way as the generic INSERT_SUBREG instructions.
986  /// E.g., on ARM,
987  /// dX = VSETLNi32 dY, rZ, Imm
988  /// is equivalent to a INSERT_SUBREG:
989  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
990  ///
991  /// Note that for the optimizers to be able to take advantage of
992  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
993  /// override accordingly.
996  }
997 
998  //===--------------------------------------------------------------------===//
999  // Side Effect Analysis
1000  //===--------------------------------------------------------------------===//
1001 
1002  /// Return true if this instruction could possibly read memory.
1003  /// Instructions with this flag set are not necessarily simple load
1004  /// instructions, they may load a value and modify it, for example.
1006  if (isInlineAsm()) {
1007  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1008  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1009  return true;
1010  }
1011  return hasProperty(MCID::MayLoad, Type);
1012  }
1013 
1014  /// Return true if this instruction could possibly modify memory.
1015  /// Instructions with this flag set are not necessarily simple store
1016  /// instructions, they may store a modified value based on their operands, or
1017  /// may not actually modify anything, for example.
1019  if (isInlineAsm()) {
1020  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1021  if (ExtraInfo & InlineAsm::Extra_MayStore)
1022  return true;
1023  }
1024  return hasProperty(MCID::MayStore, Type);
1025  }
1026 
1027  /// Return true if this instruction could possibly read or modify memory.
1029  return mayLoad(Type) || mayStore(Type);
1030  }
1031 
1032  /// Return true if this instruction could possibly raise a floating-point
1033  /// exception. This is the case if the instruction is a floating-point
1034  /// instruction that can in principle raise an exception, as indicated
1035  /// by the MCID::MayRaiseFPException property, *and* at the same time,
1036  /// the instruction is used in a context where we expect floating-point
1037  /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1038  bool mayRaiseFPException() const {
1040  !getFlag(MachineInstr::MIFlag::NoFPExcept);
1041  }
1042 
1043  //===--------------------------------------------------------------------===//
1044  // Flags that indicate whether an instruction can be modified by a method.
1045  //===--------------------------------------------------------------------===//
1046 
1047  /// Return true if this may be a 2- or 3-address
1048  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1049  /// result if Y and Z are exchanged. If this flag is set, then the
1050  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1051  /// instruction.
1052  ///
1053  /// Note that this flag may be set on instructions that are only commutable
1054  /// sometimes. In these cases, the call to commuteInstruction will fail.
1055  /// Also note that some instructions require non-trivial modification to
1056  /// commute them.
1059  }
1060 
1061  /// Return true if this is a 2-address instruction
1062  /// which can be changed into a 3-address instruction if needed. Doing this
1063  /// transformation can be profitable in the register allocator, because it
1064  /// means that the instruction can use a 2-address form if possible, but
1065  /// degrade into a less efficient form if the source and dest register cannot
1066  /// be assigned to the same register. For example, this allows the x86
1067  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1068  /// is the same speed as the shift but has bigger code size.
1069  ///
1070  /// If this returns true, then the target must implement the
1071  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1072  /// is allowed to fail if the transformation isn't valid for this specific
1073  /// instruction (e.g. shl reg, 4 on x86).
1074  ///
1077  }
1078 
1079  /// Return true if this instruction requires
1080  /// custom insertion support when the DAG scheduler is inserting it into a
1081  /// machine basic block. If this is true for the instruction, it basically
1082  /// means that it is a pseudo instruction used at SelectionDAG time that is
1083  /// expanded out into magic code by the target when MachineInstrs are formed.
1084  ///
1085  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1086  /// is used to insert this into the MachineBasicBlock.
1089  }
1090 
1091  /// Return true if this instruction requires *adjustment*
1092  /// after instruction selection by calling a target hook. For example, this
1093  /// can be used to fill in ARM 's' optional operand depending on whether
1094  /// the conditional flag register is used.
1097  }
1098 
1099  /// Returns true if this instruction is a candidate for remat.
1100  /// This flag is deprecated, please don't use it anymore. If this
1101  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1102  /// verify the instruction is really rematable.
1104  // It's only possible to re-mat a bundle if all bundled instructions are
1105  // re-materializable.
1107  }
1108 
1109  /// Returns true if this instruction has the same cost (or less) than a move
1110  /// instruction. This is useful during certain types of optimizations
1111  /// (e.g., remat during two-address conversion or machine licm)
1112  /// where we would like to remat or hoist the instruction, but not if it costs
1113  /// more than moving the instruction into the appropriate register. Note, we
1114  /// are not marking copies from and to the same register class with this flag.
1116  // Only returns true for a bundle if all bundled instructions are cheap.
1118  }
1119 
1120  /// Returns true if this instruction source operands
1121  /// have special register allocation requirements that are not captured by the
1122  /// operand register classes. e.g. ARM::STRD's two source registers must be an
1123  /// even / odd pair, ARM::STM registers have to be in ascending order.
1124  /// Post-register allocation passes should not attempt to change allocations
1125  /// for sources of instructions with this flag.
1128  }
1129 
1130  /// Returns true if this instruction def operands
1131  /// have special register allocation requirements that are not captured by the
1132  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1133  /// even / odd pair, ARM::LDM registers have to be in ascending order.
1134  /// Post-register allocation passes should not attempt to change allocations
1135  /// for definitions of instructions with this flag.
1138  }
1139 
1141  CheckDefs, // Check all operands for equality
1142  CheckKillDead, // Check all operands including kill / dead markers
1143  IgnoreDefs, // Ignore all definitions
1144  IgnoreVRegDefs // Ignore virtual register definitions
1145  };
1146 
1147  /// Return true if this instruction is identical to \p Other.
1148  /// Two instructions are identical if they have the same opcode and all their
1149  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1150  /// Note that this means liveness related flags (dead, undef, kill) do not
1151  /// affect the notion of identical.
1152  bool isIdenticalTo(const MachineInstr &Other,
1153  MICheckType Check = CheckDefs) const;
1154 
1155  /// Unlink 'this' from the containing basic block, and return it without
1156  /// deleting it.
1157  ///
1158  /// This function can not be used on bundled instructions, use
1159  /// removeFromBundle() to remove individual instructions from a bundle.
1161 
1162  /// Unlink this instruction from its basic block and return it without
1163  /// deleting it.
1164  ///
1165  /// If the instruction is part of a bundle, the other instructions in the
1166  /// bundle remain bundled.
1168 
1169  /// Unlink 'this' from the containing basic block and delete it.
1170  ///
1171  /// If this instruction is the header of a bundle, the whole bundle is erased.
1172  /// This function can not be used for instructions inside a bundle, use
1173  /// eraseFromBundle() to erase individual bundled instructions.
1174  void eraseFromParent();
1175 
1176  /// Unlink 'this' from the containing basic block and delete it.
1177  ///
1178  /// For all definitions mark their uses in DBG_VALUE nodes
1179  /// as undefined. Otherwise like eraseFromParent().
1181 
1182  /// Unlink 'this' form its basic block and delete it.
1183  ///
1184  /// If the instruction is part of a bundle, the other instructions in the
1185  /// bundle remain bundled.
1186  void eraseFromBundle();
1187 
1188  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1189  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1190  bool isAnnotationLabel() const {
1192  }
1193 
1194  /// Returns true if the MachineInstr represents a label.
1195  bool isLabel() const {
1196  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1197  }
1198 
1199  bool isCFIInstruction() const {
1200  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1201  }
1202 
1203  bool isPseudoProbe() const {
1205  }
1206 
1207  // True if the instruction represents a position in the function.
1208  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1209 
1210  bool isNonListDebugValue() const {
1211  return getOpcode() == TargetOpcode::DBG_VALUE;
1212  }
1213  bool isDebugValueList() const {
1214  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1215  }
1216  bool isDebugValue() const {
1217  return isNonListDebugValue() || isDebugValueList();
1218  }
1219  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1220  bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1221  bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1222  bool isDebugInstr() const {
1223  return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1224  }
1225  bool isDebugOrPseudoInstr() const {
1226  return isDebugInstr() || isPseudoProbe();
1227  }
1228 
1229  bool isDebugOffsetImm() const {
1230  return isNonListDebugValue() && getDebugOffset().isImm();
1231  }
1232 
1233  /// A DBG_VALUE is indirect iff the location operand is a register and
1234  /// the offset operand is an immediate.
1235  bool isIndirectDebugValue() const {
1236  return isDebugOffsetImm() && getDebugOperand(0).isReg();
1237  }
1238 
1239  /// A DBG_VALUE is an entry value iff its debug expression contains the
1240  /// DW_OP_LLVM_entry_value operation.
1241  bool isDebugEntryValue() const;
1242 
1243  /// Return true if the instruction is a debug value which describes a part of
1244  /// a variable as unavailable.
1245  bool isUndefDebugValue() const {
1246  if (!isDebugValue())
1247  return false;
1248  // If any $noreg locations are given, this DV is undef.
1249  for (const MachineOperand &Op : debug_operands())
1250  if (Op.isReg() && !Op.getReg().isValid())
1251  return true;
1252  return false;
1253  }
1254 
1255  bool isPHI() const {
1256  return getOpcode() == TargetOpcode::PHI ||
1257  getOpcode() == TargetOpcode::G_PHI;
1258  }
1259  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1260  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1261  bool isInlineAsm() const {
1262  return getOpcode() == TargetOpcode::INLINEASM ||
1264  }
1265 
1266  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1267  /// specific, be attached to a generic MachineInstr.
1268  bool isMSInlineAsm() const {
1270  }
1271 
1272  bool isStackAligningInlineAsm() const;
1274 
1275  bool isInsertSubreg() const {
1276  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1277  }
1278 
1279  bool isSubregToReg() const {
1280  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1281  }
1282 
1283  bool isRegSequence() const {
1284  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1285  }
1286 
1287  bool isBundle() const {
1288  return getOpcode() == TargetOpcode::BUNDLE;
1289  }
1290 
1291  bool isCopy() const {
1292  return getOpcode() == TargetOpcode::COPY;
1293  }
1294 
1295  bool isFullCopy() const {
1296  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1297  }
1298 
1299  bool isExtractSubreg() const {
1300  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1301  }
1302 
1303  /// Return true if the instruction behaves like a copy.
1304  /// This does not include native copy instructions.
1305  bool isCopyLike() const {
1306  return isCopy() || isSubregToReg();
1307  }
1308 
1309  /// Return true is the instruction is an identity copy.
1310  bool isIdentityCopy() const {
1311  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1313  }
1314 
1315  /// Return true if this instruction doesn't produce any output in the form of
1316  /// executable instructions.
1317  bool isMetaInstruction() const {
1318  switch (getOpcode()) {
1319  default:
1320  return false;
1321  case TargetOpcode::IMPLICIT_DEF:
1322  case TargetOpcode::KILL:
1323  case TargetOpcode::CFI_INSTRUCTION:
1325  case TargetOpcode::GC_LABEL:
1326  case TargetOpcode::DBG_VALUE:
1327  case TargetOpcode::DBG_VALUE_LIST:
1328  case TargetOpcode::DBG_INSTR_REF:
1329  case TargetOpcode::DBG_PHI:
1330  case TargetOpcode::DBG_LABEL:
1334  return true;
1335  }
1336  }
1337 
1338  /// Return true if this is a transient instruction that is either very likely
1339  /// to be eliminated during register allocation (such as copy-like
1340  /// instructions), or if this instruction doesn't have an execution-time cost.
1341  bool isTransient() const {
1342  switch (getOpcode()) {
1343  default:
1344  return isMetaInstruction();
1345  // Copy-like instructions are usually eliminated during register allocation.
1346  case TargetOpcode::PHI:
1347  case TargetOpcode::G_PHI:
1348  case TargetOpcode::COPY:
1349  case TargetOpcode::INSERT_SUBREG:
1350  case TargetOpcode::SUBREG_TO_REG:
1351  case TargetOpcode::REG_SEQUENCE:
1352  return true;
1353  }
1354  }
1355 
1356  /// Return the number of instructions inside the MI bundle, excluding the
1357  /// bundle header.
1358  ///
1359  /// This is the number of instructions that MachineBasicBlock::iterator
1360  /// skips, 0 for unbundled instructions.
1361  unsigned getBundleSize() const;
1362 
1363  /// Return true if the MachineInstr reads the specified register.
1364  /// If TargetRegisterInfo is passed, then it also checks if there
1365  /// is a read of a super-register.
1366  /// This does not count partial redefines of virtual registers as reads:
1367  /// %reg1024:6 = OP.
1369  const TargetRegisterInfo *TRI = nullptr) const {
1370  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1371  }
1372 
1373  /// Return true if the MachineInstr reads the specified virtual register.
1374  /// Take into account that a partial define is a
1375  /// read-modify-write operation.
1377  return readsWritesVirtualRegister(Reg).first;
1378  }
1379 
1380  /// Return a pair of bools (reads, writes) indicating if this instruction
1381  /// reads or writes Reg. This also considers partial defines.
1382  /// If Ops is not null, all operand indices for Reg are added.
1383  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1384  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1385 
1386  /// Return true if the MachineInstr kills the specified register.
1387  /// If TargetRegisterInfo is passed, then it also checks if there is
1388  /// a kill of a super-register.
1390  const TargetRegisterInfo *TRI = nullptr) const {
1391  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1392  }
1393 
1394  /// Return true if the MachineInstr fully defines the specified register.
1395  /// If TargetRegisterInfo is passed, then it also checks
1396  /// if there is a def of a super-register.
1397  /// NOTE: It's ignoring subreg indices on virtual registers.
1399  const TargetRegisterInfo *TRI = nullptr) const {
1400  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1401  }
1402 
1403  /// Return true if the MachineInstr modifies (fully define or partially
1404  /// define) the specified register.
1405  /// NOTE: It's ignoring subreg indices on virtual registers.
1407  const TargetRegisterInfo *TRI = nullptr) const {
1408  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1409  }
1410 
1411  /// Returns true if the register is dead in this machine instruction.
1412  /// If TargetRegisterInfo is passed, then it also checks
1413  /// if there is a dead def of a super-register.
1415  const TargetRegisterInfo *TRI = nullptr) const {
1416  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1417  }
1418 
1419  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1420  /// the given register (not considering sub/super-registers).
1422 
1423  /// Returns the operand index that is a use of the specific register or -1
1424  /// if it is not found. It further tightens the search criteria to a use
1425  /// that kills the register if isKill is true.
1426  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1427  const TargetRegisterInfo *TRI = nullptr) const;
1428 
1429  /// Wrapper for findRegisterUseOperandIdx, it returns
1430  /// a pointer to the MachineOperand rather than an index.
1432  const TargetRegisterInfo *TRI = nullptr) {
1433  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1434  return (Idx == -1) ? nullptr : &getOperand(Idx);
1435  }
1436 
1438  Register Reg, bool isKill = false,
1439  const TargetRegisterInfo *TRI = nullptr) const {
1440  return const_cast<MachineInstr *>(this)->
1442  }
1443 
1444  /// Returns the operand index that is a def of the specified register or
1445  /// -1 if it is not found. If isDead is true, defs that are not dead are
1446  /// skipped. If Overlap is true, then it also looks for defs that merely
1447  /// overlap the specified register. If TargetRegisterInfo is non-null,
1448  /// then it also checks if there is a def of a super-register.
1449  /// This may also return a register mask operand when Overlap is true.
1451  bool isDead = false, bool Overlap = false,
1452  const TargetRegisterInfo *TRI = nullptr) const;
1453 
1454  /// Wrapper for findRegisterDefOperandIdx, it returns
1455  /// a pointer to the MachineOperand rather than an index.
1456  MachineOperand *
1457  findRegisterDefOperand(Register Reg, bool isDead = false,
1458  bool Overlap = false,
1459  const TargetRegisterInfo *TRI = nullptr) {
1460  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1461  return (Idx == -1) ? nullptr : &getOperand(Idx);
1462  }
1463 
1464  const MachineOperand *
1465  findRegisterDefOperand(Register Reg, bool isDead = false,
1466  bool Overlap = false,
1467  const TargetRegisterInfo *TRI = nullptr) const {
1468  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1469  Reg, isDead, Overlap, TRI);
1470  }
1471 
1472  /// Find the index of the first operand in the
1473  /// operand list that is used to represent the predicate. It returns -1 if
1474  /// none is found.
1475  int findFirstPredOperandIdx() const;
1476 
1477  /// Find the index of the flag word operand that
1478  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1479  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1480  ///
1481  /// If GroupNo is not NULL, it will receive the number of the operand group
1482  /// containing OpIdx.
1483  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1484 
1485  /// Compute the static register class constraint for operand OpIdx.
1486  /// For normal instructions, this is derived from the MCInstrDesc.
1487  /// For inline assembly it is derived from the flag words.
1488  ///
1489  /// Returns NULL if the static register class constraint cannot be
1490  /// determined.
1491  const TargetRegisterClass*
1492  getRegClassConstraint(unsigned OpIdx,
1493  const TargetInstrInfo *TII,
1494  const TargetRegisterInfo *TRI) const;
1495 
1496  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1497  /// the given \p CurRC.
1498  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1499  /// instructions inside the bundle will be taken into account. In other words,
1500  /// this method accumulates all the constraints of the operand of this MI and
1501  /// the related bundle if MI is a bundle or inside a bundle.
1502  ///
1503  /// Returns the register class that satisfies both \p CurRC and the
1504  /// constraints set by MI. Returns NULL if such a register class does not
1505  /// exist.
1506  ///
1507  /// \pre CurRC must not be NULL.
1509  Register Reg, const TargetRegisterClass *CurRC,
1510  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1511  bool ExploreBundle = false) const;
1512 
1513  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1514  /// to the given \p CurRC.
1515  ///
1516  /// Returns the register class that satisfies both \p CurRC and the
1517  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1518  /// does not exist.
1519  ///
1520  /// \pre CurRC must not be NULL.
1521  /// \pre The operand at \p OpIdx must be a register.
1522  const TargetRegisterClass *
1523  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1524  const TargetInstrInfo *TII,
1525  const TargetRegisterInfo *TRI) const;
1526 
1527  /// Add a tie between the register operands at DefIdx and UseIdx.
1528  /// The tie will cause the register allocator to ensure that the two
1529  /// operands are assigned the same physical register.
1530  ///
1531  /// Tied operands are managed automatically for explicit operands in the
1532  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1533  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1534 
1535  /// Given the index of a tied register operand, find the
1536  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1537  /// index of the tied operand which must exist.
1538  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1539 
1540  /// Given the index of a register def operand,
1541  /// check if the register def is tied to a source operand, due to either
1542  /// two-address elimination or inline assembly constraints. Returns the
1543  /// first tied use operand index by reference if UseOpIdx is not null.
1544  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1545  unsigned *UseOpIdx = nullptr) const {
1546  const MachineOperand &MO = getOperand(DefOpIdx);
1547  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1548  return false;
1549  if (UseOpIdx)
1550  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1551  return true;
1552  }
1553 
1554  /// Return true if the use operand of the specified index is tied to a def
1555  /// operand. It also returns the def operand index by reference if DefOpIdx
1556  /// is not null.
1557  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1558  unsigned *DefOpIdx = nullptr) const {
1559  const MachineOperand &MO = getOperand(UseOpIdx);
1560  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1561  return false;
1562  if (DefOpIdx)
1563  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1564  return true;
1565  }
1566 
1567  /// Clears kill flags on all operands.
1568  void clearKillInfo();
1569 
1570  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1571  /// properly composing subreg indices where necessary.
1572  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1573  const TargetRegisterInfo &RegInfo);
1574 
1575  /// We have determined MI kills a register. Look for the
1576  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1577  /// add a implicit operand if it's not found. Returns true if the operand
1578  /// exists / is added.
1579  bool addRegisterKilled(Register IncomingReg,
1580  const TargetRegisterInfo *RegInfo,
1581  bool AddIfNotFound = false);
1582 
1583  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1584  /// all aliasing registers.
1586 
1587  /// We have determined MI defined a register without a use.
1588  /// Look for the operand that defines it and mark it as IsDead. If
1589  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1590  /// true if the operand exists / is added.
1592  bool AddIfNotFound = false);
1593 
1594  /// Clear all dead flags on operands defining register @p Reg.
1596 
1597  /// Mark all subregister defs of register @p Reg with the undef flag.
1598  /// This function is used when we determined to have a subregister def in an
1599  /// otherwise undefined super register.
1600  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1601 
1602  /// We have determined MI defines a register. Make sure there is an operand
1603  /// defining Reg.
1605  const TargetRegisterInfo *RegInfo = nullptr);
1606 
1607  /// Mark every physreg used by this instruction as
1608  /// dead except those in the UsedRegs list.
1609  ///
1610  /// On instructions with register mask operands, also add implicit-def
1611  /// operands for all registers in UsedRegs.
1613  const TargetRegisterInfo &TRI);
1614 
1615  /// Return true if it is safe to move this instruction. If
1616  /// SawStore is set to true, it means that there is a store (or call) between
1617  /// the instruction's location and its intended destination.
1618  bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1619 
1620  /// Returns true if this instruction's memory access aliases the memory
1621  /// access of Other.
1622  //
1623  /// Assumes any physical registers used to compute addresses
1624  /// have the same value for both instructions. Returns false if neither
1625  /// instruction writes to memory.
1626  ///
1627  /// @param AA Optional alias analysis, used to compare memory operands.
1628  /// @param Other MachineInstr to check aliasing against.
1629  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1630  bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1631 
1632  /// Return true if this instruction may have an ordered
1633  /// or volatile memory reference, or if the information describing the memory
1634  /// reference is not available. Return false if it is known to have no
1635  /// ordered or volatile memory references.
1636  bool hasOrderedMemoryRef() const;
1637 
1638  /// Return true if this load instruction never traps and points to a memory
1639  /// location whose value doesn't change during the execution of this function.
1640  ///
1641  /// Examples include loading a value from the constant pool or from the
1642  /// argument area of a function (if it does not change). If the instruction
1643  /// does multiple loads, this returns true only if all of the loads are
1644  /// dereferenceable and invariant.
1645  bool isDereferenceableInvariantLoad(AAResults *AA) const;
1646 
1647  /// If the specified instruction is a PHI that always merges together the
1648  /// same virtual register, return the register, otherwise return 0.
1649  unsigned isConstantValuePHI() const;
1650 
1651  /// Return true if this instruction has side effects that are not modeled
1652  /// by mayLoad / mayStore, etc.
1653  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1654  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1655  /// INLINEASM instruction, in which case the side effect property is encoded
1656  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1657  ///
1658  bool hasUnmodeledSideEffects() const;
1659 
1660  /// Returns true if it is illegal to fold a load across this instruction.
1661  bool isLoadFoldBarrier() const;
1662 
1663  /// Return true if all the defs of this instruction are dead.
1664  bool allDefsAreDead() const;
1665 
1666  /// Return a valid size if the instruction is a spill instruction.
1668 
1669  /// Return a valid size if the instruction is a folded spill instruction.
1671 
1672  /// Return a valid size if the instruction is a restore instruction.
1674 
1675  /// Return a valid size if the instruction is a folded restore instruction.
1678 
1679  /// Copy implicit register operands from specified
1680  /// instruction to this instruction.
1681  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1682 
1683  /// Debugging support
1684  /// @{
1685  /// Determine the generic type to be printed (if needed) on uses and defs.
1686  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1687  const MachineRegisterInfo &MRI) const;
1688 
1689  /// Return true when an instruction has tied register that can't be determined
1690  /// by the instruction's descriptor. This is useful for MIR printing, to
1691  /// determine whether we need to print the ties or not.
1692  bool hasComplexRegisterTies() const;
1693 
1694  /// Print this MI to \p OS.
1695  /// Don't print information that can be inferred from other instructions if
1696  /// \p IsStandalone is false. It is usually true when only a fragment of the
1697  /// function is printed.
1698  /// Only print the defs and the opcode if \p SkipOpers is true.
1699  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1700  /// Otherwise, also print the debug loc, with a terminating newline.
1701  /// \p TII is used to print the opcode name. If it's not present, but the
1702  /// MI is in a function, the opcode will be printed using the function's TII.
1703  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1704  bool SkipDebugLoc = false, bool AddNewLine = true,
1705  const TargetInstrInfo *TII = nullptr) const;
1706  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1707  bool SkipOpers = false, bool SkipDebugLoc = false,
1708  bool AddNewLine = true,
1709  const TargetInstrInfo *TII = nullptr) const;
1710  void dump() const;
1711  /// Print on dbgs() the current instruction and the instructions defining its
1712  /// operands and so on until we reach \p MaxDepth.
1713  void dumpr(const MachineRegisterInfo &MRI,
1714  unsigned MaxDepth = UINT_MAX) const;
1715  /// @}
1716 
1717  //===--------------------------------------------------------------------===//
1718  // Accessors used to build up machine instructions.
1719 
1720  /// Add the specified operand to the instruction. If it is an implicit
1721  /// operand, it is added to the end of the operand list. If it is an
1722  /// explicit operand it is added at the end of the explicit operand list
1723  /// (before the first implicit operand).
1724  ///
1725  /// MF must be the machine function that was used to allocate this
1726  /// instruction.
1727  ///
1728  /// MachineInstrBuilder provides a more convenient interface for creating
1729  /// instructions and adding operands.
1730  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1731 
1732  /// Add an operand without providing an MF reference. This only works for
1733  /// instructions that are inserted in a basic block.
1734  ///
1735  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1736  /// preferred.
1737  void addOperand(const MachineOperand &Op);
1738 
1739  /// Replace the instruction descriptor (thus opcode) of
1740  /// the current instruction with a new one.
1741  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1742 
1743  /// Replace current source information with new such.
1744  /// Avoid using this, the constructor argument is preferable.
1746  debugLoc = std::move(dl);
1747  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1748  }
1749 
1750  /// Erase an operand from an instruction, leaving it with one
1751  /// fewer operand than it started with.
1752  void RemoveOperand(unsigned OpNo);
1753 
1754  /// Clear this MachineInstr's memory reference descriptor list. This resets
1755  /// the memrefs to their most conservative state. This should be used only
1756  /// as a last resort since it greatly pessimizes our knowledge of the memory
1757  /// access performed by the instruction.
1758  void dropMemRefs(MachineFunction &MF);
1759 
1760  /// Assign this MachineInstr's memory reference descriptor list.
1761  ///
1762  /// Unlike other methods, this *will* allocate them into a new array
1763  /// associated with the provided `MachineFunction`.
1765 
1766  /// Add a MachineMemOperand to the machine instruction.
1767  /// This function should be used only occasionally. The setMemRefs function
1768  /// is the primary method for setting up a MachineInstr's MemRefs list.
1770 
1771  /// Clone another MachineInstr's memory reference descriptor list and replace
1772  /// ours with it.
1773  ///
1774  /// Note that `*this` may be the incoming MI!
1775  ///
1776  /// Prefer this API whenever possible as it can avoid allocations in common
1777  /// cases.
1778  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1779 
1780  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1781  /// list and replace ours with it.
1782  ///
1783  /// Note that `*this` may be one of the incoming MIs!
1784  ///
1785  /// Prefer this API whenever possible as it can avoid allocations in common
1786  /// cases.
1789 
1790  /// Set a symbol that will be emitted just prior to the instruction itself.
1791  ///
1792  /// Setting this to a null pointer will remove any such symbol.
1793  ///
1794  /// FIXME: This is not fully implemented yet.
1796 
1797  /// Set a symbol that will be emitted just after the instruction itself.
1798  ///
1799  /// Setting this to a null pointer will remove any such symbol.
1800  ///
1801  /// FIXME: This is not fully implemented yet.
1803 
1804  /// Clone another MachineInstr's pre- and post- instruction symbols and
1805  /// replace ours with it.
1807 
1808  /// Set a marker on instructions that denotes where we should create and emit
1809  /// heap alloc site labels. This waits until after instruction selection and
1810  /// optimizations to create the label, so it should still work if the
1811  /// instruction is removed or duplicated.
1812  void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1813 
1814  /// Return the MIFlags which represent both MachineInstrs. This
1815  /// should be used when merging two MachineInstrs into one. This routine does
1816  /// not modify the MIFlags of this MachineInstr.
1817  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1818 
1820 
1821  /// Copy all flags to MachineInst MIFlags
1822  void copyIRFlags(const Instruction &I);
1823 
1824  /// Break any tie involving OpIdx.
1825  void untieRegOperand(unsigned OpIdx) {
1826  MachineOperand &MO = getOperand(OpIdx);
1827  if (MO.isReg() && MO.isTied()) {
1828  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1829  MO.TiedTo = 0;
1830  }
1831  }
1832 
1833  /// Add all implicit def and use operands to this instruction.
1835 
1836  /// Scan instructions immediately following MI and collect any matching
1837  /// DBG_VALUEs.
1839 
1840  /// Find all DBG_VALUEs that point to the register def in this instruction
1841  /// and point them to \p Reg instead.
1843 
1844  /// Returns the Intrinsic::ID for this instruction.
1845  /// \pre Must have an intrinsic ID operand.
1846  unsigned getIntrinsicID() const {
1848  }
1849 
1850  /// Sets all register debug operands in this debug value instruction to be
1851  /// undef.
1853  assert(isDebugValue() && "Must be a debug value instruction.");
1854  for (MachineOperand &MO : debug_operands()) {
1855  if (MO.isReg()) {
1856  MO.setReg(0);
1857  MO.setSubReg(0);
1858  }
1859  }
1860  }
1861 
1862 private:
1863  /// If this instruction is embedded into a MachineFunction, return the
1864  /// MachineRegisterInfo object for the current function, otherwise
1865  /// return null.
1866  MachineRegisterInfo *getRegInfo();
1867 
1868  /// Unlink all of the register operands in this instruction from their
1869  /// respective use lists. This requires that the operands already be on their
1870  /// use lists.
1871  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1872 
1873  /// Add all of the register operands in this instruction from their
1874  /// respective use lists. This requires that the operands not be on their
1875  /// use lists yet.
1876  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1877 
1878  /// Slow path for hasProperty when we're dealing with a bundle.
1879  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1880 
1881  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1882  /// this MI and the given operand index \p OpIdx.
1883  /// If the related operand does not constrained Reg, this returns CurRC.
1884  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1885  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1886  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1887 
1888  /// Stores extra instruction information inline or allocates as ExtraInfo
1889  /// based on the number of pointers.
1890  void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1891  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1892  MDNode *HeapAllocMarker);
1893 };
1894 
1895 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1896 /// instruction rather than by pointer value.
1897 /// The hashing and equality testing functions ignore definitions so this is
1898 /// useful for CSE, etc.
1900  static inline MachineInstr *getEmptyKey() {
1901  return nullptr;
1902  }
1903 
1904  static inline MachineInstr *getTombstoneKey() {
1905  return reinterpret_cast<MachineInstr*>(-1);
1906  }
1907 
1908  static unsigned getHashValue(const MachineInstr* const &MI);
1909 
1910  static bool isEqual(const MachineInstr* const &LHS,
1911  const MachineInstr* const &RHS) {
1912  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1913  LHS == getEmptyKey() || LHS == getTombstoneKey())
1914  return LHS == RHS;
1915  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1916  }
1917 };
1918 
1919 //===----------------------------------------------------------------------===//
1920 // Debugging Support
1921 
1923  MI.print(OS);
1924  return OS;
1925 }
1926 
1927 } // end namespace llvm
1928 
1929 #endif // LLVM_CODEGEN_MACHINEINSTR_H
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1216
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:768
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:859
llvm::MachineInstr::getNumDebugOperands
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:495
llvm::MachineInstr::isBranch
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:855
llvm::MachineInstr::setDebugValueUndef
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
Definition: MachineInstr.h:1852
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:152
TrailingObjects.h
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2010
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2044
llvm::MachineInstr::isUndefDebugValue
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
Definition: MachineInstr.h:1245
llvm::MachineInstr::isExtractSubregLike
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MachineInstr.h:980
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2372
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:666
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1957
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:158
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:683
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:163
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1260
llvm::MachineInstr::getDebugOperandIndex
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:561
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:861
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2070
llvm::MachineInstr::usesCustomInsertionHook
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:1087
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1178
llvm::TrailingObjects< ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode * >::TrailingObjects
TrailingObjects(const TrailingObjects &)=delete
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:77
llvm::MachineInstr::explicit_operands
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:624
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:921
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1232
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:640
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1028
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:164
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:228
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:726
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:708
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1177
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:741
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:534
llvm::MachineInstr::isCompare
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:892
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:303
llvm::MachineInstr::isEHScopeReturn
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:819
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:672
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:169
llvm::MachineInstr::isRegSequenceLike
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:965
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::ArrayRef::iterator
const_pointer iterator
Definition: ArrayRef.h:50
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1235
llvm::MachineInstr::implicit_operands
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:632
ilist.h
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1142
InlineAsm.h
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:171
llvm::ilist_node_with_parent
An ilist node that can access its parent list.
Definition: ilist_node.h:256
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MachineInstr::clearAsmPrinterFlags
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:307
llvm::MachineInstr::isMoveImmediate
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:898
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:988
llvm::MachineInstr::isInsertSubregLike
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MachineInstr.h:994
llvm::MachineInstr::isDebugOffsetImm
bool isDebugOffsetImm() const
Definition: MachineInstr.h:1229
llvm::MachineInstr::NoSchedComment
@ NoSchedComment
Definition: MachineInstr.h:76
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:759
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1203
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2026
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1476
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1444
llvm::MachineInstr::isEHLabel
bool isEHLabel() const
Definition: MachineInstr.h:1188
llvm::ilist_callback_traits
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:64
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:655
llvm::MachineInstr::hasPostISelHook
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:1095
llvm::MachineInstr::isBundled
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:391
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineInstr::operands_begin
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:615
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::filter_iterator_impl
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:412
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:98
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineInstr::findRegisterUseOperand
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1431
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:980
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::Optional< unsigned >
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1291
llvm::MachineInstr::peekDebugInstrNum
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:465
llvm::MachineInstr::setDebugLoc
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
Definition: MachineInstr.h:1745
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:182
llvm::MachineInstr::operands_end
mop_iterator operands_end()
Definition: MachineInstr.h:613
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:797
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:227
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2557
llvm::MachineInstr::uses
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:670
llvm::MachineInstr::hasDebugOperandForReg
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:528
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:546
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineInstr::getMF
MachineFunction * getMF()
Definition: MachineInstr.h:298
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:723
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:838
llvm::MachineInstr::isPreISelOpcode
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:789
llvm::MachineInstrExpressionTrait::getTombstoneKey
static MachineInstr * getTombstoneKey()
Definition: MachineInstr.h:1904
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1376
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1557
llvm::MachineInstr::isInsertSubreg
bool isInsertSubreg() const
Definition: MachineInstr.h:1275
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:567
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:980
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1197
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1126
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:226
llvm::MachineInstr::readsVirtualRegister
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:1376
llvm::MachineInstr::getParent
MachineBasicBlock * getParent()
Definition: MachineInstr.h:287
llvm::MachineInstrExpressionTrait::isEqual
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Definition: MachineInstr.h:1910
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:325
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:539
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:877
llvm::MachineInstr::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:1126
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:153
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1292
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::MachineInstr::isLabel
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:1195
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineInstr::isGCLabel
bool isGCLabel() const
Definition: MachineInstr.h:1189
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:505
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::MachineInstr::isPredicable
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:885
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3053
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:371
llvm::adl_end
decltype(auto) adl_end(ContainerTy &&container)
Definition: STLExtras.h:242
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2346
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1202
llvm::MachineInstr::implicit_operands
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:635
llvm::MachineInstr::isInsideBundle
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:385
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1140
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:168
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:424
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1328
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::isIdentityCopy
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:1310
MCSymbol.h
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:667
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:786
llvm::MachineInstr::isDebugOrPseudoInstr
bool isDebugOrPseudoInstr() const
Definition: MachineInstr.h:1225
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:104
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1222
llvm::MachineInstr::CommentFlag
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:74
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1878
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:90
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:151
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::isPseudo
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:809
llvm::MachineInstr::getAsmPrinterFlags
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:304
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:346
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1209
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:720
llvm::MachineInstr::getIntrinsicID
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
Definition: MachineInstr.h:1846
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:968
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineInstr::isConvertibleTo3Addr
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:1075
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:197
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:795
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:475
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:592
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:776
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:104
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1469
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1398
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1570
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:179
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:92
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1389
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1210
llvm::MachineInstrExpressionTrait
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
Definition: MachineInstr.h:1899
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:166
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:767
llvm::MachineInstr::isConvergent
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:928
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:165
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:167
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:89
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:572
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:177
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:243
llvm::MachineInstr::~MachineInstr
~MachineInstr()=delete
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:150
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1515
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:423
llvm::MachineInstr::getDebugOperand
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:508
llvm::MachineInstr::clearAsmPrinterFlag
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:320
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:157
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2084
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:871
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:726
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:75
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:154
llvm::MachineInstr::findRegisterDefOperand
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1465
llvm::MachineInstr::isCommutable
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MachineInstr.h:1057
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:843
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:390
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:100
llvm::MachineInstr::getNumImplicitOperands
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:583
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:67
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2018
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineInstr::operands_begin
mop_iterator operands_begin()
Definition: MachineInstr.h:612
llvm::MachineInstr::isAsCheapAsAMove
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:1115
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:768
llvm::MachineInstr::getDebugOffset
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:427
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:175
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:68
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2281
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:339
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:161
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:777
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1944
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1012
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:176
llvm::MachineInstr::isMoveReg
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:904
llvm::MachineInstr::isDebugPHI
bool isDebugPHI() const
Definition: MachineInstr.h:1221
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:715
iterator_range.h
llvm::MachineInstr::operator=
MachineInstr & operator=(const MachineInstr &)=delete
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1255
llvm::MachineInstr::hasDelaySlot
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:939
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:804
llvm::MachineInstr::isMetaInstruction
bool isMetaInstruction() const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:1317
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1398
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:588
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1368
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1144
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1540
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:994
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:702
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:855
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:106
llvm::MachineInstr::isRegTiedToUseOperand
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
Definition: MachineInstr.h:1544
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:810
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:572
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:174
llvm::MachineInstr::getUsedDebugRegs
SmallSet< Register, 4 > getUsedDebugRegs() const
Definition: MachineInstr.h:517
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:246
RegInfo
Definition: AMDGPUAsmParser.cpp:2366
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1554
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1261
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1825
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:753
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2365
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:173
llvm::MachineInstr::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:1136
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1069
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:110
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1577
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:847
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1219
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:729
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:159
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1208
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::MachineInstr::findRegisterUseOperand
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1437
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:880
llvm::make_filter_range
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:486
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1199
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:859
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::ArrayRecycler
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
llvm::MachineInstr::isExtractSubreg
bool isExtractSubreg() const
Definition: MachineInstr.h:1299
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:148
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:180
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:948
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1406
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:951
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1283
llvm::MachineInstr::operands_end
const_mop_iterator operands_end() const
Definition: MachineInstr.h:616
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:219
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:528
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1305
uint16_t
llvm::MachineInstr::explicit_uses
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:677
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:153
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:514
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:315
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1457
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:156
llvm::MachineInstr::getOperand
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:503
llvm::adl_begin
decltype(auto) adl_begin(ContainerTy &&container)
Definition: STLExtras.h:237
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:983
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:875
llvm::MachineInstr::explicit_operands
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:628
llvm::TrailingObjects
See the file comment for details on the usage of the TrailingObjects type.
Definition: TrailingObjects.h:212
PseudoProbe.h
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:707
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:96
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:160
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:397
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:720
llvm::MachineInstr::getDebugOperand
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:512
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1287
llvm::MachineInstr::getAsmPrinterFlag
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:310
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:682
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1220
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:766
llvm::MachineInstr::dropDebugNumber
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:475
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:149
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:552
llvm::MachineInstr::explicit_uses
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:673
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1041
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:102
ArrayRecycler.h
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:146
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:401
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::MachineInstr::isMSInlineAsm
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific,...
Definition: MachineInstr.h:1268
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::MachineInstr::CheckDefs
@ CheckDefs
Definition: MachineInstr.h:1141
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MachineInstr::debug_operands
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:647
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:363
llvm::MachineInstr::isTransient
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:1341
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:147
llvm::MachineInstr::isDebugOperand
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:557
ilist_node.h
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:94
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:690
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1498
llvm::SmallVectorImpl< unsigned >
MachineOperand.h
DenseMapInfo.h
llvm::MachineInstr::isConditionalBranch
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:869
llvm::MachineInstr::isBitcast
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:909
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1741
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:172
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstrExpressionTrait::getEmptyKey
static MachineInstr * getEmptyKey()
Definition: MachineInstr.h:1900
llvm::MachineInstr::isSelect
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:914
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2354
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:919
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1143
llvm::MachineInstr::isAnnotationLabel
bool isAnnotationLabel() const
Definition: MachineInstr.h:1190
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3133
llvm::MachineInstr::operands
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:621
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1259
llvm::MachineInstr::setDebugInstrNum
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:469
llvm::MachineInstr::isSubregToReg
bool isSubregToReg() const
Definition: MachineInstr.h:1279
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstr::isRematerializable
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:1103
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1295
PointerSumType.h
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:178
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1038
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1414
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1213
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1457
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstr::hasOptionalDef
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:803
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:838
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:765
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:155
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:992
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:181
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:154
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:490
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2335
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:745
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:335
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1172
llvm::MachineInstr::defs
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:660
SmallSet.h
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2297
llvm::LLT
Definition: LowLevelTypeImpl.h:40