LLVM 17.0.0git
MachineInstr.h
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1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/ADT/ilist.h"
22#include "llvm/ADT/ilist_node.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
33#include <algorithm>
34#include <cassert>
35#include <cstdint>
36#include <utility>
37
38namespace llvm {
39
40class DILabel;
41class Instruction;
42class MDNode;
43class AAResults;
44template <typename T> class ArrayRef;
45class DIExpression;
46class DILocalVariable;
47class MachineBasicBlock;
48class MachineFunction;
49class MachineRegisterInfo;
50class ModuleSlotTracker;
51class raw_ostream;
52template <typename T> class SmallVectorImpl;
53class SmallBitVector;
54class StringRef;
55class TargetInstrInfo;
56class TargetRegisterClass;
57class TargetRegisterInfo;
58
59//===----------------------------------------------------------------------===//
60/// Representation of each machine instruction.
61///
62/// This class isn't a POD type, but it must have a trivial destructor. When a
63/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
64/// without having their destructor called.
65///
67 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
68 ilist_sentinel_tracking<true>> {
69public:
71
72 /// Flags to specify different kinds of comments to output in
73 /// assembly code. These flags carry semantic information not
74 /// otherwise easily derivable from the IR text.
75 ///
77 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
79 TAsmComments = 0x4 // Target Asm comments should start from this value.
80 };
81
82 enum MIFlag {
84 FrameSetup = 1 << 0, // Instruction is used as a part of
85 // function frame setup code.
86 FrameDestroy = 1 << 1, // Instruction is used as a part of
87 // function frame destruction code.
88 BundledPred = 1 << 2, // Instruction has bundled predecessors.
89 BundledSucc = 1 << 3, // Instruction has bundled successors.
90 FmNoNans = 1 << 4, // Instruction does not support Fast
91 // math nan values.
92 FmNoInfs = 1 << 5, // Instruction does not support Fast
93 // math infinity values.
94 FmNsz = 1 << 6, // Instruction is not required to retain
95 // signed zero values.
96 FmArcp = 1 << 7, // Instruction supports Fast math
97 // reciprocal approximations.
98 FmContract = 1 << 8, // Instruction supports Fast math
99 // contraction operations like fma.
100 FmAfn = 1 << 9, // Instruction may map to Fast math
101 // intrinsic approximation.
102 FmReassoc = 1 << 10, // Instruction supports Fast math
103 // reassociation of operand order.
104 NoUWrap = 1 << 11, // Instruction supports binary operator
105 // no unsigned wrap.
106 NoSWrap = 1 << 12, // Instruction supports binary operator
107 // no signed wrap.
108 IsExact = 1 << 13, // Instruction supports division is
109 // known to be exact.
110 NoFPExcept = 1 << 14, // Instruction does not raise
111 // floatint-point exceptions.
112 NoMerge = 1 << 15, // Passes that drop source location info
113 // (e.g. branch folding) should skip
114 // this instruction.
115 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
116 };
117
118private:
119 const MCInstrDesc *MCID; // Instruction descriptor.
120 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
121
122 // Operands are allocated by an ArrayRecycler.
123 MachineOperand *Operands = nullptr; // Pointer to the first operand.
124 uint32_t Flags = 0; // Various bits of additional
125 // information about machine
126 // instruction.
127 uint16_t NumOperands = 0; // Number of operands on instruction.
128 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
129 // the AsmPrinter to emit helpful
130 // comments. This is *not* semantic
131 // information. Do not use this for
132 // anything other than to convey comment
133 // information to AsmPrinter.
134
135 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
136 // to properly pack.
137 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
138 OperandCapacity CapOperands; // Capacity of the Operands array.
139
140 /// Internal implementation detail class that provides out-of-line storage for
141 /// extra info used by the machine instruction when this info cannot be stored
142 /// in-line within the instruction itself.
143 ///
144 /// This has to be defined eagerly due to the implementation constraints of
145 /// `PointerSumType` where it is used.
146 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
147 MCSymbol *, MDNode *, uint32_t> {
148 public:
149 static ExtraInfo *create(BumpPtrAllocator &Allocator,
151 MCSymbol *PreInstrSymbol = nullptr,
152 MCSymbol *PostInstrSymbol = nullptr,
153 MDNode *HeapAllocMarker = nullptr,
154 MDNode *PCSections = nullptr,
155 uint32_t CFIType = 0) {
156 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
157 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
158 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
159 bool HasCFIType = CFIType != 0;
160 bool HasPCSections = PCSections != nullptr;
161 auto *Result = new (Allocator.Allocate(
162 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
163 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
164 HasHeapAllocMarker + HasPCSections, HasCFIType),
165 alignof(ExtraInfo)))
166 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
167 HasHeapAllocMarker, HasPCSections, HasCFIType);
168
169 // Copy the actual data into the trailing objects.
170 std::copy(MMOs.begin(), MMOs.end(),
171 Result->getTrailingObjects<MachineMemOperand *>());
172
173 if (HasPreInstrSymbol)
174 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
175 if (HasPostInstrSymbol)
176 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
177 PostInstrSymbol;
178 if (HasHeapAllocMarker)
179 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
180 if (HasPCSections)
181 Result->getTrailingObjects<MDNode *>()[HasHeapAllocMarker] =
182 PCSections;
183 if (HasCFIType)
184 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
185
186 return Result;
187 }
188
189 ArrayRef<MachineMemOperand *> getMMOs() const {
190 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
191 }
192
193 MCSymbol *getPreInstrSymbol() const {
194 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
195 }
196
197 MCSymbol *getPostInstrSymbol() const {
198 return HasPostInstrSymbol
199 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
200 : nullptr;
201 }
202
203 MDNode *getHeapAllocMarker() const {
204 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
205 }
206
207 MDNode *getPCSections() const {
208 return HasPCSections
209 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
210 : nullptr;
211 }
212
213 uint32_t getCFIType() const {
214 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
215 }
216
217 private:
218 friend TrailingObjects;
219
220 // Description of the extra info, used to interpret the actual optional
221 // data appended.
222 //
223 // Note that this is not terribly space optimized. This leaves a great deal
224 // of flexibility to fit more in here later.
225 const int NumMMOs;
226 const bool HasPreInstrSymbol;
227 const bool HasPostInstrSymbol;
228 const bool HasHeapAllocMarker;
229 const bool HasPCSections;
230 const bool HasCFIType;
231
232 // Implement the `TrailingObjects` internal API.
233 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
234 return NumMMOs;
235 }
236 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
237 return HasPreInstrSymbol + HasPostInstrSymbol;
238 }
239 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
240 return HasHeapAllocMarker + HasPCSections;
241 }
242 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
243 return HasCFIType;
244 }
245
246 // Just a boring constructor to allow us to initialize the sizes. Always use
247 // the `create` routine above.
248 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
249 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType)
250 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
251 HasPostInstrSymbol(HasPostInstrSymbol),
252 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
253 HasCFIType(HasCFIType) {}
254 };
255
256 /// Enumeration of the kinds of inline extra info available. It is important
257 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
258 /// it accessible as an `ArrayRef`.
259 enum ExtraInfoInlineKinds {
260 EIIK_MMO = 0,
261 EIIK_PreInstrSymbol,
262 EIIK_PostInstrSymbol,
263 EIIK_OutOfLine
264 };
265
266 // We store extra information about the instruction here. The common case is
267 // expected to be nothing or a single pointer (typically a MMO or a symbol).
268 // We work to optimize this common case by storing it inline here rather than
269 // requiring a separate allocation, but we fall back to an allocation when
270 // multiple pointers are needed.
271 PointerSumType<ExtraInfoInlineKinds,
272 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
273 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
274 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
275 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
276 Info;
277
278 DebugLoc DbgLoc; // Source line information.
279
280 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
281 /// defined by this instruction.
282 unsigned DebugInstrNum;
283
284 // Intrusive list support
285 friend struct ilist_traits<MachineInstr>;
287 void setParent(MachineBasicBlock *P) { Parent = P; }
288
289 /// This constructor creates a copy of the given
290 /// MachineInstr in the given MachineFunction.
292
293 /// This constructor create a MachineInstr and add the implicit operands.
294 /// It reserves space for number of operands specified by
295 /// MCInstrDesc. An explicit DebugLoc is supplied.
297 bool NoImp = false);
298
299 // MachineInstrs are pool-allocated and owned by MachineFunction.
300 friend class MachineFunction;
301
302 void
303 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
304 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
305
306 static bool opIsRegDef(const MachineOperand &Op) {
307 return Op.isReg() && Op.isDef();
308 }
309
310 static bool opIsRegUse(const MachineOperand &Op) {
311 return Op.isReg() && Op.isUse();
312 }
313
314public:
315 MachineInstr(const MachineInstr &) = delete;
317 // Use MachineFunction::DeleteMachineInstr() instead.
318 ~MachineInstr() = delete;
319
320 const MachineBasicBlock* getParent() const { return Parent; }
321 MachineBasicBlock* getParent() { return Parent; }
322
323 /// Move the instruction before \p MovePos.
324 void moveBefore(MachineInstr *MovePos);
325
326 /// Return the function that contains the basic block that this instruction
327 /// belongs to.
328 ///
329 /// Note: this is undefined behaviour if the instruction does not have a
330 /// parent.
331 const MachineFunction *getMF() const;
333 return const_cast<MachineFunction *>(
334 static_cast<const MachineInstr *>(this)->getMF());
335 }
336
337 /// Return the asm printer flags bitvector.
338 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
339
340 /// Clear the AsmPrinter bitvector.
341 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
342
343 /// Return whether an AsmPrinter flag is set.
345 return AsmPrinterFlags & Flag;
346 }
347
348 /// Set a flag for the AsmPrinter.
349 void setAsmPrinterFlag(uint8_t Flag) {
350 AsmPrinterFlags |= Flag;
351 }
352
353 /// Clear specific AsmPrinter flags.
355 AsmPrinterFlags &= ~Flag;
356 }
357
358 /// Return the MI flags bitvector.
360 return Flags;
361 }
362
363 /// Return whether an MI flag is set.
364 bool getFlag(MIFlag Flag) const {
365 return Flags & Flag;
366 }
367
368 /// Set a MI flag.
369 void setFlag(MIFlag Flag) {
370 Flags |= (uint32_t)Flag;
371 }
372
373 void setFlags(unsigned flags) {
374 // Filter out the automatically maintained flags.
375 unsigned Mask = BundledPred | BundledSucc;
376 Flags = (Flags & Mask) | (flags & ~Mask);
377 }
378
379 /// clearFlag - Clear a MI flag.
380 void clearFlag(MIFlag Flag) {
381 Flags &= ~((uint32_t)Flag);
382 }
383
384 /// Return true if MI is in a bundle (but not the first MI in a bundle).
385 ///
386 /// A bundle looks like this before it's finalized:
387 /// ----------------
388 /// | MI |
389 /// ----------------
390 /// |
391 /// ----------------
392 /// | MI * |
393 /// ----------------
394 /// |
395 /// ----------------
396 /// | MI * |
397 /// ----------------
398 /// In this case, the first MI starts a bundle but is not inside a bundle, the
399 /// next 2 MIs are considered "inside" the bundle.
400 ///
401 /// After a bundle is finalized, it looks like this:
402 /// ----------------
403 /// | Bundle |
404 /// ----------------
405 /// |
406 /// ----------------
407 /// | MI * |
408 /// ----------------
409 /// |
410 /// ----------------
411 /// | MI * |
412 /// ----------------
413 /// |
414 /// ----------------
415 /// | MI * |
416 /// ----------------
417 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
418 /// a bundle, but the next three MIs are.
419 bool isInsideBundle() const {
420 return getFlag(BundledPred);
421 }
422
423 /// Return true if this instruction part of a bundle. This is true
424 /// if either itself or its following instruction is marked "InsideBundle".
425 bool isBundled() const {
427 }
428
429 /// Return true if this instruction is part of a bundle, and it is not the
430 /// first instruction in the bundle.
431 bool isBundledWithPred() const { return getFlag(BundledPred); }
432
433 /// Return true if this instruction is part of a bundle, and it is not the
434 /// last instruction in the bundle.
435 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
436
437 /// Bundle this instruction with its predecessor. This can be an unbundled
438 /// instruction, or it can be the first instruction in a bundle.
439 void bundleWithPred();
440
441 /// Bundle this instruction with its successor. This can be an unbundled
442 /// instruction, or it can be the last instruction in a bundle.
443 void bundleWithSucc();
444
445 /// Break bundle above this instruction.
446 void unbundleFromPred();
447
448 /// Break bundle below this instruction.
449 void unbundleFromSucc();
450
451 /// Returns the debug location id of this MachineInstr.
452 const DebugLoc &getDebugLoc() const { return DbgLoc; }
453
454 /// Return the operand containing the offset to be used if this DBG_VALUE
455 /// instruction is indirect; will be an invalid register if this value is
456 /// not indirect, and an immediate with value 0 otherwise.
458 assert(isNonListDebugValue() && "not a DBG_VALUE");
459 return getOperand(1);
460 }
462 assert(isNonListDebugValue() && "not a DBG_VALUE");
463 return getOperand(1);
464 }
465
466 /// Return the operand for the debug variable referenced by
467 /// this DBG_VALUE instruction.
468 const MachineOperand &getDebugVariableOp() const;
470
471 /// Return the debug variable referenced by
472 /// this DBG_VALUE instruction.
473 const DILocalVariable *getDebugVariable() const;
474
475 /// Return the operand for the complex address expression referenced by
476 /// this DBG_VALUE instruction.
479
480 /// Return the complex address expression referenced by
481 /// this DBG_VALUE instruction.
482 const DIExpression *getDebugExpression() const;
483
484 /// Return the debug label referenced by
485 /// this DBG_LABEL instruction.
486 const DILabel *getDebugLabel() const;
487
488 /// Fetch the instruction number of this MachineInstr. If it does not have
489 /// one already, a new and unique number will be assigned.
490 unsigned getDebugInstrNum();
491
492 /// Fetch instruction number of this MachineInstr -- but before it's inserted
493 /// into \p MF. Needed for transformations that create an instruction but
494 /// don't immediately insert them.
495 unsigned getDebugInstrNum(MachineFunction &MF);
496
497 /// Examine the instruction number of this MachineInstr. May be zero if
498 /// it hasn't been assigned a number yet.
499 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
500
501 /// Set instruction number of this MachineInstr. Avoid using unless you're
502 /// deserializing this information.
503 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
504
505 /// Drop any variable location debugging information associated with this
506 /// instruction. Use when an instruction is modified in such a way that it no
507 /// longer defines the value it used to. Variable locations using that value
508 /// will be dropped.
509 void dropDebugNumber() { DebugInstrNum = 0; }
510
511 /// Emit an error referring to the source location of this instruction.
512 /// This should only be used for inline assembly that is somehow
513 /// impossible to compile. Other errors should have been handled much
514 /// earlier.
515 ///
516 /// If this method returns, the caller should try to recover from the error.
517 void emitError(StringRef Msg) const;
518
519 /// Returns the target instruction descriptor of this MachineInstr.
520 const MCInstrDesc &getDesc() const { return *MCID; }
521
522 /// Returns the opcode of this MachineInstr.
523 unsigned getOpcode() const { return MCID->Opcode; }
524
525 /// Retuns the total number of operands.
526 unsigned getNumOperands() const { return NumOperands; }
527
528 /// Returns the total number of operands which are debug locations.
529 unsigned getNumDebugOperands() const {
530 return std::distance(debug_operands().begin(), debug_operands().end());
531 }
532
533 const MachineOperand& getOperand(unsigned i) const {
534 assert(i < getNumOperands() && "getOperand() out of range!");
535 return Operands[i];
536 }
538 assert(i < getNumOperands() && "getOperand() out of range!");
539 return Operands[i];
540 }
541
543 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
544 return *(debug_operands().begin() + Index);
545 }
546 const MachineOperand &getDebugOperand(unsigned Index) const {
547 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
548 return *(debug_operands().begin() + Index);
549 }
550
552 assert(isDebugValue() && "not a DBG_VALUE*");
553 SmallSet<Register, 4> UsedRegs;
554 for (const auto &MO : debug_operands())
555 if (MO.isReg() && MO.getReg())
556 UsedRegs.insert(MO.getReg());
557 return UsedRegs;
558 }
559
560 /// Returns whether this debug value has at least one debug operand with the
561 /// register \p Reg.
563 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
564 return Op.isReg() && Op.getReg() == Reg;
565 });
566 }
567
568 /// Returns a range of all of the operands that correspond to a debug use of
569 /// \p Reg.
570 template <typename Operand, typename Instruction>
571 static iterator_range<
572 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
574 std::function<bool(Operand & Op)> OpUsesReg(
575 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
576 return make_filter_range(MI->debug_operands(), OpUsesReg);
577 }
579 std::function<bool(const MachineOperand &Op)>>>
582 const MachineInstr>(this, Reg);
583 }
585 std::function<bool(MachineOperand &Op)>>>
587 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
588 this, Reg);
589 }
590
591 bool isDebugOperand(const MachineOperand *Op) const {
592 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
593 }
594
595 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
596 assert(isDebugOperand(Op) && "Expected a debug operand.");
597 return std::distance(adl_begin(debug_operands()), Op);
598 }
599
600 /// Returns the total number of definitions.
601 unsigned getNumDefs() const {
602 return getNumExplicitDefs() + MCID->implicit_defs().size();
603 }
604
605 /// Returns true if the instruction has implicit definition.
606 bool hasImplicitDef() const {
607 for (const MachineOperand &MO : implicit_operands())
608 if (MO.isDef() && MO.isImplicit())
609 return true;
610 return false;
611 }
612
613 /// Returns the implicit operands number.
614 unsigned getNumImplicitOperands() const {
616 }
617
618 /// Return true if operand \p OpIdx is a subregister index.
619 bool isOperandSubregIdx(unsigned OpIdx) const {
620 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
621 if (isExtractSubreg() && OpIdx == 2)
622 return true;
623 if (isInsertSubreg() && OpIdx == 3)
624 return true;
625 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
626 return true;
627 if (isSubregToReg() && OpIdx == 3)
628 return true;
629 return false;
630 }
631
632 /// Returns the number of non-implicit operands.
633 unsigned getNumExplicitOperands() const;
634
635 /// Returns the number of non-implicit definitions.
636 unsigned getNumExplicitDefs() const;
637
638 /// iterator/begin/end - Iterate over all operands of a machine instruction.
641
643 mop_iterator operands_end() { return Operands + NumOperands; }
644
646 const_mop_iterator operands_end() const { return Operands + NumOperands; }
647
650 }
653 }
655 return make_range(operands_begin(),
657 }
659 return make_range(operands_begin(),
661 }
663 return make_range(explicit_operands().end(), operands_end());
664 }
666 return make_range(explicit_operands().end(), operands_end());
667 }
668 /// Returns a range over all operands that are used to determine the variable
669 /// location for this DBG_VALUE instruction.
671 assert((isDebugValueLike()) && "Must be a debug value instruction.");
672 return isNonListDebugValue()
675 }
676 /// \copydoc debug_operands()
678 assert((isDebugValueLike()) && "Must be a debug value instruction.");
679 return isNonListDebugValue()
682 }
683 /// Returns a range over all explicit operands that are register definitions.
684 /// Implicit definition are not included!
686 return make_range(operands_begin(),
688 }
689 /// \copydoc defs()
691 return make_range(operands_begin(),
693 }
694 /// Returns a range that includes all operands that are register uses.
695 /// This may include unrelated operands which are not register uses.
698 }
699 /// \copydoc uses()
702 }
706 }
710 }
711
716
717 /// Returns an iterator range over all operands that are (explicit or
718 /// implicit) register defs.
720 return make_filter_range(operands(), opIsRegDef);
721 }
722 /// \copydoc all_defs()
724 return make_filter_range(operands(), opIsRegDef);
725 }
726
727 /// Returns an iterator range over all operands that are (explicit or
728 /// implicit) register uses.
730 return make_filter_range(uses(), opIsRegUse);
731 }
732 /// \copydoc all_uses()
734 return make_filter_range(uses(), opIsRegUse);
735 }
736
737 /// Returns the number of the operand iterator \p I points to.
739 return I - operands_begin();
740 }
741
742 /// Access to memory operands of the instruction. If there are none, that does
743 /// not imply anything about whether the function accesses memory. Instead,
744 /// the caller must behave conservatively.
746 if (!Info)
747 return {};
748
749 if (Info.is<EIIK_MMO>())
750 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
751
752 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
753 return EI->getMMOs();
754
755 return {};
756 }
757
758 /// Access to memory operands of the instruction.
759 ///
760 /// If `memoperands_begin() == memoperands_end()`, that does not imply
761 /// anything about whether the function accesses memory. Instead, the caller
762 /// must behave conservatively.
763 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
764
765 /// Access to memory operands of the instruction.
766 ///
767 /// If `memoperands_begin() == memoperands_end()`, that does not imply
768 /// anything about whether the function accesses memory. Instead, the caller
769 /// must behave conservatively.
770 mmo_iterator memoperands_end() const { return memoperands().end(); }
771
772 /// Return true if we don't have any memory operands which described the
773 /// memory access done by this instruction. If this is true, calling code
774 /// must be conservative.
775 bool memoperands_empty() const { return memoperands().empty(); }
776
777 /// Return true if this instruction has exactly one MachineMemOperand.
778 bool hasOneMemOperand() const { return memoperands().size() == 1; }
779
780 /// Return the number of memory operands.
781 unsigned getNumMemOperands() const { return memoperands().size(); }
782
783 /// Helper to extract a pre-instruction symbol if one has been added.
785 if (!Info)
786 return nullptr;
787 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
788 return S;
789 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
790 return EI->getPreInstrSymbol();
791
792 return nullptr;
793 }
794
795 /// Helper to extract a post-instruction symbol if one has been added.
797 if (!Info)
798 return nullptr;
799 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
800 return S;
801 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
802 return EI->getPostInstrSymbol();
803
804 return nullptr;
805 }
806
807 /// Helper to extract a heap alloc marker if one has been added.
809 if (!Info)
810 return nullptr;
811 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
812 return EI->getHeapAllocMarker();
813
814 return nullptr;
815 }
816
817 /// Helper to extract PCSections metadata target sections.
819 if (!Info)
820 return nullptr;
821 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
822 return EI->getPCSections();
823
824 return nullptr;
825 }
826
827 /// Helper to extract a CFI type hash if one has been added.
829 if (!Info)
830 return 0;
831 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
832 return EI->getCFIType();
833
834 return 0;
835 }
836
837 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
838 /// queries but they are bundle aware.
839
841 IgnoreBundle, // Ignore bundles
842 AnyInBundle, // Return true if any instruction in bundle has property
843 AllInBundle // Return true if all instructions in bundle have property
844 };
845
846 /// Return true if the instruction (or in the case of a bundle,
847 /// the instructions inside the bundle) has the specified property.
848 /// The first argument is the property being queried.
849 /// The second argument indicates whether the query should look inside
850 /// instruction bundles.
851 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
852 assert(MCFlag < 64 &&
853 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
854 // Inline the fast path for unbundled or bundle-internal instructions.
856 return getDesc().getFlags() & (1ULL << MCFlag);
857
858 // If this is the first instruction in a bundle, take the slow path.
859 return hasPropertyInBundle(1ULL << MCFlag, Type);
860 }
861
862 /// Return true if this is an instruction that should go through the usual
863 /// legalization steps.
866 }
867
868 /// Return true if this instruction can have a variable number of operands.
869 /// In this case, the variable operands will be after the normal
870 /// operands but before the implicit definitions and uses (if any are
871 /// present).
874 }
875
876 /// Set if this instruction has an optional definition, e.g.
877 /// ARM instructions which can set condition code if 's' bit is set.
880 }
881
882 /// Return true if this is a pseudo instruction that doesn't
883 /// correspond to a real machine instruction.
886 }
887
888 /// Return true if this instruction doesn't produce any output in the form of
889 /// executable instructions.
891 return hasProperty(MCID::Meta, Type);
892 }
893
896 }
897
898 /// Return true if this is an instruction that marks the end of an EH scope,
899 /// i.e., a catchpad or a cleanuppad instruction.
902 }
903
905 return hasProperty(MCID::Call, Type);
906 }
907
908 /// Return true if this is a call instruction that may have an associated
909 /// call site entry in the debug info.
911 /// Return true if copying, moving, or erasing this instruction requires
912 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
913 /// \ref eraseCallSiteInfo).
914 bool shouldUpdateCallSiteInfo() const;
915
916 /// Returns true if the specified instruction stops control flow
917 /// from executing the instruction immediately following it. Examples include
918 /// unconditional branches and return instructions.
921 }
922
923 /// Returns true if this instruction part of the terminator for a basic block.
924 /// Typically this is things like return and branch instructions.
925 ///
926 /// Various passes use this to insert code into the bottom of a basic block,
927 /// but before control flow occurs.
930 }
931
932 /// Returns true if this is a conditional, unconditional, or indirect branch.
933 /// Predicates below can be used to discriminate between
934 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
935 /// get more information.
938 }
939
940 /// Return true if this is an indirect branch, such as a
941 /// branch through a register.
944 }
945
946 /// Return true if this is a branch which may fall
947 /// through to the next instruction or may transfer control flow to some other
948 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
949 /// information about this branch.
952 }
953
954 /// Return true if this is a branch which always
955 /// transfers control flow to some other block. The
956 /// TargetInstrInfo::analyzeBranch method can be used to get more information
957 /// about this branch.
960 }
961
962 /// Return true if this instruction has a predicate operand that
963 /// controls execution. It may be set to 'always', or may be set to other
964 /// values. There are various methods in TargetInstrInfo that can be used to
965 /// control and modify the predicate in this instruction.
967 // If it's a bundle than all bundled instructions must be predicable for this
968 // to return true.
970 }
971
972 /// Return true if this instruction is a comparison.
975 }
976
977 /// Return true if this instruction is a move immediate
978 /// (including conditional moves) instruction.
981 }
982
983 /// Return true if this instruction is a register move.
984 /// (including moving values from subreg to reg)
987 }
988
989 /// Return true if this instruction is a bitcast instruction.
992 }
993
994 /// Return true if this instruction is a select instruction.
997 }
998
999 /// Return true if this instruction cannot be safely duplicated.
1000 /// For example, if the instruction has a unique labels attached
1001 /// to it, duplicating it would cause multiple definition errors.
1004 return true;
1006 }
1007
1008 /// Return true if this instruction is convergent.
1009 /// Convergent instructions can not be made control-dependent on any
1010 /// additional values.
1012 if (isInlineAsm()) {
1013 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1014 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1015 return true;
1016 }
1018 }
1019
1020 /// Returns true if the specified instruction has a delay slot
1021 /// which must be filled by the code generator.
1024 }
1025
1026 /// Return true for instructions that can be folded as
1027 /// memory operands in other instructions. The most common use for this
1028 /// is instructions that are simple loads from memory that don't modify
1029 /// the loaded value in any way, but it can also be used for instructions
1030 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1031 /// on x86, to allow them to be folded when it is beneficial.
1032 /// This should only be set on instructions that return a value in their
1033 /// only virtual register definition.
1036 }
1037
1038 /// Return true if this instruction behaves
1039 /// the same way as the generic REG_SEQUENCE instructions.
1040 /// E.g., on ARM,
1041 /// dX VMOVDRR rY, rZ
1042 /// is equivalent to
1043 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1044 ///
1045 /// Note that for the optimizers to be able to take advantage of
1046 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1047 /// override accordingly.
1050 }
1051
1052 /// Return true if this instruction behaves
1053 /// the same way as the generic EXTRACT_SUBREG instructions.
1054 /// E.g., on ARM,
1055 /// rX, rY VMOVRRD dZ
1056 /// is equivalent to two EXTRACT_SUBREG:
1057 /// rX = EXTRACT_SUBREG dZ, ssub_0
1058 /// rY = EXTRACT_SUBREG dZ, ssub_1
1059 ///
1060 /// Note that for the optimizers to be able to take advantage of
1061 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1062 /// override accordingly.
1065 }
1066
1067 /// Return true if this instruction behaves
1068 /// the same way as the generic INSERT_SUBREG instructions.
1069 /// E.g., on ARM,
1070 /// dX = VSETLNi32 dY, rZ, Imm
1071 /// is equivalent to a INSERT_SUBREG:
1072 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1073 ///
1074 /// Note that for the optimizers to be able to take advantage of
1075 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1076 /// override accordingly.
1079 }
1080
1081 //===--------------------------------------------------------------------===//
1082 // Side Effect Analysis
1083 //===--------------------------------------------------------------------===//
1084
1085 /// Return true if this instruction could possibly read memory.
1086 /// Instructions with this flag set are not necessarily simple load
1087 /// instructions, they may load a value and modify it, for example.
1089 if (isInlineAsm()) {
1090 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1091 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1092 return true;
1093 }
1095 }
1096
1097 /// Return true if this instruction could possibly modify memory.
1098 /// Instructions with this flag set are not necessarily simple store
1099 /// instructions, they may store a modified value based on their operands, or
1100 /// may not actually modify anything, for example.
1102 if (isInlineAsm()) {
1103 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1104 if (ExtraInfo & InlineAsm::Extra_MayStore)
1105 return true;
1106 }
1108 }
1109
1110 /// Return true if this instruction could possibly read or modify memory.
1112 return mayLoad(Type) || mayStore(Type);
1113 }
1114
1115 /// Return true if this instruction could possibly raise a floating-point
1116 /// exception. This is the case if the instruction is a floating-point
1117 /// instruction that can in principle raise an exception, as indicated
1118 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1119 /// the instruction is used in a context where we expect floating-point
1120 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1121 bool mayRaiseFPException() const {
1124 }
1125
1126 //===--------------------------------------------------------------------===//
1127 // Flags that indicate whether an instruction can be modified by a method.
1128 //===--------------------------------------------------------------------===//
1129
1130 /// Return true if this may be a 2- or 3-address
1131 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1132 /// result if Y and Z are exchanged. If this flag is set, then the
1133 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1134 /// instruction.
1135 ///
1136 /// Note that this flag may be set on instructions that are only commutable
1137 /// sometimes. In these cases, the call to commuteInstruction will fail.
1138 /// Also note that some instructions require non-trivial modification to
1139 /// commute them.
1142 }
1143
1144 /// Return true if this is a 2-address instruction
1145 /// which can be changed into a 3-address instruction if needed. Doing this
1146 /// transformation can be profitable in the register allocator, because it
1147 /// means that the instruction can use a 2-address form if possible, but
1148 /// degrade into a less efficient form if the source and dest register cannot
1149 /// be assigned to the same register. For example, this allows the x86
1150 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1151 /// is the same speed as the shift but has bigger code size.
1152 ///
1153 /// If this returns true, then the target must implement the
1154 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1155 /// is allowed to fail if the transformation isn't valid for this specific
1156 /// instruction (e.g. shl reg, 4 on x86).
1157 ///
1160 }
1161
1162 /// Return true if this instruction requires
1163 /// custom insertion support when the DAG scheduler is inserting it into a
1164 /// machine basic block. If this is true for the instruction, it basically
1165 /// means that it is a pseudo instruction used at SelectionDAG time that is
1166 /// expanded out into magic code by the target when MachineInstrs are formed.
1167 ///
1168 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1169 /// is used to insert this into the MachineBasicBlock.
1172 }
1173
1174 /// Return true if this instruction requires *adjustment*
1175 /// after instruction selection by calling a target hook. For example, this
1176 /// can be used to fill in ARM 's' optional operand depending on whether
1177 /// the conditional flag register is used.
1180 }
1181
1182 /// Returns true if this instruction is a candidate for remat.
1183 /// This flag is deprecated, please don't use it anymore. If this
1184 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1185 /// verify the instruction is really rematable.
1187 // It's only possible to re-mat a bundle if all bundled instructions are
1188 // re-materializable.
1190 }
1191
1192 /// Returns true if this instruction has the same cost (or less) than a move
1193 /// instruction. This is useful during certain types of optimizations
1194 /// (e.g., remat during two-address conversion or machine licm)
1195 /// where we would like to remat or hoist the instruction, but not if it costs
1196 /// more than moving the instruction into the appropriate register. Note, we
1197 /// are not marking copies from and to the same register class with this flag.
1199 // Only returns true for a bundle if all bundled instructions are cheap.
1201 }
1202
1203 /// Returns true if this instruction source operands
1204 /// have special register allocation requirements that are not captured by the
1205 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1206 /// even / odd pair, ARM::STM registers have to be in ascending order.
1207 /// Post-register allocation passes should not attempt to change allocations
1208 /// for sources of instructions with this flag.
1211 }
1212
1213 /// Returns true if this instruction def operands
1214 /// have special register allocation requirements that are not captured by the
1215 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1216 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1217 /// Post-register allocation passes should not attempt to change allocations
1218 /// for definitions of instructions with this flag.
1221 }
1222
1224 CheckDefs, // Check all operands for equality
1225 CheckKillDead, // Check all operands including kill / dead markers
1226 IgnoreDefs, // Ignore all definitions
1227 IgnoreVRegDefs // Ignore virtual register definitions
1229
1230 /// Return true if this instruction is identical to \p Other.
1231 /// Two instructions are identical if they have the same opcode and all their
1232 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1233 /// Note that this means liveness related flags (dead, undef, kill) do not
1234 /// affect the notion of identical.
1235 bool isIdenticalTo(const MachineInstr &Other,
1236 MICheckType Check = CheckDefs) const;
1237
1238 /// Returns true if this instruction is a debug instruction that represents an
1239 /// identical debug value to \p Other.
1240 /// This function considers these debug instructions equivalent if they have
1241 /// identical variables, debug locations, and debug operands, and if the
1242 /// DIExpressions combined with the directness flags are equivalent.
1243 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1244
1245 /// Unlink 'this' from the containing basic block, and return it without
1246 /// deleting it.
1247 ///
1248 /// This function can not be used on bundled instructions, use
1249 /// removeFromBundle() to remove individual instructions from a bundle.
1251
1252 /// Unlink this instruction from its basic block and return it without
1253 /// deleting it.
1254 ///
1255 /// If the instruction is part of a bundle, the other instructions in the
1256 /// bundle remain bundled.
1258
1259 /// Unlink 'this' from the containing basic block and delete it.
1260 ///
1261 /// If this instruction is the header of a bundle, the whole bundle is erased.
1262 /// This function can not be used for instructions inside a bundle, use
1263 /// eraseFromBundle() to erase individual bundled instructions.
1264 void eraseFromParent();
1265
1266 /// Unlink 'this' form its basic block and delete it.
1267 ///
1268 /// If the instruction is part of a bundle, the other instructions in the
1269 /// bundle remain bundled.
1270 void eraseFromBundle();
1271
1272 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1273 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1274 bool isAnnotationLabel() const {
1275 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1276 }
1277
1278 /// Returns true if the MachineInstr represents a label.
1279 bool isLabel() const {
1280 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1281 }
1282
1283 bool isCFIInstruction() const {
1284 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1285 }
1286
1287 bool isPseudoProbe() const {
1288 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1289 }
1290
1291 // True if the instruction represents a position in the function.
1292 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1293
1294 bool isNonListDebugValue() const {
1295 return getOpcode() == TargetOpcode::DBG_VALUE;
1296 }
1297 bool isDebugValueList() const {
1298 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1299 }
1300 bool isDebugValue() const {
1302 }
1303 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1304 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1305 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1306 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1307 bool isDebugInstr() const {
1308 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1309 }
1311 return isDebugInstr() || isPseudoProbe();
1312 }
1313
1314 bool isDebugOffsetImm() const {
1316 }
1317
1318 /// A DBG_VALUE is indirect iff the location operand is a register and
1319 /// the offset operand is an immediate.
1321 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1322 }
1323
1324 /// A DBG_VALUE is an entry value iff its debug expression contains the
1325 /// DW_OP_LLVM_entry_value operation.
1326 bool isDebugEntryValue() const;
1327
1328 /// Return true if the instruction is a debug value which describes a part of
1329 /// a variable as unavailable.
1330 bool isUndefDebugValue() const {
1331 if (!isDebugValue())
1332 return false;
1333 // If any $noreg locations are given, this DV is undef.
1334 for (const MachineOperand &Op : debug_operands())
1335 if (Op.isReg() && !Op.getReg().isValid())
1336 return true;
1337 return false;
1338 }
1339
1340 bool isPHI() const {
1341 return getOpcode() == TargetOpcode::PHI ||
1342 getOpcode() == TargetOpcode::G_PHI;
1343 }
1344 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1345 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1346 bool isInlineAsm() const {
1347 return getOpcode() == TargetOpcode::INLINEASM ||
1348 getOpcode() == TargetOpcode::INLINEASM_BR;
1349 }
1350
1351 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1352 /// specific, be attached to a generic MachineInstr.
1353 bool isMSInlineAsm() const {
1355 }
1356
1357 bool isStackAligningInlineAsm() const;
1359
1360 bool isInsertSubreg() const {
1361 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1362 }
1363
1364 bool isSubregToReg() const {
1365 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1366 }
1367
1368 bool isRegSequence() const {
1369 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1370 }
1371
1372 bool isBundle() const {
1373 return getOpcode() == TargetOpcode::BUNDLE;
1374 }
1375
1376 bool isCopy() const {
1377 return getOpcode() == TargetOpcode::COPY;
1378 }
1379
1380 bool isFullCopy() const {
1381 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1382 }
1383
1384 bool isExtractSubreg() const {
1385 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1386 }
1387
1388 /// Return true if the instruction behaves like a copy.
1389 /// This does not include native copy instructions.
1390 bool isCopyLike() const {
1391 return isCopy() || isSubregToReg();
1392 }
1393
1394 /// Return true is the instruction is an identity copy.
1395 bool isIdentityCopy() const {
1396 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1398 }
1399
1400 /// Return true if this is a transient instruction that is either very likely
1401 /// to be eliminated during register allocation (such as copy-like
1402 /// instructions), or if this instruction doesn't have an execution-time cost.
1403 bool isTransient() const {
1404 switch (getOpcode()) {
1405 default:
1406 return isMetaInstruction();
1407 // Copy-like instructions are usually eliminated during register allocation.
1408 case TargetOpcode::PHI:
1409 case TargetOpcode::G_PHI:
1410 case TargetOpcode::COPY:
1411 case TargetOpcode::INSERT_SUBREG:
1412 case TargetOpcode::SUBREG_TO_REG:
1413 case TargetOpcode::REG_SEQUENCE:
1414 return true;
1415 }
1416 }
1417
1418 /// Return the number of instructions inside the MI bundle, excluding the
1419 /// bundle header.
1420 ///
1421 /// This is the number of instructions that MachineBasicBlock::iterator
1422 /// skips, 0 for unbundled instructions.
1423 unsigned getBundleSize() const;
1424
1425 /// Return true if the MachineInstr reads the specified register.
1426 /// If TargetRegisterInfo is passed, then it also checks if there
1427 /// is a read of a super-register.
1428 /// This does not count partial redefines of virtual registers as reads:
1429 /// %reg1024:6 = OP.
1431 const TargetRegisterInfo *TRI = nullptr) const {
1432 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1433 }
1434
1435 /// Return true if the MachineInstr reads the specified virtual register.
1436 /// Take into account that a partial define is a
1437 /// read-modify-write operation.
1439 return readsWritesVirtualRegister(Reg).first;
1440 }
1441
1442 /// Return a pair of bools (reads, writes) indicating if this instruction
1443 /// reads or writes Reg. This also considers partial defines.
1444 /// If Ops is not null, all operand indices for Reg are added.
1445 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1446 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1447
1448 /// Return true if the MachineInstr kills the specified register.
1449 /// If TargetRegisterInfo is passed, then it also checks if there is
1450 /// a kill of a super-register.
1452 const TargetRegisterInfo *TRI = nullptr) const {
1453 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1454 }
1455
1456 /// Return true if the MachineInstr fully defines the specified register.
1457 /// If TargetRegisterInfo is passed, then it also checks
1458 /// if there is a def of a super-register.
1459 /// NOTE: It's ignoring subreg indices on virtual registers.
1461 const TargetRegisterInfo *TRI = nullptr) const {
1462 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1463 }
1464
1465 /// Return true if the MachineInstr modifies (fully define or partially
1466 /// define) the specified register.
1467 /// NOTE: It's ignoring subreg indices on virtual registers.
1469 const TargetRegisterInfo *TRI = nullptr) const {
1470 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1471 }
1472
1473 /// Returns true if the register is dead in this machine instruction.
1474 /// If TargetRegisterInfo is passed, then it also checks
1475 /// if there is a dead def of a super-register.
1477 const TargetRegisterInfo *TRI = nullptr) const {
1478 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1479 }
1480
1481 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1482 /// the given register (not considering sub/super-registers).
1484
1485 /// Returns the operand index that is a use of the specific register or -1
1486 /// if it is not found. It further tightens the search criteria to a use
1487 /// that kills the register if isKill is true.
1488 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1489 const TargetRegisterInfo *TRI = nullptr) const;
1490
1491 /// Wrapper for findRegisterUseOperandIdx, it returns
1492 /// a pointer to the MachineOperand rather than an index.
1494 const TargetRegisterInfo *TRI = nullptr) {
1496 return (Idx == -1) ? nullptr : &getOperand(Idx);
1497 }
1498
1500 Register Reg, bool isKill = false,
1501 const TargetRegisterInfo *TRI = nullptr) const {
1502 return const_cast<MachineInstr *>(this)->
1504 }
1505
1506 /// Returns the operand index that is a def of the specified register or
1507 /// -1 if it is not found. If isDead is true, defs that are not dead are
1508 /// skipped. If Overlap is true, then it also looks for defs that merely
1509 /// overlap the specified register. If TargetRegisterInfo is non-null,
1510 /// then it also checks if there is a def of a super-register.
1511 /// This may also return a register mask operand when Overlap is true.
1513 bool isDead = false, bool Overlap = false,
1514 const TargetRegisterInfo *TRI = nullptr) const;
1515
1516 /// Wrapper for findRegisterDefOperandIdx, it returns
1517 /// a pointer to the MachineOperand rather than an index.
1520 bool Overlap = false,
1521 const TargetRegisterInfo *TRI = nullptr) {
1522 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1523 return (Idx == -1) ? nullptr : &getOperand(Idx);
1524 }
1525
1526 const MachineOperand *
1528 bool Overlap = false,
1529 const TargetRegisterInfo *TRI = nullptr) const {
1530 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1531 Reg, isDead, Overlap, TRI);
1532 }
1533
1534 /// Find the index of the first operand in the
1535 /// operand list that is used to represent the predicate. It returns -1 if
1536 /// none is found.
1537 int findFirstPredOperandIdx() const;
1538
1539 /// Find the index of the flag word operand that
1540 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1541 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1542 ///
1543 /// If GroupNo is not NULL, it will receive the number of the operand group
1544 /// containing OpIdx.
1545 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1546
1547 /// Compute the static register class constraint for operand OpIdx.
1548 /// For normal instructions, this is derived from the MCInstrDesc.
1549 /// For inline assembly it is derived from the flag words.
1550 ///
1551 /// Returns NULL if the static register class constraint cannot be
1552 /// determined.
1553 const TargetRegisterClass*
1554 getRegClassConstraint(unsigned OpIdx,
1555 const TargetInstrInfo *TII,
1556 const TargetRegisterInfo *TRI) const;
1557
1558 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1559 /// the given \p CurRC.
1560 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1561 /// instructions inside the bundle will be taken into account. In other words,
1562 /// this method accumulates all the constraints of the operand of this MI and
1563 /// the related bundle if MI is a bundle or inside a bundle.
1564 ///
1565 /// Returns the register class that satisfies both \p CurRC and the
1566 /// constraints set by MI. Returns NULL if such a register class does not
1567 /// exist.
1568 ///
1569 /// \pre CurRC must not be NULL.
1571 Register Reg, const TargetRegisterClass *CurRC,
1573 bool ExploreBundle = false) const;
1574
1575 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1576 /// to the given \p CurRC.
1577 ///
1578 /// Returns the register class that satisfies both \p CurRC and the
1579 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1580 /// does not exist.
1581 ///
1582 /// \pre CurRC must not be NULL.
1583 /// \pre The operand at \p OpIdx must be a register.
1584 const TargetRegisterClass *
1585 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1586 const TargetInstrInfo *TII,
1587 const TargetRegisterInfo *TRI) const;
1588
1589 /// Add a tie between the register operands at DefIdx and UseIdx.
1590 /// The tie will cause the register allocator to ensure that the two
1591 /// operands are assigned the same physical register.
1592 ///
1593 /// Tied operands are managed automatically for explicit operands in the
1594 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1595 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1596
1597 /// Given the index of a tied register operand, find the
1598 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1599 /// index of the tied operand which must exist.
1600 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1601
1602 /// Given the index of a register def operand,
1603 /// check if the register def is tied to a source operand, due to either
1604 /// two-address elimination or inline assembly constraints. Returns the
1605 /// first tied use operand index by reference if UseOpIdx is not null.
1606 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1607 unsigned *UseOpIdx = nullptr) const {
1608 const MachineOperand &MO = getOperand(DefOpIdx);
1609 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1610 return false;
1611 if (UseOpIdx)
1612 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1613 return true;
1614 }
1615
1616 /// Return true if the use operand of the specified index is tied to a def
1617 /// operand. It also returns the def operand index by reference if DefOpIdx
1618 /// is not null.
1620 unsigned *DefOpIdx = nullptr) const {
1621 const MachineOperand &MO = getOperand(UseOpIdx);
1622 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1623 return false;
1624 if (DefOpIdx)
1625 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1626 return true;
1627 }
1628
1629 /// Clears kill flags on all operands.
1630 void clearKillInfo();
1631
1632 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1633 /// properly composing subreg indices where necessary.
1634 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1636
1637 /// We have determined MI kills a register. Look for the
1638 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1639 /// add a implicit operand if it's not found. Returns true if the operand
1640 /// exists / is added.
1641 bool addRegisterKilled(Register IncomingReg,
1643 bool AddIfNotFound = false);
1644
1645 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1646 /// all aliasing registers.
1648
1649 /// We have determined MI defined a register without a use.
1650 /// Look for the operand that defines it and mark it as IsDead. If
1651 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1652 /// true if the operand exists / is added.
1654 bool AddIfNotFound = false);
1655
1656 /// Clear all dead flags on operands defining register @p Reg.
1658
1659 /// Mark all subregister defs of register @p Reg with the undef flag.
1660 /// This function is used when we determined to have a subregister def in an
1661 /// otherwise undefined super register.
1662 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1663
1664 /// We have determined MI defines a register. Make sure there is an operand
1665 /// defining Reg.
1667 const TargetRegisterInfo *RegInfo = nullptr);
1668
1669 /// Mark every physreg used by this instruction as
1670 /// dead except those in the UsedRegs list.
1671 ///
1672 /// On instructions with register mask operands, also add implicit-def
1673 /// operands for all registers in UsedRegs.
1675 const TargetRegisterInfo &TRI);
1676
1677 /// Return true if it is safe to move this instruction. If
1678 /// SawStore is set to true, it means that there is a store (or call) between
1679 /// the instruction's location and its intended destination.
1680 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1681
1682 /// Returns true if this instruction's memory access aliases the memory
1683 /// access of Other.
1684 //
1685 /// Assumes any physical registers used to compute addresses
1686 /// have the same value for both instructions. Returns false if neither
1687 /// instruction writes to memory.
1688 ///
1689 /// @param AA Optional alias analysis, used to compare memory operands.
1690 /// @param Other MachineInstr to check aliasing against.
1691 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1692 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1693
1694 /// Return true if this instruction may have an ordered
1695 /// or volatile memory reference, or if the information describing the memory
1696 /// reference is not available. Return false if it is known to have no
1697 /// ordered or volatile memory references.
1698 bool hasOrderedMemoryRef() const;
1699
1700 /// Return true if this load instruction never traps and points to a memory
1701 /// location whose value doesn't change during the execution of this function.
1702 ///
1703 /// Examples include loading a value from the constant pool or from the
1704 /// argument area of a function (if it does not change). If the instruction
1705 /// does multiple loads, this returns true only if all of the loads are
1706 /// dereferenceable and invariant.
1707 bool isDereferenceableInvariantLoad() const;
1708
1709 /// If the specified instruction is a PHI that always merges together the
1710 /// same virtual register, return the register, otherwise return 0.
1711 unsigned isConstantValuePHI() const;
1712
1713 /// Return true if this instruction has side effects that are not modeled
1714 /// by mayLoad / mayStore, etc.
1715 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1716 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1717 /// INLINEASM instruction, in which case the side effect property is encoded
1718 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1719 ///
1720 bool hasUnmodeledSideEffects() const;
1721
1722 /// Returns true if it is illegal to fold a load across this instruction.
1723 bool isLoadFoldBarrier() const;
1724
1725 /// Return true if all the defs of this instruction are dead.
1726 bool allDefsAreDead() const;
1727
1728 /// Return a valid size if the instruction is a spill instruction.
1729 std::optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1730
1731 /// Return a valid size if the instruction is a folded spill instruction.
1732 std::optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1733
1734 /// Return a valid size if the instruction is a restore instruction.
1735 std::optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1736
1737 /// Return a valid size if the instruction is a folded restore instruction.
1738 std::optional<unsigned>
1740
1741 /// Copy implicit register operands from specified
1742 /// instruction to this instruction.
1744
1745 /// Debugging support
1746 /// @{
1747 /// Determine the generic type to be printed (if needed) on uses and defs.
1748 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1749 const MachineRegisterInfo &MRI) const;
1750
1751 /// Return true when an instruction has tied register that can't be determined
1752 /// by the instruction's descriptor. This is useful for MIR printing, to
1753 /// determine whether we need to print the ties or not.
1754 bool hasComplexRegisterTies() const;
1755
1756 /// Print this MI to \p OS.
1757 /// Don't print information that can be inferred from other instructions if
1758 /// \p IsStandalone is false. It is usually true when only a fragment of the
1759 /// function is printed.
1760 /// Only print the defs and the opcode if \p SkipOpers is true.
1761 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1762 /// Otherwise, also print the debug loc, with a terminating newline.
1763 /// \p TII is used to print the opcode name. If it's not present, but the
1764 /// MI is in a function, the opcode will be printed using the function's TII.
1765 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1766 bool SkipDebugLoc = false, bool AddNewLine = true,
1767 const TargetInstrInfo *TII = nullptr) const;
1768 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1769 bool SkipOpers = false, bool SkipDebugLoc = false,
1770 bool AddNewLine = true,
1771 const TargetInstrInfo *TII = nullptr) const;
1772 void dump() const;
1773 /// Print on dbgs() the current instruction and the instructions defining its
1774 /// operands and so on until we reach \p MaxDepth.
1775 void dumpr(const MachineRegisterInfo &MRI,
1776 unsigned MaxDepth = UINT_MAX) const;
1777 /// @}
1778
1779 //===--------------------------------------------------------------------===//
1780 // Accessors used to build up machine instructions.
1781
1782 /// Add the specified operand to the instruction. If it is an implicit
1783 /// operand, it is added to the end of the operand list. If it is an
1784 /// explicit operand it is added at the end of the explicit operand list
1785 /// (before the first implicit operand).
1786 ///
1787 /// MF must be the machine function that was used to allocate this
1788 /// instruction.
1789 ///
1790 /// MachineInstrBuilder provides a more convenient interface for creating
1791 /// instructions and adding operands.
1792 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1793
1794 /// Add an operand without providing an MF reference. This only works for
1795 /// instructions that are inserted in a basic block.
1796 ///
1797 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1798 /// preferred.
1799 void addOperand(const MachineOperand &Op);
1800
1801 /// Replace the instruction descriptor (thus opcode) of
1802 /// the current instruction with a new one.
1803 void setDesc(const MCInstrDesc &TID) { MCID = &TID; }
1804
1805 /// Replace current source information with new such.
1806 /// Avoid using this, the constructor argument is preferable.
1808 DbgLoc = std::move(DL);
1809 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1810 }
1811
1812 /// Erase an operand from an instruction, leaving it with one
1813 /// fewer operand than it started with.
1814 void removeOperand(unsigned OpNo);
1815
1816 /// Clear this MachineInstr's memory reference descriptor list. This resets
1817 /// the memrefs to their most conservative state. This should be used only
1818 /// as a last resort since it greatly pessimizes our knowledge of the memory
1819 /// access performed by the instruction.
1820 void dropMemRefs(MachineFunction &MF);
1821
1822 /// Assign this MachineInstr's memory reference descriptor list.
1823 ///
1824 /// Unlike other methods, this *will* allocate them into a new array
1825 /// associated with the provided `MachineFunction`.
1827
1828 /// Add a MachineMemOperand to the machine instruction.
1829 /// This function should be used only occasionally. The setMemRefs function
1830 /// is the primary method for setting up a MachineInstr's MemRefs list.
1832
1833 /// Clone another MachineInstr's memory reference descriptor list and replace
1834 /// ours with it.
1835 ///
1836 /// Note that `*this` may be the incoming MI!
1837 ///
1838 /// Prefer this API whenever possible as it can avoid allocations in common
1839 /// cases.
1840 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1841
1842 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1843 /// list and replace ours with it.
1844 ///
1845 /// Note that `*this` may be one of the incoming MIs!
1846 ///
1847 /// Prefer this API whenever possible as it can avoid allocations in common
1848 /// cases.
1851
1852 /// Set a symbol that will be emitted just prior to the instruction itself.
1853 ///
1854 /// Setting this to a null pointer will remove any such symbol.
1855 ///
1856 /// FIXME: This is not fully implemented yet.
1857 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1858
1859 /// Set a symbol that will be emitted just after the instruction itself.
1860 ///
1861 /// Setting this to a null pointer will remove any such symbol.
1862 ///
1863 /// FIXME: This is not fully implemented yet.
1864 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1865
1866 /// Clone another MachineInstr's pre- and post- instruction symbols and
1867 /// replace ours with it.
1869
1870 /// Set a marker on instructions that denotes where we should create and emit
1871 /// heap alloc site labels. This waits until after instruction selection and
1872 /// optimizations to create the label, so it should still work if the
1873 /// instruction is removed or duplicated.
1875
1876 // Set metadata on instructions that say which sections to emit instruction
1877 // addresses into.
1878 void setPCSections(MachineFunction &MF, MDNode *MD);
1879
1880 /// Set the CFI type for the instruction.
1882
1883 /// Return the MIFlags which represent both MachineInstrs. This
1884 /// should be used when merging two MachineInstrs into one. This routine does
1885 /// not modify the MIFlags of this MachineInstr.
1887
1889
1890 /// Copy all flags to MachineInst MIFlags
1891 void copyIRFlags(const Instruction &I);
1892
1893 /// Break any tie involving OpIdx.
1894 void untieRegOperand(unsigned OpIdx) {
1895 MachineOperand &MO = getOperand(OpIdx);
1896 if (MO.isReg() && MO.isTied()) {
1897 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1898 MO.TiedTo = 0;
1899 }
1900 }
1901
1902 /// Add all implicit def and use operands to this instruction.
1904
1905 /// Scan instructions immediately following MI and collect any matching
1906 /// DBG_VALUEs.
1908
1909 /// Find all DBG_VALUEs that point to the register def in this instruction
1910 /// and point them to \p Reg instead.
1912
1913 /// Returns the Intrinsic::ID for this instruction.
1914 /// \pre Must have an intrinsic ID operand.
1915 unsigned getIntrinsicID() const {
1917 }
1918
1919 /// Sets all register debug operands in this debug value instruction to be
1920 /// undef.
1922 assert(isDebugValue() && "Must be a debug value instruction.");
1923 for (MachineOperand &MO : debug_operands()) {
1924 if (MO.isReg()) {
1925 MO.setReg(0);
1926 MO.setSubReg(0);
1927 }
1928 }
1929 }
1930
1931 std::tuple<Register, Register> getFirst2Regs() const {
1932 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg());
1933 }
1934
1935 std::tuple<Register, Register, Register> getFirst3Regs() const {
1936 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1937 getOperand(2).getReg());
1938 }
1939
1940 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1941 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1942 getOperand(2).getReg(), getOperand(3).getReg());
1943 }
1944
1945 std::tuple<Register, Register, Register, Register, Register>
1947 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1949 getOperand(4).getReg());
1950 }
1951
1952 std::tuple<LLT, LLT> getFirst2LLTs() const;
1953 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
1954 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
1955 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
1956
1957 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
1958 std::tuple<Register, LLT, Register, LLT, Register, LLT>
1959 getFirst3RegLLTs() const;
1960 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
1961 getFirst4RegLLTs() const;
1962 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
1963 Register, LLT>
1964 getFirst5RegLLTs() const;
1965
1966private:
1967 /// If this instruction is embedded into a MachineFunction, return the
1968 /// MachineRegisterInfo object for the current function, otherwise
1969 /// return null.
1970 MachineRegisterInfo *getRegInfo();
1971 const MachineRegisterInfo *getRegInfo() const;
1972
1973 /// Unlink all of the register operands in this instruction from their
1974 /// respective use lists. This requires that the operands already be on their
1975 /// use lists.
1976 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
1977
1978 /// Add all of the register operands in this instruction from their
1979 /// respective use lists. This requires that the operands not be on their
1980 /// use lists yet.
1981 void addRegOperandsToUseLists(MachineRegisterInfo&);
1982
1983 /// Slow path for hasProperty when we're dealing with a bundle.
1984 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1985
1986 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1987 /// this MI and the given operand index \p OpIdx.
1988 /// If the related operand does not constrained Reg, this returns CurRC.
1989 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1990 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1991 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1992
1993 /// Stores extra instruction information inline or allocates as ExtraInfo
1994 /// based on the number of pointers.
1995 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1996 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1997 MDNode *HeapAllocMarker, MDNode *PCSections,
1998 uint32_t CFIType);
1999};
2000
2001/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2002/// instruction rather than by pointer value.
2003/// The hashing and equality testing functions ignore definitions so this is
2004/// useful for CSE, etc.
2006 static inline MachineInstr *getEmptyKey() {
2007 return nullptr;
2008 }
2009
2011 return reinterpret_cast<MachineInstr*>(-1);
2012 }
2013
2014 static unsigned getHashValue(const MachineInstr* const &MI);
2015
2016 static bool isEqual(const MachineInstr* const &LHS,
2017 const MachineInstr* const &RHS) {
2018 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2019 LHS == getEmptyKey() || LHS == getTombstoneKey())
2020 return LHS == RHS;
2021 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
2022 }
2023};
2024
2025//===----------------------------------------------------------------------===//
2026// Debugging Support
2027
2029 MI.print(OS);
2030 return OS;
2031}
2032
2033} // end namespace llvm
2034
2035#endif // LLVM_CODEGEN_MACHINEINSTR_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define Check(C,...)
Definition: Lint.cpp:168
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:114
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define P(N)
unsigned UseOpIdx
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file defines the SmallSet class.
@ Flags
Definition: TextStubV5.cpp:93
This header defines support for implementing classes that have some trailing object (or arrays of obj...
Value * RHS
Value * LHS
The size of an allocated array is represented by a Capacity instance.
Definition: ArrayRecycler.h:71
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:152
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
iterator begin() const
Definition: ArrayRef.h:151
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
DWARF expression.
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:251
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:580
unsigned short Opcode
Definition: MCInstrDesc.h:205
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:950
Representation of each machine instruction.
Definition: MachineInstr.h:68
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
mop_iterator operands_begin()
Definition: MachineInstr.h:642
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific,...
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:523
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:614
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:894
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:573
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:562
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:703
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:76
bool isPosition() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:928
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:700
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopy() const
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:341
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:670
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:320
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:509
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:828
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:851
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:373
MachineFunction * getMF()
Definition: MachineInstr.h:332
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:840
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:966
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:919
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:321
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:995
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:904
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:364
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:354
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:696
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:707
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:729
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:529
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:526
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:503
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:658
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:640
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:344
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:775
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:770
bool isDebugRef() const
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:461
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:654
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:499
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:690
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:738
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
SmallSet< Register, 4 > getUsedDebugRegs() const
Definition: MachineInstr.h:551
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:973
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:606
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:936
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:431
bool isDebugPHI() const
std::optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:537
std::tuple< LLT, LLT > getFirst2LLTs() const
const_mop_iterator operands_end() const
Definition: MachineInstr.h:646
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:349
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
Definition: MachineInstr.h:643
bool isFullCopy() const
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:818
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:520
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:733
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:950
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:677
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:781
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:380
bool isGCLabel() const
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:338
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:619
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:645
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:958
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:778
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:648
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:985
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:723
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:586
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:685
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:763
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:419
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
std::optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:651
std::optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:745
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:639
std::optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:369
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:452
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:979
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:864
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:900
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:884
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:665
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:784
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:990
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:878
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:595
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:457
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:542
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:662
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:435
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:808
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:591
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:533
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:359
bool isEHLabel() const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:796
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:719
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:546
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:601
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
bool isKill() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:890
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:580
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:942
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:872
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:425
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
std::tuple< Register, Register > getFirst2Regs() const
~MachineInstr()=delete
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
See the file comment for details on the usage of the TrailingObjects type.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:589
An ilist node that can access its parent list.
Definition: ilist_node.h:257
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:181
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:175
@ MayRaiseFPException
Definition: MCInstrDesc.h:170
@ Rematerializable
Definition: MCInstrDesc.h:178
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:180
@ UsesCustomInserter
Definition: MCInstrDesc.h:176
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
Definition: STLExtras.h:93
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
Definition: STLExtras.h:101
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1826
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:664
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:51
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
Template traits for intrusive list.
Definition: ilist.h:90