LLVM  16.0.0git
MachineInstr.h
Go to the documentation of this file.
1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/ilist.h"
22 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSymbol.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <utility>
37 
38 namespace llvm {
39 
40 class DILabel;
41 class Instruction;
42 class MDNode;
43 class AAResults;
44 template <typename T> class ArrayRef;
45 class DIExpression;
46 class DILocalVariable;
47 class MachineBasicBlock;
48 class MachineFunction;
49 class MachineRegisterInfo;
50 class ModuleSlotTracker;
51 class raw_ostream;
52 template <typename T> class SmallVectorImpl;
53 class SmallBitVector;
54 class StringRef;
55 class TargetInstrInfo;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 
59 //===----------------------------------------------------------------------===//
60 /// Representation of each machine instruction.
61 ///
62 /// This class isn't a POD type, but it must have a trivial destructor. When a
63 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
64 /// without having their destructor called.
65 ///
67  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
68  ilist_sentinel_tracking<true>> {
69 public:
71 
72  /// Flags to specify different kinds of comments to output in
73  /// assembly code. These flags carry semantic information not
74  /// otherwise easily derivable from the IR text.
75  ///
76  enum CommentFlag {
77  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
79  TAsmComments = 0x4 // Target Asm comments should start from this value.
80  };
81 
82  enum MIFlag {
83  NoFlags = 0,
84  FrameSetup = 1 << 0, // Instruction is used as a part of
85  // function frame setup code.
86  FrameDestroy = 1 << 1, // Instruction is used as a part of
87  // function frame destruction code.
88  BundledPred = 1 << 2, // Instruction has bundled predecessors.
89  BundledSucc = 1 << 3, // Instruction has bundled successors.
90  FmNoNans = 1 << 4, // Instruction does not support Fast
91  // math nan values.
92  FmNoInfs = 1 << 5, // Instruction does not support Fast
93  // math infinity values.
94  FmNsz = 1 << 6, // Instruction is not required to retain
95  // signed zero values.
96  FmArcp = 1 << 7, // Instruction supports Fast math
97  // reciprocal approximations.
98  FmContract = 1 << 8, // Instruction supports Fast math
99  // contraction operations like fma.
100  FmAfn = 1 << 9, // Instruction may map to Fast math
101  // intrinsic approximation.
102  FmReassoc = 1 << 10, // Instruction supports Fast math
103  // reassociation of operand order.
104  NoUWrap = 1 << 11, // Instruction supports binary operator
105  // no unsigned wrap.
106  NoSWrap = 1 << 12, // Instruction supports binary operator
107  // no signed wrap.
108  IsExact = 1 << 13, // Instruction supports division is
109  // known to be exact.
110  NoFPExcept = 1 << 14, // Instruction does not raise
111  // floatint-point exceptions.
112  NoMerge = 1 << 15, // Passes that drop source location info
113  // (e.g. branch folding) should skip
114  // this instruction.
115  };
116 
117 private:
118  const MCInstrDesc *MCID; // Instruction descriptor.
119  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
120 
121  // Operands are allocated by an ArrayRecycler.
122  MachineOperand *Operands = nullptr; // Pointer to the first operand.
123  unsigned NumOperands = 0; // Number of operands on instruction.
124 
125  uint16_t Flags = 0; // Various bits of additional
126  // information about machine
127  // instruction.
128 
129  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
130  // the AsmPrinter to emit helpful
131  // comments. This is *not* semantic
132  // information. Do not use this for
133  // anything other than to convey comment
134  // information to AsmPrinter.
135 
136  // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
137  // to properly pack.
138  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
139  OperandCapacity CapOperands; // Capacity of the Operands array.
140 
141  /// Internal implementation detail class that provides out-of-line storage for
142  /// extra info used by the machine instruction when this info cannot be stored
143  /// in-line within the instruction itself.
144  ///
145  /// This has to be defined eagerly due to the implementation constraints of
146  /// `PointerSumType` where it is used.
147  class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
148  MCSymbol *, MDNode *, uint32_t> {
149  public:
150  static ExtraInfo *create(BumpPtrAllocator &Allocator,
152  MCSymbol *PreInstrSymbol = nullptr,
153  MCSymbol *PostInstrSymbol = nullptr,
154  MDNode *HeapAllocMarker = nullptr,
155  MDNode *PCSections = nullptr,
156  uint32_t CFIType = 0) {
157  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
158  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
159  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
160  bool HasCFIType = CFIType != 0;
161  bool HasPCSections = PCSections != nullptr;
162  auto *Result = new (Allocator.Allocate(
163  totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
164  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
165  HasHeapAllocMarker + HasPCSections, HasCFIType),
166  alignof(ExtraInfo)))
167  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
168  HasHeapAllocMarker, HasPCSections, HasCFIType);
169 
170  // Copy the actual data into the trailing objects.
171  std::copy(MMOs.begin(), MMOs.end(),
172  Result->getTrailingObjects<MachineMemOperand *>());
173 
174  if (HasPreInstrSymbol)
175  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
176  if (HasPostInstrSymbol)
177  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
178  PostInstrSymbol;
179  if (HasHeapAllocMarker)
180  Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
181  if (HasPCSections)
182  Result->getTrailingObjects<MDNode *>()[HasHeapAllocMarker] =
183  PCSections;
184  if (HasCFIType)
185  Result->getTrailingObjects<uint32_t>()[0] = CFIType;
186 
187  return Result;
188  }
189 
190  ArrayRef<MachineMemOperand *> getMMOs() const {
191  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
192  }
193 
194  MCSymbol *getPreInstrSymbol() const {
195  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
196  }
197 
198  MCSymbol *getPostInstrSymbol() const {
199  return HasPostInstrSymbol
200  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
201  : nullptr;
202  }
203 
204  MDNode *getHeapAllocMarker() const {
205  return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
206  }
207 
208  MDNode *getPCSections() const {
209  return HasPCSections
210  ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
211  : nullptr;
212  }
213 
214  uint32_t getCFIType() const {
215  return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
216  }
217 
218  private:
219  friend TrailingObjects;
220 
221  // Description of the extra info, used to interpret the actual optional
222  // data appended.
223  //
224  // Note that this is not terribly space optimized. This leaves a great deal
225  // of flexibility to fit more in here later.
226  const int NumMMOs;
227  const bool HasPreInstrSymbol;
228  const bool HasPostInstrSymbol;
229  const bool HasHeapAllocMarker;
230  const bool HasPCSections;
231  const bool HasCFIType;
232 
233  // Implement the `TrailingObjects` internal API.
234  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
235  return NumMMOs;
236  }
237  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
238  return HasPreInstrSymbol + HasPostInstrSymbol;
239  }
240  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
241  return HasHeapAllocMarker + HasPCSections;
242  }
243  size_t numTrailingObjects(OverloadToken<uint32_t>) const {
244  return HasCFIType;
245  }
246 
247  // Just a boring constructor to allow us to initialize the sizes. Always use
248  // the `create` routine above.
249  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
250  bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType)
251  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
252  HasPostInstrSymbol(HasPostInstrSymbol),
253  HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
254  HasCFIType(HasCFIType) {}
255  };
256 
257  /// Enumeration of the kinds of inline extra info available. It is important
258  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
259  /// it accessible as an `ArrayRef`.
260  enum ExtraInfoInlineKinds {
261  EIIK_MMO = 0,
262  EIIK_PreInstrSymbol,
263  EIIK_PostInstrSymbol,
264  EIIK_OutOfLine
265  };
266 
267  // We store extra information about the instruction here. The common case is
268  // expected to be nothing or a single pointer (typically a MMO or a symbol).
269  // We work to optimize this common case by storing it inline here rather than
270  // requiring a separate allocation, but we fall back to an allocation when
271  // multiple pointers are needed.
272  PointerSumType<ExtraInfoInlineKinds,
273  PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
274  PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
275  PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
276  PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
277  Info;
278 
279  DebugLoc DbgLoc; // Source line information.
280 
281  /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
282  /// defined by this instruction.
283  unsigned DebugInstrNum;
284 
285  // Intrusive list support
286  friend struct ilist_traits<MachineInstr>;
288  void setParent(MachineBasicBlock *P) { Parent = P; }
289 
290  /// This constructor creates a copy of the given
291  /// MachineInstr in the given MachineFunction.
293 
294  /// This constructor create a MachineInstr and add the implicit operands.
295  /// It reserves space for number of operands specified by
296  /// MCInstrDesc. An explicit DebugLoc is supplied.
298  bool NoImp = false);
299 
300  // MachineInstrs are pool-allocated and owned by MachineFunction.
301  friend class MachineFunction;
302 
303  void
304  dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
305  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
306 
307 public:
308  MachineInstr(const MachineInstr &) = delete;
309  MachineInstr &operator=(const MachineInstr &) = delete;
310  // Use MachineFunction::DeleteMachineInstr() instead.
311  ~MachineInstr() = delete;
312 
313  const MachineBasicBlock* getParent() const { return Parent; }
314  MachineBasicBlock* getParent() { return Parent; }
315 
316  /// Move the instruction before \p MovePos.
317  void moveBefore(MachineInstr *MovePos);
318 
319  /// Return the function that contains the basic block that this instruction
320  /// belongs to.
321  ///
322  /// Note: this is undefined behaviour if the instruction does not have a
323  /// parent.
324  const MachineFunction *getMF() const;
326  return const_cast<MachineFunction *>(
327  static_cast<const MachineInstr *>(this)->getMF());
328  }
329 
330  /// Return the asm printer flags bitvector.
331  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
332 
333  /// Clear the AsmPrinter bitvector.
334  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
335 
336  /// Return whether an AsmPrinter flag is set.
338  return AsmPrinterFlags & Flag;
339  }
340 
341  /// Set a flag for the AsmPrinter.
342  void setAsmPrinterFlag(uint8_t Flag) {
343  AsmPrinterFlags |= Flag;
344  }
345 
346  /// Clear specific AsmPrinter flags.
348  AsmPrinterFlags &= ~Flag;
349  }
350 
351  /// Return the MI flags bitvector.
352  uint16_t getFlags() const {
353  return Flags;
354  }
355 
356  /// Return whether an MI flag is set.
357  bool getFlag(MIFlag Flag) const {
358  return Flags & Flag;
359  }
360 
361  /// Set a MI flag.
363  Flags |= (uint16_t)Flag;
364  }
365 
366  void setFlags(unsigned flags) {
367  // Filter out the automatically maintained flags.
368  unsigned Mask = BundledPred | BundledSucc;
369  Flags = (Flags & Mask) | (flags & ~Mask);
370  }
371 
372  /// clearFlag - Clear a MI flag.
374  Flags &= ~((uint16_t)Flag);
375  }
376 
377  /// Return true if MI is in a bundle (but not the first MI in a bundle).
378  ///
379  /// A bundle looks like this before it's finalized:
380  /// ----------------
381  /// | MI |
382  /// ----------------
383  /// |
384  /// ----------------
385  /// | MI * |
386  /// ----------------
387  /// |
388  /// ----------------
389  /// | MI * |
390  /// ----------------
391  /// In this case, the first MI starts a bundle but is not inside a bundle, the
392  /// next 2 MIs are considered "inside" the bundle.
393  ///
394  /// After a bundle is finalized, it looks like this:
395  /// ----------------
396  /// | Bundle |
397  /// ----------------
398  /// |
399  /// ----------------
400  /// | MI * |
401  /// ----------------
402  /// |
403  /// ----------------
404  /// | MI * |
405  /// ----------------
406  /// |
407  /// ----------------
408  /// | MI * |
409  /// ----------------
410  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
411  /// a bundle, but the next three MIs are.
412  bool isInsideBundle() const {
413  return getFlag(BundledPred);
414  }
415 
416  /// Return true if this instruction part of a bundle. This is true
417  /// if either itself or its following instruction is marked "InsideBundle".
418  bool isBundled() const {
419  return isBundledWithPred() || isBundledWithSucc();
420  }
421 
422  /// Return true if this instruction is part of a bundle, and it is not the
423  /// first instruction in the bundle.
424  bool isBundledWithPred() const { return getFlag(BundledPred); }
425 
426  /// Return true if this instruction is part of a bundle, and it is not the
427  /// last instruction in the bundle.
428  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
429 
430  /// Bundle this instruction with its predecessor. This can be an unbundled
431  /// instruction, or it can be the first instruction in a bundle.
432  void bundleWithPred();
433 
434  /// Bundle this instruction with its successor. This can be an unbundled
435  /// instruction, or it can be the last instruction in a bundle.
436  void bundleWithSucc();
437 
438  /// Break bundle above this instruction.
439  void unbundleFromPred();
440 
441  /// Break bundle below this instruction.
442  void unbundleFromSucc();
443 
444  /// Returns the debug location id of this MachineInstr.
445  const DebugLoc &getDebugLoc() const { return DbgLoc; }
446 
447  /// Return the operand containing the offset to be used if this DBG_VALUE
448  /// instruction is indirect; will be an invalid register if this value is
449  /// not indirect, and an immediate with value 0 otherwise.
451  assert(isNonListDebugValue() && "not a DBG_VALUE");
452  return getOperand(1);
453  }
455  assert(isNonListDebugValue() && "not a DBG_VALUE");
456  return getOperand(1);
457  }
458 
459  /// Return the operand for the debug variable referenced by
460  /// this DBG_VALUE instruction.
461  const MachineOperand &getDebugVariableOp() const;
463 
464  /// Return the debug variable referenced by
465  /// this DBG_VALUE instruction.
466  const DILocalVariable *getDebugVariable() const;
467 
468  /// Return the operand for the complex address expression referenced by
469  /// this DBG_VALUE instruction.
470  const MachineOperand &getDebugExpressionOp() const;
472 
473  /// Return the complex address expression referenced by
474  /// this DBG_VALUE instruction.
475  const DIExpression *getDebugExpression() const;
476 
477  /// Return the debug label referenced by
478  /// this DBG_LABEL instruction.
479  const DILabel *getDebugLabel() const;
480 
481  /// Fetch the instruction number of this MachineInstr. If it does not have
482  /// one already, a new and unique number will be assigned.
483  unsigned getDebugInstrNum();
484 
485  /// Fetch instruction number of this MachineInstr -- but before it's inserted
486  /// into \p MF. Needed for transformations that create an instruction but
487  /// don't immediately insert them.
488  unsigned getDebugInstrNum(MachineFunction &MF);
489 
490  /// Examine the instruction number of this MachineInstr. May be zero if
491  /// it hasn't been assigned a number yet.
492  unsigned peekDebugInstrNum() const { return DebugInstrNum; }
493 
494  /// Set instruction number of this MachineInstr. Avoid using unless you're
495  /// deserializing this information.
496  void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
497 
498  /// Drop any variable location debugging information associated with this
499  /// instruction. Use when an instruction is modified in such a way that it no
500  /// longer defines the value it used to. Variable locations using that value
501  /// will be dropped.
502  void dropDebugNumber() { DebugInstrNum = 0; }
503 
504  /// Emit an error referring to the source location of this instruction.
505  /// This should only be used for inline assembly that is somehow
506  /// impossible to compile. Other errors should have been handled much
507  /// earlier.
508  ///
509  /// If this method returns, the caller should try to recover from the error.
510  void emitError(StringRef Msg) const;
511 
512  /// Returns the target instruction descriptor of this MachineInstr.
513  const MCInstrDesc &getDesc() const { return *MCID; }
514 
515  /// Returns the opcode of this MachineInstr.
516  unsigned getOpcode() const { return MCID->Opcode; }
517 
518  /// Retuns the total number of operands.
519  unsigned getNumOperands() const { return NumOperands; }
520 
521  /// Returns the total number of operands which are debug locations.
522  unsigned getNumDebugOperands() const {
523  return std::distance(debug_operands().begin(), debug_operands().end());
524  }
525 
526  const MachineOperand& getOperand(unsigned i) const {
527  assert(i < getNumOperands() && "getOperand() out of range!");
528  return Operands[i];
529  }
531  assert(i < getNumOperands() && "getOperand() out of range!");
532  return Operands[i];
533  }
534 
536  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
537  return *(debug_operands().begin() + Index);
538  }
539  const MachineOperand &getDebugOperand(unsigned Index) const {
540  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
541  return *(debug_operands().begin() + Index);
542  }
543 
545  assert(isDebugValue() && "not a DBG_VALUE*");
546  SmallSet<Register, 4> UsedRegs;
547  for (const auto &MO : debug_operands())
548  if (MO.isReg() && MO.getReg())
549  UsedRegs.insert(MO.getReg());
550  return UsedRegs;
551  }
552 
553  /// Returns whether this debug value has at least one debug operand with the
554  /// register \p Reg.
556  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
557  return Op.isReg() && Op.getReg() == Reg;
558  });
559  }
560 
561  /// Returns a range of all of the operands that correspond to a debug use of
562  /// \p Reg.
563  template <typename Operand, typename Instruction>
564  static iterator_range<
565  filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
567  std::function<bool(Operand & Op)> OpUsesReg(
568  [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
569  return make_filter_range(MI->debug_operands(), OpUsesReg);
570  }
572  std::function<bool(const MachineOperand &Op)>>>
575  const MachineInstr>(this, Reg);
576  }
580  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
581  this, Reg);
582  }
583 
584  bool isDebugOperand(const MachineOperand *Op) const {
585  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
586  }
587 
588  unsigned getDebugOperandIndex(const MachineOperand *Op) const {
589  assert(isDebugOperand(Op) && "Expected a debug operand.");
590  return std::distance(adl_begin(debug_operands()), Op);
591  }
592 
593  /// Returns the total number of definitions.
594  unsigned getNumDefs() const {
595  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
596  }
597 
598  /// Returns true if the instruction has implicit definition.
599  bool hasImplicitDef() const {
600  for (const MachineOperand &MO : implicit_operands())
601  if (MO.isDef() && MO.isImplicit())
602  return true;
603  return false;
604  }
605 
606  /// Returns the implicit operands number.
607  unsigned getNumImplicitOperands() const {
609  }
610 
611  /// Return true if operand \p OpIdx is a subregister index.
612  bool isOperandSubregIdx(unsigned OpIdx) const {
613  assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
614  if (isExtractSubreg() && OpIdx == 2)
615  return true;
616  if (isInsertSubreg() && OpIdx == 3)
617  return true;
618  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
619  return true;
620  if (isSubregToReg() && OpIdx == 3)
621  return true;
622  return false;
623  }
624 
625  /// Returns the number of non-implicit operands.
626  unsigned getNumExplicitOperands() const;
627 
628  /// Returns the number of non-implicit definitions.
629  unsigned getNumExplicitDefs() const;
630 
631  /// iterator/begin/end - Iterate over all operands of a machine instruction.
634 
636  mop_iterator operands_end() { return Operands + NumOperands; }
637 
639  const_mop_iterator operands_end() const { return Operands + NumOperands; }
640 
643  }
646  }
648  return make_range(operands_begin(),
650  }
652  return make_range(operands_begin(),
654  }
657  }
660  }
661  /// Returns a range over all operands that are used to determine the variable
662  /// location for this DBG_VALUE instruction.
664  assert(isDebugValue() && "Must be a debug value instruction.");
665  return isDebugValueList()
668  }
669  /// \copydoc debug_operands()
671  assert(isDebugValue() && "Must be a debug value instruction.");
672  return isDebugValueList()
675  }
676  /// Returns a range over all explicit operands that are register definitions.
677  /// Implicit definition are not included!
679  return make_range(operands_begin(),
681  }
682  /// \copydoc defs()
684  return make_range(operands_begin(),
686  }
687  /// Returns a range that includes all operands that are register uses.
688  /// This may include unrelated operands which are not register uses.
691  }
692  /// \copydoc uses()
695  }
699  }
703  }
704 
705  /// Returns the number of the operand iterator \p I points to.
707  return I - operands_begin();
708  }
709 
710  /// Access to memory operands of the instruction. If there are none, that does
711  /// not imply anything about whether the function accesses memory. Instead,
712  /// the caller must behave conservatively.
714  if (!Info)
715  return {};
716 
717  if (Info.is<EIIK_MMO>())
718  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
719 
720  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
721  return EI->getMMOs();
722 
723  return {};
724  }
725 
726  /// Access to memory operands of the instruction.
727  ///
728  /// If `memoperands_begin() == memoperands_end()`, that does not imply
729  /// anything about whether the function accesses memory. Instead, the caller
730  /// must behave conservatively.
731  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
732 
733  /// Access to memory operands of the instruction.
734  ///
735  /// If `memoperands_begin() == memoperands_end()`, that does not imply
736  /// anything about whether the function accesses memory. Instead, the caller
737  /// must behave conservatively.
738  mmo_iterator memoperands_end() const { return memoperands().end(); }
739 
740  /// Return true if we don't have any memory operands which described the
741  /// memory access done by this instruction. If this is true, calling code
742  /// must be conservative.
743  bool memoperands_empty() const { return memoperands().empty(); }
744 
745  /// Return true if this instruction has exactly one MachineMemOperand.
746  bool hasOneMemOperand() const { return memoperands().size() == 1; }
747 
748  /// Return the number of memory operands.
749  unsigned getNumMemOperands() const { return memoperands().size(); }
750 
751  /// Helper to extract a pre-instruction symbol if one has been added.
753  if (!Info)
754  return nullptr;
755  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
756  return S;
757  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
758  return EI->getPreInstrSymbol();
759 
760  return nullptr;
761  }
762 
763  /// Helper to extract a post-instruction symbol if one has been added.
765  if (!Info)
766  return nullptr;
767  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
768  return S;
769  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
770  return EI->getPostInstrSymbol();
771 
772  return nullptr;
773  }
774 
775  /// Helper to extract a heap alloc marker if one has been added.
777  if (!Info)
778  return nullptr;
779  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
780  return EI->getHeapAllocMarker();
781 
782  return nullptr;
783  }
784 
785  /// Helper to extract PCSections metadata target sections.
787  if (!Info)
788  return nullptr;
789  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
790  return EI->getPCSections();
791 
792  return nullptr;
793  }
794 
795  /// Helper to extract a CFI type hash if one has been added.
797  if (!Info)
798  return 0;
799  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
800  return EI->getCFIType();
801 
802  return 0;
803  }
804 
805  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
806  /// queries but they are bundle aware.
807 
808  enum QueryType {
809  IgnoreBundle, // Ignore bundles
810  AnyInBundle, // Return true if any instruction in bundle has property
811  AllInBundle // Return true if all instructions in bundle have property
812  };
813 
814  /// Return true if the instruction (or in the case of a bundle,
815  /// the instructions inside the bundle) has the specified property.
816  /// The first argument is the property being queried.
817  /// The second argument indicates whether the query should look inside
818  /// instruction bundles.
819  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
820  assert(MCFlag < 64 &&
821  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
822  // Inline the fast path for unbundled or bundle-internal instructions.
823  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
824  return getDesc().getFlags() & (1ULL << MCFlag);
825 
826  // If this is the first instruction in a bundle, take the slow path.
827  return hasPropertyInBundle(1ULL << MCFlag, Type);
828  }
829 
830  /// Return true if this is an instruction that should go through the usual
831  /// legalization steps.
834  }
835 
836  /// Return true if this instruction can have a variable number of operands.
837  /// In this case, the variable operands will be after the normal
838  /// operands but before the implicit definitions and uses (if any are
839  /// present).
842  }
843 
844  /// Set if this instruction has an optional definition, e.g.
845  /// ARM instructions which can set condition code if 's' bit is set.
848  }
849 
850  /// Return true if this is a pseudo instruction that doesn't
851  /// correspond to a real machine instruction.
853  return hasProperty(MCID::Pseudo, Type);
854  }
855 
856  /// Return true if this instruction doesn't produce any output in the form of
857  /// executable instructions.
859  return hasProperty(MCID::Meta, Type);
860  }
861 
863  return hasProperty(MCID::Return, Type);
864  }
865 
866  /// Return true if this is an instruction that marks the end of an EH scope,
867  /// i.e., a catchpad or a cleanuppad instruction.
870  }
871 
873  return hasProperty(MCID::Call, Type);
874  }
875 
876  /// Return true if this is a call instruction that may have an associated
877  /// call site entry in the debug info.
879  /// Return true if copying, moving, or erasing this instruction requires
880  /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
881  /// \ref eraseCallSiteInfo).
882  bool shouldUpdateCallSiteInfo() const;
883 
884  /// Returns true if the specified instruction stops control flow
885  /// from executing the instruction immediately following it. Examples include
886  /// unconditional branches and return instructions.
888  return hasProperty(MCID::Barrier, Type);
889  }
890 
891  /// Returns true if this instruction part of the terminator for a basic block.
892  /// Typically this is things like return and branch instructions.
893  ///
894  /// Various passes use this to insert code into the bottom of a basic block,
895  /// but before control flow occurs.
898  }
899 
900  /// Returns true if this is a conditional, unconditional, or indirect branch.
901  /// Predicates below can be used to discriminate between
902  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
903  /// get more information.
905  return hasProperty(MCID::Branch, Type);
906  }
907 
908  /// Return true if this is an indirect branch, such as a
909  /// branch through a register.
912  }
913 
914  /// Return true if this is a branch which may fall
915  /// through to the next instruction or may transfer control flow to some other
916  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
917  /// information about this branch.
919  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
920  }
921 
922  /// Return true if this is a branch which always
923  /// transfers control flow to some other block. The
924  /// TargetInstrInfo::analyzeBranch method can be used to get more information
925  /// about this branch.
927  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
928  }
929 
930  /// Return true if this instruction has a predicate operand that
931  /// controls execution. It may be set to 'always', or may be set to other
932  /// values. There are various methods in TargetInstrInfo that can be used to
933  /// control and modify the predicate in this instruction.
935  // If it's a bundle than all bundled instructions must be predicable for this
936  // to return true.
938  }
939 
940  /// Return true if this instruction is a comparison.
942  return hasProperty(MCID::Compare, Type);
943  }
944 
945  /// Return true if this instruction is a move immediate
946  /// (including conditional moves) instruction.
948  return hasProperty(MCID::MoveImm, Type);
949  }
950 
951  /// Return true if this instruction is a register move.
952  /// (including moving values from subreg to reg)
954  return hasProperty(MCID::MoveReg, Type);
955  }
956 
957  /// Return true if this instruction is a bitcast instruction.
959  return hasProperty(MCID::Bitcast, Type);
960  }
961 
962  /// Return true if this instruction is a select instruction.
964  return hasProperty(MCID::Select, Type);
965  }
966 
967  /// Return true if this instruction cannot be safely duplicated.
968  /// For example, if the instruction has a unique labels attached
969  /// to it, duplicating it would cause multiple definition errors.
972  return true;
974  }
975 
976  /// Return true if this instruction is convergent.
977  /// Convergent instructions can not be made control-dependent on any
978  /// additional values.
980  if (isInlineAsm()) {
981  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
982  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
983  return true;
984  }
986  }
987 
988  /// Returns true if the specified instruction has a delay slot
989  /// which must be filled by the code generator.
992  }
993 
994  /// Return true for instructions that can be folded as
995  /// memory operands in other instructions. The most common use for this
996  /// is instructions that are simple loads from memory that don't modify
997  /// the loaded value in any way, but it can also be used for instructions
998  /// that can be expressed as constant-pool loads, such as V_SETALLONES
999  /// on x86, to allow them to be folded when it is beneficial.
1000  /// This should only be set on instructions that return a value in their
1001  /// only virtual register definition.
1004  }
1005 
1006  /// Return true if this instruction behaves
1007  /// the same way as the generic REG_SEQUENCE instructions.
1008  /// E.g., on ARM,
1009  /// dX VMOVDRR rY, rZ
1010  /// is equivalent to
1011  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1012  ///
1013  /// Note that for the optimizers to be able to take advantage of
1014  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1015  /// override accordingly.
1018  }
1019 
1020  /// Return true if this instruction behaves
1021  /// the same way as the generic EXTRACT_SUBREG instructions.
1022  /// E.g., on ARM,
1023  /// rX, rY VMOVRRD dZ
1024  /// is equivalent to two EXTRACT_SUBREG:
1025  /// rX = EXTRACT_SUBREG dZ, ssub_0
1026  /// rY = EXTRACT_SUBREG dZ, ssub_1
1027  ///
1028  /// Note that for the optimizers to be able to take advantage of
1029  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1030  /// override accordingly.
1033  }
1034 
1035  /// Return true if this instruction behaves
1036  /// the same way as the generic INSERT_SUBREG instructions.
1037  /// E.g., on ARM,
1038  /// dX = VSETLNi32 dY, rZ, Imm
1039  /// is equivalent to a INSERT_SUBREG:
1040  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1041  ///
1042  /// Note that for the optimizers to be able to take advantage of
1043  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1044  /// override accordingly.
1047  }
1048 
1049  //===--------------------------------------------------------------------===//
1050  // Side Effect Analysis
1051  //===--------------------------------------------------------------------===//
1052 
1053  /// Return true if this instruction could possibly read memory.
1054  /// Instructions with this flag set are not necessarily simple load
1055  /// instructions, they may load a value and modify it, for example.
1057  if (isInlineAsm()) {
1058  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1059  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1060  return true;
1061  }
1062  return hasProperty(MCID::MayLoad, Type);
1063  }
1064 
1065  /// Return true if this instruction could possibly modify memory.
1066  /// Instructions with this flag set are not necessarily simple store
1067  /// instructions, they may store a modified value based on their operands, or
1068  /// may not actually modify anything, for example.
1070  if (isInlineAsm()) {
1071  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1072  if (ExtraInfo & InlineAsm::Extra_MayStore)
1073  return true;
1074  }
1075  return hasProperty(MCID::MayStore, Type);
1076  }
1077 
1078  /// Return true if this instruction could possibly read or modify memory.
1080  return mayLoad(Type) || mayStore(Type);
1081  }
1082 
1083  /// Return true if this instruction could possibly raise a floating-point
1084  /// exception. This is the case if the instruction is a floating-point
1085  /// instruction that can in principle raise an exception, as indicated
1086  /// by the MCID::MayRaiseFPException property, *and* at the same time,
1087  /// the instruction is used in a context where we expect floating-point
1088  /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1089  bool mayRaiseFPException() const {
1091  !getFlag(MachineInstr::MIFlag::NoFPExcept);
1092  }
1093 
1094  //===--------------------------------------------------------------------===//
1095  // Flags that indicate whether an instruction can be modified by a method.
1096  //===--------------------------------------------------------------------===//
1097 
1098  /// Return true if this may be a 2- or 3-address
1099  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1100  /// result if Y and Z are exchanged. If this flag is set, then the
1101  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1102  /// instruction.
1103  ///
1104  /// Note that this flag may be set on instructions that are only commutable
1105  /// sometimes. In these cases, the call to commuteInstruction will fail.
1106  /// Also note that some instructions require non-trivial modification to
1107  /// commute them.
1110  }
1111 
1112  /// Return true if this is a 2-address instruction
1113  /// which can be changed into a 3-address instruction if needed. Doing this
1114  /// transformation can be profitable in the register allocator, because it
1115  /// means that the instruction can use a 2-address form if possible, but
1116  /// degrade into a less efficient form if the source and dest register cannot
1117  /// be assigned to the same register. For example, this allows the x86
1118  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1119  /// is the same speed as the shift but has bigger code size.
1120  ///
1121  /// If this returns true, then the target must implement the
1122  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1123  /// is allowed to fail if the transformation isn't valid for this specific
1124  /// instruction (e.g. shl reg, 4 on x86).
1125  ///
1128  }
1129 
1130  /// Return true if this instruction requires
1131  /// custom insertion support when the DAG scheduler is inserting it into a
1132  /// machine basic block. If this is true for the instruction, it basically
1133  /// means that it is a pseudo instruction used at SelectionDAG time that is
1134  /// expanded out into magic code by the target when MachineInstrs are formed.
1135  ///
1136  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1137  /// is used to insert this into the MachineBasicBlock.
1140  }
1141 
1142  /// Return true if this instruction requires *adjustment*
1143  /// after instruction selection by calling a target hook. For example, this
1144  /// can be used to fill in ARM 's' optional operand depending on whether
1145  /// the conditional flag register is used.
1148  }
1149 
1150  /// Returns true if this instruction is a candidate for remat.
1151  /// This flag is deprecated, please don't use it anymore. If this
1152  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1153  /// verify the instruction is really rematable.
1155  // It's only possible to re-mat a bundle if all bundled instructions are
1156  // re-materializable.
1158  }
1159 
1160  /// Returns true if this instruction has the same cost (or less) than a move
1161  /// instruction. This is useful during certain types of optimizations
1162  /// (e.g., remat during two-address conversion or machine licm)
1163  /// where we would like to remat or hoist the instruction, but not if it costs
1164  /// more than moving the instruction into the appropriate register. Note, we
1165  /// are not marking copies from and to the same register class with this flag.
1167  // Only returns true for a bundle if all bundled instructions are cheap.
1169  }
1170 
1171  /// Returns true if this instruction source operands
1172  /// have special register allocation requirements that are not captured by the
1173  /// operand register classes. e.g. ARM::STRD's two source registers must be an
1174  /// even / odd pair, ARM::STM registers have to be in ascending order.
1175  /// Post-register allocation passes should not attempt to change allocations
1176  /// for sources of instructions with this flag.
1179  }
1180 
1181  /// Returns true if this instruction def operands
1182  /// have special register allocation requirements that are not captured by the
1183  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1184  /// even / odd pair, ARM::LDM registers have to be in ascending order.
1185  /// Post-register allocation passes should not attempt to change allocations
1186  /// for definitions of instructions with this flag.
1189  }
1190 
1192  CheckDefs, // Check all operands for equality
1193  CheckKillDead, // Check all operands including kill / dead markers
1194  IgnoreDefs, // Ignore all definitions
1195  IgnoreVRegDefs // Ignore virtual register definitions
1196  };
1197 
1198  /// Return true if this instruction is identical to \p Other.
1199  /// Two instructions are identical if they have the same opcode and all their
1200  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1201  /// Note that this means liveness related flags (dead, undef, kill) do not
1202  /// affect the notion of identical.
1203  bool isIdenticalTo(const MachineInstr &Other,
1204  MICheckType Check = CheckDefs) const;
1205 
1206  /// Unlink 'this' from the containing basic block, and return it without
1207  /// deleting it.
1208  ///
1209  /// This function can not be used on bundled instructions, use
1210  /// removeFromBundle() to remove individual instructions from a bundle.
1212 
1213  /// Unlink this instruction from its basic block and return it without
1214  /// deleting it.
1215  ///
1216  /// If the instruction is part of a bundle, the other instructions in the
1217  /// bundle remain bundled.
1219 
1220  /// Unlink 'this' from the containing basic block and delete it.
1221  ///
1222  /// If this instruction is the header of a bundle, the whole bundle is erased.
1223  /// This function can not be used for instructions inside a bundle, use
1224  /// eraseFromBundle() to erase individual bundled instructions.
1225  void eraseFromParent();
1226 
1227  /// Unlink 'this' form its basic block and delete it.
1228  ///
1229  /// If the instruction is part of a bundle, the other instructions in the
1230  /// bundle remain bundled.
1231  void eraseFromBundle();
1232 
1233  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1234  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1235  bool isAnnotationLabel() const {
1237  }
1238 
1239  /// Returns true if the MachineInstr represents a label.
1240  bool isLabel() const {
1241  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1242  }
1243 
1244  bool isCFIInstruction() const {
1245  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1246  }
1247 
1248  bool isPseudoProbe() const {
1250  }
1251 
1252  // True if the instruction represents a position in the function.
1253  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1254 
1255  bool isNonListDebugValue() const {
1256  return getOpcode() == TargetOpcode::DBG_VALUE;
1257  }
1258  bool isDebugValueList() const {
1259  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1260  }
1261  bool isDebugValue() const {
1262  return isNonListDebugValue() || isDebugValueList();
1263  }
1264  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1265  bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1266  bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1267  bool isDebugInstr() const {
1268  return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1269  }
1270  bool isDebugOrPseudoInstr() const {
1271  return isDebugInstr() || isPseudoProbe();
1272  }
1273 
1274  bool isDebugOffsetImm() const {
1275  return isNonListDebugValue() && getDebugOffset().isImm();
1276  }
1277 
1278  /// A DBG_VALUE is indirect iff the location operand is a register and
1279  /// the offset operand is an immediate.
1280  bool isIndirectDebugValue() const {
1281  return isDebugOffsetImm() && getDebugOperand(0).isReg();
1282  }
1283 
1284  /// A DBG_VALUE is an entry value iff its debug expression contains the
1285  /// DW_OP_LLVM_entry_value operation.
1286  bool isDebugEntryValue() const;
1287 
1288  /// Return true if the instruction is a debug value which describes a part of
1289  /// a variable as unavailable.
1290  bool isUndefDebugValue() const {
1291  if (!isDebugValue())
1292  return false;
1293  // If any $noreg locations are given, this DV is undef.
1294  for (const MachineOperand &Op : debug_operands())
1295  if (Op.isReg() && !Op.getReg().isValid())
1296  return true;
1297  return false;
1298  }
1299 
1300  bool isPHI() const {
1301  return getOpcode() == TargetOpcode::PHI ||
1302  getOpcode() == TargetOpcode::G_PHI;
1303  }
1304  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1305  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1306  bool isInlineAsm() const {
1307  return getOpcode() == TargetOpcode::INLINEASM ||
1309  }
1310 
1311  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1312  /// specific, be attached to a generic MachineInstr.
1313  bool isMSInlineAsm() const {
1315  }
1316 
1317  bool isStackAligningInlineAsm() const;
1319 
1320  bool isInsertSubreg() const {
1321  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1322  }
1323 
1324  bool isSubregToReg() const {
1325  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1326  }
1327 
1328  bool isRegSequence() const {
1329  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1330  }
1331 
1332  bool isBundle() const {
1333  return getOpcode() == TargetOpcode::BUNDLE;
1334  }
1335 
1336  bool isCopy() const {
1337  return getOpcode() == TargetOpcode::COPY;
1338  }
1339 
1340  bool isFullCopy() const {
1341  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1342  }
1343 
1344  bool isExtractSubreg() const {
1345  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1346  }
1347 
1348  /// Return true if the instruction behaves like a copy.
1349  /// This does not include native copy instructions.
1350  bool isCopyLike() const {
1351  return isCopy() || isSubregToReg();
1352  }
1353 
1354  /// Return true is the instruction is an identity copy.
1355  bool isIdentityCopy() const {
1356  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1358  }
1359 
1360  /// Return true if this is a transient instruction that is either very likely
1361  /// to be eliminated during register allocation (such as copy-like
1362  /// instructions), or if this instruction doesn't have an execution-time cost.
1363  bool isTransient() const {
1364  switch (getOpcode()) {
1365  default:
1366  return isMetaInstruction();
1367  // Copy-like instructions are usually eliminated during register allocation.
1368  case TargetOpcode::PHI:
1369  case TargetOpcode::G_PHI:
1370  case TargetOpcode::COPY:
1371  case TargetOpcode::INSERT_SUBREG:
1372  case TargetOpcode::SUBREG_TO_REG:
1373  case TargetOpcode::REG_SEQUENCE:
1374  return true;
1375  }
1376  }
1377 
1378  /// Return the number of instructions inside the MI bundle, excluding the
1379  /// bundle header.
1380  ///
1381  /// This is the number of instructions that MachineBasicBlock::iterator
1382  /// skips, 0 for unbundled instructions.
1383  unsigned getBundleSize() const;
1384 
1385  /// Return true if the MachineInstr reads the specified register.
1386  /// If TargetRegisterInfo is passed, then it also checks if there
1387  /// is a read of a super-register.
1388  /// This does not count partial redefines of virtual registers as reads:
1389  /// %reg1024:6 = OP.
1391  const TargetRegisterInfo *TRI = nullptr) const {
1392  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1393  }
1394 
1395  /// Return true if the MachineInstr reads the specified virtual register.
1396  /// Take into account that a partial define is a
1397  /// read-modify-write operation.
1399  return readsWritesVirtualRegister(Reg).first;
1400  }
1401 
1402  /// Return a pair of bools (reads, writes) indicating if this instruction
1403  /// reads or writes Reg. This also considers partial defines.
1404  /// If Ops is not null, all operand indices for Reg are added.
1405  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1406  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1407 
1408  /// Return true if the MachineInstr kills the specified register.
1409  /// If TargetRegisterInfo is passed, then it also checks if there is
1410  /// a kill of a super-register.
1412  const TargetRegisterInfo *TRI = nullptr) const {
1413  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1414  }
1415 
1416  /// Return true if the MachineInstr fully defines the specified register.
1417  /// If TargetRegisterInfo is passed, then it also checks
1418  /// if there is a def of a super-register.
1419  /// NOTE: It's ignoring subreg indices on virtual registers.
1421  const TargetRegisterInfo *TRI = nullptr) const {
1422  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1423  }
1424 
1425  /// Return true if the MachineInstr modifies (fully define or partially
1426  /// define) the specified register.
1427  /// NOTE: It's ignoring subreg indices on virtual registers.
1429  const TargetRegisterInfo *TRI = nullptr) const {
1430  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1431  }
1432 
1433  /// Returns true if the register is dead in this machine instruction.
1434  /// If TargetRegisterInfo is passed, then it also checks
1435  /// if there is a dead def of a super-register.
1437  const TargetRegisterInfo *TRI = nullptr) const {
1438  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1439  }
1440 
1441  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1442  /// the given register (not considering sub/super-registers).
1444 
1445  /// Returns the operand index that is a use of the specific register or -1
1446  /// if it is not found. It further tightens the search criteria to a use
1447  /// that kills the register if isKill is true.
1448  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1449  const TargetRegisterInfo *TRI = nullptr) const;
1450 
1451  /// Wrapper for findRegisterUseOperandIdx, it returns
1452  /// a pointer to the MachineOperand rather than an index.
1454  const TargetRegisterInfo *TRI = nullptr) {
1455  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1456  return (Idx == -1) ? nullptr : &getOperand(Idx);
1457  }
1458 
1460  Register Reg, bool isKill = false,
1461  const TargetRegisterInfo *TRI = nullptr) const {
1462  return const_cast<MachineInstr *>(this)->
1464  }
1465 
1466  /// Returns the operand index that is a def of the specified register or
1467  /// -1 if it is not found. If isDead is true, defs that are not dead are
1468  /// skipped. If Overlap is true, then it also looks for defs that merely
1469  /// overlap the specified register. If TargetRegisterInfo is non-null,
1470  /// then it also checks if there is a def of a super-register.
1471  /// This may also return a register mask operand when Overlap is true.
1473  bool isDead = false, bool Overlap = false,
1474  const TargetRegisterInfo *TRI = nullptr) const;
1475 
1476  /// Wrapper for findRegisterDefOperandIdx, it returns
1477  /// a pointer to the MachineOperand rather than an index.
1478  MachineOperand *
1479  findRegisterDefOperand(Register Reg, bool isDead = false,
1480  bool Overlap = false,
1481  const TargetRegisterInfo *TRI = nullptr) {
1482  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1483  return (Idx == -1) ? nullptr : &getOperand(Idx);
1484  }
1485 
1486  const MachineOperand *
1487  findRegisterDefOperand(Register Reg, bool isDead = false,
1488  bool Overlap = false,
1489  const TargetRegisterInfo *TRI = nullptr) const {
1490  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1491  Reg, isDead, Overlap, TRI);
1492  }
1493 
1494  /// Find the index of the first operand in the
1495  /// operand list that is used to represent the predicate. It returns -1 if
1496  /// none is found.
1497  int findFirstPredOperandIdx() const;
1498 
1499  /// Find the index of the flag word operand that
1500  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1501  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1502  ///
1503  /// If GroupNo is not NULL, it will receive the number of the operand group
1504  /// containing OpIdx.
1505  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1506 
1507  /// Compute the static register class constraint for operand OpIdx.
1508  /// For normal instructions, this is derived from the MCInstrDesc.
1509  /// For inline assembly it is derived from the flag words.
1510  ///
1511  /// Returns NULL if the static register class constraint cannot be
1512  /// determined.
1513  const TargetRegisterClass*
1514  getRegClassConstraint(unsigned OpIdx,
1515  const TargetInstrInfo *TII,
1516  const TargetRegisterInfo *TRI) const;
1517 
1518  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1519  /// the given \p CurRC.
1520  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1521  /// instructions inside the bundle will be taken into account. In other words,
1522  /// this method accumulates all the constraints of the operand of this MI and
1523  /// the related bundle if MI is a bundle or inside a bundle.
1524  ///
1525  /// Returns the register class that satisfies both \p CurRC and the
1526  /// constraints set by MI. Returns NULL if such a register class does not
1527  /// exist.
1528  ///
1529  /// \pre CurRC must not be NULL.
1531  Register Reg, const TargetRegisterClass *CurRC,
1532  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1533  bool ExploreBundle = false) const;
1534 
1535  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1536  /// to the given \p CurRC.
1537  ///
1538  /// Returns the register class that satisfies both \p CurRC and the
1539  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1540  /// does not exist.
1541  ///
1542  /// \pre CurRC must not be NULL.
1543  /// \pre The operand at \p OpIdx must be a register.
1544  const TargetRegisterClass *
1545  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1546  const TargetInstrInfo *TII,
1547  const TargetRegisterInfo *TRI) const;
1548 
1549  /// Add a tie between the register operands at DefIdx and UseIdx.
1550  /// The tie will cause the register allocator to ensure that the two
1551  /// operands are assigned the same physical register.
1552  ///
1553  /// Tied operands are managed automatically for explicit operands in the
1554  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1555  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1556 
1557  /// Given the index of a tied register operand, find the
1558  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1559  /// index of the tied operand which must exist.
1560  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1561 
1562  /// Given the index of a register def operand,
1563  /// check if the register def is tied to a source operand, due to either
1564  /// two-address elimination or inline assembly constraints. Returns the
1565  /// first tied use operand index by reference if UseOpIdx is not null.
1566  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1567  unsigned *UseOpIdx = nullptr) const {
1568  const MachineOperand &MO = getOperand(DefOpIdx);
1569  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1570  return false;
1571  if (UseOpIdx)
1572  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1573  return true;
1574  }
1575 
1576  /// Return true if the use operand of the specified index is tied to a def
1577  /// operand. It also returns the def operand index by reference if DefOpIdx
1578  /// is not null.
1579  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1580  unsigned *DefOpIdx = nullptr) const {
1581  const MachineOperand &MO = getOperand(UseOpIdx);
1582  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1583  return false;
1584  if (DefOpIdx)
1585  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1586  return true;
1587  }
1588 
1589  /// Clears kill flags on all operands.
1590  void clearKillInfo();
1591 
1592  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1593  /// properly composing subreg indices where necessary.
1594  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1595  const TargetRegisterInfo &RegInfo);
1596 
1597  /// We have determined MI kills a register. Look for the
1598  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1599  /// add a implicit operand if it's not found. Returns true if the operand
1600  /// exists / is added.
1601  bool addRegisterKilled(Register IncomingReg,
1602  const TargetRegisterInfo *RegInfo,
1603  bool AddIfNotFound = false);
1604 
1605  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1606  /// all aliasing registers.
1608 
1609  /// We have determined MI defined a register without a use.
1610  /// Look for the operand that defines it and mark it as IsDead. If
1611  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1612  /// true if the operand exists / is added.
1614  bool AddIfNotFound = false);
1615 
1616  /// Clear all dead flags on operands defining register @p Reg.
1618 
1619  /// Mark all subregister defs of register @p Reg with the undef flag.
1620  /// This function is used when we determined to have a subregister def in an
1621  /// otherwise undefined super register.
1622  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1623 
1624  /// We have determined MI defines a register. Make sure there is an operand
1625  /// defining Reg.
1627  const TargetRegisterInfo *RegInfo = nullptr);
1628 
1629  /// Mark every physreg used by this instruction as
1630  /// dead except those in the UsedRegs list.
1631  ///
1632  /// On instructions with register mask operands, also add implicit-def
1633  /// operands for all registers in UsedRegs.
1635  const TargetRegisterInfo &TRI);
1636 
1637  /// Return true if it is safe to move this instruction. If
1638  /// SawStore is set to true, it means that there is a store (or call) between
1639  /// the instruction's location and its intended destination.
1640  bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1641 
1642  /// Returns true if this instruction's memory access aliases the memory
1643  /// access of Other.
1644  //
1645  /// Assumes any physical registers used to compute addresses
1646  /// have the same value for both instructions. Returns false if neither
1647  /// instruction writes to memory.
1648  ///
1649  /// @param AA Optional alias analysis, used to compare memory operands.
1650  /// @param Other MachineInstr to check aliasing against.
1651  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1652  bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1653 
1654  /// Return true if this instruction may have an ordered
1655  /// or volatile memory reference, or if the information describing the memory
1656  /// reference is not available. Return false if it is known to have no
1657  /// ordered or volatile memory references.
1658  bool hasOrderedMemoryRef() const;
1659 
1660  /// Return true if this load instruction never traps and points to a memory
1661  /// location whose value doesn't change during the execution of this function.
1662  ///
1663  /// Examples include loading a value from the constant pool or from the
1664  /// argument area of a function (if it does not change). If the instruction
1665  /// does multiple loads, this returns true only if all of the loads are
1666  /// dereferenceable and invariant.
1667  bool isDereferenceableInvariantLoad() const;
1668 
1669  /// If the specified instruction is a PHI that always merges together the
1670  /// same virtual register, return the register, otherwise return 0.
1671  unsigned isConstantValuePHI() const;
1672 
1673  /// Return true if this instruction has side effects that are not modeled
1674  /// by mayLoad / mayStore, etc.
1675  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1676  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1677  /// INLINEASM instruction, in which case the side effect property is encoded
1678  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1679  ///
1680  bool hasUnmodeledSideEffects() const;
1681 
1682  /// Returns true if it is illegal to fold a load across this instruction.
1683  bool isLoadFoldBarrier() const;
1684 
1685  /// Return true if all the defs of this instruction are dead.
1686  bool allDefsAreDead() const;
1687 
1688  /// Return a valid size if the instruction is a spill instruction.
1690 
1691  /// Return a valid size if the instruction is a folded spill instruction.
1693 
1694  /// Return a valid size if the instruction is a restore instruction.
1696 
1697  /// Return a valid size if the instruction is a folded restore instruction.
1700 
1701  /// Copy implicit register operands from specified
1702  /// instruction to this instruction.
1703  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1704 
1705  /// Debugging support
1706  /// @{
1707  /// Determine the generic type to be printed (if needed) on uses and defs.
1708  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1709  const MachineRegisterInfo &MRI) const;
1710 
1711  /// Return true when an instruction has tied register that can't be determined
1712  /// by the instruction's descriptor. This is useful for MIR printing, to
1713  /// determine whether we need to print the ties or not.
1714  bool hasComplexRegisterTies() const;
1715 
1716  /// Print this MI to \p OS.
1717  /// Don't print information that can be inferred from other instructions if
1718  /// \p IsStandalone is false. It is usually true when only a fragment of the
1719  /// function is printed.
1720  /// Only print the defs and the opcode if \p SkipOpers is true.
1721  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1722  /// Otherwise, also print the debug loc, with a terminating newline.
1723  /// \p TII is used to print the opcode name. If it's not present, but the
1724  /// MI is in a function, the opcode will be printed using the function's TII.
1725  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1726  bool SkipDebugLoc = false, bool AddNewLine = true,
1727  const TargetInstrInfo *TII = nullptr) const;
1728  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1729  bool SkipOpers = false, bool SkipDebugLoc = false,
1730  bool AddNewLine = true,
1731  const TargetInstrInfo *TII = nullptr) const;
1732  void dump() const;
1733  /// Print on dbgs() the current instruction and the instructions defining its
1734  /// operands and so on until we reach \p MaxDepth.
1735  void dumpr(const MachineRegisterInfo &MRI,
1736  unsigned MaxDepth = UINT_MAX) const;
1737  /// @}
1738 
1739  //===--------------------------------------------------------------------===//
1740  // Accessors used to build up machine instructions.
1741 
1742  /// Add the specified operand to the instruction. If it is an implicit
1743  /// operand, it is added to the end of the operand list. If it is an
1744  /// explicit operand it is added at the end of the explicit operand list
1745  /// (before the first implicit operand).
1746  ///
1747  /// MF must be the machine function that was used to allocate this
1748  /// instruction.
1749  ///
1750  /// MachineInstrBuilder provides a more convenient interface for creating
1751  /// instructions and adding operands.
1752  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1753 
1754  /// Add an operand without providing an MF reference. This only works for
1755  /// instructions that are inserted in a basic block.
1756  ///
1757  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1758  /// preferred.
1759  void addOperand(const MachineOperand &Op);
1760 
1761  /// Replace the instruction descriptor (thus opcode) of
1762  /// the current instruction with a new one.
1763  void setDesc(const MCInstrDesc &TID) { MCID = &TID; }
1764 
1765  /// Replace current source information with new such.
1766  /// Avoid using this, the constructor argument is preferable.
1768  DbgLoc = std::move(DL);
1769  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1770  }
1771 
1772  /// Erase an operand from an instruction, leaving it with one
1773  /// fewer operand than it started with.
1774  void removeOperand(unsigned OpNo);
1775 
1776  /// Clear this MachineInstr's memory reference descriptor list. This resets
1777  /// the memrefs to their most conservative state. This should be used only
1778  /// as a last resort since it greatly pessimizes our knowledge of the memory
1779  /// access performed by the instruction.
1780  void dropMemRefs(MachineFunction &MF);
1781 
1782  /// Assign this MachineInstr's memory reference descriptor list.
1783  ///
1784  /// Unlike other methods, this *will* allocate them into a new array
1785  /// associated with the provided `MachineFunction`.
1787 
1788  /// Add a MachineMemOperand to the machine instruction.
1789  /// This function should be used only occasionally. The setMemRefs function
1790  /// is the primary method for setting up a MachineInstr's MemRefs list.
1792 
1793  /// Clone another MachineInstr's memory reference descriptor list and replace
1794  /// ours with it.
1795  ///
1796  /// Note that `*this` may be the incoming MI!
1797  ///
1798  /// Prefer this API whenever possible as it can avoid allocations in common
1799  /// cases.
1800  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1801 
1802  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1803  /// list and replace ours with it.
1804  ///
1805  /// Note that `*this` may be one of the incoming MIs!
1806  ///
1807  /// Prefer this API whenever possible as it can avoid allocations in common
1808  /// cases.
1811 
1812  /// Set a symbol that will be emitted just prior to the instruction itself.
1813  ///
1814  /// Setting this to a null pointer will remove any such symbol.
1815  ///
1816  /// FIXME: This is not fully implemented yet.
1818 
1819  /// Set a symbol that will be emitted just after the instruction itself.
1820  ///
1821  /// Setting this to a null pointer will remove any such symbol.
1822  ///
1823  /// FIXME: This is not fully implemented yet.
1825 
1826  /// Clone another MachineInstr's pre- and post- instruction symbols and
1827  /// replace ours with it.
1829 
1830  /// Set a marker on instructions that denotes where we should create and emit
1831  /// heap alloc site labels. This waits until after instruction selection and
1832  /// optimizations to create the label, so it should still work if the
1833  /// instruction is removed or duplicated.
1834  void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1835 
1836  // Set metadata on instructions that say which sections to emit instruction
1837  // addresses into.
1838  void setPCSections(MachineFunction &MF, MDNode *MD);
1839 
1840  /// Set the CFI type for the instruction.
1842 
1843  /// Return the MIFlags which represent both MachineInstrs. This
1844  /// should be used when merging two MachineInstrs into one. This routine does
1845  /// not modify the MIFlags of this MachineInstr.
1846  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1847 
1849 
1850  /// Copy all flags to MachineInst MIFlags
1851  void copyIRFlags(const Instruction &I);
1852 
1853  /// Break any tie involving OpIdx.
1854  void untieRegOperand(unsigned OpIdx) {
1855  MachineOperand &MO = getOperand(OpIdx);
1856  if (MO.isReg() && MO.isTied()) {
1857  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1858  MO.TiedTo = 0;
1859  }
1860  }
1861 
1862  /// Add all implicit def and use operands to this instruction.
1864 
1865  /// Scan instructions immediately following MI and collect any matching
1866  /// DBG_VALUEs.
1868 
1869  /// Find all DBG_VALUEs that point to the register def in this instruction
1870  /// and point them to \p Reg instead.
1872 
1873  /// Returns the Intrinsic::ID for this instruction.
1874  /// \pre Must have an intrinsic ID operand.
1875  unsigned getIntrinsicID() const {
1877  }
1878 
1879  /// Sets all register debug operands in this debug value instruction to be
1880  /// undef.
1882  assert(isDebugValue() && "Must be a debug value instruction.");
1883  for (MachineOperand &MO : debug_operands()) {
1884  if (MO.isReg()) {
1885  MO.setReg(0);
1886  MO.setSubReg(0);
1887  }
1888  }
1889  }
1890 
1891 private:
1892  /// If this instruction is embedded into a MachineFunction, return the
1893  /// MachineRegisterInfo object for the current function, otherwise
1894  /// return null.
1895  MachineRegisterInfo *getRegInfo();
1896 
1897  /// Unlink all of the register operands in this instruction from their
1898  /// respective use lists. This requires that the operands already be on their
1899  /// use lists.
1900  void removeRegOperandsFromUseLists(MachineRegisterInfo&);
1901 
1902  /// Add all of the register operands in this instruction from their
1903  /// respective use lists. This requires that the operands not be on their
1904  /// use lists yet.
1905  void addRegOperandsToUseLists(MachineRegisterInfo&);
1906 
1907  /// Slow path for hasProperty when we're dealing with a bundle.
1908  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1909 
1910  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1911  /// this MI and the given operand index \p OpIdx.
1912  /// If the related operand does not constrained Reg, this returns CurRC.
1913  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1914  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1915  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1916 
1917  /// Stores extra instruction information inline or allocates as ExtraInfo
1918  /// based on the number of pointers.
1919  void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1920  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1921  MDNode *HeapAllocMarker, MDNode *PCSections,
1922  uint32_t CFIType);
1923 };
1924 
1925 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1926 /// instruction rather than by pointer value.
1927 /// The hashing and equality testing functions ignore definitions so this is
1928 /// useful for CSE, etc.
1930  static inline MachineInstr *getEmptyKey() {
1931  return nullptr;
1932  }
1933 
1934  static inline MachineInstr *getTombstoneKey() {
1935  return reinterpret_cast<MachineInstr*>(-1);
1936  }
1937 
1938  static unsigned getHashValue(const MachineInstr* const &MI);
1939 
1940  static bool isEqual(const MachineInstr* const &LHS,
1941  const MachineInstr* const &RHS) {
1942  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1943  LHS == getEmptyKey() || LHS == getTombstoneKey())
1944  return LHS == RHS;
1945  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1946  }
1947 };
1948 
1949 //===----------------------------------------------------------------------===//
1950 // Debugging Support
1951 
1953  MI.print(OS);
1954  return OS;
1955 }
1956 
1957 } // end namespace llvm
1958 
1959 #endif // LLVM_CODEGEN_MACHINEINSTR_H
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1261
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:755
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:846
llvm::MachineInstr::getNumDebugOperands
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:522
llvm::MachineInstr::isBranch
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:904
llvm::MachineInstr::setDebugValueUndef
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
Definition: MachineInstr.h:1881
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:154
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:224
TrailingObjects.h
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2001
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2035
llvm::MachineInstr::isUndefDebugValue
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
Definition: MachineInstr.h:1290
llvm::MachineInstr::isExtractSubregLike
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MachineInstr.h:1031
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2363
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:689
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1948
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:160
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:706
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1305
llvm::MachineInstr::getDebugOperandIndex
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:588
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:34
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:910
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2061
llvm::MachineInstr::usesCustomInsertionHook
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:1138
llvm::TrailingObjects< ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *, uint32_t >::TrailingObjects
TrailingObjects(const TrailingObjects &)=delete
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:79
llvm::MachineInstr::explicit_operands
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:647
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:970
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1219
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:663
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1079
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:166
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:713
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:731
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:764
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:532
llvm::MachineInstr::isCompare
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:941
llvm::MachineInstr::isEHScopeReturn
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:868
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:679
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:171
llvm::MachineInstr::isRegSequenceLike
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:1016
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::ArrayRef::iterator
const_pointer iterator
Definition: ArrayRef.h:49
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1280
llvm::MachineInstr::implicit_operands
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:655
ilist.h
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1193
InlineAsm.h
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:173
llvm::ilist_node_with_parent
An ilist node that can access its parent list.
Definition: ilist_node.h:257
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineInstr::clearAsmPrinterFlags
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:334
llvm::MachineInstr::isMoveImmediate
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:947
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::MachineInstr::isInsertSubregLike
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MachineInstr.h:1045
llvm::MachineInstr::isDebugOffsetImm
bool isDebugOffsetImm() const
Definition: MachineInstr.h:1274
llvm::MachineInstr::NoSchedComment
@ NoSchedComment
Definition: MachineInstr.h:78
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:746
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1248
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2017
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1456
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1424
llvm::MachineInstr::isEHLabel
bool isEHLabel() const
Definition: MachineInstr.h:1233
llvm::ilist_callback_traits
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:678
llvm::MachineInstr::hasPostISelHook
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:1146
llvm::MachineInstr::isBundled
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:418
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MachineInstr::operands_begin
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:638
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::filter_iterator_impl
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:440
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:100
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::findRegisterUseOperand
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1453
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:967
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:670
llvm::Optional< unsigned >
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1336
llvm::MachineInstr::peekDebugInstrNum
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:492
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:184
llvm::MachineInstr::operands_end
mop_iterator operands_end()
Definition: MachineInstr.h:636
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:840
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachineInstr::uses
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:693
llvm::MachineInstr::hasDebugOperandForReg
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:555
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:573
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineInstr::getMF
MachineFunction * getMF()
Definition: MachineInstr.h:325
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:746
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:360
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:825
llvm::MachineInstr::isPreISelOpcode
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:832
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:1218
llvm::MachineInstrExpressionTrait::getTombstoneKey
static MachineInstr * getTombstoneKey()
Definition: MachineInstr.h:1934
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1363
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1579
llvm::MachineInstr::isInsertSubreg
bool isInsertSubreg() const
Definition: MachineInstr.h:1320
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:594
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1244
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1113
llvm::MachineInstr::readsVirtualRegister
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:1398
llvm::MachineInstr::getParent
MachineBasicBlock * getParent()
Definition: MachineInstr.h:314
llvm::MachineInstrExpressionTrait::isEqual
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Definition: MachineInstr.h:1940
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:352
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:566
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:926
llvm::MachineInstr::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:1177
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:136
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:232
llvm::MachineInstr::isLabel
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:1240
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:872
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineInstr::isGCLabel
bool isGCLabel() const
Definition: MachineInstr.h:1234
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:484
llvm::AAResults
Definition: AliasAnalysis.h:518
llvm::MachineInstr::isPredicable
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:934
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3058
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1468
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:349
llvm::adl_end
decltype(auto) adl_end(ContainerTy &&container)
Definition: STLExtras.h:243
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2337
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1189
llvm::MachineInstr::implicit_operands
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:658
llvm::MachineInstr::isInsideBundle
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:412
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1191
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:170
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:403
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1315
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::isIdentityCopy
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:1355
MCSymbol.h
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:674
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:773
llvm::MachineInstr::isDebugOrPseudoInstr
bool isDebugOrPseudoInstr() const
Definition: MachineInstr.h:1270
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:87
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1267
llvm::MachineInstr::CommentFlag
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:76
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1869
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:92
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:153
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineInstr::isPseudo
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:852
llvm::MachineInstr::getAsmPrinterFlags
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:331
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:373
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1196
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:707
llvm::MachineInstr::getCFIType
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:796
llvm::MachineInstr::getIntrinsicID
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
Definition: MachineInstr.h:1875
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:955
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineInstr::isConvertibleTo3Addr
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:1126
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:199
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:782
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:454
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:590
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:819
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1449
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1420
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1548
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:181
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:94
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1411
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1255
llvm::MachineInstrExpressionTrait
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
Definition: MachineInstr.h:1929
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:168
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:129
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:810
llvm::MachineInstr::isConvergent
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:979
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:167
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:169
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:90
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:570
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:179
llvm::MachineInstr::~MachineInstr
~MachineInstr()=delete
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:151
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1493
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:450
llvm::MachineInstr::getDebugOperand
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:535
llvm::MachineInstr::clearAsmPrinterFlag
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:347
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:159
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2075
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:858
Index
uint32_t Index
Definition: ELFObjHandler.cpp:82
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:749
uint64_t
llvm::MachineInstr::ReloadReuse
@ ReloadReuse
Definition: MachineInstr.h:77
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:357
llvm::MachineInstr::getPCSections
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:786
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:156
llvm::MachineInstr::findRegisterDefOperand
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1487
llvm::MachineInstr::isCommutable
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MachineInstr.h:1108
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:830
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:368
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:102
llvm::MachineInstr::isMetaInstruction
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:858
llvm::MachineInstr::getNumImplicitOperands
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:607
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2009
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:233
llvm::MachineInstr::operands_begin
mop_iterator operands_begin()
Definition: MachineInstr.h:635
llvm::MachineInstr::isAsCheapAsAMove
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:1166
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:811
llvm::MachineInstr::getDebugOffset
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:454
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:177
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:70
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2272
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:366
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:163
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:764
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1935
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:999
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:178
llvm::MachineInstr::isMoveReg
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:953
llvm::MachineInstr::isDebugPHI
bool isDebugPHI() const
Definition: MachineInstr.h:1266
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:738
iterator_range.h
llvm::MachineInstr::operator=
MachineInstr & operator=(const MachineInstr &)=delete
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1300
llvm::MachineInstr::hasDelaySlot
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:990
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:791
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:862
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:612
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1390
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1195
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1518
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1039
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:689
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:842
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:108
llvm::MachineInstr::isRegTiedToUseOperand
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
Definition: MachineInstr.h:1566
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:797
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:599
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:176
llvm::MachineInstr::getUsedDebugRegs
SmallSet< Register, 4 > getUsedDebugRegs() const
Definition: MachineInstr.h:544
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:248
RegInfo
Definition: AMDGPUAsmParser.cpp:2561
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:36
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1597
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1306
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1854
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:776
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2356
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:175
llvm::MachineInstr::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:1187
uint32_t
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1056
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:112
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1555
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:896
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1264
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:752
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:161
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1253
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
llvm::MachineInstr::findRegisterUseOperand
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:1459
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:867
llvm::make_filter_range
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:512
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1244
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:949
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::ArrayRecycler
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::MachineInstr::isExtractSubreg
bool isExtractSubreg() const
Definition: MachineInstr.h:1344
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:149
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:182
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:935
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1428
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:1002
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1328
llvm::MachineInstr::operands_end
const_mop_iterator operands_end() const
Definition: MachineInstr.h:639
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:526
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1350
uint16_t
llvm::MachineInstr::explicit_uses
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:700
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:511
llvm::MachineInstr::setAsmPrinterFlag
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:342
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1069
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1437
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1385
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:158
llvm::MachineInstr::getOperand
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:530
llvm::adl_begin
decltype(auto) adl_begin(ContainerTy &&container)
Definition: STLExtras.h:238
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:862
llvm::MachineInstr::explicit_operands
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:651
llvm::MachineInstr::setPCSections
void setPCSections(MachineFunction &MF, MDNode *MD)
Definition: MachineInstr.cpp:493
llvm::TrailingObjects
See the file comment for details on the usage of the TrailingObjects type.
Definition: TrailingObjects.h:212
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:90
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:694
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:98
llvm::MachineInstr::setDebugLoc
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
Definition: MachineInstr.h:1767
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:162
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:424
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:743
llvm::MachineInstr::getDebugOperand
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:539
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1332
llvm::MachineInstr::getAsmPrinterFlag
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:337
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1763
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:276
AA
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1265
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:809
llvm::MachineInstr::dropDebugNumber
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:502
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:150
llvm::MachineInstr::getDebugOperandsForReg
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:579
llvm::MachineInstr::explicit_uses
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:696
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1028
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:104
ArrayRecycler.h
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:428
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::MachineInstr::isMSInlineAsm
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific,...
Definition: MachineInstr.h:1313
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:184
llvm::MachineInstr::CheckDefs
@ CheckDefs
Definition: MachineInstr.h:1192
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:89
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineInstr::debug_operands
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:670
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineInstr::setCFIType
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
Definition: MachineInstr.cpp:502
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:341
llvm::MachineInstr::isTransient
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:1363
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:148
llvm::MachineInstr::isDebugOperand
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:584
ilist_node.h
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:96
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:713
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1476
llvm::SmallVectorImpl< unsigned >
MachineOperand.h
DenseMapInfo.h
llvm::MachineInstr::isConditionalBranch
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:918
llvm::MachineInstr::isBitcast
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:958
llvm::MCID::Meta
@ Meta
Definition: MCInstrDesc.h:152
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:174
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstrExpressionTrait::getEmptyKey
static MachineInstr * getEmptyKey()
Definition: MachineInstr.h:1930
llvm::MachineInstr::isSelect
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:963
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2345
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:906
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1194
llvm::MachineInstr::isAnnotationLabel
bool isAnnotationLabel() const
Definition: MachineInstr.h:1235
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3148
llvm::MachineInstr::operands
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:644
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1304
llvm::MachineInstr::setDebugInstrNum
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:496
llvm::MachineInstr::isSubregToReg
bool isSubregToReg() const
Definition: MachineInstr.h:1324
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstr::isRematerializable
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:1154
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1340
PointerSumType.h
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:180
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1086
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1089
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:88
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1436
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1258
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1479
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:684
llvm::MachineInstr::hasOptionalDef
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:846
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:231
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:887
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:808
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:157
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:979
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:183
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:469
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2326
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:732
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:362
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1247
llvm::MachineInstr::defs
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:683
SmallSet.h
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2288
llvm::LLT
Definition: LowLevelTypeImpl.h:39