LLVM  16.0.0git
SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/SetVector.h"
24 
25 #define GET_INSTRINFO_HEADER
26 #include "AMDGPUGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class APInt;
31 class GCNSubtarget;
32 class LiveVariables;
33 class MachineDominatorTree;
34 class MachineRegisterInfo;
35 class RegScavenger;
36 class TargetRegisterClass;
37 class ScheduleHazardRecognizer;
38 
39 /// Mark the MMO of a uniform load if there are no potentially clobbering stores
40 /// on any path from the start of an entry function to this load.
43 
44 class SIInstrInfo final : public AMDGPUGenInstrInfo {
45 private:
46  const SIRegisterInfo RI;
47  const GCNSubtarget &ST;
48  TargetSchedModel SchedModel;
49  mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
50 
51  // The inverse predicate should have the negative value.
52  enum BranchPredicate {
53  INVALID_BR = 0,
54  SCC_TRUE = 1,
55  SCC_FALSE = -1,
56  VCCNZ = 2,
57  VCCZ = -2,
58  EXECNZ = -3,
59  EXECZ = 3
60  };
61 
63 
64  static unsigned getBranchOpcode(BranchPredicate Cond);
65  static BranchPredicate getBranchPredicate(unsigned Opcode);
66 
67 public:
70  MachineOperand &SuperReg,
71  const TargetRegisterClass *SuperRC,
72  unsigned SubIdx,
73  const TargetRegisterClass *SubRC) const;
76  MachineOperand &SuperReg,
77  const TargetRegisterClass *SuperRC,
78  unsigned SubIdx,
79  const TargetRegisterClass *SubRC) const;
80 private:
81  void swapOperands(MachineInstr &Inst) const;
82 
83  std::pair<bool, MachineBasicBlock *>
84  moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
85  MachineDominatorTree *MDT = nullptr) const;
86 
87  void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
88  MachineDominatorTree *MDT = nullptr) const;
89 
90  void lowerScalarAbs(SetVectorType &Worklist,
91  MachineInstr &Inst) const;
92 
93  void lowerScalarXnor(SetVectorType &Worklist,
94  MachineInstr &Inst) const;
95 
96  void splitScalarNotBinop(SetVectorType &Worklist,
97  MachineInstr &Inst,
98  unsigned Opcode) const;
99 
100  void splitScalarBinOpN2(SetVectorType &Worklist,
101  MachineInstr &Inst,
102  unsigned Opcode) const;
103 
104  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
105  MachineInstr &Inst, unsigned Opcode,
106  bool Swap = false) const;
107 
108  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
109  MachineDominatorTree *MDT = nullptr) const;
110 
111  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
112  unsigned Opcode,
113  MachineDominatorTree *MDT = nullptr) const;
114 
115  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
116  MachineDominatorTree *MDT = nullptr) const;
117 
118  void splitScalar64BitBCNT(SetVectorType &Worklist,
119  MachineInstr &Inst) const;
120  void splitScalar64BitBFE(SetVectorType &Worklist,
121  MachineInstr &Inst) const;
122  void movePackToVALU(SetVectorType &Worklist,
124  MachineInstr &Inst) const;
125 
126  void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
127  SetVectorType &Worklist) const;
128 
129  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
130  MachineInstr &SCCDefInst,
131  SetVectorType &Worklist,
132  Register NewCond = Register()) const;
133  void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
134  SetVectorType &Worklist) const;
135 
136  const TargetRegisterClass *
137  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
138 
139  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
140  const MachineInstr &MIb) const;
141 
142  Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
143 
144 protected:
146  MachineOperand &Src0, unsigned Src0OpName,
147  MachineOperand &Src1, unsigned Src1OpName) const;
148 
150  unsigned OpIdx0,
151  unsigned OpIdx1) const override;
152 
153 public:
155  MO_MASK = 0xf,
156 
157  MO_NONE = 0,
158  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
160  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
163  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
165  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
166  MO_REL32 = 4,
168  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
170 
172 
175  };
176 
177  explicit SIInstrInfo(const GCNSubtarget &ST);
178 
180  return RI;
181  }
182 
183  const GCNSubtarget &getSubtarget() const {
184  return ST;
185  }
186 
187  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
188 
189  bool isIgnorableUse(const MachineOperand &MO) const override;
190 
191  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
192  int64_t &Offset1,
193  int64_t &Offset2) const override;
194 
196  const MachineInstr &LdSt,
197  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
198  bool &OffsetIsScalable, unsigned &Width,
199  const TargetRegisterInfo *TRI) const final;
200 
203  unsigned NumLoads, unsigned NumBytes) const override;
204 
205  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
206  int64_t Offset1, unsigned NumLoads) const override;
207 
209  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
210  bool KillSrc) const override;
211 
214  Register DestReg, int64_t Value) const;
215 
217  unsigned Size) const;
218 
221  Register SrcReg, int Value) const;
222 
225  Register SrcReg, int Value) const;
226 
229  bool isKill, int FrameIndex,
230  const TargetRegisterClass *RC,
231  const TargetRegisterInfo *TRI) const override;
232 
235  int FrameIndex, const TargetRegisterClass *RC,
236  const TargetRegisterInfo *TRI) const override;
237 
238  bool expandPostRAPseudo(MachineInstr &MI) const override;
239 
240  // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
241  // instructions. Returns a pair of generated instructions.
242  // Can split either post-RA with physical registers or pre-RA with
243  // virtual registers. In latter case IR needs to be in SSA form and
244  // and a REG_SEQUENCE is produced to define original register.
245  std::pair<MachineInstr*, MachineInstr*>
247 
248  // Returns an opcode that can be used to move a value to a \p DstRC
249  // register. If there is no hardware instruction that can store to \p
250  // DstRC, then AMDGPU::COPY is returned.
251  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
252 
254  unsigned EltSize,
255  bool IsSGPR) const;
256 
258  bool IsIndirectSrc) const;
260  int commuteOpcode(unsigned Opc) const;
261 
263  inline int commuteOpcode(const MachineInstr &MI) const {
264  return commuteOpcode(MI.getOpcode());
265  }
266 
267  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
268  unsigned &SrcOpIdx2) const override;
269 
270  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
271  unsigned & SrcOpIdx1) const;
272 
273  bool isBranchOffsetInRange(unsigned BranchOpc,
274  int64_t BrOffset) const override;
275 
276  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
277 
278  /// Return whether the block terminate with divergent branch.
279  /// Note this only work before lowering the pseudo control flow instructions.
280  bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
281 
283  MachineBasicBlock &NewDestBB,
284  MachineBasicBlock &RestoreBB, const DebugLoc &DL,
285  int64_t BrOffset, RegScavenger *RS) const override;
286 
290  MachineBasicBlock *&FBB,
292  bool AllowModify) const;
293 
295  MachineBasicBlock *&FBB,
297  bool AllowModify = false) const override;
298 
300  int *BytesRemoved = nullptr) const override;
301 
304  const DebugLoc &DL,
305  int *BytesAdded = nullptr) const override;
306 
308  SmallVectorImpl<MachineOperand> &Cond) const override;
309 
312  Register TrueReg, Register FalseReg, int &CondCycles,
313  int &TrueCycles, int &FalseCycles) const override;
314 
318  Register TrueReg, Register FalseReg) const override;
319 
323  Register TrueReg, Register FalseReg) const;
324 
325  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
326  Register &SrcReg2, int64_t &CmpMask,
327  int64_t &CmpValue) const override;
328 
329  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
330  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
331  const MachineRegisterInfo *MRI) const override;
332 
333  bool
335  const MachineInstr &MIb) const override;
336 
337  static bool isFoldableCopy(const MachineInstr &MI);
338 
339  void removeModOperands(MachineInstr &MI) const;
340 
342  MachineRegisterInfo *MRI) const final;
343 
344  unsigned getMachineCSELookAheadLimit() const override { return 500; }
345 
347  LiveIntervals *LIS) const override;
348 
350  const MachineBasicBlock *MBB,
351  const MachineFunction &MF) const override;
352 
353  static bool isSALU(const MachineInstr &MI) {
354  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
355  }
356 
357  bool isSALU(uint16_t Opcode) const {
358  return get(Opcode).TSFlags & SIInstrFlags::SALU;
359  }
360 
361  static bool isVALU(const MachineInstr &MI) {
362  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
363  }
364 
365  bool isVALU(uint16_t Opcode) const {
366  return get(Opcode).TSFlags & SIInstrFlags::VALU;
367  }
368 
369  static bool isVMEM(const MachineInstr &MI) {
370  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
371  }
372 
373  bool isVMEM(uint16_t Opcode) const {
374  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
375  }
376 
377  static bool isSOP1(const MachineInstr &MI) {
378  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
379  }
380 
381  bool isSOP1(uint16_t Opcode) const {
382  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
383  }
384 
385  static bool isSOP2(const MachineInstr &MI) {
386  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
387  }
388 
389  bool isSOP2(uint16_t Opcode) const {
390  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
391  }
392 
393  static bool isSOPC(const MachineInstr &MI) {
394  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
395  }
396 
397  bool isSOPC(uint16_t Opcode) const {
398  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
399  }
400 
401  static bool isSOPK(const MachineInstr &MI) {
402  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
403  }
404 
405  bool isSOPK(uint16_t Opcode) const {
406  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
407  }
408 
409  static bool isSOPP(const MachineInstr &MI) {
410  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
411  }
412 
413  bool isSOPP(uint16_t Opcode) const {
414  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
415  }
416 
417  static bool isPacked(const MachineInstr &MI) {
418  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
419  }
420 
421  bool isPacked(uint16_t Opcode) const {
422  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
423  }
424 
425  static bool isVOP1(const MachineInstr &MI) {
426  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
427  }
428 
429  bool isVOP1(uint16_t Opcode) const {
430  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
431  }
432 
433  static bool isVOP2(const MachineInstr &MI) {
434  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
435  }
436 
437  bool isVOP2(uint16_t Opcode) const {
438  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
439  }
440 
441  static bool isVOP3(const MachineInstr &MI) {
442  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
443  }
444 
445  bool isVOP3(uint16_t Opcode) const {
446  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
447  }
448 
449  static bool isSDWA(const MachineInstr &MI) {
450  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
451  }
452 
453  bool isSDWA(uint16_t Opcode) const {
454  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
455  }
456 
457  static bool isVOPC(const MachineInstr &MI) {
458  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
459  }
460 
461  bool isVOPC(uint16_t Opcode) const {
462  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
463  }
464 
465  static bool isMUBUF(const MachineInstr &MI) {
466  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
467  }
468 
469  bool isMUBUF(uint16_t Opcode) const {
470  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
471  }
472 
473  static bool isMTBUF(const MachineInstr &MI) {
474  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
475  }
476 
477  bool isMTBUF(uint16_t Opcode) const {
478  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
479  }
480 
481  static bool isSMRD(const MachineInstr &MI) {
482  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
483  }
484 
485  bool isSMRD(uint16_t Opcode) const {
486  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
487  }
488 
489  bool isBufferSMRD(const MachineInstr &MI) const;
490 
491  static bool isDS(const MachineInstr &MI) {
492  return MI.getDesc().TSFlags & SIInstrFlags::DS;
493  }
494 
495  bool isDS(uint16_t Opcode) const {
496  return get(Opcode).TSFlags & SIInstrFlags::DS;
497  }
498 
499  bool isAlwaysGDS(uint16_t Opcode) const;
500 
501  static bool isMIMG(const MachineInstr &MI) {
502  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
503  }
504 
505  bool isMIMG(uint16_t Opcode) const {
506  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
507  }
508 
509  static bool isGather4(const MachineInstr &MI) {
510  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
511  }
512 
513  bool isGather4(uint16_t Opcode) const {
514  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
515  }
516 
517  static bool isFLAT(const MachineInstr &MI) {
518  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
519  }
520 
521  // Is a FLAT encoded instruction which accesses a specific segment,
522  // i.e. global_* or scratch_*.
523  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
524  auto Flags = MI.getDesc().TSFlags;
526  }
527 
528  bool isSegmentSpecificFLAT(uint16_t Opcode) const {
529  auto Flags = get(Opcode).TSFlags;
531  }
532 
533  static bool isFLATGlobal(const MachineInstr &MI) {
534  return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
535  }
536 
537  bool isFLATGlobal(uint16_t Opcode) const {
538  return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
539  }
540 
541  static bool isFLATScratch(const MachineInstr &MI) {
542  return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
543  }
544 
545  bool isFLATScratch(uint16_t Opcode) const {
546  return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
547  }
548 
549  // Any FLAT encoded instruction, including global_* and scratch_*.
550  bool isFLAT(uint16_t Opcode) const {
551  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
552  }
553 
554  static bool isEXP(const MachineInstr &MI) {
555  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
556  }
557 
558  static bool isDualSourceBlendEXP(const MachineInstr &MI) {
559  if (!isEXP(MI))
560  return false;
561  unsigned Target = MI.getOperand(0).getImm();
564  }
565 
566  bool isEXP(uint16_t Opcode) const {
567  return get(Opcode).TSFlags & SIInstrFlags::EXP;
568  }
569 
570  static bool isAtomicNoRet(const MachineInstr &MI) {
571  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
572  }
573 
574  bool isAtomicNoRet(uint16_t Opcode) const {
575  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
576  }
577 
578  static bool isAtomicRet(const MachineInstr &MI) {
579  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
580  }
581 
582  bool isAtomicRet(uint16_t Opcode) const {
583  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
584  }
585 
586  static bool isAtomic(const MachineInstr &MI) {
587  return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
589  }
590 
591  bool isAtomic(uint16_t Opcode) const {
592  return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
594  }
595 
596  static bool isWQM(const MachineInstr &MI) {
597  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
598  }
599 
600  bool isWQM(uint16_t Opcode) const {
601  return get(Opcode).TSFlags & SIInstrFlags::WQM;
602  }
603 
604  static bool isDisableWQM(const MachineInstr &MI) {
605  return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
606  }
607 
608  bool isDisableWQM(uint16_t Opcode) const {
609  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
610  }
611 
612  static bool isVGPRSpill(const MachineInstr &MI) {
613  return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
614  }
615 
616  bool isVGPRSpill(uint16_t Opcode) const {
617  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
618  }
619 
620  static bool isSGPRSpill(const MachineInstr &MI) {
621  return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
622  }
623 
624  bool isSGPRSpill(uint16_t Opcode) const {
625  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
626  }
627 
628  static bool isDPP(const MachineInstr &MI) {
629  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
630  }
631 
632  bool isDPP(uint16_t Opcode) const {
633  return get(Opcode).TSFlags & SIInstrFlags::DPP;
634  }
635 
636  static bool isTRANS(const MachineInstr &MI) {
637  return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
638  }
639 
640  bool isTRANS(uint16_t Opcode) const {
641  return get(Opcode).TSFlags & SIInstrFlags::TRANS;
642  }
643 
644  static bool isVOP3P(const MachineInstr &MI) {
645  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
646  }
647 
648  bool isVOP3P(uint16_t Opcode) const {
649  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
650  }
651 
652  static bool isVINTRP(const MachineInstr &MI) {
653  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
654  }
655 
656  bool isVINTRP(uint16_t Opcode) const {
657  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
658  }
659 
660  static bool isMAI(const MachineInstr &MI) {
661  return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
662  }
663 
664  bool isMAI(uint16_t Opcode) const {
665  return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
666  }
667 
668  static bool isMFMA(const MachineInstr &MI) {
669  return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
670  MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
671  }
672 
673  static bool isDOT(const MachineInstr &MI) {
674  return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
675  }
676 
677  static bool isWMMA(const MachineInstr &MI) {
678  return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
679  }
680 
681  bool isWMMA(uint16_t Opcode) const {
682  return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
683  }
684 
685  bool isDOT(uint16_t Opcode) const {
686  return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
687  }
688 
689  static bool isLDSDIR(const MachineInstr &MI) {
690  return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
691  }
692 
693  bool isLDSDIR(uint16_t Opcode) const {
694  return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
695  }
696 
697  static bool isVINTERP(const MachineInstr &MI) {
698  return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
699  }
700 
701  bool isVINTERP(uint16_t Opcode) const {
702  return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
703  }
704 
705  static bool isScalarUnit(const MachineInstr &MI) {
706  return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
707  }
708 
709  static bool usesVM_CNT(const MachineInstr &MI) {
710  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
711  }
712 
713  static bool usesLGKM_CNT(const MachineInstr &MI) {
714  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
715  }
716 
717  static bool sopkIsZext(const MachineInstr &MI) {
718  return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
719  }
720 
721  bool sopkIsZext(uint16_t Opcode) const {
722  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
723  }
724 
725  /// \returns true if this is an s_store_dword* instruction. This is more
726  /// specific than isSMEM && mayStore.
727  static bool isScalarStore(const MachineInstr &MI) {
728  return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
729  }
730 
731  bool isScalarStore(uint16_t Opcode) const {
732  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
733  }
734 
735  static bool isFixedSize(const MachineInstr &MI) {
736  return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
737  }
738 
739  bool isFixedSize(uint16_t Opcode) const {
740  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
741  }
742 
743  static bool hasFPClamp(const MachineInstr &MI) {
744  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
745  }
746 
747  bool hasFPClamp(uint16_t Opcode) const {
748  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
749  }
750 
751  static bool hasIntClamp(const MachineInstr &MI) {
752  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
753  }
754 
756  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
760  return MI.getDesc().TSFlags & ClampFlags;
761  }
762 
763  static bool usesFPDPRounding(const MachineInstr &MI) {
764  return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
765  }
766 
767  bool usesFPDPRounding(uint16_t Opcode) const {
768  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
769  }
770 
771  static bool isFPAtomic(const MachineInstr &MI) {
772  return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
773  }
774 
775  bool isFPAtomic(uint16_t Opcode) const {
776  return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
777  }
778 
779  bool isVGPRCopy(const MachineInstr &MI) const {
780  assert(MI.isCopy());
781  Register Dest = MI.getOperand(0).getReg();
782  const MachineFunction &MF = *MI.getParent()->getParent();
783  const MachineRegisterInfo &MRI = MF.getRegInfo();
784  return !RI.isSGPRReg(MRI, Dest);
785  }
786 
787  bool hasVGPRUses(const MachineInstr &MI) const {
788  const MachineFunction &MF = *MI.getParent()->getParent();
789  const MachineRegisterInfo &MRI = MF.getRegInfo();
790  return llvm::any_of(MI.explicit_uses(),
791  [&MRI, this](const MachineOperand &MO) {
792  return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
793  }
794 
795  /// Return true if the instruction modifies the mode register.q
796  static bool modifiesModeRegister(const MachineInstr &MI);
797 
798  /// Whether we must prevent this instruction from executing with EXEC = 0.
800 
801  /// Returns true if the instruction could potentially depend on the value of
802  /// exec. If false, exec dependencies may safely be ignored.
803  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
804 
805  bool isInlineConstant(const APInt &Imm) const;
806 
807  bool isInlineConstant(const APFloat &Imm) const {
808  return isInlineConstant(Imm.bitcastToAPInt());
809  }
810 
811  // Returns true if this non-register operand definitely does not need to be
812  // encoded as a 32-bit literal. Note that this function handles all kinds of
813  // operands, not just immediates.
814  //
815  // Some operands like FrameIndexes could resolve to an inline immediate value
816  // that will not require an additional 4-bytes; this function assumes that it
817  // will.
818  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
819 
821  const MCOperandInfo &OpInfo) const {
822  return isInlineConstant(MO, OpInfo.OperandType);
823  }
824 
825  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
826  /// be an inline immediate.
828  const MachineOperand &UseMO,
829  const MachineOperand &DefMO) const {
830  assert(UseMO.getParent() == &MI);
831  int OpIdx = MI.getOperandNo(&UseMO);
832  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
833  return false;
834  }
835 
836  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
837  }
838 
839  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
840  /// immediate.
841  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
842  const MachineOperand &MO = MI.getOperand(OpIdx);
843  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
844  }
845 
846  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
847  const MachineOperand &MO) const {
848  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
849  return false;
850 
851  if (MI.isCopy()) {
852  unsigned Size = getOpSize(MI, OpIdx);
853  assert(Size == 8 || Size == 4);
854 
855  uint8_t OpType = (Size == 8) ?
857  return isInlineConstant(MO, OpType);
858  }
859 
860  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
861  }
862 
863  bool isInlineConstant(const MachineOperand &MO) const {
864  const MachineInstr *Parent = MO.getParent();
865  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
866  }
867 
868  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
869  const MachineOperand &MO) const;
870 
871  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
872  /// This function will return false if you pass it a 32-bit instruction.
873  bool hasVALU32BitEncoding(unsigned Opcode) const;
874 
875  /// Returns true if this operand uses the constant bus.
877  const MachineOperand &MO,
878  const MCOperandInfo &OpInfo) const;
879 
880  /// Return true if this instruction has any modifiers.
881  /// e.g. src[012]_mod, omod, clamp.
882  bool hasModifiers(unsigned Opcode) const;
883 
884  bool hasModifiersSet(const MachineInstr &MI,
885  unsigned OpName) const;
886  bool hasAnyModifiersSet(const MachineInstr &MI) const;
887 
888  bool canShrink(const MachineInstr &MI,
889  const MachineRegisterInfo &MRI) const;
890 
892  unsigned NewOpcode) const;
893 
894  bool verifyInstruction(const MachineInstr &MI,
895  StringRef &ErrInfo) const override;
896 
897  unsigned getVALUOp(const MachineInstr &MI) const;
898 
899  /// Return the correct register class for \p OpNo. For target-specific
900  /// instructions, this will return the register class that has been defined
901  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
902  /// the register class of its machine operand.
903  /// to infer the correct register class base on the other operands.
905  unsigned OpNo) const;
906 
907  /// Return the size in bytes of the operand OpNo on the given
908  // instruction opcode.
909  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
910  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
911 
912  if (OpInfo.RegClass == -1) {
913  // If this is an immediate operand, this must be a 32-bit literal.
915  return 4;
916  }
917 
918  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
919  }
920 
921  /// This form should usually be preferred since it handles operands
922  /// with unknown register classes.
923  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
924  const MachineOperand &MO = MI.getOperand(OpNo);
925  if (MO.isReg()) {
926  if (unsigned SubReg = MO.getSubReg()) {
927  return RI.getSubRegIdxSize(SubReg) / 8;
928  }
929  }
930  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
931  }
932 
933  /// Legalize the \p OpIndex operand of this instruction by inserting
934  /// a MOV. For example:
935  /// ADD_I32_e32 VGPR0, 15
936  /// to
937  /// MOV VGPR1, 15
938  /// ADD_I32_e32 VGPR0, VGPR1
939  ///
940  /// If the operand being legalized is a register, then a COPY will be used
941  /// instead of MOV.
942  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
943 
944  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
945  /// for \p MI.
946  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
947  const MachineOperand *MO = nullptr) const;
948 
949  /// Check if \p MO would be a valid operand for the given operand
950  /// definition \p OpInfo. Note this does not attempt to validate constant bus
951  /// restrictions (e.g. literal constant usage).
953  const MCOperandInfo &OpInfo,
954  const MachineOperand &MO) const;
955 
956  /// Check if \p MO (a register operand) is a legal register for the
957  /// given operand description.
959  const MCOperandInfo &OpInfo,
960  const MachineOperand &MO) const;
961 
962  /// Legalize operands in \p MI by either commuting it or inserting a
963  /// copy of src1.
965 
966  /// Fix operands in \p MI to satisfy constant bus requirements.
968 
969  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
970  /// be used when it is know that the value in SrcReg is same across all
971  /// threads in the wave.
972  /// \returns The SGPR register that \p SrcReg was copied to.
974  MachineRegisterInfo &MRI) const;
975 
978 
981  const TargetRegisterClass *DstRC,
983  const DebugLoc &DL) const;
984 
985  /// Legalize all operands in this instruction. This function may create new
986  /// instructions and control-flow around \p MI. If present, \p MDT is
987  /// updated.
988  /// \returns A new basic block that contains \p MI if new blocks were created.
990  legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
991 
992  /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
993  /// was moved to VGPR. \returns true if succeeded.
994  bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
995 
996  /// Replace this instruction's opcode with the equivalent VALU
997  /// opcode. This function will also move the users of \p MI to the
998  /// VALU if necessary. If present, \p MDT is updated.
1000  MachineDominatorTree *MDT = nullptr) const;
1001 
1003  MachineBasicBlock::iterator MI) const override;
1004 
1006  unsigned Quantity) const override;
1007 
1008  void insertReturn(MachineBasicBlock &MBB) const;
1009  /// Return the number of wait states that result from executing this
1010  /// instruction.
1011  static unsigned getNumWaitStates(const MachineInstr &MI);
1012 
1013  /// Returns the operand named \p Op. If \p MI does not have an
1014  /// operand named \c Op, this function returns nullptr.
1016  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1017 
1020  unsigned OpName) const {
1021  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1022  }
1023 
1024  /// Get required immediate operand
1025  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1026  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1027  return MI.getOperand(Idx).getImm();
1028  }
1029 
1032 
1033  bool isLowLatencyInstruction(const MachineInstr &MI) const;
1034  bool isHighLatencyDef(int Opc) const override;
1035 
1036  /// Return the descriptor of the target-specific machine instruction
1037  /// that corresponds to the specified pseudo or native opcode.
1038  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1039  return get(pseudoToMCOpcode(Opcode));
1040  }
1041 
1042  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1043  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1044 
1045  unsigned isLoadFromStackSlot(const MachineInstr &MI,
1046  int &FrameIndex) const override;
1047  unsigned isStoreToStackSlot(const MachineInstr &MI,
1048  int &FrameIndex) const override;
1049 
1050  unsigned getInstBundleSize(const MachineInstr &MI) const;
1051  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1052 
1053  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1054 
1055  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1056 
1058  MachineBasicBlock *IfEnd) const;
1059 
1061  MachineBasicBlock *LoopEnd) const;
1062 
1063  std::pair<unsigned, unsigned>
1064  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1065 
1067  getSerializableTargetIndices() const override;
1068 
1071 
1074 
1077  const ScheduleDAG *DAG) const override;
1078 
1080  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1081 
1084  const ScheduleDAGMI *DAG) const override;
1085 
1086  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1087 
1090  const DebugLoc &DL, Register Src,
1091  Register Dst) const override;
1092 
1095  const DebugLoc &DL, Register Src,
1096  unsigned SrcSubReg,
1097  Register Dst) const override;
1098 
1099  bool isWave32() const;
1100 
1101  /// Return a partially built integer add instruction without carry.
1102  /// Caller must add source operands.
1103  /// For pre-GFX9 it will generate unused carry destination operand.
1104  /// TODO: After GFX9 it should return a no-carry operation.
1107  const DebugLoc &DL,
1108  Register DestReg) const;
1109 
1112  const DebugLoc &DL,
1113  Register DestReg,
1114  RegScavenger &RS) const;
1115 
1116  static bool isKillTerminator(unsigned Opcode);
1117  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1118 
1119  static bool isLegalMUBUFImmOffset(unsigned Imm) {
1120  return isUInt<12>(Imm);
1121  }
1122 
1123  /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1124  /// encoded instruction. If \p Signed, this is for an instruction that
1125  /// interprets the offset as signed.
1126  bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1127  uint64_t FlatVariant) const;
1128 
1129  /// Split \p COffsetVal into {immediate offset field, remainder offset}
1130  /// values.
1131  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1132  unsigned AddrSpace,
1133  uint64_t FlatVariant) const;
1134 
1135  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1136  /// Return -1 if the target-specific opcode for the pseudo instruction does
1137  /// not exist. If Opcode is not a pseudo instruction, this is identity.
1138  int pseudoToMCOpcode(int Opcode) const;
1139 
1140  /// \brief Check if this instruction should only be used by assembler.
1141  /// Return true if this opcode should not be used by codegen.
1142  bool isAsmOnlyOpcode(int MCOp) const;
1143 
1144  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1145  const TargetRegisterInfo *TRI,
1146  const MachineFunction &MF)
1147  const override;
1148 
1149  void fixImplicitOperands(MachineInstr &MI) const;
1150 
1152  ArrayRef<unsigned> Ops,
1153  MachineBasicBlock::iterator InsertPt,
1154  int FrameIndex,
1155  LiveIntervals *LIS = nullptr,
1156  VirtRegMap *VRM = nullptr) const override;
1157 
1158  unsigned getInstrLatency(const InstrItineraryData *ItinData,
1159  const MachineInstr &MI,
1160  unsigned *PredCost = nullptr) const override;
1161 
1162  const MIRFormatter *getMIRFormatter() const override {
1163  if (!Formatter.get())
1164  Formatter = std::make_unique<AMDGPUMIRFormatter>();
1165  return Formatter.get();
1166  }
1167 
1168  static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1169 
1170  const TargetSchedModel &getSchedModel() const { return SchedModel; }
1171 
1172  // Enforce operand's \p OpName even alignment if required by target.
1173  // This is used if an operand is a 32 bit register but needs to be aligned
1174  // regardless.
1175  void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1176 };
1177 
1178 /// \brief Returns true if a reg:subreg pair P has a TRC class
1180  const TargetRegisterClass &TRC,
1182  auto *RC = MRI.getRegClass(P.Reg);
1183  if (!P.SubReg)
1184  return RC == &TRC;
1185  auto *TRI = MRI.getTargetRegisterInfo();
1186  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1187 }
1188 
1189 /// \brief Create RegSubRegPair from a register MachineOperand
1190 inline
1192  assert(O.isReg());
1193  return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1194 }
1195 
1196 /// \brief Return the SubReg component from REG_SEQUENCE
1198  unsigned SubReg);
1199 
1200 /// \brief Return the defining instruction for a given reg:subreg pair
1201 /// skipping copy like instructions and subreg-manipulation pseudos.
1202 /// Following another subreg of a reg:subreg isn't supported.
1204  MachineRegisterInfo &MRI);
1205 
1206 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1207 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1208 /// attempt to track between blocks.
1209 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1210  Register VReg,
1211  const MachineInstr &DefMI,
1212  const MachineInstr &UseMI);
1213 
1214 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1215 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1216 /// track between blocks.
1217 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1218  Register VReg,
1219  const MachineInstr &DefMI);
1220 
1221 namespace AMDGPU {
1222 
1224  int getVOPe64(uint16_t Opcode);
1225 
1227  int getVOPe32(uint16_t Opcode);
1228 
1230  int getSDWAOp(uint16_t Opcode);
1231 
1233  int getDPPOp32(uint16_t Opcode);
1234 
1236  int getDPPOp64(uint16_t Opcode);
1237 
1239  int getBasicFromSDWAOp(uint16_t Opcode);
1240 
1242  int getCommuteRev(uint16_t Opcode);
1243 
1245  int getCommuteOrig(uint16_t Opcode);
1246 
1248  int getAddr64Inst(uint16_t Opcode);
1249 
1250  /// Check if \p Opcode is an Addr64 opcode.
1251  ///
1252  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1254  int getIfAddr64Inst(uint16_t Opcode);
1255 
1257  int getAtomicNoRetOp(uint16_t Opcode);
1258 
1260  int getSOPKOp(uint16_t Opcode);
1261 
1262  /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1263  /// of a VADDR form.
1265  int getGlobalSaddrOp(uint16_t Opcode);
1266 
1267  /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1268  /// of a SADDR form.
1270  int getGlobalVaddrOp(uint16_t Opcode);
1271 
1273  int getVCMPXNoSDstOp(uint16_t Opcode);
1274 
1275  /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1276  /// given an \p Opcode of an SS (SADDR) form.
1279 
1280  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1281  /// of an SVS (SADDR + VADDR) form.
1284 
1285  /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1286  /// of an SV (VADDR) form.
1289 
1290  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1291  /// of an SS (SADDR) form.
1294 
1295  /// \returns earlyclobber version of a MAC MFMA is exists.
1297  int getMFMAEarlyClobberOp(uint16_t Opcode);
1298 
1299  /// \returns v_cmpx version of a v_cmp instruction.
1301  int getVCMPXOpFromVCMP(uint16_t Opcode);
1302 
1303  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1306  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1307 
1308 } // end namespace AMDGPU
1309 
1310 namespace SI {
1311 namespace KernelInputOffsets {
1312 
1313 /// Offsets in bytes from the start of the input buffer
1314 enum Offsets {
1324 };
1325 
1326 } // end namespace KernelInputOffsets
1327 } // end namespace SI
1328 
1329 } // end namespace llvm
1330 
1331 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:77
llvm::SIInstrInfo::isIgnorableUse
bool isIgnorableUse(const MachineOperand &MO) const override
Definition: SIInstrInfo.cpp:166
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
llvm::AMDGPU::getVCMPXNoSDstOp
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
llvm::SIInstrInfo::isMIMG
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:505
llvm::SIInstrInfo::isMTBUF
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:477
llvm::SIInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SIInstrInfo.cpp:2593
llvm::SIInstrInfo::isAtomicRet
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:578
llvm::SIInstrInfo::insertNoops
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
Definition: SIInstrInfo.cpp:1739
llvm::SIInstrInfo::isFLAT
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:550
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:196
llvm::SIInstrInfo::isDPP
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:632
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:706
llvm::SIInstrInfo::isFLATGlobal
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:537
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:102
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SIInstrInfo::insertNE
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1260
llvm::SIInstrInfo::isDisableWQM
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:608
llvm::SIInstrInfo::swapSourceModifiers
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
Definition: SIInstrInfo.cpp:2237
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::SIInstrInfo::hasFPClamp
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:743
llvm::MONoClobber
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:41
llvm::SIInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:3497
llvm::AMDGPU::getMFMAEarlyClobberOp
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
llvm::SIInstrInfo::isDualSourceBlendEXP
static bool isDualSourceBlendEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:558
llvm::AMDGPU::getFlatScratchInstSVfromSS
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
llvm::SIInstrInfo::isSGPRSpill
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:620
llvm::SIInstrInfo::isVINTERP
static bool isVINTERP(const MachineInstr &MI)
Definition: SIInstrInfo.h:697
llvm::SIInstrInfo::isSOP2
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:389
llvm::SIInstrInfo::isFixedSize
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:735
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2975
llvm::SIInstrInfo::isMAI
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:664
llvm::SIInstrInfo::materializeImmediate
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
Definition: SIInstrInfo.cpp:1060
llvm::SIInstrInfo::getClampMask
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:755
llvm::SIInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:108
llvm::getRegSubRegPair
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1191
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::AMDGPU::getAtomicNoRetOp
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
llvm::SIInstrInfo::usesLGKM_CNT
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:713
llvm::SIInstrInfo::usesVM_CNT
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:709
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SIInstrInfo::isVOP3
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:441
llvm::SIInstrInfo::hasVGPRUses
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:787
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y
@ GLOBAL_SIZE_Y
Definition: SIInstrInfo.h:1319
llvm::SIInstrInfo::getMovOpcode
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
Definition: SIInstrInfo.cpp:1273
llvm::SIInstrInfo::isSOPP
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:413
llvm::SIInstrInfo::isBufferSMRD
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7776
llvm::SIInstrInfo::getNumWaitStates
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
Definition: SIInstrInfo.cpp:1768
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::SIInstrInfo::MO_GOTPCREL32
@ MO_GOTPCREL32
Definition: SIInstrInfo.h:161
llvm::SIInstrInfo::isImmOperandLegal
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
Definition: SIInstrInfo.cpp:3738
llvm::SIInstrInfo::convertNonUniformLoopRegion
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
Definition: SIInstrInfo.cpp:7589
llvm::SIInstrInfo::isHighLatencyDef
bool isHighLatencyDef(int Opc) const override
Definition: SIInstrInfo.cpp:7419
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:114
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:45
llvm::SIInstrInfo::isDisableWQM
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:604
llvm::SIInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SIInstrInfo.cpp:2722
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SIInstrInfo::analyzeBranchImpl
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: SIInstrInfo.cpp:2550
llvm::SIInstrInfo::isScalarStore
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:727
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::SIInstrInfo::createPHIDestinationCopy
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
Definition: SIInstrInfo.cpp:8164
llvm::SIInstrInfo::isEXP
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:554
llvm::SIInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: SIInstrInfo.cpp:3268
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:35
llvm::SIInstrInfo::isFoldableCopy
static bool isFoldableCopy(const MachineInstr &MI)
Definition: SIInstrInfo.cpp:2885
llvm::SIInstrInfo::moveToVALU
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Definition: SIInstrInfo.cpp:6045
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::SIInstrInfo::modifiesModeRegister
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Definition: SIInstrInfo.cpp:3538
llvm::AMDGPU::getSOPKOp
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
llvm::SIInstrInfo::isSDWA
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:453
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::SIInstrInfo::isMUBUF
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:469
llvm::SIInstrInfo::isWMMA
bool isWMMA(uint16_t Opcode) const
Definition: SIInstrInfo.h:681
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:126
llvm::AMDGPU::getGlobalSaddrOp
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7459
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:78
TargetInstrInfo.h
llvm::SIInstrInfo::isVOP3P
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:644
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
llvm::SIInstrInfo::isAsmOnlyOpcode
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
Definition: SIInstrInfo.cpp:7913
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIInstrInfo::isVGPRSpill
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:612
llvm::SIInstrInfo::MO_MASK
@ MO_MASK
Definition: SIInstrInfo.h:155
llvm::SIInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
Definition: SIInstrInfo.cpp:7647
llvm::SIInstrInfo::getScratchRsrcWords23
uint64_t getScratchRsrcWords23() const
Definition: SIInstrInfo.cpp:7389
llvm::SIInstrInfo::MO_GOTPCREL
@ MO_GOTPCREL
Definition: SIInstrInfo.h:159
llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
Definition: SIInstrInfo.cpp:1389
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIInstrInfo::hasAnyModifiersSet
bool hasAnyModifiersSet(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:3793
llvm::SIInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: SIInstrInfo.cpp:2362
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SIInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: SIInstrInfo.cpp:1734
llvm::SIInstrInfo::isBasicBlockPrologue
bool isBasicBlockPrologue(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7703
llvm::SIInstrInfo::insertVectorSelect
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Definition: SIInstrInfo.cpp:1121
llvm::SIInstrInfo::isVOP1
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:429
llvm::SIInstrInfo::fixImplicitOperands
void fixImplicitOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7766
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:494
llvm::SIInstrInfo::isVOPC
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:461
llvm::AMDGPU::getVOPe64
LLVM_READONLY int getVOPe64(uint16_t Opcode)
llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
Definition: SIInstrInfo.cpp:3552
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:909
llvm::SIInstrInfo::isWave32
bool isWave32() const
Definition: SIInstrInfo.cpp:8199
llvm::SIInstrInfo::isWMMA
static bool isWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:677
llvm::SIInstrInfo::isVOPC
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:457
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::SIInstrInfo::canShrink
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: SIInstrInfo.cpp:3798
llvm::AMDGPU::getCommuteOrig
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::SIInstrInfo::hasDivergentBranch
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
Definition: SIInstrInfo.cpp:2389
llvm::SIInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SIInstrInfo.cpp:711
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:36
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:157
llvm::SIInstrInfo::MO_GOTPCREL32_LO
@ MO_GOTPCREL32_LO
Definition: SIInstrInfo.h:162
llvm::SIInstrInfo::isMIMG
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:501
llvm::SIInstrInfo::isSOPK
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:405
llvm::SIInstrInfo::isAtomicNoRet
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:574
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:120
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:79
llvm::SIInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7485
llvm::SIInstrFlags::IsWMMA
@ IsWMMA
Definition: SIDefines.h:132
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APInt &Imm) const
Definition: SIInstrInfo.cpp:3618
llvm::SIInstrFlags::LDSDIR
@ LDSDIR
Definition: SIDefines.h:67
llvm::SIInstrInfo::isSOPC
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:393
llvm::SIInstrInfo::getSchedModel
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1170
llvm::AMDGPU::getDPPOp64
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
llvm::SIInstrInfo::createPHISourceCopy
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Definition: SIInstrInfo.cpp:8179
llvm::SIInstrInfo::isNonUniformBranchInstr
bool isNonUniformBranchInstr(MachineInstr &Instr) const
Definition: SIInstrInfo.cpp:7560
llvm::SIInstrInfo::isMAI
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:660
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:81
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:95
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:50
llvm::SIInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:172
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::SIInstrInfo::isSOPK
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:401
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::AMDGPU::getFlatScratchInstSSfromSV
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIInstrInfo::isOperandLegal
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition: SIInstrInfo.cpp:4984
llvm::SIInstrInfo::hasIntClamp
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:751
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::AMDGPU::getDPPOp32
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
llvm::SIInstrFlags::VINTERP
@ VINTERP
Definition: SIDefines.h:70
llvm::AMDGPU::getVOPe32
LLVM_READONLY int getVOPe32(uint16_t Opcode)
AMDGPUMIRFormatter.h
llvm::SIInstrInfo::isVOP3
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:445
llvm::SIInstrInfo::isSegmentSpecificFLAT
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:528
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SIInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: SIInstrInfo.cpp:7634
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
OpName
Definition: R600Defines.h:62
llvm::SIInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: SIInstrInfo.cpp:7674
llvm::SIInstrInfo::isGather4
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:513
llvm::SIInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: SIInstrInfo.cpp:8238
llvm::SIInstrInfo::legalizeOperands
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
Definition: SIInstrInfo.cpp:5719
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:41
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:37
llvm::getVRegSubRegDef
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
Definition: SIInstrInfo.cpp:8040
llvm::SIInstrInfo::moveFlatAddrToVGPR
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
Definition: SIInstrInfo.cpp:5336
llvm::SIInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: SIInstrInfo.cpp:2339
llvm::SIInstrInfo::isVINTERP
bool isVINTERP(uint16_t Opcode) const
Definition: SIInstrInfo.h:701
llvm::SIInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
Definition: SIInstrInfo.cpp:2918
llvm::SIInstrInfo::sopkIsZext
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:717
llvm::SIInstrInfo::isVOP2
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:437
llvm::SIInstrInfo::getNamedOperand
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Definition: SIInstrInfo.cpp:7355
llvm::SIInstrInfo::hasModifiers
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
Definition: SIInstrInfo.cpp:3780
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::SIInstrInfo::isVOP3P
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:648
llvm::SIInstrInfo::isGather4
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:509
llvm::SIInstrInfo::MO_REL32
@ MO_REL32
Definition: SIInstrInfo.h:166
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::SIInstrInfo::legalizeGenericOperand
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
Definition: SIInstrInfo.cpp:5435
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:51
llvm::AMDGPU::getSDWAOp
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::SIInstrInfo::isScalarUnit
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:705
llvm::SIInstrInfo::MO_FAR_BRANCH_OFFSET
@ MO_FAR_BRANCH_OFFSET
Definition: SIInstrInfo.h:171
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0
@ ET_DUAL_SRC_BLEND0
Definition: SIDefines.h:868
llvm::SI::KernelInputOffsets::NGROUPS_Z
@ NGROUPS_Z
Definition: SIInstrInfo.h:1317
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SIInstrInfo::isVALU
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:365
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:129
llvm::SIInstrInfo::MO_ABS32_LO
@ MO_ABS32_LO
Definition: SIInstrInfo.h:173
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::SIInstrInfo::TargetOperandFlags
TargetOperandFlags
Definition: SIInstrInfo.h:154
llvm::SIInstrInfo::getAddNoCarry
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
Definition: SIInstrInfo.cpp:7709
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:99
llvm::SIInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7445
llvm::SIInstrInfo::removeModOperands
void removeModOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2909
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:807
llvm::SIInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7679
llvm::AMDGPU::getFlatScratchInstSVfromSVS
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
llvm::APFloat
Definition: APFloat.h:716
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:923
llvm::SIInstrInfo::MO_ABS32_HI
@ MO_ABS32_HI
Definition: SIInstrInfo.h:174
llvm::SIInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SIInstrInfo.cpp:2778
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::SIInstrInfo::isDPP
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:628
llvm::SIInstrInfo::isWQM
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:600
llvm::SIInstrInfo::isLowLatencyInstruction
bool isLowLatencyInstruction(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7413
TargetSchedule.h
llvm::SIInstrInfo::hasVALU32BitEncoding
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
Definition: SIInstrInfo.cpp:3768
AMDGPUMCTargetDesc.h
llvm::SIInstrInfo::getNamedImmOperand
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1025
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:117
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::execMayBeModifiedBeforeAnyUse
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
Definition: SIInstrInfo.cpp:8108
uint64_t
llvm::SIInstrInfo::hasFPClamp
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:747
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:80
llvm::SI::KernelInputOffsets::LOCAL_SIZE_X
@ LOCAL_SIZE_X
Definition: SIInstrInfo.h:1321
llvm::SIInstrInfo::getMIRFormatter
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1162
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:92
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:89
llvm::SIInstrInfo::buildExtractSubReg
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4885
llvm::SIInstrInfo::sopkIsZext
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:721
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:541
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1
@ ET_DUAL_SRC_BLEND1
Definition: SIDefines.h:869
llvm::SIInstrInfo::isDS
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:491
llvm::SIInstrInfo::isDS
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:495
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2712
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:481
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::execMayBeModifiedBeforeUse
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
Definition: SIInstrInfo.cpp:8075
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIInstrInfo::isLegalFLATOffset
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
Definition: SIInstrInfo.cpp:7819
llvm::SIInstrInfo::legalizeOperandsFLAT
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5417
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:57
llvm::SIInstrInfo::enforceOperandRCAlignment
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:8483
llvm::SIInstrInfo::isSOP2
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:385
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::SIInstrInfo::isScalarStore
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:731
llvm::SIInstrInfo::isMFMA
static bool isMFMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:668
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:100
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInstrInfo::MO_REL32_LO
@ MO_REL32_LO
Definition: SIInstrInfo.h:167
llvm::SIInstrInfo::isAlwaysGDS
bool isAlwaysGDS(uint16_t Opcode) const
Definition: SIInstrInfo.cpp:3528
llvm::SIInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:2378
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:841
llvm::SIInstrInfo::isVMEM
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:373
llvm::SIInstrInfo::isFPAtomic
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:771
llvm::SIInstrInfo::isSGPRSpill
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:624
llvm::SIInstrInfo::isPacked
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:417
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:34
llvm::SIInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1681
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:586
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:29
llvm::SIInstrInfo::isSOP1
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:377
llvm::SIInstrInfo::isSALU
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:353
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SIInstrInfo::insertReturn
void insertReturn(MachineBasicBlock &MBB) const
Definition: SIInstrInfo.cpp:1750
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::SIInstrInfo::mayAccessFlatAddressSpace
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7546
llvm::SIInstrInfo::isVOP1
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:425
llvm::SI::KernelInputOffsets::NGROUPS_Y
@ NGROUPS_Y
Definition: SIInstrInfo.h:1316
llvm::AMDGPU::RSRC_DATA_FORMAT
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1303
llvm::SIInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Definition: SIInstrInfo.cpp:481
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SIInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SIInstrInfo.cpp:2662
llvm::SIInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
Definition: SIInstrInfo.cpp:2736
llvm::SIInstrInfo::MO_REL32_HI
@ MO_REL32_HI
Definition: SIInstrInfo.h:169
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1716
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::SIInstrInfo::usesConstantBus
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
Definition: SIInstrInfo.cpp:3914
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:111
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::SIInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3994
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:820
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
llvm::SIInstrInfo::isFixedSize
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:739
llvm::SIInstrInfo::isSDWA
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:449
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:40
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIInstrInfo::isSALU
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:357
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:64
llvm::SIInstrInfo::isVOP2
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:433
llvm::SIInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Definition: SIInstrInfo.cpp:8336
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:263
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:75
AMDGPUGenInstrInfo
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:465
llvm::SIInstrInfo::isAtomic
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:591
llvm::SIInstrInfo::isDOT
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:673
llvm::SIInstrInfo::isVINTRP
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:656
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::SIInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
Definition: SIInstrInfo.cpp:2287
llvm::SIInstrInfo::CreateTargetMIHazardRecognizer
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
Definition: SIInstrInfo.cpp:7662
llvm::SIInstrInfo::isKillTerminator
static bool isKillTerminator(unsigned Opcode)
Definition: SIInstrInfo.cpp:7745
llvm::AMDGPU::getCommuteRev
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1119
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:108
llvm::SIInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:1782
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SIInstrInfo::legalizeOpWithMove
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
Definition: SIInstrInfo.cpp:4858
llvm::SIInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
Definition: SIInstrInfo.cpp:294
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:63
llvm::SIInstrInfo::isTRANS
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:640
llvm::SIInstrInfo::splitFlatOffset
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition: SIInstrInfo.cpp:7846
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:123
llvm::SIInstrInfo::convertNonUniformIfRegion
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
Definition: SIInstrInfo.cpp:7564
llvm::SIInstrInfo::isVGPRSpill
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:616
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:48
llvm::SIInstrInfo::getMCOpcodeFromPseudo
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1038
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SIInstrInfo::isAtomicNoRet
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:570
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::SIInstrInfo::legalizeOperandsVOP2
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition: SIInstrInfo.cpp:5078
llvm::SIInstrInfo::getMachineCSELookAheadLimit
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:344
llvm::SIInstrInfo::isSegmentSpecificFLAT
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:523
llvm::ARMII::VecSize
@ VecSize
Definition: ARMBaseInfo.h:421
llvm::AMDGPU::getAddr64Inst
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
llvm::SIInstrInfo::getVALUOp
unsigned getVALUOp(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4694
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:369
llvm::getRegSequenceSubReg
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
Definition: SIInstrInfo.cpp:8003
llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SIInstrInfo.cpp:3183
llvm::SIInstrInfo::expandMovDPP64
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2174
llvm::SIInstrInfo::buildExtractSubRegOrImm
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4917
llvm::AMDGPU::getIfAddr64Inst
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
llvm::SIInstrInfo::isStackAccess
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7424
llvm::SIInstrInfo::getRegisterInfo
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:179
llvm::SIInstrInfo::getPreferredSelectRegClass
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
Definition: SIInstrInfo.cpp:1117
llvm::SIInstrInfo::isMTBUF
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:473
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::SIInstrInfo::isLDSDIR
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:693
llvm::SIInstrInfo::isSMRD
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:485
llvm::SIInstrInfo::buildShrunkInst
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
Definition: SIInstrInfo.cpp:3868
llvm::SIInstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7694
llvm::SIInstrInfo::isFLATScratch
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:545
llvm::SIInstrInfo::getDSShaderTypeValue
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
Definition: SIInstrInfo.cpp:8255
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y
@ LOCAL_SIZE_Y
Definition: SIInstrInfo.h:1322
llvm::SIInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SIInstrInfo.cpp:8201
llvm::SIInstrInfo::SIInstrInfo
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:64
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::SIInstrInfo::isDOT
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:685
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::AMDGPU::RSRC_TID_ENABLE
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1306
llvm::SIInstrInfo::usesFPDPRounding
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:767
llvm::SIInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SIInstrInfo.cpp:2636
llvm::SIInstrInfo::legalizeOperandsSMRD
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5317
llvm::SI::KernelInputOffsets::NGROUPS_X
@ NGROUPS_X
Definition: SIInstrInfo.h:1315
llvm::SIInstrInfo::getDefaultRsrcDataFormat
uint64_t getDefaultRsrcDataFormat() const
Definition: SIInstrInfo.cpp:7364
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(unsigned Opc) const
Definition: SIInstrInfo.cpp:1042
llvm::AMDGPU::getBasicFromSDWAOp
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:863
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
llvm::SIInstrInfo::isSOPP
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:409
llvm::SIInstrInfo::isLegalRegOperand
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
Definition: SIInstrInfo.cpp:4946
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z
@ GLOBAL_SIZE_Z
Definition: SIInstrInfo.h:1320
llvm::SIInstrInfo::usesFPDPRounding
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:763
llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1305
llvm::SIInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
Definition: SIInstrInfo.cpp:524
llvm::SIInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: SIInstrInfo.cpp:2399
llvm::SIInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
Definition: SIInstrInfo.cpp:8277
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:33
llvm::SIInstrInfo::isFLATGlobal
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:533
llvm::SIInstrInfo::MO_GOTPCREL32_HI
@ MO_GOTPCREL32_HI
Definition: SIInstrInfo.h:164
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z
@ LOCAL_SIZE_Z
Definition: SIInstrInfo.h:1323
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:361
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::SIInstrInfo::isFPAtomic
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:775
llvm::SIInstrInfo::isWQM
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:596
llvm::SIInstrInfo::getNamedOperand
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1019
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:154
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X
@ GLOBAL_SIZE_X
Definition: SIInstrInfo.h:1318
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:73
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:82
llvm::SIInstrInfo::isLegalVSrcOperand
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
Definition: SIInstrInfo.cpp:4973
llvm::SIInstrInfo::getOpRegClass
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Definition: SIInstrInfo.cpp:4841
llvm::SIInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1514
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::SIInstrInfo::readlaneVGPRToSGPR
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
Definition: SIInstrInfo.cpp:5275
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::SIInstrInfo::isVGPRCopy
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:779
llvm::SIInstrInfo::isSGPRStackAccess
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7437
llvm::SIInstrInfo::isEXP
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:566
llvm::SIInstrInfo::isTRANS
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:636
llvm::SIInstrInfo::isAtomicRet
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:582
llvm::SIInstrInfo::getSubtarget
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:183
llvm::SIInstrInfo::isPacked
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:421
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:517
llvm::SIInstrInfo::insertEQ
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1247
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1304
llvm::SIInstrInfo::isLDSDIR
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:689
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:49
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1314
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:846
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::isOfRegClass
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1179
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIInstrInfo::getRegClass
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:4811
llvm::SIInstrInfo::hasModifiersSet
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:3787
llvm::SIInstrInfo::mayReadEXEC
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
Definition: SIInstrInfo.cpp:3593
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SIInstrInfo::getKillTerminatorFromPseudo
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Definition: SIInstrInfo.cpp:7755
SIRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SIInstrInfo::isSOPC
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:397
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:155
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIInstrInfo::getIndirectGPRIDXPseudo
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
Definition: SIInstrInfo.cpp:1288
llvm::AMDGPU::getVCMPXOpFromVCMP
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
llvm::SIInstrInfo::pseudoToMCOpcode
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Definition: SIInstrInfo.cpp:7933
llvm::AMDGPU::getGlobalVaddrOp
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isVINTRP
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:652
llvm::SIInstrInfo::isSOP1
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:381
llvm::SIInstrInfo::legalizeOperandsVOP3
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Definition: SIInstrInfo.cpp:5189
SetVector.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
AMDGPUBaseInfo.h
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:827
llvm::SIInstrInfo::getInstBundleSize
unsigned getInstBundleSize(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7473