14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
25#define GET_INSTRINFO_HEADER
26#include "AMDGPUGenInstrInfo.inc"
33class MachineDominatorTree;
34class MachineRegisterInfo;
36class TargetRegisterClass;
37class ScheduleHazardRecognizer;
55 auto iter = InstrList.begin();
60 auto iter = InstrList.begin();
61 InstrList.erase(iter);
64 bool empty()
const {
return InstrList.empty(); }
88 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
91 enum BranchPredicate {
103 static unsigned getBranchOpcode(BranchPredicate
Cond);
104 static BranchPredicate getBranchPredicate(
unsigned Opcode);
121 std::pair<bool, MachineBasicBlock *>
133 unsigned Opcode)
const;
136 unsigned Opcode)
const;
139 unsigned Opcode,
bool Swap =
false)
const;
174 getDestEquivalentVGPRClass(
const MachineInstr &Inst)
const;
176 bool checkInstOffsetsDoNotOverlap(
const MachineInstr &MIa,
185 std::optional<DestSourcePair>
194 unsigned OpIdx1)
const override;
238 int64_t &Offset1)
const override;
247 int64_t Offset1,
bool OffsetIsScalable1,
249 int64_t Offset2,
bool OffsetIsScalable2,
250 unsigned ClusterSize,
251 unsigned NumBytes)
const override;
254 int64_t Offset1,
unsigned NumLoads)
const override;
258 bool KillSrc)
const override;
265 unsigned Size)
const;
277 bool isKill,
int FrameIndex,
300 std::pair<MachineInstr*, MachineInstr*>
313 bool IsIndirectSrc)
const;
323 unsigned &SrcOpIdx1)
const override;
326 unsigned &SrcOpIdx1)
const;
329 int64_t BrOffset)
const override;
347 bool AllowModify)
const;
352 bool AllowModify =
false)
const override;
355 int *BytesRemoved =
nullptr)
const override;
360 int *BytesAdded =
nullptr)
const override;
368 int &TrueCycles,
int &FalseCycles)
const override;
381 Register &SrcReg2, int64_t &CmpMask,
382 int64_t &CmpValue)
const override;
385 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
619 auto Flags =
MI.getDesc().TSFlags;
624 auto Flags =
get(Opcode).TSFlags;
656 unsigned Target =
MI.getOperand(0).getImm();
692 return isLDSDMA(
MI) &&
MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
717 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
718 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
723 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
724 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
729 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
730 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
735 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
736 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
749 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
750 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
751 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
752 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
756 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
757 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
801 return isMAI(
MI) &&
MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
802 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
864 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
865 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
866 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
867 Opcode == AMDGPU::S_GETREG_B32;
905 return MI.getDesc().TSFlags & ClampFlags;
932 return Opcode == AMDGPU::S_BARRIER ||
933 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
934 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
935 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
936 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
940 return isBarrierStart(Opcode) || Opcode == AMDGPU::S_BARRIER_WAIT ||
941 Opcode == AMDGPU::S_BARRIER_INIT_M0 ||
942 Opcode == AMDGPU::S_BARRIER_INIT_IMM ||
943 Opcode == AMDGPU::S_BARRIER_JOIN_IMM ||
944 Opcode == AMDGPU::S_BARRIER_LEAVE ||
945 Opcode == AMDGPU::DS_GWS_INIT ||
946 Opcode == AMDGPU::DS_GWS_BARRIER;
959 case AMDGPU::S_WAITCNT_soft:
960 return AMDGPU::S_WAITCNT;
961 case AMDGPU::S_WAITCNT_VSCNT_soft:
962 return AMDGPU::S_WAITCNT_VSCNT;
963 case AMDGPU::S_WAIT_LOADCNT_soft:
964 return AMDGPU::S_WAIT_LOADCNT;
965 case AMDGPU::S_WAIT_STORECNT_soft:
966 return AMDGPU::S_WAIT_STORECNT;
967 case AMDGPU::S_WAIT_SAMPLECNT_soft:
968 return AMDGPU::S_WAIT_SAMPLECNT;
969 case AMDGPU::S_WAIT_BVHCNT_soft:
970 return AMDGPU::S_WAIT_BVHCNT;
971 case AMDGPU::S_WAIT_DSCNT_soft:
972 return AMDGPU::S_WAIT_DSCNT;
973 case AMDGPU::S_WAIT_KMCNT_soft:
974 return AMDGPU::S_WAIT_KMCNT;
982 case AMDGPU::S_WAITCNT:
983 case AMDGPU::S_WAITCNT_VSCNT:
984 case AMDGPU::S_WAITCNT_VMCNT:
985 case AMDGPU::S_WAITCNT_EXPCNT:
986 case AMDGPU::S_WAITCNT_LGKMCNT:
987 case AMDGPU::S_WAIT_LOADCNT:
988 case AMDGPU::S_WAIT_LOADCNT_DSCNT:
989 case AMDGPU::S_WAIT_STORECNT:
990 case AMDGPU::S_WAIT_STORECNT_DSCNT:
991 case AMDGPU::S_WAIT_SAMPLECNT:
992 case AMDGPU::S_WAIT_BVHCNT:
993 case AMDGPU::S_WAIT_EXPCNT:
994 case AMDGPU::S_WAIT_DSCNT:
995 case AMDGPU::S_WAIT_KMCNT:
996 case AMDGPU::S_WAIT_IDLE:
1016 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
1060 if (OpIdx >=
MI.getDesc().NumOperands)
1075 if (OpIdx >=
MI.getDesc().NumOperands)
1078 if (isCopyInstr(
MI)) {
1082 uint8_t OpType = (
Size == 8) ?
1118 unsigned NewOpcode)
const;
1140 unsigned OpNo)
const;
1162 return RI.getSubRegIdxSize(
SubReg) / 8;
1244 unsigned Quantity)
const override;
1274 return MI.getOperand(
Idx).getImm();
1293 int &FrameIndex)
const override;
1295 int &FrameIndex)
const override;
1310 std::pair<unsigned, unsigned>
1417 unsigned *PredCost =
nullptr)
const override;
1427 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1428 return Formatter.get();
1445 auto *RC =
MRI.getRegClass(
P.Reg);
1448 auto *
TRI =
MRI.getTargetRegisterInfo();
1449 return RC ==
TRI->getMatchingSuperRegClass(RC, &TRC,
P.SubReg);
1467 MachineRegisterInfo &
MRI);
1474 const MachineInstr &
DefMI,
1475 const MachineInstr &
UseMI);
1482 const MachineInstr &
DefMI);
1578namespace KernelInputOffsets {
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Provides AMDGPU specific target descriptions.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
StandardInstrumentations SI(Mod->getContext(), Debug, VerifyEach)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file implements a set that has insertion order iteration characteristics.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
Itinerary data supplied by a subtarget to be used by a target.
Describe properties that are true of each instruction in the target description file.
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Wrapper class representing physical registers. Should be passed by value.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Represents one node in the SelectionDAG.
bool isLegalMUBUFImmOffset(unsigned Imm) const
bool isFLATGlobal(uint16_t Opcode) const
bool isInlineConstant(const APInt &Imm) const
static bool isMAI(const MachineInstr &MI)
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
static bool isDS(const MachineInstr &MI)
static bool isVMEM(const MachineInstr &MI)
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override
bool isNonUniformBranchInstr(MachineInstr &Instr) const
static bool isVOP3(const MachineInstr &MI)
unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const override
bool isSMRD(uint16_t Opcode) const
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const final
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
static bool isNeverUniform(const MachineInstr &MI)
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
bool isAtomic(uint16_t Opcode) const
bool isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const override
bool isLDSDIR(uint16_t Opcode) const
bool isFLATScratch(uint16_t Opcode) const
uint64_t getDefaultRsrcDataFormat() const
static bool isSOPP(const MachineInstr &MI)
InstructionUniformity getGenericInstructionUniformity(const MachineInstr &MI) const
bool hasVGPRUses(const MachineInstr &MI) const
uint64_t getClampMask(const MachineInstr &MI) const
static bool isFLATScratch(const MachineInstr &MI)
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
static bool isSpill(const MachineInstr &MI)
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, Align Alignment=Align(4)) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const
Replace the instructions opcode with the equivalent VALU opcode.
static bool isSMRD(const MachineInstr &MI)
void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, SlotIndexes *Indexes=nullptr) const
bool isVGPRSpill(uint16_t Opcode) const
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST)
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool isSegmentSpecificFLAT(uint16_t Opcode) const
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
bool isVSAMPLE(uint16_t Opcode) const
bool isPacked(uint16_t Opcode) const
static bool isMTBUF(const MachineInstr &MI)
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
void insertReturn(MachineBasicBlock &MBB) const
static bool isEXP(const MachineInstr &MI)
static bool isSALU(const MachineInstr &MI)
bool isVIMAGE(uint16_t Opcode) const
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isVOP2(const MachineInstr &MI)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isSDWA(const MachineInstr &MI)
bool isSOP1(uint16_t Opcode) const
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
static bool mayWriteLDSThroughDMA(const MachineInstr &MI)
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
static bool isVINTRP(const MachineInstr &MI)
bool isSWMMAC(uint16_t Opcode) const
bool isAtomicRet(uint16_t Opcode) const
static bool isGather4(const MachineInstr &MI)
static bool isMFMAorWMMA(const MachineInstr &MI)
static bool isWQM(const MachineInstr &MI)
static bool doesNotReadTiedSource(const MachineInstr &MI)
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
bool isSOPC(uint16_t Opcode) const
static bool isDOT(const MachineInstr &MI)
static bool usesFPDPRounding(const MachineInstr &MI)
bool isFixedSize(uint16_t Opcode) const
bool isImage(uint16_t Opcode) const
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
bool isGWS(uint16_t Opcode) const
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isInlineConstant(const MachineOperand &MO) const
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isVOP3(uint16_t Opcode) const
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
static bool isSWMMAC(const MachineInstr &MI)
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
bool isDOT(uint16_t Opcode) const
bool isHighLatencyDef(int Opc) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVOPC(const MachineInstr &MI)
void removeModOperands(MachineInstr &MI) const
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
bool isGather4(uint16_t Opcode) const
bool isSpill(uint16_t Opcode) const
bool isFLAT(uint16_t Opcode) const
static bool isVIMAGE(const MachineInstr &MI)
static bool isLDSDIR(const MachineInstr &MI)
static bool isSOP2(const MachineInstr &MI)
static bool isGWS(const MachineInstr &MI)
const TargetSchedModel & getSchedModel() const
bool isVOPC(uint16_t Opcode) const
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MIRFormatter * getMIRFormatter() const override
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool isMAI(uint16_t Opcode) const
static bool isFLATGlobal(const MachineInstr &MI)
unsigned getMachineCSELookAheadLimit() const override
static bool isVSAMPLE(const MachineInstr &MI)
static bool isAtomicRet(const MachineInstr &MI)
bool isBufferSMRD(const MachineInstr &MI) const
static bool isKillTerminator(unsigned Opcode)
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override
const GCNSubtarget & getSubtarget() const
bool isDS(uint16_t Opcode) const
void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, bool IsSCCLive, SlotIndexes *Indexes=nullptr) const
bool isFPAtomic(uint16_t Opcode) const
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isDisableWQM(const MachineInstr &MI)
bool isAtomicNoRet(uint16_t Opcode) const
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
static bool isTRANS(const MachineInstr &MI)
static bool isImage(const MachineInstr &MI)
static bool isSOPK(const MachineInstr &MI)
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
MachineBasicBlock * insertSimulatedTrap(MachineRegisterInfo &MRI, MachineBasicBlock &MBB, MachineInstr &MI, const DebugLoc &DL) const
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely,...
static unsigned getNonSoftWaitcntOpcode(unsigned Opcode)
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
static bool isFoldableCopy(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isIgnorableUse(const MachineOperand &MO) const override
static bool isVINTERP(const MachineInstr &MI)
static bool isMUBUF(const MachineInstr &MI)
bool expandPostRAPseudo(MachineInstr &MI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool isSALU(uint16_t Opcode) const
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
bool isVOP2(uint16_t Opcode) const
static bool hasFPClamp(const MachineInstr &MI)
InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const override final
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
bool isSDWA(uint16_t Opcode) const
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
bool isSOPK(uint16_t Opcode) const
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isChainCallOpcode(uint64_t Opcode)
static bool isDPP(const MachineInstr &MI)
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isMFMA(const MachineInstr &MI)
bool isSGPRSpill(uint16_t Opcode) const
bool isLowLatencyInstruction(const MachineInstr &MI) const
static bool isScalarStore(const MachineInstr &MI)
bool isTRANS(uint16_t Opcode) const
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
bool isLDSDMA(uint16_t Opcode)
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
bool isSOP2(uint16_t Opcode) const
bool isVALU(uint16_t Opcode) const
bool isVOP1(uint16_t Opcode) const
bool isAlwaysGDS(uint16_t Opcode) const
bool isMUBUF(uint16_t Opcode) const
static bool isFPAtomic(const MachineInstr &MI)
static bool usesLGKM_CNT(const MachineInstr &MI)
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT, MachineInstr &Inst) const
static bool isPacked(const MachineInstr &MI)
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
bool isWMMA(uint16_t Opcode) const
bool isMTBUF(uint16_t Opcode) const
bool isDisableWQM(uint16_t Opcode) const
static bool isVGPRSpill(const MachineInstr &MI)
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
bool isWaitcnt(unsigned Opcode) const
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
static bool isWWMRegSpillOpcode(uint16_t Opcode)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVMEM(uint16_t Opcode) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isVINTRP(uint16_t Opcode) const
bool isVGPRCopy(const MachineInstr &MI) const
bool isScalarStore(uint16_t Opcode) const
static bool isMIMG(const MachineInstr &MI)
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
bool allowNegativeFlatOffset(uint64_t FlatVariant) const
Returns true if negative offsets are allowed for the given FlatVariant.
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
static bool isVOP3P(const MachineInstr &MI)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isWQM(uint16_t Opcode) const
unsigned getVALUOp(const MachineInstr &MI) const
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void fixImplicitOperands(MachineInstr &MI) const
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
bool isVOP3P(uint16_t Opcode) const
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
bool isEXP(uint16_t Opcode) const
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
static bool isDualSourceBlendEXP(const MachineInstr &MI)
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
This function is used to determine if an instruction can be safely executed under EXEC = 0 without ha...
static bool isAtomic(const MachineInstr &MI)
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
static bool sopkIsZext(unsigned Opcode)
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
static bool isSGPRSpill(const MachineInstr &MI)
static bool isWMMA(const MachineInstr &MI)
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
bool isVINTERP(uint16_t Opcode) const
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool doesNotReadTiedSource(uint16_t Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isDPP(uint16_t Opcode) const
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
static bool isSOP1(const MachineInstr &MI)
static bool isSOPC(const MachineInstr &MI)
static bool isFLAT(const MachineInstr &MI)
const SIRegisterInfo & getRegisterInfo() const
static bool isVALU(const MachineInstr &MI)
bool isBarrier(unsigned Opcode) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
static bool hasIntClamp(const MachineInstr &MI)
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
static bool isScalarUnit(const MachineInstr &MI)
bool isSOPP(uint16_t Opcode) const
bool isMIMG(uint16_t Opcode) const
bool hasFPClamp(uint16_t Opcode) const
static bool usesVM_CNT(const MachineInstr &MI)
bool usesFPDPRounding(uint16_t Opcode) const
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
static bool isFixedSize(const MachineInstr &MI)
bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const override
LLVM_READONLY int commuteOpcode(unsigned Opc) const
uint64_t getScratchRsrcWords23() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isBarrierStart(unsigned Opcode) const
static bool isLDSDMA(const MachineInstr &MI)
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static bool isAtomicNoRet(const MachineInstr &MI)
static bool isVOP1(const MachineInstr &MI)
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool hasAnyModifiersSet(const MachineInstr &MI) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A vector that has set insertion semantics.
A SetVector that performs no allocations if smaller than a certain size.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
Target - Wrapper for Target specific information.
LLVM Value Representation.
const uint64_t RSRC_DATA_FORMAT
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
This is an optimization pass for GlobalISel generic memory operations.
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
static const MachineMemOperand::Flags MOLastUse
Mark the MMO of a load as the last use.
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
Utility to store machine instructions worklist.
MachineInstr * top() const
SIInstrWorklist()=default
bool isDeferred(MachineInstr *MI)
SetVector< MachineInstr * > & getDeferredList()
void insert(MachineInstr *MI)
A pair composed of a register and a sub-register index.