LLVM  15.0.0git
SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 /// Mark the MMO of a uniform load if there are no potentially clobbering stores
39 /// on any path from the start of an entry function to this load.
42 
43 class SIInstrInfo final : public AMDGPUGenInstrInfo {
44 private:
45  const SIRegisterInfo RI;
46  const GCNSubtarget &ST;
47  TargetSchedModel SchedModel;
48  mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
49 
50  // The inverse predicate should have the negative value.
51  enum BranchPredicate {
52  INVALID_BR = 0,
53  SCC_TRUE = 1,
54  SCC_FALSE = -1,
55  VCCNZ = 2,
56  VCCZ = -2,
57  EXECNZ = -3,
58  EXECZ = 3
59  };
60 
62 
63  static unsigned getBranchOpcode(BranchPredicate Cond);
64  static BranchPredicate getBranchPredicate(unsigned Opcode);
65 
66 public:
69  MachineOperand &SuperReg,
70  const TargetRegisterClass *SuperRC,
71  unsigned SubIdx,
72  const TargetRegisterClass *SubRC) const;
75  MachineOperand &SuperReg,
76  const TargetRegisterClass *SuperRC,
77  unsigned SubIdx,
78  const TargetRegisterClass *SubRC) const;
79 private:
80  void swapOperands(MachineInstr &Inst) const;
81 
82  std::pair<bool, MachineBasicBlock *>
83  moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
84  MachineDominatorTree *MDT = nullptr) const;
85 
86  void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
87  MachineDominatorTree *MDT = nullptr) const;
88 
89  void lowerScalarAbs(SetVectorType &Worklist,
90  MachineInstr &Inst) const;
91 
92  void lowerScalarXnor(SetVectorType &Worklist,
93  MachineInstr &Inst) const;
94 
95  void splitScalarNotBinop(SetVectorType &Worklist,
96  MachineInstr &Inst,
97  unsigned Opcode) const;
98 
99  void splitScalarBinOpN2(SetVectorType &Worklist,
100  MachineInstr &Inst,
101  unsigned Opcode) const;
102 
103  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
104  MachineInstr &Inst, unsigned Opcode,
105  bool Swap = false) const;
106 
107  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
108  MachineDominatorTree *MDT = nullptr) const;
109 
110  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
111  unsigned Opcode,
112  MachineDominatorTree *MDT = nullptr) const;
113 
114  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
115  MachineDominatorTree *MDT = nullptr) const;
116 
117  void splitScalar64BitBCNT(SetVectorType &Worklist,
118  MachineInstr &Inst) const;
119  void splitScalar64BitBFE(SetVectorType &Worklist,
120  MachineInstr &Inst) const;
121  void movePackToVALU(SetVectorType &Worklist,
123  MachineInstr &Inst) const;
124 
125  void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
126  SetVectorType &Worklist) const;
127 
128  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
129  MachineInstr &SCCDefInst,
130  SetVectorType &Worklist,
131  Register NewCond = Register()) const;
132  void addSCCDefsToVALUWorklist(MachineOperand &Op,
133  SetVectorType &Worklist) const;
134 
135  const TargetRegisterClass *
136  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
137 
138  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
139  const MachineInstr &MIb) const;
140 
141  Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
142 
143 protected:
145  MachineOperand &Src0, unsigned Src0OpName,
146  MachineOperand &Src1, unsigned Src1OpName) const;
147 
149  unsigned OpIdx0,
150  unsigned OpIdx1) const override;
151 
152 public:
154  MO_MASK = 0xf,
155 
156  MO_NONE = 0,
157  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
159  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
162  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
164  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
165  MO_REL32 = 4,
167  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
169 
171 
174  };
175 
176  explicit SIInstrInfo(const GCNSubtarget &ST);
177 
179  return RI;
180  }
181 
182  const GCNSubtarget &getSubtarget() const {
183  return ST;
184  }
185 
187  AAResults *AA) const override;
188 
189  bool isIgnorableUse(const MachineOperand &MO) const override;
190 
191  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
192  int64_t &Offset1,
193  int64_t &Offset2) const override;
194 
196  const MachineInstr &LdSt,
197  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
198  bool &OffsetIsScalable, unsigned &Width,
199  const TargetRegisterInfo *TRI) const final;
200 
203  unsigned NumLoads, unsigned NumBytes) const override;
204 
205  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
206  int64_t Offset1, unsigned NumLoads) const override;
207 
209  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
210  bool KillSrc) const override;
211 
214  const DebugLoc &DL,
215  unsigned DestReg,
216  int64_t Value) const;
217 
219  unsigned Size) const;
220 
223  Register SrcReg, int Value) const;
224 
227  Register SrcReg, int Value) const;
228 
231  bool isKill, int FrameIndex,
232  const TargetRegisterClass *RC,
233  const TargetRegisterInfo *TRI) const override;
234 
237  int FrameIndex, const TargetRegisterClass *RC,
238  const TargetRegisterInfo *TRI) const override;
239 
240  bool expandPostRAPseudo(MachineInstr &MI) const override;
241 
242  // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
243  // instructions. Returns a pair of generated instructions.
244  // Can split either post-RA with physical registers or pre-RA with
245  // virtual registers. In latter case IR needs to be in SSA form and
246  // and a REG_SEQUENCE is produced to define original register.
247  std::pair<MachineInstr*, MachineInstr*>
249 
250  // Returns an opcode that can be used to move a value to a \p DstRC
251  // register. If there is no hardware instruction that can store to \p
252  // DstRC, then AMDGPU::COPY is returned.
253  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
254 
256  unsigned EltSize,
257  bool IsSGPR) const;
258 
260  bool IsIndirectSrc) const;
262  int commuteOpcode(unsigned Opc) const;
263 
265  inline int commuteOpcode(const MachineInstr &MI) const {
266  return commuteOpcode(MI.getOpcode());
267  }
268 
269  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
270  unsigned &SrcOpIdx2) const override;
271 
272  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
273  unsigned & SrcOpIdx1) const;
274 
275  bool isBranchOffsetInRange(unsigned BranchOpc,
276  int64_t BrOffset) const override;
277 
278  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
279 
281  MachineBasicBlock &NewDestBB,
282  MachineBasicBlock &RestoreBB, const DebugLoc &DL,
283  int64_t BrOffset, RegScavenger *RS) const override;
284 
287  MachineBasicBlock *&TBB,
288  MachineBasicBlock *&FBB,
290  bool AllowModify) const;
291 
293  MachineBasicBlock *&FBB,
295  bool AllowModify = false) const override;
296 
298  int *BytesRemoved = nullptr) const override;
299 
302  const DebugLoc &DL,
303  int *BytesAdded = nullptr) const override;
304 
306  SmallVectorImpl<MachineOperand> &Cond) const override;
307 
310  Register TrueReg, Register FalseReg, int &CondCycles,
311  int &TrueCycles, int &FalseCycles) const override;
312 
316  Register TrueReg, Register FalseReg) const override;
317 
321  Register TrueReg, Register FalseReg) const;
322 
323  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
324  Register &SrcReg2, int64_t &CmpMask,
325  int64_t &CmpValue) const override;
326 
327  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
328  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
329  const MachineRegisterInfo *MRI) const override;
330 
332  unsigned Kind) const override;
333 
334  bool
336  const MachineInstr &MIb) const override;
337 
338  static bool isFoldableCopy(const MachineInstr &MI);
339 
340  void removeModOperands(MachineInstr &MI) const;
341 
343  MachineRegisterInfo *MRI) const final;
344 
345  unsigned getMachineCSELookAheadLimit() const override { return 500; }
346 
348  LiveIntervals *LIS) const override;
349 
351  const MachineBasicBlock *MBB,
352  const MachineFunction &MF) const override;
353 
354  static bool isSALU(const MachineInstr &MI) {
355  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
356  }
357 
358  bool isSALU(uint16_t Opcode) const {
359  return get(Opcode).TSFlags & SIInstrFlags::SALU;
360  }
361 
362  static bool isVALU(const MachineInstr &MI) {
363  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
364  }
365 
366  bool isVALU(uint16_t Opcode) const {
367  return get(Opcode).TSFlags & SIInstrFlags::VALU;
368  }
369 
370  static bool isVMEM(const MachineInstr &MI) {
371  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
372  }
373 
374  bool isVMEM(uint16_t Opcode) const {
375  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
376  }
377 
378  static bool isSOP1(const MachineInstr &MI) {
379  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
380  }
381 
382  bool isSOP1(uint16_t Opcode) const {
383  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
384  }
385 
386  static bool isSOP2(const MachineInstr &MI) {
387  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
388  }
389 
390  bool isSOP2(uint16_t Opcode) const {
391  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
392  }
393 
394  static bool isSOPC(const MachineInstr &MI) {
395  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
396  }
397 
398  bool isSOPC(uint16_t Opcode) const {
399  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
400  }
401 
402  static bool isSOPK(const MachineInstr &MI) {
403  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
404  }
405 
406  bool isSOPK(uint16_t Opcode) const {
407  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
408  }
409 
410  static bool isSOPP(const MachineInstr &MI) {
411  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
412  }
413 
414  bool isSOPP(uint16_t Opcode) const {
415  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
416  }
417 
418  static bool isPacked(const MachineInstr &MI) {
419  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
420  }
421 
422  bool isPacked(uint16_t Opcode) const {
423  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
424  }
425 
426  static bool isVOP1(const MachineInstr &MI) {
427  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
428  }
429 
430  bool isVOP1(uint16_t Opcode) const {
431  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
432  }
433 
434  static bool isVOP2(const MachineInstr &MI) {
435  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
436  }
437 
438  bool isVOP2(uint16_t Opcode) const {
439  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
440  }
441 
442  static bool isVOP3(const MachineInstr &MI) {
443  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
444  }
445 
446  bool isVOP3(uint16_t Opcode) const {
447  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
448  }
449 
450  static bool isSDWA(const MachineInstr &MI) {
451  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
452  }
453 
454  bool isSDWA(uint16_t Opcode) const {
455  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
456  }
457 
458  static bool isVOPC(const MachineInstr &MI) {
459  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
460  }
461 
462  bool isVOPC(uint16_t Opcode) const {
463  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
464  }
465 
466  static bool isMUBUF(const MachineInstr &MI) {
467  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
468  }
469 
470  bool isMUBUF(uint16_t Opcode) const {
471  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
472  }
473 
474  static bool isMTBUF(const MachineInstr &MI) {
475  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
476  }
477 
478  bool isMTBUF(uint16_t Opcode) const {
479  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
480  }
481 
482  static bool isSMRD(const MachineInstr &MI) {
483  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
484  }
485 
486  bool isSMRD(uint16_t Opcode) const {
487  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
488  }
489 
490  bool isBufferSMRD(const MachineInstr &MI) const;
491 
492  static bool isDS(const MachineInstr &MI) {
493  return MI.getDesc().TSFlags & SIInstrFlags::DS;
494  }
495 
496  bool isDS(uint16_t Opcode) const {
497  return get(Opcode).TSFlags & SIInstrFlags::DS;
498  }
499 
500  bool isAlwaysGDS(uint16_t Opcode) const;
501 
502  static bool isMIMG(const MachineInstr &MI) {
503  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
504  }
505 
506  bool isMIMG(uint16_t Opcode) const {
507  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
508  }
509 
510  static bool isGather4(const MachineInstr &MI) {
511  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
512  }
513 
514  bool isGather4(uint16_t Opcode) const {
515  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
516  }
517 
518  static bool isFLAT(const MachineInstr &MI) {
519  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
520  }
521 
522  // Is a FLAT encoded instruction which accesses a specific segment,
523  // i.e. global_* or scratch_*.
524  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
525  auto Flags = MI.getDesc().TSFlags;
527  }
528 
529  bool isSegmentSpecificFLAT(uint16_t Opcode) const {
530  auto Flags = get(Opcode).TSFlags;
532  }
533 
534  static bool isFLATGlobal(const MachineInstr &MI) {
535  return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
536  }
537 
538  bool isFLATGlobal(uint16_t Opcode) const {
539  return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
540  }
541 
542  static bool isFLATScratch(const MachineInstr &MI) {
543  return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
544  }
545 
546  bool isFLATScratch(uint16_t Opcode) const {
547  return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
548  }
549 
550  // Any FLAT encoded instruction, including global_* and scratch_*.
551  bool isFLAT(uint16_t Opcode) const {
552  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
553  }
554 
555  static bool isEXP(const MachineInstr &MI) {
556  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
557  }
558 
559  bool isEXP(uint16_t Opcode) const {
560  return get(Opcode).TSFlags & SIInstrFlags::EXP;
561  }
562 
563  static bool isAtomicNoRet(const MachineInstr &MI) {
564  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
565  }
566 
567  bool isAtomicNoRet(uint16_t Opcode) const {
568  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
569  }
570 
571  static bool isAtomicRet(const MachineInstr &MI) {
572  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
573  }
574 
575  bool isAtomicRet(uint16_t Opcode) const {
576  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
577  }
578 
579  static bool isAtomic(const MachineInstr &MI) {
580  return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
582  }
583 
584  bool isAtomic(uint16_t Opcode) const {
585  return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
587  }
588 
589  static bool isWQM(const MachineInstr &MI) {
590  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
591  }
592 
593  bool isWQM(uint16_t Opcode) const {
594  return get(Opcode).TSFlags & SIInstrFlags::WQM;
595  }
596 
597  static bool isDisableWQM(const MachineInstr &MI) {
598  return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
599  }
600 
601  bool isDisableWQM(uint16_t Opcode) const {
602  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
603  }
604 
605  static bool isVGPRSpill(const MachineInstr &MI) {
606  return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
607  }
608 
609  bool isVGPRSpill(uint16_t Opcode) const {
610  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
611  }
612 
613  static bool isSGPRSpill(const MachineInstr &MI) {
614  return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
615  }
616 
617  bool isSGPRSpill(uint16_t Opcode) const {
618  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
619  }
620 
621  static bool isDPP(const MachineInstr &MI) {
622  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
623  }
624 
625  bool isDPP(uint16_t Opcode) const {
626  return get(Opcode).TSFlags & SIInstrFlags::DPP;
627  }
628 
629  static bool isTRANS(const MachineInstr &MI) {
630  return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
631  }
632 
633  bool isTRANS(uint16_t Opcode) const {
634  return get(Opcode).TSFlags & SIInstrFlags::TRANS;
635  }
636 
637  static bool isVOP3P(const MachineInstr &MI) {
638  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
639  }
640 
641  bool isVOP3P(uint16_t Opcode) const {
642  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
643  }
644 
645  static bool isVINTRP(const MachineInstr &MI) {
646  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
647  }
648 
649  bool isVINTRP(uint16_t Opcode) const {
650  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
651  }
652 
653  static bool isMAI(const MachineInstr &MI) {
654  return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
655  }
656 
657  bool isMAI(uint16_t Opcode) const {
658  return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
659  }
660 
661  static bool isDOT(const MachineInstr &MI) {
662  return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
663  }
664 
665  bool isDOT(uint16_t Opcode) const {
666  return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
667  }
668 
669  static bool isLDSDIR(const MachineInstr &MI) {
670  return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
671  }
672 
673  bool isLDSDIR(uint16_t Opcode) const {
674  return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
675  }
676 
677  static bool isScalarUnit(const MachineInstr &MI) {
678  return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
679  }
680 
681  static bool usesVM_CNT(const MachineInstr &MI) {
682  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
683  }
684 
685  static bool usesLGKM_CNT(const MachineInstr &MI) {
686  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
687  }
688 
689  static bool sopkIsZext(const MachineInstr &MI) {
690  return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
691  }
692 
693  bool sopkIsZext(uint16_t Opcode) const {
694  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
695  }
696 
697  /// \returns true if this is an s_store_dword* instruction. This is more
698  /// specific than than isSMEM && mayStore.
699  static bool isScalarStore(const MachineInstr &MI) {
700  return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
701  }
702 
703  bool isScalarStore(uint16_t Opcode) const {
704  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
705  }
706 
707  static bool isFixedSize(const MachineInstr &MI) {
708  return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
709  }
710 
711  bool isFixedSize(uint16_t Opcode) const {
712  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
713  }
714 
715  static bool hasFPClamp(const MachineInstr &MI) {
716  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
717  }
718 
719  bool hasFPClamp(uint16_t Opcode) const {
720  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
721  }
722 
723  static bool hasIntClamp(const MachineInstr &MI) {
724  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
725  }
726 
728  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
732  return MI.getDesc().TSFlags & ClampFlags;
733  }
734 
735  static bool usesFPDPRounding(const MachineInstr &MI) {
736  return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
737  }
738 
739  bool usesFPDPRounding(uint16_t Opcode) const {
740  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
741  }
742 
743  static bool isFPAtomic(const MachineInstr &MI) {
744  return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
745  }
746 
747  bool isFPAtomic(uint16_t Opcode) const {
748  return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
749  }
750 
751  bool isVGPRCopy(const MachineInstr &MI) const {
752  assert(MI.isCopy());
753  Register Dest = MI.getOperand(0).getReg();
754  const MachineFunction &MF = *MI.getParent()->getParent();
755  const MachineRegisterInfo &MRI = MF.getRegInfo();
756  return !RI.isSGPRReg(MRI, Dest);
757  }
758 
759  bool hasVGPRUses(const MachineInstr &MI) const {
760  const MachineFunction &MF = *MI.getParent()->getParent();
761  const MachineRegisterInfo &MRI = MF.getRegInfo();
762  return llvm::any_of(MI.explicit_uses(),
763  [&MRI, this](const MachineOperand &MO) {
764  return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
765  }
766 
767  /// Return true if the instruction modifies the mode register.q
768  static bool modifiesModeRegister(const MachineInstr &MI);
769 
770  /// Whether we must prevent this instruction from executing with EXEC = 0.
772 
773  /// Returns true if the instruction could potentially depend on the value of
774  /// exec. If false, exec dependencies may safely be ignored.
775  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
776 
777  bool isInlineConstant(const APInt &Imm) const;
778 
779  bool isInlineConstant(const APFloat &Imm) const {
780  return isInlineConstant(Imm.bitcastToAPInt());
781  }
782 
783  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
784 
786  const MCOperandInfo &OpInfo) const {
787  return isInlineConstant(MO, OpInfo.OperandType);
788  }
789 
790  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
791  /// be an inline immediate.
793  const MachineOperand &UseMO,
794  const MachineOperand &DefMO) const {
795  assert(UseMO.getParent() == &MI);
796  int OpIdx = MI.getOperandNo(&UseMO);
797  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
798  return false;
799  }
800 
801  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
802  }
803 
804  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
805  /// immediate.
806  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
807  const MachineOperand &MO = MI.getOperand(OpIdx);
808  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
809  }
810 
811  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
812  const MachineOperand &MO) const {
813  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
814  return false;
815 
816  if (MI.isCopy()) {
817  unsigned Size = getOpSize(MI, OpIdx);
818  assert(Size == 8 || Size == 4);
819 
820  uint8_t OpType = (Size == 8) ?
822  return isInlineConstant(MO, OpType);
823  }
824 
825  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
826  }
827 
828  bool isInlineConstant(const MachineOperand &MO) const {
829  const MachineInstr *Parent = MO.getParent();
830  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
831  }
832 
834  const MCOperandInfo &OpInfo) const {
835  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
836  }
837 
838  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
839  const MachineOperand &MO = MI.getOperand(OpIdx);
840  return MO.isImm() && !isInlineConstant(MI, OpIdx);
841  }
842 
843  // Returns true if this operand could potentially require a 32-bit literal
844  // operand, but not necessarily. A FrameIndex for example could resolve to an
845  // inline immediate value that will not require an additional 4-bytes; this
846  // assumes that it will.
847  bool isLiteralConstantLike(const MachineOperand &MO,
848  const MCOperandInfo &OpInfo) const;
849 
850  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
851  const MachineOperand &MO) const;
852 
853  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
854  /// This function will return false if you pass it a 32-bit instruction.
855  bool hasVALU32BitEncoding(unsigned Opcode) const;
856 
857  /// Returns true if this operand uses the constant bus.
859  const MachineOperand &MO,
860  const MCOperandInfo &OpInfo) const;
861 
862  /// Return true if this instruction has any modifiers.
863  /// e.g. src[012]_mod, omod, clamp.
864  bool hasModifiers(unsigned Opcode) const;
865 
866  bool hasModifiersSet(const MachineInstr &MI,
867  unsigned OpName) const;
868  bool hasAnyModifiersSet(const MachineInstr &MI) const;
869 
870  bool canShrink(const MachineInstr &MI,
871  const MachineRegisterInfo &MRI) const;
872 
874  unsigned NewOpcode) const;
875 
876  bool verifyInstruction(const MachineInstr &MI,
877  StringRef &ErrInfo) const override;
878 
879  unsigned getVALUOp(const MachineInstr &MI) const;
880 
881  /// Return the correct register class for \p OpNo. For target-specific
882  /// instructions, this will return the register class that has been defined
883  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
884  /// the register class of its machine operand.
885  /// to infer the correct register class base on the other operands.
887  unsigned OpNo) const;
888 
889  /// Return the size in bytes of the operand OpNo on the given
890  // instruction opcode.
891  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
892  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
893 
894  if (OpInfo.RegClass == -1) {
895  // If this is an immediate operand, this must be a 32-bit literal.
897  return 4;
898  }
899 
900  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
901  }
902 
903  /// This form should usually be preferred since it handles operands
904  /// with unknown register classes.
905  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
906  const MachineOperand &MO = MI.getOperand(OpNo);
907  if (MO.isReg()) {
908  if (unsigned SubReg = MO.getSubReg()) {
909  return RI.getSubRegIdxSize(SubReg) / 8;
910  }
911  }
912  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
913  }
914 
915  /// Legalize the \p OpIndex operand of this instruction by inserting
916  /// a MOV. For example:
917  /// ADD_I32_e32 VGPR0, 15
918  /// to
919  /// MOV VGPR1, 15
920  /// ADD_I32_e32 VGPR0, VGPR1
921  ///
922  /// If the operand being legalized is a register, then a COPY will be used
923  /// instead of MOV.
924  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
925 
926  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
927  /// for \p MI.
928  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
929  const MachineOperand *MO = nullptr) const;
930 
931  /// Check if \p MO would be a valid operand for the given operand
932  /// definition \p OpInfo. Note this does not attempt to validate constant bus
933  /// restrictions (e.g. literal constant usage).
935  const MCOperandInfo &OpInfo,
936  const MachineOperand &MO) const;
937 
938  /// Check if \p MO (a register operand) is a legal register for the
939  /// given operand description.
941  const MCOperandInfo &OpInfo,
942  const MachineOperand &MO) const;
943 
944  /// Legalize operands in \p MI by either commuting it or inserting a
945  /// copy of src1.
947 
948  /// Fix operands in \p MI to satisfy constant bus requirements.
950 
951  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
952  /// be used when it is know that the value in SrcReg is same across all
953  /// threads in the wave.
954  /// \returns The SGPR register that \p SrcReg was copied to.
956  MachineRegisterInfo &MRI) const;
957 
960 
963  const TargetRegisterClass *DstRC,
965  const DebugLoc &DL) const;
966 
967  /// Legalize all operands in this instruction. This function may create new
968  /// instructions and control-flow around \p MI. If present, \p MDT is
969  /// updated.
970  /// \returns A new basic block that contains \p MI if new blocks were created.
972  legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
973 
974  /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
975  /// was moved to VGPR. \returns true if succeeded.
976  bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
977 
978  /// Replace this instruction's opcode with the equivalent VALU
979  /// opcode. This function will also move the users of \p MI to the
980  /// VALU if necessary. If present, \p MDT is updated.
982  MachineDominatorTree *MDT = nullptr) const;
983 
985  MachineBasicBlock::iterator MI) const override;
986 
988  unsigned Quantity) const override;
989 
990  void insertReturn(MachineBasicBlock &MBB) const;
991  /// Return the number of wait states that result from executing this
992  /// instruction.
993  static unsigned getNumWaitStates(const MachineInstr &MI);
994 
995  /// Returns the operand named \p Op. If \p MI does not have an
996  /// operand named \c Op, this function returns nullptr.
998  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
999 
1002  unsigned OpName) const {
1003  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1004  }
1005 
1006  /// Get required immediate operand
1007  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1008  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1009  return MI.getOperand(Idx).getImm();
1010  }
1011 
1014 
1015  bool isLowLatencyInstruction(const MachineInstr &MI) const;
1016  bool isHighLatencyDef(int Opc) const override;
1017 
1018  /// Return the descriptor of the target-specific machine instruction
1019  /// that corresponds to the specified pseudo or native opcode.
1020  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1021  return get(pseudoToMCOpcode(Opcode));
1022  }
1023 
1024  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1025  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1026 
1027  unsigned isLoadFromStackSlot(const MachineInstr &MI,
1028  int &FrameIndex) const override;
1029  unsigned isStoreToStackSlot(const MachineInstr &MI,
1030  int &FrameIndex) const override;
1031 
1032  unsigned getInstBundleSize(const MachineInstr &MI) const;
1033  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1034 
1035  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1036 
1037  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1038 
1040  MachineBasicBlock *IfEnd) const;
1041 
1043  MachineBasicBlock *LoopEnd) const;
1044 
1045  std::pair<unsigned, unsigned>
1046  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1047 
1049  getSerializableTargetIndices() const override;
1050 
1053 
1056 
1059  const ScheduleDAG *DAG) const override;
1060 
1062  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1063 
1066  const ScheduleDAGMI *DAG) const override;
1067 
1068  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1069 
1072  const DebugLoc &DL, Register Src,
1073  Register Dst) const override;
1074 
1077  const DebugLoc &DL, Register Src,
1078  unsigned SrcSubReg,
1079  Register Dst) const override;
1080 
1081  bool isWave32() const;
1082 
1083  /// Return a partially built integer add instruction without carry.
1084  /// Caller must add source operands.
1085  /// For pre-GFX9 it will generate unused carry destination operand.
1086  /// TODO: After GFX9 it should return a no-carry operation.
1089  const DebugLoc &DL,
1090  Register DestReg) const;
1091 
1094  const DebugLoc &DL,
1095  Register DestReg,
1096  RegScavenger &RS) const;
1097 
1098  static bool isKillTerminator(unsigned Opcode);
1099  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1100 
1101  static bool isLegalMUBUFImmOffset(unsigned Imm) {
1102  return isUInt<12>(Imm);
1103  }
1104 
1105  /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1106  /// encoded instruction. If \p Signed, this is for an instruction that
1107  /// interprets the offset as signed.
1108  bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1109  uint64_t FlatVariant) const;
1110 
1111  /// Split \p COffsetVal into {immediate offset field, remainder offset}
1112  /// values.
1113  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1114  unsigned AddrSpace,
1115  uint64_t FlatVariant) const;
1116 
1117  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1118  /// Return -1 if the target-specific opcode for the pseudo instruction does
1119  /// not exist. If Opcode is not a pseudo instruction, this is identity.
1120  int pseudoToMCOpcode(int Opcode) const;
1121 
1122  /// \brief Check if this instruction should only be used by assembler.
1123  /// Return true if this opcode should not be used by codegen.
1124  bool isAsmOnlyOpcode(int MCOp) const;
1125 
1126  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1127  const TargetRegisterInfo *TRI,
1128  const MachineFunction &MF)
1129  const override;
1130 
1131  void fixImplicitOperands(MachineInstr &MI) const;
1132 
1134  ArrayRef<unsigned> Ops,
1135  MachineBasicBlock::iterator InsertPt,
1136  int FrameIndex,
1137  LiveIntervals *LIS = nullptr,
1138  VirtRegMap *VRM = nullptr) const override;
1139 
1140  unsigned getInstrLatency(const InstrItineraryData *ItinData,
1141  const MachineInstr &MI,
1142  unsigned *PredCost = nullptr) const override;
1143 
1144  const MIRFormatter *getMIRFormatter() const override {
1145  if (!Formatter.get())
1146  Formatter = std::make_unique<AMDGPUMIRFormatter>();
1147  return Formatter.get();
1148  }
1149 
1150  static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1151 
1152  const TargetSchedModel &getSchedModel() const { return SchedModel; }
1153 };
1154 
1155 /// \brief Returns true if a reg:subreg pair P has a TRC class
1157  const TargetRegisterClass &TRC,
1159  auto *RC = MRI.getRegClass(P.Reg);
1160  if (!P.SubReg)
1161  return RC == &TRC;
1162  auto *TRI = MRI.getTargetRegisterInfo();
1163  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1164 }
1165 
1166 /// \brief Create RegSubRegPair from a register MachineOperand
1167 inline
1169  assert(O.isReg());
1170  return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1171 }
1172 
1173 /// \brief Return the SubReg component from REG_SEQUENCE
1175  unsigned SubReg);
1176 
1177 /// \brief Return the defining instruction for a given reg:subreg pair
1178 /// skipping copy like instructions and subreg-manipulation pseudos.
1179 /// Following another subreg of a reg:subreg isn't supported.
1181  MachineRegisterInfo &MRI);
1182 
1183 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1184 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1185 /// attempt to track between blocks.
1186 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1187  Register VReg,
1188  const MachineInstr &DefMI,
1189  const MachineInstr &UseMI);
1190 
1191 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1192 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1193 /// track between blocks.
1194 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1195  Register VReg,
1196  const MachineInstr &DefMI);
1197 
1198 namespace AMDGPU {
1199 
1201  int getVOPe64(uint16_t Opcode);
1202 
1204  int getVOPe32(uint16_t Opcode);
1205 
1207  int getSDWAOp(uint16_t Opcode);
1208 
1210  int getDPPOp32(uint16_t Opcode);
1211 
1213  int getBasicFromSDWAOp(uint16_t Opcode);
1214 
1216  int getCommuteRev(uint16_t Opcode);
1217 
1219  int getCommuteOrig(uint16_t Opcode);
1220 
1222  int getAddr64Inst(uint16_t Opcode);
1223 
1224  /// Check if \p Opcode is an Addr64 opcode.
1225  ///
1226  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1228  int getIfAddr64Inst(uint16_t Opcode);
1229 
1231  int getAtomicNoRetOp(uint16_t Opcode);
1232 
1234  int getSOPKOp(uint16_t Opcode);
1235 
1236  /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1237  /// of a VADDR form.
1239  int getGlobalSaddrOp(uint16_t Opcode);
1240 
1241  /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1242  /// of a SADDR form.
1244  int getGlobalVaddrOp(uint16_t Opcode);
1245 
1247  int getVCMPXNoSDstOp(uint16_t Opcode);
1248 
1249  /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1250  /// given an \p Opcode of an SS (SADDR) form.
1253 
1254  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1255  /// of an SVS (SADDR + VADDR) form.
1258 
1259  /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1260  /// of an SV (VADDR) form.
1263 
1264  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1265  /// of an SS (SADDR) form.
1268 
1269  /// \returns earlyclobber version of a MAC MFMA is exists.
1271  int getMFMAEarlyClobberOp(uint16_t Opcode);
1272 
1273  /// \returns v_cmpx version of a v_cmp instruction.
1275  int getVCMPXOpFromVCMP(uint16_t Opcode);
1276 
1277  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1280  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1281 
1282 } // end namespace AMDGPU
1283 
1284 namespace SI {
1285 namespace KernelInputOffsets {
1286 
1287 /// Offsets in bytes from the start of the input buffer
1288 enum Offsets {
1298 };
1299 
1300 } // end namespace KernelInputOffsets
1301 } // end namespace SI
1302 
1303 } // end namespace llvm
1304 
1305 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:64
llvm::SIInstrInfo::isIgnorableUse
bool isIgnorableUse(const MachineOperand &MO) const override
Definition: SIInstrInfo.cpp:170
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:99
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:45
llvm::AMDGPU::getVCMPXNoSDstOp
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
llvm::SIInstrInfo::isMIMG
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:506
llvm::SIInstrInfo::isMTBUF
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:478
llvm::SIInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SIInstrInfo.cpp:2579
llvm::SIInstrInfo::isAtomicRet
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:571
llvm::SIInstrInfo::insertNoops
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
Definition: SIInstrInfo.cpp:1736
llvm::SIInstrInfo::isFLAT
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:551
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:206
llvm::SIInstrInfo::isDPP
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:625
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:685
llvm::SIInstrInfo::isFLATGlobal
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:538
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SIInstrInfo::insertNE
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1257
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:89
llvm::SIInstrInfo::isDisableWQM
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:601
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:40
llvm::SIInstrInfo::swapSourceModifiers
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
Definition: SIInstrInfo.cpp:2233
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::SIInstrInfo::hasFPClamp
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:715
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:36
llvm::MONoClobber
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:40
llvm::SIInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:3465
llvm::SIInstrInfo::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
Definition: SIInstrInfo.cpp:2890
llvm::AMDGPU::getMFMAEarlyClobberOp
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
llvm::AMDGPU::getFlatScratchInstSVfromSS
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
llvm::SIInstrInfo::isSGPRSpill
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:613
llvm::SIInstrInfo::isSOP2
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:390
llvm::SIInstrInfo::isFixedSize
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:707
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2945
llvm::SIInstrInfo::isMAI
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:657
llvm::SIInstrInfo::getClampMask
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:727
llvm::getRegSubRegPair
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1168
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::AMDGPU::getAtomicNoRetOp
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
llvm::SIInstrInfo::usesLGKM_CNT
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:685
llvm::SIInstrInfo::usesVM_CNT
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:681
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SIInstrInfo::isVOP3
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:442
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::SIInstrInfo::hasVGPRUses
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:759
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y
@ GLOBAL_SIZE_Y
Definition: SIInstrInfo.h:1293
llvm::SIInstrInfo::getMovOpcode
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
Definition: SIInstrInfo.cpp:1270
llvm::SIInstrInfo::isSOPP
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:414
llvm::SIInstrInfo::isBufferSMRD
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7724
llvm::SIInstrInfo::getNumWaitStates
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
Definition: SIInstrInfo.cpp:1765
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:34
llvm::SIInstrInfo::MO_GOTPCREL32
@ MO_GOTPCREL32
Definition: SIInstrInfo.h:160
llvm::SIInstrInfo::isImmOperandLegal
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
Definition: SIInstrInfo.cpp:3722
llvm::SIInstrInfo::convertNonUniformLoopRegion
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
Definition: SIInstrInfo.cpp:7537
llvm::SIInstrInfo::isHighLatencyDef
bool isHighLatencyDef(int Opc) const override
Definition: SIInstrInfo.cpp:7367
llvm::SIInstrInfo::isDisableWQM
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:597
llvm::SIInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SIInstrInfo.cpp:2708
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SIInstrInfo::analyzeBranchImpl
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: SIInstrInfo.cpp:2536
llvm::SIInstrInfo::isScalarStore
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:699
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:123
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::SIInstrInfo::createPHIDestinationCopy
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
Definition: SIInstrInfo.cpp:8112
llvm::SIInstrInfo::isEXP
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:555
llvm::SIInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: SIInstrInfo.cpp:3263
llvm::SIInstrInfo::isFoldableCopy
static bool isFoldableCopy(const MachineInstr &MI)
Definition: SIInstrInfo.cpp:2871
llvm::SIInstrInfo::moveToVALU
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Definition: SIInstrInfo.cpp:6020
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::SIInstrInfo::modifiesModeRegister
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Definition: SIInstrInfo.cpp:3505
llvm::AMDGPU::getSOPKOp
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
llvm::SIInstrInfo::isSDWA
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::SIInstrInfo::isMUBUF
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:470
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:35
llvm::AMDGPU::getGlobalSaddrOp
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7407
TargetInstrInfo.h
llvm::SIInstrInfo::isVOP3P
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:637
llvm::SIInstrInfo::isAsmOnlyOpcode
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
Definition: SIInstrInfo.cpp:7861
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIInstrInfo::isVGPRSpill
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:605
llvm::SIInstrInfo::MO_MASK
@ MO_MASK
Definition: SIInstrInfo.h:154
llvm::SIInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
Definition: SIInstrInfo.cpp:7595
llvm::SIInstrInfo::getScratchRsrcWords23
uint64_t getScratchRsrcWords23() const
Definition: SIInstrInfo.cpp:7337
llvm::SIInstrInfo::MO_GOTPCREL
@ MO_GOTPCREL
Definition: SIInstrInfo.h:158
llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
Definition: SIInstrInfo.cpp:1386
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIInstrInfo::hasAnyModifiersSet
bool hasAnyModifiersSet(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:3778
llvm::SIInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: SIInstrInfo.cpp:2358
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:70
llvm::SIInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: SIInstrInfo.cpp:1731
llvm::SIInstrInfo::isBasicBlockPrologue
bool isBasicBlockPrologue(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7651
llvm::SIInstrInfo::insertVectorSelect
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Definition: SIInstrInfo.cpp:1118
llvm::SIInstrInfo::isVOP1
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:430
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:37
llvm::SIInstrInfo::fixImplicitOperands
void fixImplicitOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7714
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:491
llvm::SIInstrInfo::isVOPC
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:462
llvm::AMDGPU::getVOPe64
LLVM_READONLY int getVOPe64(uint16_t Opcode)
llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
Definition: SIInstrInfo.cpp:3519
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:891
llvm::SIInstrInfo::isWave32
bool isWave32() const
Definition: SIInstrInfo.cpp:8147
llvm::SIInstrInfo::isVOPC
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:458
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::SIInstrInfo::canShrink
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: SIInstrInfo.cpp:3783
llvm::AMDGPU::getCommuteOrig
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:149
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:72
llvm::SIInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SIInstrInfo.cpp:708
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:156
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:49
llvm::SIInstrInfo::MO_GOTPCREL32_LO
@ MO_GOTPCREL32_LO
Definition: SIInstrInfo.h:161
llvm::SIInstrInfo::isMIMG
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:502
llvm::SIInstrInfo::isSOPK
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:406
llvm::SIInstrInfo::isAtomicNoRet
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:567
llvm::SIInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7433
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APInt &Imm) const
Definition: SIInstrInfo.cpp:3585
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::SIInstrInfo::isSOPC
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:394
llvm::SIInstrInfo::getSchedModel
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1152
llvm::SIInstrInfo::createPHISourceCopy
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Definition: SIInstrInfo.cpp:8127
llvm::SIInstrInfo::isNonUniformBranchInstr
bool isNonUniformBranchInstr(MachineInstr &Instr) const
Definition: SIInstrInfo.cpp:7508
llvm::SIInstrInfo::isMAI
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:653
llvm::SIInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:176
llvm::SIInstrInfo::isSOPK
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:402
llvm::AMDGPU::getFlatScratchInstSSfromSV
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SIInstrInfo::isOperandLegal
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition: SIInstrInfo.cpp:4956
llvm::SIInstrInfo::hasIntClamp
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:723
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:78
llvm::AMDGPU::getDPPOp32
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
llvm::AMDGPU::getVOPe32
LLVM_READONLY int getVOPe32(uint16_t Opcode)
AMDGPUMIRFormatter.h
llvm::SIInstrInfo::isVOP3
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:446
llvm::SIInstrInfo::isSegmentSpecificFLAT
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:529
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SIInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: SIInstrInfo.cpp:7582
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
OpName
Definition: R600Defines.h:62
llvm::SIInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: SIInstrInfo.cpp:7622
llvm::SIInstrInfo::isGather4
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:514
llvm::SIInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: SIInstrInfo.cpp:8186
llvm::SIInstrInfo::legalizeOperands
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
Definition: SIInstrInfo.cpp:5694
llvm::getVRegSubRegDef
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
Definition: SIInstrInfo.cpp:7988
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:96
llvm::SIInstrInfo::moveFlatAddrToVGPR
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
Definition: SIInstrInfo.cpp:5311
llvm::SIInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: SIInstrInfo.cpp:2335
llvm::SIInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
Definition: SIInstrInfo.cpp:2918
llvm::SIInstrInfo::sopkIsZext
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:689
llvm::SIInstrInfo::isVOP2
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:438
llvm::SIInstrInfo::getNamedOperand
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Definition: SIInstrInfo.cpp:7303
llvm::SIInstrInfo::hasModifiers
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
Definition: SIInstrInfo.cpp:3764
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::SIInstrInfo::isVOP3P
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:641
llvm::SIInstrInfo::isGather4
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:510
llvm::SIInstrInfo::MO_REL32
@ MO_REL32
Definition: SIInstrInfo.h:165
llvm::SIInstrFlags::LDSDIR
@ LDSDIR
Definition: SIDefines.h:67
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1129
llvm::SIInstrInfo::legalizeGenericOperand
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
Definition: SIInstrInfo.cpp:5410
llvm::AMDGPU::getSDWAOp
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::SIInstrInfo::isScalarUnit
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:677
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::SIInstrInfo::MO_FAR_BRANCH_OFFSET
@ MO_FAR_BRANCH_OFFSET
Definition: SIInstrInfo.h:170
llvm::SI::KernelInputOffsets::NGROUPS_Z
@ NGROUPS_Z
Definition: SIInstrInfo.h:1291
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SIInstrInfo::isVALU
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:366
llvm::SIInstrInfo::MO_ABS32_LO
@ MO_ABS32_LO
Definition: SIInstrInfo.h:172
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::SIInstrInfo::TargetOperandFlags
TargetOperandFlags
Definition: SIInstrInfo.h:153
llvm::SIInstrInfo::getAddNoCarry
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
Definition: SIInstrInfo.cpp:7657
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:50
llvm::SIInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7393
llvm::SIInstrInfo::removeModOperands
void removeModOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2912
llvm::SIInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: SIInstrInfo.cpp:112
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:779
llvm::SIInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7627
llvm::AMDGPU::getFlatScratchInstSVfromSVS
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
llvm::APFloat
Definition: APFloat.h:700
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:905
llvm::SIInstrInfo::MO_ABS32_HI
@ MO_ABS32_HI
Definition: SIInstrInfo.h:173
llvm::SIInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SIInstrInfo.cpp:2764
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::SIInstrInfo::isDPP
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:621
llvm::SIInstrInfo::isWQM
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:593
llvm::SIInstrInfo::isLowLatencyInstruction
bool isLowLatencyInstruction(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7361
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
TargetSchedule.h
llvm::SIInstrInfo::hasVALU32BitEncoding
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
Definition: SIInstrInfo.cpp:3752
llvm::SIInstrInfo::getNamedImmOperand
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1007
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::execMayBeModifiedBeforeAnyUse
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
Definition: SIInstrInfo.cpp:8056
llvm::ARMII::VecSize
@ VecSize
Definition: ARMBaseInfo.h:421
uint64_t
llvm::SIInstrInfo::hasFPClamp
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:719
llvm::SI::KernelInputOffsets::LOCAL_SIZE_X
@ LOCAL_SIZE_X
Definition: SIInstrInfo.h:1295
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:111
llvm::SIInstrInfo::getMIRFormatter
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1144
llvm::SIInstrInfo::buildExtractSubReg
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4857
llvm::SIInstrInfo::sopkIsZext
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:693
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:542
llvm::SIInstrInfo::isDS
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:492
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:75
llvm::SIInstrInfo::isDS
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:496
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2673
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:482
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::execMayBeModifiedBeforeUse
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
Definition: SIInstrInfo.cpp:8023
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:51
llvm::SIInstrInfo::isLegalFLATOffset
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
Definition: SIInstrInfo.cpp:7767
llvm::SIInstrInfo::legalizeOperandsFLAT
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5392
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:57
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:48
llvm::SIInstrInfo::isSOP2
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:386
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::SIInstrInfo::isScalarStore
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:703
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:100
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInstrInfo::MO_REL32_LO
@ MO_REL32_LO
Definition: SIInstrInfo.h:166
llvm::SIInstrInfo::isAlwaysGDS
bool isAlwaysGDS(uint16_t Opcode) const
Definition: SIInstrInfo.cpp:3495
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:74
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:79
llvm::SIInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:2374
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:806
llvm::SIInstrInfo::isVMEM
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:374
llvm::SIInstrInfo::isFPAtomic
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:743
llvm::SIInstrInfo::isSGPRSpill
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:617
llvm::SIInstrInfo::isPacked
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:418
llvm::SIInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1678
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:579
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
llvm::SIInstrInfo::isSOP1
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:378
llvm::SIInstrInfo::isSALU
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:354
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SIInstrInfo::insertReturn
void insertReturn(MachineBasicBlock &MBB) const
Definition: SIInstrInfo.cpp:1747
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:29
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::SIInstrInfo::mayAccessFlatAddressSpace
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7494
llvm::SIInstrInfo::isVOP1
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:426
llvm::SI::KernelInputOffsets::NGROUPS_Y
@ NGROUPS_Y
Definition: SIInstrInfo.h:1290
llvm::AMDGPU::RSRC_DATA_FORMAT
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1277
llvm::SIInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Definition: SIInstrInfo.cpp:478
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SIInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SIInstrInfo.cpp:2648
llvm::SIInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
Definition: SIInstrInfo.cpp:2722
llvm::SIInstrInfo::MO_REL32_HI
@ MO_REL32_HI
Definition: SIInstrInfo.h:168
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1614
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::SIInstrInfo::usesConstantBus
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
Definition: SIInstrInfo.cpp:3898
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SIInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3983
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:785
llvm::SIInstrInfo::isFixedSize
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:711
llvm::SIInstrInfo::isSDWA
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:450
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIInstrInfo::isSALU
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:358
llvm::SIInstrInfo::isVOP2
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:434
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
llvm::SIInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Definition: SIInstrInfo.cpp:8284
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:265
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:833
AMDGPUGenInstrInfo
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:466
llvm::SIInstrInfo::isAtomic
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:584
llvm::SIInstrInfo::isDOT
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:661
llvm::SIInstrInfo::isVINTRP
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:649
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:105
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:41
llvm::SIInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
Definition: SIInstrInfo.cpp:2283
llvm::SIInstrInfo::CreateTargetMIHazardRecognizer
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
Definition: SIInstrInfo.cpp:7610
llvm::SIInstrInfo::isKillTerminator
static bool isKillTerminator(unsigned Opcode)
Definition: SIInstrInfo.cpp:7693
llvm::AMDGPU::getCommuteRev
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1101
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:92
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::SIInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:1785
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SIInstrInfo::legalizeOpWithMove
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
Definition: SIInstrInfo.cpp:4830
llvm::SIInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
Definition: SIInstrInfo.cpp:291
llvm::SIInstrInfo::isTRANS
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:633
llvm::SIInstrInfo::splitFlatOffset
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition: SIInstrInfo.cpp:7794
llvm::SIInstrInfo::convertNonUniformIfRegion
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
Definition: SIInstrInfo.cpp:7512
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:120
llvm::SIInstrInfo::isVGPRSpill
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:609
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:86
llvm::SIInstrInfo::getMCOpcodeFromPseudo
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1020
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SIInstrInfo::isAtomicNoRet
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:563
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::SIInstrInfo::legalizeOperandsVOP2
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition: SIInstrInfo.cpp:5052
llvm::SIInstrInfo::getMachineCSELookAheadLimit
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:345
llvm::SIInstrInfo::isSegmentSpecificFLAT
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:524
llvm::AMDGPU::getAddr64Inst
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
llvm::SIInstrInfo::getVALUOp
unsigned getVALUOp(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4665
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:370
llvm::getRegSequenceSubReg
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
Definition: SIInstrInfo.cpp:7951
llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SIInstrInfo.cpp:3178
llvm::SIInstrInfo::expandMovDPP64
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2170
llvm::SIInstrInfo::buildExtractSubRegOrImm
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4889
llvm::AMDGPU::getIfAddr64Inst
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
llvm::SIInstrInfo::isStackAccess
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7372
llvm::SIInstrInfo::getRegisterInfo
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:178
llvm::SIInstrInfo::getPreferredSelectRegClass
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
Definition: SIInstrInfo.cpp:1114
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:108
llvm::SIInstrInfo::isMTBUF
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:474
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIInstrInfo::isLDSDIR
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:673
llvm::SIInstrInfo::isSMRD
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:486
llvm::SIInstrInfo::buildShrunkInst
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
Definition: SIInstrInfo.cpp:3852
llvm::SIInstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7642
llvm::SIInstrInfo::isFLATScratch
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:546
llvm::SIInstrInfo::getDSShaderTypeValue
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
Definition: SIInstrInfo.cpp:8203
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y
@ LOCAL_SIZE_Y
Definition: SIInstrInfo.h:1296
llvm::SIInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SIInstrInfo.cpp:8149
llvm::SIInstrInfo::SIInstrInfo
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:68
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:114
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:432
llvm::SIInstrInfo::isDOT
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:665
llvm::SIInstrInfo
Definition: SIInstrInfo.h:43
llvm::AMDGPU::RSRC_TID_ENABLE
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1280
AA
llvm::SIInstrInfo::usesFPDPRounding
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:739
llvm::SIInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SIInstrInfo.cpp:2622
llvm::SIInstrInfo::legalizeOperandsSMRD
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5292
llvm::SI::KernelInputOffsets::NGROUPS_X
@ NGROUPS_X
Definition: SIInstrInfo.h:1289
llvm::SIInstrInfo::getDefaultRsrcDataFormat
uint64_t getDefaultRsrcDataFormat() const
Definition: SIInstrInfo.cpp:7312
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:126
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(unsigned Opc) const
Definition: SIInstrInfo.cpp:1039
llvm::AMDGPU::getBasicFromSDWAOp
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:828
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
llvm::SIInstrInfo::isSOPP
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:410
llvm::SIInstrInfo::isLegalRegOperand
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
Definition: SIInstrInfo.cpp:4918
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z
@ GLOBAL_SIZE_Z
Definition: SIInstrInfo.h:1294
llvm::SIInstrInfo::usesFPDPRounding
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:735
llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1279
llvm::SIInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
Definition: SIInstrInfo.cpp:521
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:76
llvm::SIInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: SIInstrInfo.cpp:2385
llvm::SIInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
Definition: SIInstrInfo.cpp:8225
llvm::SIInstrInfo::isFLATGlobal
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:534
llvm::SIInstrInfo::MO_GOTPCREL32_HI
@ MO_GOTPCREL32_HI
Definition: SIInstrInfo.h:163
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z
@ LOCAL_SIZE_Z
Definition: SIInstrInfo.h:1297
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:362
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:63
llvm::SIInstrInfo::isLiteralConstantLike
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.cpp:3689
llvm::SIInstrInfo::isFPAtomic
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:747
llvm::SIInstrInfo::isWQM
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:589
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:838
llvm::SIInstrInfo::getNamedOperand
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1001
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:148
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X
@ GLOBAL_SIZE_X
Definition: SIInstrInfo.h:1292
llvm::SIInstrInfo::isLegalVSrcOperand
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
Definition: SIInstrInfo.cpp:4945
llvm::SIInstrInfo::getOpRegClass
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Definition: SIInstrInfo.cpp:4813
llvm::SIInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1511
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SIInstrInfo::materializeImmediate
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
Definition: SIInstrInfo.cpp:1057
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::SIInstrInfo::readlaneVGPRToSGPR
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
Definition: SIInstrInfo.cpp:5250
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:30
llvm::SIInstrInfo::isVGPRCopy
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:751
llvm::SIInstrInfo::isSGPRStackAccess
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7385
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:77
llvm::SIInstrInfo::isEXP
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:559
llvm::SIInstrInfo::isTRANS
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:629
llvm::SIInstrInfo::isAtomicRet
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:575
llvm::SIInstrInfo::getSubtarget
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:182
llvm::SIInstrInfo::isPacked
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:422
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:518
llvm::SIInstrInfo::insertEQ
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1244
llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1278
llvm::SIInstrInfo::isLDSDIR
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:669
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1288
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:811
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::isOfRegClass
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1156
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIInstrInfo::getRegClass
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:4782
llvm::SIInstrInfo::hasModifiersSet
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:3772
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:117
llvm::SIInstrInfo::mayReadEXEC
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
Definition: SIInstrInfo.cpp:3560
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SIInstrInfo::getKillTerminatorFromPseudo
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Definition: SIInstrInfo.cpp:7703
SIRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SIInstrInfo::isSOPC
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:398
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:149
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:33
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIInstrInfo::getIndirectGPRIDXPseudo
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
Definition: SIInstrInfo.cpp:1285
llvm::AMDGPU::getVCMPXOpFromVCMP
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
llvm::SIInstrInfo::pseudoToMCOpcode
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Definition: SIInstrInfo.cpp:7881
llvm::AMDGPU::getGlobalVaddrOp
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isVINTRP
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:645
llvm::SIInstrInfo::isSOP1
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:382
llvm::SIInstrInfo::legalizeOperandsVOP3
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Definition: SIInstrInfo.cpp:5164
SetVector.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
AMDGPUBaseInfo.h
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:792
llvm::SIInstrInfo::getInstBundleSize
unsigned getInstBundleSize(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7421