LLVM  14.0.0git
SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 class SIInstrInfo final : public AMDGPUGenInstrInfo {
39 private:
40  const SIRegisterInfo RI;
41  const GCNSubtarget &ST;
42  TargetSchedModel SchedModel;
43  mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
44 
45  // The inverse predicate should have the negative value.
46  enum BranchPredicate {
47  INVALID_BR = 0,
48  SCC_TRUE = 1,
49  SCC_FALSE = -1,
50  VCCNZ = 2,
51  VCCZ = -2,
52  EXECNZ = -3,
53  EXECZ = 3
54  };
55 
57 
58  static unsigned getBranchOpcode(BranchPredicate Cond);
59  static BranchPredicate getBranchPredicate(unsigned Opcode);
60 
61 public:
64  MachineOperand &SuperReg,
65  const TargetRegisterClass *SuperRC,
66  unsigned SubIdx,
67  const TargetRegisterClass *SubRC) const;
70  MachineOperand &SuperReg,
71  const TargetRegisterClass *SuperRC,
72  unsigned SubIdx,
73  const TargetRegisterClass *SubRC) const;
74 private:
75  void swapOperands(MachineInstr &Inst) const;
76 
77  std::pair<bool, MachineBasicBlock *>
78  moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
79  MachineDominatorTree *MDT = nullptr) const;
80 
81  void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
82  MachineDominatorTree *MDT = nullptr) const;
83 
84  void lowerScalarAbs(SetVectorType &Worklist,
85  MachineInstr &Inst) const;
86 
87  void lowerScalarXnor(SetVectorType &Worklist,
88  MachineInstr &Inst) const;
89 
90  void splitScalarNotBinop(SetVectorType &Worklist,
91  MachineInstr &Inst,
92  unsigned Opcode) const;
93 
94  void splitScalarBinOpN2(SetVectorType &Worklist,
95  MachineInstr &Inst,
96  unsigned Opcode) const;
97 
98  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
99  MachineInstr &Inst, unsigned Opcode,
100  bool Swap = false) const;
101 
102  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
103  MachineDominatorTree *MDT = nullptr) const;
104 
105  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
106  unsigned Opcode,
107  MachineDominatorTree *MDT = nullptr) const;
108 
109  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
110  MachineDominatorTree *MDT = nullptr) const;
111 
112  void splitScalar64BitBCNT(SetVectorType &Worklist,
113  MachineInstr &Inst) const;
114  void splitScalar64BitBFE(SetVectorType &Worklist,
115  MachineInstr &Inst) const;
116  void movePackToVALU(SetVectorType &Worklist,
118  MachineInstr &Inst) const;
119 
120  void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
121  SetVectorType &Worklist) const;
122 
123  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
124  MachineInstr &SCCDefInst,
125  SetVectorType &Worklist) const;
126  void addSCCDefsToVALUWorklist(MachineOperand &Op,
127  SetVectorType &Worklist) const;
128 
129  const TargetRegisterClass *
130  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
131 
132  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
133  const MachineInstr &MIb) const;
134 
135  Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
136 
137 protected:
139  MachineOperand &Src0, unsigned Src0OpName,
140  MachineOperand &Src1, unsigned Src1OpName) const;
141 
143  unsigned OpIdx0,
144  unsigned OpIdx1) const override;
145 
146 public:
148  MO_MASK = 0xf,
149 
150  MO_NONE = 0,
151  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
153  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
156  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
158  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
159  MO_REL32 = 4,
161  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
163 
165 
168  };
169 
170  explicit SIInstrInfo(const GCNSubtarget &ST);
171 
173  return RI;
174  }
175 
176  const GCNSubtarget &getSubtarget() const {
177  return ST;
178  }
179 
181  AAResults *AA) const override;
182 
183  bool isIgnorableUse(const MachineOperand &MO) const override;
184 
185  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
186  int64_t &Offset1,
187  int64_t &Offset2) const override;
188 
190  const MachineInstr &LdSt,
192  bool &OffsetIsScalable, unsigned &Width,
193  const TargetRegisterInfo *TRI) const final;
194 
197  unsigned NumLoads, unsigned NumBytes) const override;
198 
199  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
200  int64_t Offset1, unsigned NumLoads) const override;
201 
203  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
204  bool KillSrc) const override;
205 
208  const DebugLoc &DL,
209  unsigned DestReg,
210  int64_t Value) const;
211 
213  unsigned Size) const;
214 
217  Register SrcReg, int Value) const;
218 
221  Register SrcReg, int Value) const;
222 
225  bool isKill, int FrameIndex,
226  const TargetRegisterClass *RC,
227  const TargetRegisterInfo *TRI) const override;
228 
231  int FrameIndex, const TargetRegisterClass *RC,
232  const TargetRegisterInfo *TRI) const override;
233 
234  bool expandPostRAPseudo(MachineInstr &MI) const override;
235 
236  // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
237  // instructions. Returns a pair of generated instructions.
238  // Can split either post-RA with physical registers or pre-RA with
239  // virtual registers. In latter case IR needs to be in SSA form and
240  // and a REG_SEQUENCE is produced to define original register.
241  std::pair<MachineInstr*, MachineInstr*>
243 
244  // Returns an opcode that can be used to move a value to a \p DstRC
245  // register. If there is no hardware instruction that can store to \p
246  // DstRC, then AMDGPU::COPY is returned.
247  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
248 
249  const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
250  unsigned EltSize,
251  bool IsSGPR) const;
252 
253  const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
254  bool IsIndirectSrc) const;
256  int commuteOpcode(unsigned Opc) const;
257 
259  inline int commuteOpcode(const MachineInstr &MI) const {
260  return commuteOpcode(MI.getOpcode());
261  }
262 
263  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
264  unsigned &SrcOpIdx2) const override;
265 
266  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
267  unsigned & SrcOpIdx1) const;
268 
269  bool isBranchOffsetInRange(unsigned BranchOpc,
270  int64_t BrOffset) const override;
271 
272  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
273 
275  MachineBasicBlock &NewDestBB,
276  const DebugLoc &DL,
277  int64_t BrOffset,
278  RegScavenger *RS = nullptr) const override;
279 
282  MachineBasicBlock *&TBB,
283  MachineBasicBlock *&FBB,
285  bool AllowModify) const;
286 
288  MachineBasicBlock *&FBB,
290  bool AllowModify = false) const override;
291 
293  int *BytesRemoved = nullptr) const override;
294 
297  const DebugLoc &DL,
298  int *BytesAdded = nullptr) const override;
299 
301  SmallVectorImpl<MachineOperand> &Cond) const override;
302 
305  Register TrueReg, Register FalseReg, int &CondCycles,
306  int &TrueCycles, int &FalseCycles) const override;
307 
311  Register TrueReg, Register FalseReg) const override;
312 
316  Register TrueReg, Register FalseReg) const;
317 
319  unsigned Kind) const override;
320 
321  bool
323  const MachineInstr &MIb) const override;
324 
325  bool isFoldableCopy(const MachineInstr &MI) const;
326 
328  MachineRegisterInfo *MRI) const final;
329 
330  unsigned getMachineCSELookAheadLimit() const override { return 500; }
331 
333  MachineInstr &MI,
334  LiveVariables *LV) const override;
335 
337  const MachineBasicBlock *MBB,
338  const MachineFunction &MF) const override;
339 
340  static bool isSALU(const MachineInstr &MI) {
341  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
342  }
343 
344  bool isSALU(uint16_t Opcode) const {
345  return get(Opcode).TSFlags & SIInstrFlags::SALU;
346  }
347 
348  static bool isVALU(const MachineInstr &MI) {
349  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
350  }
351 
352  bool isVALU(uint16_t Opcode) const {
353  return get(Opcode).TSFlags & SIInstrFlags::VALU;
354  }
355 
356  static bool isVMEM(const MachineInstr &MI) {
357  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
358  }
359 
360  bool isVMEM(uint16_t Opcode) const {
361  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
362  }
363 
364  static bool isSOP1(const MachineInstr &MI) {
365  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
366  }
367 
368  bool isSOP1(uint16_t Opcode) const {
369  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
370  }
371 
372  static bool isSOP2(const MachineInstr &MI) {
373  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
374  }
375 
376  bool isSOP2(uint16_t Opcode) const {
377  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
378  }
379 
380  static bool isSOPC(const MachineInstr &MI) {
381  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
382  }
383 
384  bool isSOPC(uint16_t Opcode) const {
385  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
386  }
387 
388  static bool isSOPK(const MachineInstr &MI) {
389  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
390  }
391 
392  bool isSOPK(uint16_t Opcode) const {
393  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
394  }
395 
396  static bool isSOPP(const MachineInstr &MI) {
397  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
398  }
399 
400  bool isSOPP(uint16_t Opcode) const {
401  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
402  }
403 
404  static bool isPacked(const MachineInstr &MI) {
405  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
406  }
407 
408  bool isPacked(uint16_t Opcode) const {
409  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
410  }
411 
412  static bool isVOP1(const MachineInstr &MI) {
413  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
414  }
415 
416  bool isVOP1(uint16_t Opcode) const {
417  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
418  }
419 
420  static bool isVOP2(const MachineInstr &MI) {
421  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
422  }
423 
424  bool isVOP2(uint16_t Opcode) const {
425  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
426  }
427 
428  static bool isVOP3(const MachineInstr &MI) {
429  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
430  }
431 
432  bool isVOP3(uint16_t Opcode) const {
433  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
434  }
435 
436  static bool isSDWA(const MachineInstr &MI) {
437  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
438  }
439 
440  bool isSDWA(uint16_t Opcode) const {
441  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
442  }
443 
444  static bool isVOPC(const MachineInstr &MI) {
445  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
446  }
447 
448  bool isVOPC(uint16_t Opcode) const {
449  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
450  }
451 
452  static bool isMUBUF(const MachineInstr &MI) {
453  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
454  }
455 
456  bool isMUBUF(uint16_t Opcode) const {
457  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
458  }
459 
460  static bool isMTBUF(const MachineInstr &MI) {
461  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
462  }
463 
464  bool isMTBUF(uint16_t Opcode) const {
465  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
466  }
467 
468  static bool isSMRD(const MachineInstr &MI) {
469  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
470  }
471 
472  bool isSMRD(uint16_t Opcode) const {
473  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
474  }
475 
476  bool isBufferSMRD(const MachineInstr &MI) const;
477 
478  static bool isDS(const MachineInstr &MI) {
479  return MI.getDesc().TSFlags & SIInstrFlags::DS;
480  }
481 
482  bool isDS(uint16_t Opcode) const {
483  return get(Opcode).TSFlags & SIInstrFlags::DS;
484  }
485 
486  bool isAlwaysGDS(uint16_t Opcode) const;
487 
488  static bool isMIMG(const MachineInstr &MI) {
489  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
490  }
491 
492  bool isMIMG(uint16_t Opcode) const {
493  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
494  }
495 
496  static bool isGather4(const MachineInstr &MI) {
497  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
498  }
499 
500  bool isGather4(uint16_t Opcode) const {
501  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
502  }
503 
504  static bool isFLAT(const MachineInstr &MI) {
505  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
506  }
507 
508  // Is a FLAT encoded instruction which accesses a specific segment,
509  // i.e. global_* or scratch_*.
510  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
511  auto Flags = MI.getDesc().TSFlags;
513  }
514 
515  bool isSegmentSpecificFLAT(uint16_t Opcode) const {
516  auto Flags = get(Opcode).TSFlags;
518  }
519 
520  static bool isFLATGlobal(const MachineInstr &MI) {
521  return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
522  }
523 
524  bool isFLATGlobal(uint16_t Opcode) const {
525  return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
526  }
527 
528  static bool isFLATScratch(const MachineInstr &MI) {
529  return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
530  }
531 
532  bool isFLATScratch(uint16_t Opcode) const {
533  return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
534  }
535 
536  // Any FLAT encoded instruction, including global_* and scratch_*.
537  bool isFLAT(uint16_t Opcode) const {
538  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
539  }
540 
541  static bool isEXP(const MachineInstr &MI) {
542  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
543  }
544 
545  bool isEXP(uint16_t Opcode) const {
546  return get(Opcode).TSFlags & SIInstrFlags::EXP;
547  }
548 
549  static bool isAtomicNoRet(const MachineInstr &MI) {
550  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
551  }
552 
553  bool isAtomicNoRet(uint16_t Opcode) const {
554  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
555  }
556 
557  static bool isAtomicRet(const MachineInstr &MI) {
558  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
559  }
560 
561  bool isAtomicRet(uint16_t Opcode) const {
562  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
563  }
564 
565  static bool isAtomic(const MachineInstr &MI) {
566  return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
568  }
569 
570  bool isAtomic(uint16_t Opcode) const {
571  return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
573  }
574 
575  static bool isWQM(const MachineInstr &MI) {
576  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
577  }
578 
579  bool isWQM(uint16_t Opcode) const {
580  return get(Opcode).TSFlags & SIInstrFlags::WQM;
581  }
582 
583  static bool isDisableWQM(const MachineInstr &MI) {
584  return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
585  }
586 
587  bool isDisableWQM(uint16_t Opcode) const {
588  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
589  }
590 
591  static bool isVGPRSpill(const MachineInstr &MI) {
592  return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
593  }
594 
595  bool isVGPRSpill(uint16_t Opcode) const {
596  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
597  }
598 
599  static bool isSGPRSpill(const MachineInstr &MI) {
600  return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
601  }
602 
603  bool isSGPRSpill(uint16_t Opcode) const {
604  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
605  }
606 
607  static bool isDPP(const MachineInstr &MI) {
608  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
609  }
610 
611  bool isDPP(uint16_t Opcode) const {
612  return get(Opcode).TSFlags & SIInstrFlags::DPP;
613  }
614 
615  static bool isTRANS(const MachineInstr &MI) {
616  return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
617  }
618 
619  bool isTRANS(uint16_t Opcode) const {
620  return get(Opcode).TSFlags & SIInstrFlags::TRANS;
621  }
622 
623  static bool isVOP3P(const MachineInstr &MI) {
624  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
625  }
626 
627  bool isVOP3P(uint16_t Opcode) const {
628  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
629  }
630 
631  static bool isVINTRP(const MachineInstr &MI) {
632  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
633  }
634 
635  bool isVINTRP(uint16_t Opcode) const {
636  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
637  }
638 
639  static bool isMAI(const MachineInstr &MI) {
640  return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
641  }
642 
643  bool isMAI(uint16_t Opcode) const {
644  return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
645  }
646 
647  static bool isDOT(const MachineInstr &MI) {
648  return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
649  }
650 
651  bool isDOT(uint16_t Opcode) const {
652  return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
653  }
654 
655  static bool isScalarUnit(const MachineInstr &MI) {
656  return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
657  }
658 
659  static bool usesVM_CNT(const MachineInstr &MI) {
660  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
661  }
662 
663  static bool usesLGKM_CNT(const MachineInstr &MI) {
664  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
665  }
666 
667  static bool sopkIsZext(const MachineInstr &MI) {
668  return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
669  }
670 
671  bool sopkIsZext(uint16_t Opcode) const {
672  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
673  }
674 
675  /// \returns true if this is an s_store_dword* instruction. This is more
676  /// specific than than isSMEM && mayStore.
677  static bool isScalarStore(const MachineInstr &MI) {
678  return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
679  }
680 
681  bool isScalarStore(uint16_t Opcode) const {
682  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
683  }
684 
685  static bool isFixedSize(const MachineInstr &MI) {
686  return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
687  }
688 
689  bool isFixedSize(uint16_t Opcode) const {
690  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
691  }
692 
693  static bool hasFPClamp(const MachineInstr &MI) {
694  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
695  }
696 
697  bool hasFPClamp(uint16_t Opcode) const {
698  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
699  }
700 
701  static bool hasIntClamp(const MachineInstr &MI) {
702  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
703  }
704 
706  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
710  return MI.getDesc().TSFlags & ClampFlags;
711  }
712 
713  static bool usesFPDPRounding(const MachineInstr &MI) {
714  return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
715  }
716 
717  bool usesFPDPRounding(uint16_t Opcode) const {
718  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
719  }
720 
721  static bool isFPAtomic(const MachineInstr &MI) {
722  return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
723  }
724 
725  bool isFPAtomic(uint16_t Opcode) const {
726  return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
727  }
728 
729  bool isVGPRCopy(const MachineInstr &MI) const {
730  assert(MI.isCopy());
731  Register Dest = MI.getOperand(0).getReg();
732  const MachineFunction &MF = *MI.getParent()->getParent();
733  const MachineRegisterInfo &MRI = MF.getRegInfo();
734  return !RI.isSGPRReg(MRI, Dest);
735  }
736 
737  bool hasVGPRUses(const MachineInstr &MI) const {
738  const MachineFunction &MF = *MI.getParent()->getParent();
739  const MachineRegisterInfo &MRI = MF.getRegInfo();
740  return llvm::any_of(MI.explicit_uses(),
741  [&MRI, this](const MachineOperand &MO) {
742  return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
743  }
744 
745  /// Return true if the instruction modifies the mode register.q
746  static bool modifiesModeRegister(const MachineInstr &MI);
747 
748  /// Whether we must prevent this instruction from executing with EXEC = 0.
750 
751  /// Returns true if the instruction could potentially depend on the value of
752  /// exec. If false, exec dependencies may safely be ignored.
753  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
754 
755  bool isInlineConstant(const APInt &Imm) const;
756 
757  bool isInlineConstant(const APFloat &Imm) const {
758  return isInlineConstant(Imm.bitcastToAPInt());
759  }
760 
761  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
762 
764  const MCOperandInfo &OpInfo) const {
765  return isInlineConstant(MO, OpInfo.OperandType);
766  }
767 
768  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
769  /// be an inline immediate.
771  const MachineOperand &UseMO,
772  const MachineOperand &DefMO) const {
773  assert(UseMO.getParent() == &MI);
774  int OpIdx = MI.getOperandNo(&UseMO);
775  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
776  return false;
777  }
778 
779  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
780  }
781 
782  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
783  /// immediate.
784  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
785  const MachineOperand &MO = MI.getOperand(OpIdx);
786  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
787  }
788 
789  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
790  const MachineOperand &MO) const {
791  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
792  return false;
793 
794  if (MI.isCopy()) {
795  unsigned Size = getOpSize(MI, OpIdx);
796  assert(Size == 8 || Size == 4);
797 
798  uint8_t OpType = (Size == 8) ?
800  return isInlineConstant(MO, OpType);
801  }
802 
803  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
804  }
805 
806  bool isInlineConstant(const MachineOperand &MO) const {
807  const MachineInstr *Parent = MO.getParent();
808  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
809  }
810 
812  const MCOperandInfo &OpInfo) const {
813  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
814  }
815 
816  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
817  const MachineOperand &MO = MI.getOperand(OpIdx);
818  return MO.isImm() && !isInlineConstant(MI, OpIdx);
819  }
820 
821  // Returns true if this operand could potentially require a 32-bit literal
822  // operand, but not necessarily. A FrameIndex for example could resolve to an
823  // inline immediate value that will not require an additional 4-bytes; this
824  // assumes that it will.
825  bool isLiteralConstantLike(const MachineOperand &MO,
826  const MCOperandInfo &OpInfo) const;
827 
828  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
829  const MachineOperand &MO) const;
830 
831  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
832  /// This function will return false if you pass it a 32-bit instruction.
833  bool hasVALU32BitEncoding(unsigned Opcode) const;
834 
835  /// Returns true if this operand uses the constant bus.
837  const MachineOperand &MO,
838  const MCOperandInfo &OpInfo) const;
839 
840  /// Return true if this instruction has any modifiers.
841  /// e.g. src[012]_mod, omod, clamp.
842  bool hasModifiers(unsigned Opcode) const;
843 
844  bool hasModifiersSet(const MachineInstr &MI,
845  unsigned OpName) const;
846  bool hasAnyModifiersSet(const MachineInstr &MI) const;
847 
848  bool canShrink(const MachineInstr &MI,
849  const MachineRegisterInfo &MRI) const;
850 
852  unsigned NewOpcode) const;
853 
854  bool verifyInstruction(const MachineInstr &MI,
855  StringRef &ErrInfo) const override;
856 
857  unsigned getVALUOp(const MachineInstr &MI) const;
858 
859  /// Return the correct register class for \p OpNo. For target-specific
860  /// instructions, this will return the register class that has been defined
861  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
862  /// the register class of its machine operand.
863  /// to infer the correct register class base on the other operands.
865  unsigned OpNo) const;
866 
867  /// Return the size in bytes of the operand OpNo on the given
868  // instruction opcode.
869  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
870  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
871 
872  if (OpInfo.RegClass == -1) {
873  // If this is an immediate operand, this must be a 32-bit literal.
875  return 4;
876  }
877 
878  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
879  }
880 
881  /// This form should usually be preferred since it handles operands
882  /// with unknown register classes.
883  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
884  const MachineOperand &MO = MI.getOperand(OpNo);
885  if (MO.isReg()) {
886  if (unsigned SubReg = MO.getSubReg()) {
887  return RI.getSubRegIdxSize(SubReg) / 8;
888  }
889  }
890  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
891  }
892 
893  /// Legalize the \p OpIndex operand of this instruction by inserting
894  /// a MOV. For example:
895  /// ADD_I32_e32 VGPR0, 15
896  /// to
897  /// MOV VGPR1, 15
898  /// ADD_I32_e32 VGPR0, VGPR1
899  ///
900  /// If the operand being legalized is a register, then a COPY will be used
901  /// instead of MOV.
902  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
903 
904  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
905  /// for \p MI.
906  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
907  const MachineOperand *MO = nullptr) const;
908 
909  /// Check if \p MO would be a valid operand for the given operand
910  /// definition \p OpInfo. Note this does not attempt to validate constant bus
911  /// restrictions (e.g. literal constant usage).
913  const MCOperandInfo &OpInfo,
914  const MachineOperand &MO) const;
915 
916  /// Check if \p MO (a register operand) is a legal register for the
917  /// given operand description.
919  const MCOperandInfo &OpInfo,
920  const MachineOperand &MO) const;
921 
922  /// Legalize operands in \p MI by either commuting it or inserting a
923  /// copy of src1.
925 
926  /// Fix operands in \p MI to satisfy constant bus requirements.
928 
929  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
930  /// be used when it is know that the value in SrcReg is same across all
931  /// threads in the wave.
932  /// \returns The SGPR register that \p SrcReg was copied to.
934  MachineRegisterInfo &MRI) const;
935 
938 
941  const TargetRegisterClass *DstRC,
943  const DebugLoc &DL) const;
944 
945  /// Legalize all operands in this instruction. This function may create new
946  /// instructions and control-flow around \p MI. If present, \p MDT is
947  /// updated.
948  /// \returns A new basic block that contains \p MI if new blocks were created.
950  legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
951 
952  /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
953  /// was moved to VGPR. \returns true if succeeded.
954  bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
955 
956  /// Replace this instruction's opcode with the equivalent VALU
957  /// opcode. This function will also move the users of \p MI to the
958  /// VALU if necessary. If present, \p MDT is updated.
960  MachineDominatorTree *MDT = nullptr) const;
961 
963  MachineBasicBlock::iterator MI) const override;
964 
966  unsigned Quantity) const override;
967 
968  void insertReturn(MachineBasicBlock &MBB) const;
969  /// Return the number of wait states that result from executing this
970  /// instruction.
971  static unsigned getNumWaitStates(const MachineInstr &MI);
972 
973  /// Returns the operand named \p Op. If \p MI does not have an
974  /// operand named \c Op, this function returns nullptr.
976  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
977 
980  unsigned OpName) const {
981  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
982  }
983 
984  /// Get required immediate operand
985  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
986  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
987  return MI.getOperand(Idx).getImm();
988  }
989 
992 
993  bool isLowLatencyInstruction(const MachineInstr &MI) const;
994  bool isHighLatencyDef(int Opc) const override;
995 
996  /// Return the descriptor of the target-specific machine instruction
997  /// that corresponds to the specified pseudo or native opcode.
998  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
999  return get(pseudoToMCOpcode(Opcode));
1000  }
1001 
1002  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1003  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1004 
1005  unsigned isLoadFromStackSlot(const MachineInstr &MI,
1006  int &FrameIndex) const override;
1007  unsigned isStoreToStackSlot(const MachineInstr &MI,
1008  int &FrameIndex) const override;
1009 
1010  unsigned getInstBundleSize(const MachineInstr &MI) const;
1011  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1012 
1013  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1014 
1015  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1016 
1018  MachineBasicBlock *IfEnd) const;
1019 
1021  MachineBasicBlock *LoopEnd) const;
1022 
1023  std::pair<unsigned, unsigned>
1024  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1025 
1027  getSerializableTargetIndices() const override;
1028 
1031 
1034  const ScheduleDAG *DAG) const override;
1035 
1037  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1038 
1039  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1040 
1043  const DebugLoc &DL, Register Src,
1044  Register Dst) const override;
1045 
1048  const DebugLoc &DL, Register Src,
1049  unsigned SrcSubReg,
1050  Register Dst) const override;
1051 
1052  bool isWave32() const;
1053 
1054  /// Return a partially built integer add instruction without carry.
1055  /// Caller must add source operands.
1056  /// For pre-GFX9 it will generate unused carry destination operand.
1057  /// TODO: After GFX9 it should return a no-carry operation.
1060  const DebugLoc &DL,
1061  Register DestReg) const;
1062 
1065  const DebugLoc &DL,
1066  Register DestReg,
1067  RegScavenger &RS) const;
1068 
1069  static bool isKillTerminator(unsigned Opcode);
1070  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1071 
1072  static bool isLegalMUBUFImmOffset(unsigned Imm) {
1073  return isUInt<12>(Imm);
1074  }
1075 
1076  /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1077  /// encoded instruction. If \p Signed, this is for an instruction that
1078  /// interprets the offset as signed.
1079  bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1080  uint64_t FlatVariant) const;
1081 
1082  /// Split \p COffsetVal into {immediate offset field, remainder offset}
1083  /// values.
1084  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1085  unsigned AddrSpace,
1086  uint64_t FlatVariant) const;
1087 
1088  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1089  /// Return -1 if the target-specific opcode for the pseudo instruction does
1090  /// not exist. If Opcode is not a pseudo instruction, this is identity.
1091  int pseudoToMCOpcode(int Opcode) const;
1092 
1093  /// \brief Check if this instruction should only be used by assembler.
1094  /// Return true if this opcode should not be used by codegen.
1095  bool isAsmOnlyOpcode(int MCOp) const;
1096 
1097  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1098  const TargetRegisterInfo *TRI,
1099  const MachineFunction &MF)
1100  const override;
1101 
1102  void fixImplicitOperands(MachineInstr &MI) const;
1103 
1105  ArrayRef<unsigned> Ops,
1106  MachineBasicBlock::iterator InsertPt,
1107  int FrameIndex,
1108  LiveIntervals *LIS = nullptr,
1109  VirtRegMap *VRM = nullptr) const override;
1110 
1111  unsigned getInstrLatency(const InstrItineraryData *ItinData,
1112  const MachineInstr &MI,
1113  unsigned *PredCost = nullptr) const override;
1114 
1115  const MIRFormatter *getMIRFormatter() const override {
1116  if (!Formatter.get())
1117  Formatter = std::make_unique<AMDGPUMIRFormatter>();
1118  return Formatter.get();
1119  }
1120 
1121  static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1122 };
1123 
1124 /// \brief Returns true if a reg:subreg pair P has a TRC class
1126  const TargetRegisterClass &TRC,
1128  auto *RC = MRI.getRegClass(P.Reg);
1129  if (!P.SubReg)
1130  return RC == &TRC;
1131  auto *TRI = MRI.getTargetRegisterInfo();
1132  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1133 }
1134 
1135 /// \brief Create RegSubRegPair from a register MachineOperand
1136 inline
1138  assert(O.isReg());
1139  return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1140 }
1141 
1142 /// \brief Return the SubReg component from REG_SEQUENCE
1144  unsigned SubReg);
1145 
1146 /// \brief Return the defining instruction for a given reg:subreg pair
1147 /// skipping copy like instructions and subreg-manipulation pseudos.
1148 /// Following another subreg of a reg:subreg isn't supported.
1150  MachineRegisterInfo &MRI);
1151 
1152 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1153 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1154 /// attempt to track between blocks.
1155 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1156  Register VReg,
1157  const MachineInstr &DefMI,
1158  const MachineInstr &UseMI);
1159 
1160 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1161 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1162 /// track between blocks.
1163 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1164  Register VReg,
1165  const MachineInstr &DefMI);
1166 
1167 namespace AMDGPU {
1168 
1170  int getVOPe64(uint16_t Opcode);
1171 
1173  int getVOPe32(uint16_t Opcode);
1174 
1176  int getSDWAOp(uint16_t Opcode);
1177 
1179  int getDPPOp32(uint16_t Opcode);
1180 
1182  int getBasicFromSDWAOp(uint16_t Opcode);
1183 
1185  int getCommuteRev(uint16_t Opcode);
1186 
1188  int getCommuteOrig(uint16_t Opcode);
1189 
1191  int getAddr64Inst(uint16_t Opcode);
1192 
1193  /// Check if \p Opcode is an Addr64 opcode.
1194  ///
1195  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1197  int getIfAddr64Inst(uint16_t Opcode);
1198 
1200  int getMUBUFNoLdsInst(uint16_t Opcode);
1201 
1203  int getAtomicNoRetOp(uint16_t Opcode);
1204 
1206  int getSOPKOp(uint16_t Opcode);
1207 
1208  /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1209  /// of a VADDR form.
1211  int getGlobalSaddrOp(uint16_t Opcode);
1212 
1213  /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1214  /// of a SADDR form.
1216  int getGlobalVaddrOp(uint16_t Opcode);
1217 
1219  int getVCMPXNoSDstOp(uint16_t Opcode);
1220 
1221  /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1222  /// given an \p Opcode of an SS (SADDR) form.
1225 
1226  /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1227  /// of an SV (VADDR) form.
1230 
1231  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1232  /// of an SS (SADDR) form.
1235 
1236  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1239  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1240 
1241 } // end namespace AMDGPU
1242 
1243 namespace SI {
1244 namespace KernelInputOffsets {
1245 
1246 /// Offsets in bytes from the start of the input buffer
1247 enum Offsets {
1257 };
1258 
1259 } // end namespace KernelInputOffsets
1260 } // end namespace SI
1261 
1262 } // end namespace llvm
1263 
1264 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SIInstrInfo::isIgnorableUse
bool isIgnorableUse(const MachineOperand &MO) const override
Definition: SIInstrInfo.cpp:127
llvm::AMDGPU::getVCMPXNoSDstOp
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
llvm::SIInstrInfo::isMIMG
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:492
llvm::SIInstrInfo::isMTBUF
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:464
llvm::SIInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SIInstrInfo.cpp:2401
llvm::SIInstrInfo::isAtomicRet
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:557
llvm::SIInstrInfo::insertNoops
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
Definition: SIInstrInfo.cpp:1609
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:112
llvm::SIInstrInfo::isFLAT
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:537
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:61
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:55
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
llvm::SIInstrInfo::isDPP
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:611
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:683
llvm::SIInstrInfo::isFLATGlobal
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:524
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SIInstrInfo::insertNE
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1187
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SIInstrInfo::isDisableWQM
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:587
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:115
llvm::SIInstrInfo::swapSourceModifiers
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
Definition: SIInstrInfo.cpp:2059
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::SIInstrInfo::hasFPClamp
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:693
llvm::SIInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:3232
llvm::SIInstrInfo::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
Definition: SIInstrInfo.cpp:2718
llvm::AMDGPU::getFlatScratchInstSVfromSS
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
llvm::SIInstrInfo::isSGPRSpill
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:599
llvm::SIInstrInfo::isSOP2
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:376
llvm::SIInstrInfo::isFixedSize
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:685
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2445
llvm::SIInstrInfo::isMAI
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:643
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:64
llvm::SIInstrInfo::getClampMask
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:705
llvm::getRegSubRegPair
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1137
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:28
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::AMDGPU::getAtomicNoRetOp
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
llvm::SIInstrInfo::usesLGKM_CNT
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:663
llvm::SIInstrInfo::usesVM_CNT
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:659
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:78
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SIInstrInfo::isVOP3
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:428
llvm::SIInstrInfo::hasVGPRUses
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:737
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y
@ GLOBAL_SIZE_Y
Definition: SIInstrInfo.h:1252
llvm::SIInstrInfo::getMovOpcode
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
Definition: SIInstrInfo.cpp:1200
llvm::SIInstrInfo::isSOPP
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:400
llvm::SIInstrInfo::isBufferSMRD
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7436
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:41
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:100
llvm::SIInstrInfo::getNumWaitStates
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
Definition: SIInstrInfo.cpp:1638
llvm::SIInstrInfo::MO_GOTPCREL32
@ MO_GOTPCREL32
Definition: SIInstrInfo.h:154
llvm::SIInstrInfo::isImmOperandLegal
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
Definition: SIInstrInfo.cpp:3481
llvm::SIInstrInfo::convertNonUniformLoopRegion
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
Definition: SIInstrInfo.cpp:7270
llvm::SIInstrInfo::isHighLatencyDef
bool isHighLatencyDef(int Opc) const override
Definition: SIInstrInfo.cpp:7090
llvm::SIInstrInfo::isDisableWQM
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:583
llvm::SIInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SIInstrInfo.cpp:2531
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SIInstrInfo::analyzeBranchImpl
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: SIInstrInfo.cpp:2358
llvm::SIInstrInfo::isScalarStore
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:677
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::SIInstrInfo::createPHIDestinationCopy
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
Definition: SIInstrInfo.cpp:7810
llvm::SIInstrInfo::isEXP
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:541
llvm::SIInstrInfo::moveToVALU
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Definition: SIInstrInfo.cpp:5757
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SIInstrInfo::modifiesModeRegister
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Definition: SIInstrInfo.cpp:3269
llvm::AMDGPU::getSOPKOp
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
llvm::SIInstrInfo::isSDWA
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:440
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:88
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:67
llvm::SIInstrInfo::isMUBUF
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:456
llvm::AMDGPU::getGlobalSaddrOp
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7130
TargetInstrInfo.h
llvm::SIInstrInfo::isVOP3P
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:623
llvm::SIInstrInfo::isFoldableCopy
bool isFoldableCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2694
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SIInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
Definition: SIInstrInfo.cpp:3096
llvm::SIInstrInfo::isAsmOnlyOpcode
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
Definition: SIInstrInfo.cpp:7568
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::SIInstrInfo::isVGPRSpill
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:591
llvm::SIInstrInfo::MO_MASK
@ MO_MASK
Definition: SIInstrInfo.h:148
llvm::SIInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
Definition: SIInstrInfo.cpp:7331
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:68
llvm::SIInstrInfo::getScratchRsrcWords23
uint64_t getScratchRsrcWords23() const
Definition: SIInstrInfo.cpp:7060
llvm::SIInstrInfo::MO_GOTPCREL
@ MO_GOTPCREL
Definition: SIInstrInfo.h:152
llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
Definition: SIInstrInfo.cpp:1316
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:26
llvm::SIInstrInfo::hasAnyModifiersSet
bool hasAnyModifiersSet(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:3537
llvm::SIInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: SIInstrInfo.cpp:2184
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SIInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: SIInstrInfo.cpp:1604
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:65
llvm::SIInstrInfo::isBasicBlockPrologue
bool isBasicBlockPrologue(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7363
llvm::SIInstrInfo::insertVectorSelect
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Definition: SIInstrInfo.cpp:1048
llvm::SIInstrInfo::isVOP1
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:416
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:51
llvm::SIInstrInfo::fixImplicitOperands
void fixImplicitOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7426
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:477
llvm::SIInstrInfo::isVOPC
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:448
llvm::AMDGPU::getVOPe64
LLVM_READONLY int getVOPe64(uint16_t Opcode)
llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
Definition: SIInstrInfo.cpp:3283
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:37
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:869
llvm::SIInstrInfo::isWave32
bool isWave32() const
Definition: SIInstrInfo.cpp:7845
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:103
llvm::SIInstrInfo::isVOPC
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:444
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::SIInstrInfo::canShrink
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: SIInstrInfo.cpp:3545
llvm::AMDGPU::getCommuteOrig
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:49
llvm::SIInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SIInstrInfo.cpp:654
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:632
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:150
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:48
llvm::SIInstrInfo::MO_GOTPCREL32_LO
@ MO_GOTPCREL32_LO
Definition: SIInstrInfo.h:155
llvm::SIInstrInfo::isMIMG
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
llvm::SIInstrInfo::isSOPK
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:392
llvm::SIInstrInfo::isAtomicNoRet
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:553
llvm::SIInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7156
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APInt &Imm) const
Definition: SIInstrInfo.cpp:3349
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::SIInstrInfo::isSOPC
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:380
llvm::SIInstrInfo::createPHISourceCopy
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Definition: SIInstrInfo.cpp:7825
llvm::SIInstrInfo::isNonUniformBranchInstr
bool isNonUniformBranchInstr(MachineInstr &Instr) const
Definition: SIInstrInfo.cpp:7241
llvm::SIInstrInfo::isMAI
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:639
llvm::SIInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:133
llvm::SIInstrInfo::isSOPK
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:388
llvm::AMDGPU::getFlatScratchInstSSfromSV
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIInstrInfo::isOperandLegal
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition: SIInstrInfo.cpp:4697
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:63
llvm::SIInstrInfo::hasIntClamp
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:701
llvm::AMDGPU::getDPPOp32
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
llvm::AMDGPU::getMUBUFNoLdsInst
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
llvm::AMDGPU::getVOPe32
LLVM_READONLY int getVOPe32(uint16_t Opcode)
AMDGPUMIRFormatter.h
llvm::SIInstrInfo::isVOP3
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:432
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:32
llvm::SIInstrInfo::isSegmentSpecificFLAT
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:515
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: SIInstrInfo.cpp:7318
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:66
OpName
Definition: R600Defines.h:62
llvm::SIInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: SIInstrInfo.cpp:7344
llvm::SIInstrInfo::isGather4
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:500
llvm::SIInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: SIInstrInfo.cpp:7884
llvm::SIInstrInfo::legalizeOperands
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
Definition: SIInstrInfo.cpp:5431
llvm::getVRegSubRegDef
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
Definition: SIInstrInfo.cpp:7686
llvm::SIInstrInfo::moveFlatAddrToVGPR
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
Definition: SIInstrInfo.cpp:5052
llvm::SIInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: SIInstrInfo.cpp:2161
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:43
llvm::SIInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
Definition: SIInstrInfo.cpp:2749
llvm::SIInstrInfo::sopkIsZext
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:667
llvm::SIInstrInfo::isVOP2
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:424
llvm::SIInstrInfo::getNamedOperand
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Definition: SIInstrInfo.cpp:7029
llvm::SIInstrInfo::hasModifiers
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
Definition: SIInstrInfo.cpp:3523
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:34
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::SIInstrInfo::isVOP3P
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:627
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:59
llvm::SIInstrInfo::isGather4
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:496
llvm::SIInstrInfo::MO_REL32
@ MO_REL32
Definition: SIInstrInfo.h:159
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::SIInstrInfo::legalizeGenericOperand
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
Definition: SIInstrInfo.cpp:5151
llvm::AMDGPU::getSDWAOp
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::SIInstrInfo::isScalarUnit
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:655
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:25
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:22
llvm::SIInstrInfo::MO_FAR_BRANCH_OFFSET
@ MO_FAR_BRANCH_OFFSET
Definition: SIInstrInfo.h:164
llvm::SI::KernelInputOffsets::NGROUPS_Z
@ NGROUPS_Z
Definition: SIInstrInfo.h:1250
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIInstrInfo::isVALU
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:352
llvm::SIInstrInfo::MO_ABS32_LO
@ MO_ABS32_LO
Definition: SIInstrInfo.h:166
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::SIInstrInfo::TargetOperandFlags
TargetOperandFlags
Definition: SIInstrInfo.h:147
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:97
llvm::SIInstrInfo::getAddNoCarry
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
Definition: SIInstrInfo.cpp:7369
llvm::SIInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7116
llvm::SIInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: SIInstrInfo.cpp:109
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:757
llvm::SIInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7349
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:29
llvm::APFloat
Definition: APFloat.h:701
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:883
llvm::SIInstrInfo::MO_ABS32_HI
@ MO_ABS32_HI
Definition: SIInstrInfo.h:167
llvm::SIInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SIInstrInfo.cpp:2587
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:179
llvm::SIInstrInfo::isDPP
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:607
llvm::SIInstrInfo::isWQM
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:579
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:109
llvm::SIInstrInfo::isLowLatencyInstruction
bool isLowLatencyInstruction(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7084
TargetSchedule.h
llvm::SIInstrInfo::hasVALU32BitEncoding
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
Definition: SIInstrInfo.cpp:3511
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:27
llvm::SIInstrInfo::getNamedImmOperand
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:985
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:21
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::execMayBeModifiedBeforeAnyUse
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
Definition: SIInstrInfo.cpp:7754
uint64_t
llvm::SIInstrInfo::insertIndirectBranch
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
Definition: SIInstrInfo.cpp:2211
llvm::SIInstrInfo::hasFPClamp
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:697
llvm::SI::KernelInputOffsets::LOCAL_SIZE_X
@ LOCAL_SIZE_X
Definition: SIInstrInfo.h:1254
llvm::SIInstrInfo::getMIRFormatter
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1115
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:42
llvm::SIInstrInfo::buildExtractSubReg
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4598
llvm::SIInstrInfo::sopkIsZext
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:671
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
llvm::SIInstrInfo::isDS
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:478
llvm::SIInstrInfo::isDS
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:482
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2145
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:468
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::execMayBeModifiedBeforeUse
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
Definition: SIInstrInfo.cpp:7721
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIInstrInfo::isLegalFLATOffset
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
Definition: SIInstrInfo.cpp:7479
llvm::SIInstrInfo::legalizeOperandsFLAT
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5133
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:56
llvm::SIInstrInfo::isSOP2
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:372
llvm::SIInstrInfo::isScalarStore
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:681
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:101
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:38
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInstrInfo::MO_REL32_LO
@ MO_REL32_LO
Definition: SIInstrInfo.h:160
llvm::SIInstrInfo::isAlwaysGDS
bool isAlwaysGDS(uint16_t Opcode) const
Definition: SIInstrInfo.cpp:3259
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::SIInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:2200
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:784
llvm::SIInstrInfo::isVMEM
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:360
llvm::SIInstrInfo::isFPAtomic
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:721
llvm::SIInstrInfo::isSGPRSpill
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:603
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:81
llvm::SIInstrInfo::isPacked
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:404
llvm::SIInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1553
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:565
llvm::SIInstrInfo::isSOP1
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:364
llvm::SIInstrInfo::isSALU
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:340
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::SIInstrInfo::insertReturn
void insertReturn(MachineBasicBlock &MBB) const
Definition: SIInstrInfo.cpp:1620
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::SIInstrInfo::mayAccessFlatAddressSpace
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7227
llvm::SIInstrInfo::isVOP1
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:412
llvm::SI::KernelInputOffsets::NGROUPS_Y
@ NGROUPS_Y
Definition: SIInstrInfo.h:1249
llvm::AMDGPU::RSRC_DATA_FORMAT
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1236
llvm::SIInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Definition: SIInstrInfo.cpp:431
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SIInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SIInstrInfo.cpp:2471
llvm::SIInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
Definition: SIInstrInfo.cpp:2545
llvm::SIInstrInfo::MO_REL32_HI
@ MO_REL32_HI
Definition: SIInstrInfo.h:162
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1554
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::SIInstrInfo::usesConstantBus
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
Definition: SIInstrInfo.cpp:3663
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:46
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SIInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3748
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:763
llvm::SIInstrInfo::isFixedSize
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:689
llvm::SIInstrInfo::isSDWA
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:436
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:106
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:94
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIInstrInfo::isSALU
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:344
llvm::SIInstrInfo::isVOP2
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:420
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:259
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:811
AMDGPUGenInstrInfo
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:452
llvm::SIInstrInfo::isAtomic
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:570
llvm::SIInstrInfo::isDOT
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:647
llvm::SIInstrInfo::isVINTRP
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:635
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::SIInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
Definition: SIInstrInfo.cpp:2109
llvm::SIInstrInfo::isKillTerminator
static bool isKillTerminator(unsigned Opcode)
Definition: SIInstrInfo.cpp:7405
llvm::AMDGPU::getCommuteRev
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1072
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::SIInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:1647
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SIInstrInfo::legalizeOpWithMove
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
Definition: SIInstrInfo.cpp:4571
llvm::SIInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
Definition: SIInstrInfo.cpp:248
llvm::SIInstrInfo::isTRANS
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:619
llvm::SIInstrInfo::splitFlatOffset
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition: SIInstrInfo.cpp:7506
llvm::SIInstrInfo::convertNonUniformIfRegion
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
Definition: SIInstrInfo.cpp:7245
llvm::SIInstrInfo::isVGPRSpill
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:595
llvm::SIInstrInfo::getMCOpcodeFromPseudo
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:998
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SIInstrInfo::isAtomicNoRet
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:549
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SIInstrInfo::legalizeOperandsVOP2
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition: SIInstrInfo.cpp:4792
llvm::SIInstrInfo::getMachineCSELookAheadLimit
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:330
llvm::SIInstrInfo::isSegmentSpecificFLAT
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:510
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::AMDGPU::getAddr64Inst
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:50
llvm::SIInstrInfo::getVALUOp
unsigned getVALUOp(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4419
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:356
llvm::getRegSequenceSubReg
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
Definition: SIInstrInfo.cpp:7649
llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SIInstrInfo.cpp:3022
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:56
llvm::SIInstrInfo::expandMovDPP64
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2003
llvm::SIInstrInfo::buildExtractSubRegOrImm
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4630
llvm::AMDGPU::getIfAddr64Inst
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
llvm::SIInstrInfo::isStackAccess
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7095
llvm::SIInstrInfo::getRegisterInfo
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:172
llvm::SIInstrInfo::getPreferredSelectRegClass
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
Definition: SIInstrInfo.cpp:1044
llvm::SIInstrInfo::isMTBUF
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:460
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIInstrInfo::isSMRD
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:472
llvm::SIInstrInfo::buildShrunkInst
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
Definition: SIInstrInfo.cpp:3618
llvm::SIInstrInfo::isFLATScratch
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:532
llvm::SIInstrInfo::getDSShaderTypeValue
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
Definition: SIInstrInfo.cpp:7901
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y
@ LOCAL_SIZE_Y
Definition: SIInstrInfo.h:1255
llvm::SIInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SIInstrInfo.cpp:7847
llvm::SIInstrInfo::SIInstrInfo
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:65
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::SIInstrInfo::isDOT
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:651
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::AMDGPU::RSRC_TID_ENABLE
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1239
llvm::SIInstrInfo::usesFPDPRounding
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:717
llvm::SIInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SIInstrInfo.cpp:2444
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:52
llvm::SIInstrInfo::legalizeOperandsSMRD
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5033
llvm::SI::KernelInputOffsets::NGROUPS_X
@ NGROUPS_X
Definition: SIInstrInfo.h:1248
llvm::SIInstrInfo::getDefaultRsrcDataFormat
uint64_t getDefaultRsrcDataFormat() const
Definition: SIInstrInfo.cpp:7038
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(unsigned Opc) const
Definition: SIInstrInfo.cpp:969
llvm::AMDGPU::getBasicFromSDWAOp
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:806
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:30
llvm::SIInstrInfo::isSOPP
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:396
llvm::SIInstrInfo::isLegalRegOperand
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
Definition: SIInstrInfo.cpp:4659
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z
@ GLOBAL_SIZE_Z
Definition: SIInstrInfo.h:1253
llvm::SIInstrInfo::usesFPDPRounding
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:713
llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1238
llvm::SIInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
Definition: SIInstrInfo.cpp:474
llvm::SIInstrInfo::isFLATGlobal
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:520
llvm::SIInstrInfo::MO_GOTPCREL32_HI
@ MO_GOTPCREL32_HI
Definition: SIInstrInfo.h:157
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z
@ LOCAL_SIZE_Z
Definition: SIInstrInfo.h:1256
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:348
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:33
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:85
llvm::SIInstrInfo::isLiteralConstantLike
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.cpp:3448
llvm::SIInstrInfo::isFPAtomic
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:725
llvm::SIInstrInfo::isWQM
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:575
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:816
llvm::SIInstrInfo::getNamedOperand
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:979
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X
@ GLOBAL_SIZE_X
Definition: SIInstrInfo.h:1251
llvm::SIInstrInfo::isLegalVSrcOperand
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
Definition: SIInstrInfo.cpp:4686
llvm::SIInstrInfo::getOpRegClass
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Definition: SIInstrInfo.cpp:4553
llvm::SIInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1414
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SIInstrInfo::materializeImmediate
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
Definition: SIInstrInfo.cpp:987
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::SIInstrInfo::readlaneVGPRToSGPR
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
Definition: SIInstrInfo.cpp:4991
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:47
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::SIInstrInfo::isVGPRCopy
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:729
llvm::SIInstrInfo::isSGPRStackAccess
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7108
llvm::SIInstrInfo::isEXP
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:545
llvm::SIInstrInfo::isTRANS
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:615
llvm::SIInstrInfo::isAtomicRet
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:561
llvm::SIInstrInfo::getSubtarget
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:176
llvm::SIInstrInfo::isPacked
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:408
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:504
llvm::SIInstrInfo::insertEQ
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1174
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:40
llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1237
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1247
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:789
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::isOfRegClass
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1125
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIInstrInfo::getRegClass
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:4521
llvm::SIInstrInfo::hasModifiersSet
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:3531
llvm::SIInstrInfo::mayReadEXEC
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
Definition: SIInstrInfo.cpp:3324
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SIInstrInfo::getKillTerminatorFromPseudo
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Definition: SIInstrInfo.cpp:7415
SIRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SIInstrInfo::isSOPC
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:384
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIInstrInfo::getIndirectGPRIDXPseudo
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
Definition: SIInstrInfo.cpp:1215
llvm::SIInstrInfo::pseudoToMCOpcode
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Definition: SIInstrInfo.cpp:7588
llvm::AMDGPU::getGlobalVaddrOp
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isVINTRP
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:631
llvm::SIInstrInfo::isSOP1
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:368
llvm::SIInstrInfo::legalizeOperandsVOP3
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Definition: SIInstrInfo.cpp:4904
SetVector.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
AMDGPUBaseInfo.h
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:770
llvm::SIInstrInfo::getInstBundleSize
unsigned getInstBundleSize(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7144