LLVM 18.0.0git
SIInstrInfo.h
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1//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16
17#include "AMDGPUMIRFormatter.h"
19#include "SIRegisterInfo.h"
21#include "llvm/ADT/SetVector.h"
24
25#define GET_INSTRINFO_HEADER
26#include "AMDGPUGenInstrInfo.inc"
27
28namespace llvm {
29
30class APInt;
31class GCNSubtarget;
32class LiveVariables;
33class MachineDominatorTree;
34class MachineRegisterInfo;
35class RegScavenger;
36class TargetRegisterClass;
37class ScheduleHazardRecognizer;
38
39/// Mark the MMO of a uniform load if there are no potentially clobbering stores
40/// on any path from the start of an entry function to this load.
43
44/// Utility to store machine instructions worklist.
46 SIInstrWorklist() = default;
47
48 void insert(MachineInstr *MI);
49
50 MachineInstr *top() const {
51 auto iter = InstrList.begin();
52 return *iter;
53 }
54
55 void erase_top() {
56 auto iter = InstrList.begin();
57 InstrList.erase(iter);
58 }
59
60 bool empty() const { return InstrList.empty(); }
61
62 void clear() {
63 InstrList.clear();
64 DeferredList.clear();
65 }
66
68
69 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
70
71private:
72 /// InstrList contains the MachineInstrs.
74 /// Deferred instructions are specific MachineInstr
75 /// that will be added by insert method.
76 SetVector<MachineInstr *> DeferredList;
77};
78
79class SIInstrInfo final : public AMDGPUGenInstrInfo {
80private:
81 const SIRegisterInfo RI;
82 const GCNSubtarget &ST;
83 TargetSchedModel SchedModel;
84 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
85
86 // The inverse predicate should have the negative value.
87 enum BranchPredicate {
88 INVALID_BR = 0,
89 SCC_TRUE = 1,
90 SCC_FALSE = -1,
91 VCCNZ = 2,
92 VCCZ = -2,
93 EXECNZ = -3,
94 EXECZ = 3
95 };
96
98
99 static unsigned getBranchOpcode(BranchPredicate Cond);
100 static BranchPredicate getBranchPredicate(unsigned Opcode);
101
102public:
105 MachineOperand &SuperReg,
106 const TargetRegisterClass *SuperRC,
107 unsigned SubIdx,
108 const TargetRegisterClass *SubRC) const;
111 MachineOperand &SuperReg,
112 const TargetRegisterClass *SuperRC,
113 unsigned SubIdx,
114 const TargetRegisterClass *SubRC) const;
115private:
116 void swapOperands(MachineInstr &Inst) const;
117
118 std::pair<bool, MachineBasicBlock *>
119 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
120 MachineDominatorTree *MDT = nullptr) const;
121
122 void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
123 MachineDominatorTree *MDT = nullptr) const;
124
125 void lowerScalarAbs(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
126
127 void lowerScalarXnor(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
128
129 void splitScalarNotBinop(SIInstrWorklist &Worklist, MachineInstr &Inst,
130 unsigned Opcode) const;
131
132 void splitScalarBinOpN2(SIInstrWorklist &Worklist, MachineInstr &Inst,
133 unsigned Opcode) const;
134
135 void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
136 unsigned Opcode, bool Swap = false) const;
137
138 void splitScalar64BitAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
139 MachineDominatorTree *MDT = nullptr) const;
140
141 void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
142 unsigned Opcode,
143 MachineDominatorTree *MDT = nullptr) const;
144
145 void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst,
146 MachineDominatorTree *MDT = nullptr) const;
147
148 void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
149 MachineInstr &Inst) const;
150 void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
151 void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
152 MachineInstr &Inst) const;
153
154 void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
155 SIInstrWorklist &Worklist) const;
156
157 void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
158 MachineInstr &SCCDefInst,
159 SIInstrWorklist &Worklist,
160 Register NewCond = Register()) const;
161 void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
162 SIInstrWorklist &Worklist) const;
163
164 const TargetRegisterClass *
165 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
166
167 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
168 const MachineInstr &MIb) const;
169
170 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
171
172protected:
173 /// If the specific machine instruction is a instruction that moves/copies
174 /// value from one register to another register return destination and source
175 /// registers as machine operands.
176 std::optional<DestSourcePair>
177 isCopyInstrImpl(const MachineInstr &MI) const override;
178
180 MachineOperand &Src0, unsigned Src0OpName,
181 MachineOperand &Src1, unsigned Src1OpName) const;
182
184 unsigned OpIdx0,
185 unsigned OpIdx1) const override;
186
187public:
189 MO_MASK = 0xf,
190
192 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
194 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
197 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
199 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
202 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
204
206
209 };
210
211 explicit SIInstrInfo(const GCNSubtarget &ST);
212
214 return RI;
215 }
216
217 const GCNSubtarget &getSubtarget() const {
218 return ST;
219 }
220
221 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
222
223 bool isIgnorableUse(const MachineOperand &MO) const override;
224
225 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
226 int64_t &Offset1) const override;
227
229 const MachineInstr &LdSt,
231 bool &OffsetIsScalable, unsigned &Width,
232 const TargetRegisterInfo *TRI) const final;
233
236 unsigned NumLoads, unsigned NumBytes) const override;
237
238 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
239 int64_t Offset1, unsigned NumLoads) const override;
240
242 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
243 bool KillSrc) const override;
244
247 Register DestReg, int64_t Value) const;
248
250 unsigned Size) const;
251
254 Register SrcReg, int Value) const;
255
258 Register SrcReg, int Value) const;
259
262 bool isKill, int FrameIndex,
263 const TargetRegisterClass *RC,
264 const TargetRegisterInfo *TRI,
265 Register VReg) const override;
266
269 int FrameIndex, const TargetRegisterClass *RC,
270 const TargetRegisterInfo *TRI,
271 Register VReg) const override;
272
273 bool expandPostRAPseudo(MachineInstr &MI) const override;
274
275 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
276 // instructions. Returns a pair of generated instructions.
277 // Can split either post-RA with physical registers or pre-RA with
278 // virtual registers. In latter case IR needs to be in SSA form and
279 // and a REG_SEQUENCE is produced to define original register.
280 std::pair<MachineInstr*, MachineInstr*>
282
283 // Returns an opcode that can be used to move a value to a \p DstRC
284 // register. If there is no hardware instruction that can store to \p
285 // DstRC, then AMDGPU::COPY is returned.
286 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
287
288 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
289 unsigned EltSize,
290 bool IsSGPR) const;
291
292 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
293 bool IsIndirectSrc) const;
295 int commuteOpcode(unsigned Opc) const;
296
298 inline int commuteOpcode(const MachineInstr &MI) const {
299 return commuteOpcode(MI.getOpcode());
300 }
301
302 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
303 unsigned &SrcOpIdx1) const override;
304
305 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
306 unsigned &SrcOpIdx1) const;
307
308 bool isBranchOffsetInRange(unsigned BranchOpc,
309 int64_t BrOffset) const override;
310
311 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
312
313 /// Return whether the block terminate with divergent branch.
314 /// Note this only work before lowering the pseudo control flow instructions.
315 bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
316
318 MachineBasicBlock &NewDestBB,
319 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
320 int64_t BrOffset, RegScavenger *RS) const override;
321
325 MachineBasicBlock *&FBB,
327 bool AllowModify) const;
328
330 MachineBasicBlock *&FBB,
332 bool AllowModify = false) const override;
333
335 int *BytesRemoved = nullptr) const override;
336
339 const DebugLoc &DL,
340 int *BytesAdded = nullptr) const override;
341
343 SmallVectorImpl<MachineOperand> &Cond) const override;
344
347 Register TrueReg, Register FalseReg, int &CondCycles,
348 int &TrueCycles, int &FalseCycles) const override;
349
353 Register TrueReg, Register FalseReg) const override;
354
358 Register TrueReg, Register FalseReg) const;
359
360 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
361 Register &SrcReg2, int64_t &CmpMask,
362 int64_t &CmpValue) const override;
363
364 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
365 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
366 const MachineRegisterInfo *MRI) const override;
367
368 bool
370 const MachineInstr &MIb) const override;
371
372 static bool isFoldableCopy(const MachineInstr &MI);
373
374 void removeModOperands(MachineInstr &MI) const;
375
377 MachineRegisterInfo *MRI) const final;
378
379 unsigned getMachineCSELookAheadLimit() const override { return 500; }
380
382 LiveIntervals *LIS) const override;
383
385 const MachineBasicBlock *MBB,
386 const MachineFunction &MF) const override;
387
388 static bool isSALU(const MachineInstr &MI) {
389 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
390 }
391
392 bool isSALU(uint16_t Opcode) const {
393 return get(Opcode).TSFlags & SIInstrFlags::SALU;
394 }
395
396 static bool isVALU(const MachineInstr &MI) {
397 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
398 }
399
400 bool isVALU(uint16_t Opcode) const {
401 return get(Opcode).TSFlags & SIInstrFlags::VALU;
402 }
403
404 static bool isVMEM(const MachineInstr &MI) {
405 return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
406 }
407
408 bool isVMEM(uint16_t Opcode) const {
409 return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
410 }
411
412 static bool isSOP1(const MachineInstr &MI) {
413 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
414 }
415
416 bool isSOP1(uint16_t Opcode) const {
417 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
418 }
419
420 static bool isSOP2(const MachineInstr &MI) {
421 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
422 }
423
424 bool isSOP2(uint16_t Opcode) const {
425 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
426 }
427
428 static bool isSOPC(const MachineInstr &MI) {
429 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
430 }
431
432 bool isSOPC(uint16_t Opcode) const {
433 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
434 }
435
436 static bool isSOPK(const MachineInstr &MI) {
437 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
438 }
439
440 bool isSOPK(uint16_t Opcode) const {
441 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
442 }
443
444 static bool isSOPP(const MachineInstr &MI) {
445 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
446 }
447
448 bool isSOPP(uint16_t Opcode) const {
449 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
450 }
451
452 static bool isPacked(const MachineInstr &MI) {
453 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
454 }
455
456 bool isPacked(uint16_t Opcode) const {
457 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
458 }
459
460 static bool isVOP1(const MachineInstr &MI) {
461 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
462 }
463
464 bool isVOP1(uint16_t Opcode) const {
465 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
466 }
467
468 static bool isVOP2(const MachineInstr &MI) {
469 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
470 }
471
472 bool isVOP2(uint16_t Opcode) const {
473 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
474 }
475
476 static bool isVOP3(const MachineInstr &MI) {
477 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
478 }
479
480 bool isVOP3(uint16_t Opcode) const {
481 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
482 }
483
484 static bool isSDWA(const MachineInstr &MI) {
485 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
486 }
487
488 bool isSDWA(uint16_t Opcode) const {
489 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
490 }
491
492 static bool isVOPC(const MachineInstr &MI) {
493 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
494 }
495
496 bool isVOPC(uint16_t Opcode) const {
497 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
498 }
499
500 static bool isMUBUF(const MachineInstr &MI) {
501 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
502 }
503
504 bool isMUBUF(uint16_t Opcode) const {
505 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
506 }
507
508 static bool isMTBUF(const MachineInstr &MI) {
509 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
510 }
511
512 bool isMTBUF(uint16_t Opcode) const {
513 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
514 }
515
516 static bool isSMRD(const MachineInstr &MI) {
517 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
518 }
519
520 bool isSMRD(uint16_t Opcode) const {
521 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
522 }
523
524 bool isBufferSMRD(const MachineInstr &MI) const;
525
526 static bool isDS(const MachineInstr &MI) {
527 return MI.getDesc().TSFlags & SIInstrFlags::DS;
528 }
529
530 bool isDS(uint16_t Opcode) const {
531 return get(Opcode).TSFlags & SIInstrFlags::DS;
532 }
533
534 static bool isGWS(const MachineInstr &MI) {
535 return MI.getDesc().TSFlags & SIInstrFlags::GWS;
536 }
537
538 bool isGWS(uint16_t Opcode) const {
539 return get(Opcode).TSFlags & SIInstrFlags::GWS;
540 }
541
542 bool isAlwaysGDS(uint16_t Opcode) const;
543
544 static bool isMIMG(const MachineInstr &MI) {
545 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
546 }
547
548 bool isMIMG(uint16_t Opcode) const {
549 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
550 }
551
552 static bool isGather4(const MachineInstr &MI) {
553 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
554 }
555
556 bool isGather4(uint16_t Opcode) const {
557 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
558 }
559
560 static bool isFLAT(const MachineInstr &MI) {
561 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
562 }
563
564 // Is a FLAT encoded instruction which accesses a specific segment,
565 // i.e. global_* or scratch_*.
567 auto Flags = MI.getDesc().TSFlags;
569 }
570
571 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
572 auto Flags = get(Opcode).TSFlags;
574 }
575
576 static bool isFLATGlobal(const MachineInstr &MI) {
577 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
578 }
579
580 bool isFLATGlobal(uint16_t Opcode) const {
581 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
582 }
583
584 static bool isFLATScratch(const MachineInstr &MI) {
585 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
586 }
587
588 bool isFLATScratch(uint16_t Opcode) const {
589 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
590 }
591
592 // Any FLAT encoded instruction, including global_* and scratch_*.
593 bool isFLAT(uint16_t Opcode) const {
594 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
595 }
596
597 static bool isEXP(const MachineInstr &MI) {
598 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
599 }
600
602 if (!isEXP(MI))
603 return false;
604 unsigned Target = MI.getOperand(0).getImm();
607 }
608
609 bool isEXP(uint16_t Opcode) const {
610 return get(Opcode).TSFlags & SIInstrFlags::EXP;
611 }
612
613 static bool isAtomicNoRet(const MachineInstr &MI) {
614 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
615 }
616
617 bool isAtomicNoRet(uint16_t Opcode) const {
618 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
619 }
620
621 static bool isAtomicRet(const MachineInstr &MI) {
622 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
623 }
624
625 bool isAtomicRet(uint16_t Opcode) const {
626 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
627 }
628
629 static bool isAtomic(const MachineInstr &MI) {
630 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
632 }
633
634 bool isAtomic(uint16_t Opcode) const {
635 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
637 }
638
639 static bool isWQM(const MachineInstr &MI) {
640 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
641 }
642
643 bool isWQM(uint16_t Opcode) const {
644 return get(Opcode).TSFlags & SIInstrFlags::WQM;
645 }
646
647 static bool isDisableWQM(const MachineInstr &MI) {
648 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
649 }
650
651 bool isDisableWQM(uint16_t Opcode) const {
652 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
653 }
654
655 static bool isVGPRSpill(const MachineInstr &MI) {
656 return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
657 }
658
659 bool isVGPRSpill(uint16_t Opcode) const {
660 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
661 }
662
663 static bool isSGPRSpill(const MachineInstr &MI) {
664 return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
665 }
666
667 bool isSGPRSpill(uint16_t Opcode) const {
668 return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
669 }
670
671 static bool isWWMRegSpillOpcode(uint16_t Opcode) {
672 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
673 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
674 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
675 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
676 }
677
678 static bool isDPP(const MachineInstr &MI) {
679 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
680 }
681
682 bool isDPP(uint16_t Opcode) const {
683 return get(Opcode).TSFlags & SIInstrFlags::DPP;
684 }
685
686 static bool isTRANS(const MachineInstr &MI) {
687 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
688 }
689
690 bool isTRANS(uint16_t Opcode) const {
691 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
692 }
693
694 static bool isVOP3P(const MachineInstr &MI) {
695 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
696 }
697
698 bool isVOP3P(uint16_t Opcode) const {
699 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
700 }
701
702 static bool isVINTRP(const MachineInstr &MI) {
703 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
704 }
705
706 bool isVINTRP(uint16_t Opcode) const {
707 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
708 }
709
710 static bool isMAI(const MachineInstr &MI) {
711 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
712 }
713
714 bool isMAI(uint16_t Opcode) const {
715 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
716 }
717
718 static bool isMFMA(const MachineInstr &MI) {
719 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
720 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
721 }
722
723 static bool isDOT(const MachineInstr &MI) {
724 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
725 }
726
727 static bool isWMMA(const MachineInstr &MI) {
728 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
729 }
730
731 bool isWMMA(uint16_t Opcode) const {
732 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
733 }
734
735 static bool isMFMAorWMMA(const MachineInstr &MI) {
736 return isMFMA(MI) || isWMMA(MI);
737 }
738
739 bool isDOT(uint16_t Opcode) const {
740 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
741 }
742
743 static bool isLDSDIR(const MachineInstr &MI) {
744 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
745 }
746
747 bool isLDSDIR(uint16_t Opcode) const {
748 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
749 }
750
751 static bool isVINTERP(const MachineInstr &MI) {
752 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
753 }
754
755 bool isVINTERP(uint16_t Opcode) const {
756 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
757 }
758
759 static bool isScalarUnit(const MachineInstr &MI) {
760 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
761 }
762
763 static bool usesVM_CNT(const MachineInstr &MI) {
764 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
765 }
766
767 static bool usesLGKM_CNT(const MachineInstr &MI) {
768 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
769 }
770
771 static bool sopkIsZext(const MachineInstr &MI) {
772 return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
773 }
774
775 bool sopkIsZext(uint16_t Opcode) const {
776 return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
777 }
778
779 /// \returns true if this is an s_store_dword* instruction. This is more
780 /// specific than isSMEM && mayStore.
781 static bool isScalarStore(const MachineInstr &MI) {
782 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
783 }
784
785 bool isScalarStore(uint16_t Opcode) const {
786 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
787 }
788
789 static bool isFixedSize(const MachineInstr &MI) {
790 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
791 }
792
793 bool isFixedSize(uint16_t Opcode) const {
794 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
795 }
796
797 static bool hasFPClamp(const MachineInstr &MI) {
798 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
799 }
800
801 bool hasFPClamp(uint16_t Opcode) const {
802 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
803 }
804
805 static bool hasIntClamp(const MachineInstr &MI) {
806 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
807 }
808
810 const uint64_t ClampFlags = SIInstrFlags::FPClamp |
814 return MI.getDesc().TSFlags & ClampFlags;
815 }
816
817 static bool usesFPDPRounding(const MachineInstr &MI) {
818 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
819 }
820
821 bool usesFPDPRounding(uint16_t Opcode) const {
822 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
823 }
824
825 static bool isFPAtomic(const MachineInstr &MI) {
826 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
827 }
828
829 bool isFPAtomic(uint16_t Opcode) const {
830 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
831 }
832
833 static bool isNeverUniform(const MachineInstr &MI) {
834 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
835 }
836
838 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
839 }
840
841 bool doesNotReadTiedSource(uint16_t Opcode) const {
842 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
843 }
844
845 bool isVGPRCopy(const MachineInstr &MI) const {
846 assert(isCopyInstr(MI));
847 Register Dest = MI.getOperand(0).getReg();
848 const MachineFunction &MF = *MI.getParent()->getParent();
849 const MachineRegisterInfo &MRI = MF.getRegInfo();
850 return !RI.isSGPRReg(MRI, Dest);
851 }
852
853 bool hasVGPRUses(const MachineInstr &MI) const {
854 const MachineFunction &MF = *MI.getParent()->getParent();
855 const MachineRegisterInfo &MRI = MF.getRegInfo();
856 return llvm::any_of(MI.explicit_uses(),
857 [&MRI, this](const MachineOperand &MO) {
858 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
859 }
860
861 /// Return true if the instruction modifies the mode register.q
862 static bool modifiesModeRegister(const MachineInstr &MI);
863
864 /// Whether we must prevent this instruction from executing with EXEC = 0.
866
867 /// Returns true if the instruction could potentially depend on the value of
868 /// exec. If false, exec dependencies may safely be ignored.
869 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
870
871 bool isInlineConstant(const APInt &Imm) const;
872
873 bool isInlineConstant(const APFloat &Imm) const {
874 return isInlineConstant(Imm.bitcastToAPInt());
875 }
876
877 // Returns true if this non-register operand definitely does not need to be
878 // encoded as a 32-bit literal. Note that this function handles all kinds of
879 // operands, not just immediates.
880 //
881 // Some operands like FrameIndexes could resolve to an inline immediate value
882 // that will not require an additional 4-bytes; this function assumes that it
883 // will.
884 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
885
887 const MCOperandInfo &OpInfo) const {
888 return isInlineConstant(MO, OpInfo.OperandType);
889 }
890
891 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
892 /// be an inline immediate.
894 const MachineOperand &UseMO,
895 const MachineOperand &DefMO) const {
896 assert(UseMO.getParent() == &MI);
897 int OpIdx = UseMO.getOperandNo();
898 if (OpIdx >= MI.getDesc().NumOperands)
899 return false;
900
901 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
902 }
903
904 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
905 /// immediate.
906 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
907 const MachineOperand &MO = MI.getOperand(OpIdx);
908 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
909 }
910
911 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
912 const MachineOperand &MO) const {
913 if (OpIdx >= MI.getDesc().NumOperands)
914 return false;
915
916 if (isCopyInstr(MI)) {
917 unsigned Size = getOpSize(MI, OpIdx);
918 assert(Size == 8 || Size == 4);
919
920 uint8_t OpType = (Size == 8) ?
922 return isInlineConstant(MO, OpType);
923 }
924
925 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
926 }
927
928 bool isInlineConstant(const MachineOperand &MO) const {
929 return isInlineConstant(*MO.getParent(), MO.getOperandNo());
930 }
931
932 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
933 const MachineOperand &MO) const;
934
935 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
936 /// This function will return false if you pass it a 32-bit instruction.
937 bool hasVALU32BitEncoding(unsigned Opcode) const;
938
939 /// Returns true if this operand uses the constant bus.
941 const MachineOperand &MO,
942 const MCOperandInfo &OpInfo) const;
943
944 /// Return true if this instruction has any modifiers.
945 /// e.g. src[012]_mod, omod, clamp.
946 bool hasModifiers(unsigned Opcode) const;
947
948 bool hasModifiersSet(const MachineInstr &MI,
949 unsigned OpName) const;
950 bool hasAnyModifiersSet(const MachineInstr &MI) const;
951
952 bool canShrink(const MachineInstr &MI,
953 const MachineRegisterInfo &MRI) const;
954
956 unsigned NewOpcode) const;
957
959 StringRef &ErrInfo) const override;
960
961 unsigned getVALUOp(const MachineInstr &MI) const;
962
965 const DebugLoc &DL, Register Reg, bool IsSCCLive,
966 SlotIndexes *Indexes = nullptr) const;
967
970 Register Reg, SlotIndexes *Indexes = nullptr) const;
971
972 /// Return the correct register class for \p OpNo. For target-specific
973 /// instructions, this will return the register class that has been defined
974 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
975 /// the register class of its machine operand.
976 /// to infer the correct register class base on the other operands.
978 unsigned OpNo) const;
979
980 /// Return the size in bytes of the operand OpNo on the given
981 // instruction opcode.
982 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
983 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
984
985 if (OpInfo.RegClass == -1) {
986 // If this is an immediate operand, this must be a 32-bit literal.
988 return 4;
989 }
990
991 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
992 }
993
994 /// This form should usually be preferred since it handles operands
995 /// with unknown register classes.
996 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
997 const MachineOperand &MO = MI.getOperand(OpNo);
998 if (MO.isReg()) {
999 if (unsigned SubReg = MO.getSubReg()) {
1000 return RI.getSubRegIdxSize(SubReg) / 8;
1001 }
1002 }
1003 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
1004 }
1005
1006 /// Legalize the \p OpIndex operand of this instruction by inserting
1007 /// a MOV. For example:
1008 /// ADD_I32_e32 VGPR0, 15
1009 /// to
1010 /// MOV VGPR1, 15
1011 /// ADD_I32_e32 VGPR0, VGPR1
1012 ///
1013 /// If the operand being legalized is a register, then a COPY will be used
1014 /// instead of MOV.
1015 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1016
1017 /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
1018 /// for \p MI.
1019 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1020 const MachineOperand *MO = nullptr) const;
1021
1022 /// Check if \p MO would be a valid operand for the given operand
1023 /// definition \p OpInfo. Note this does not attempt to validate constant bus
1024 /// restrictions (e.g. literal constant usage).
1026 const MCOperandInfo &OpInfo,
1027 const MachineOperand &MO) const;
1028
1029 /// Check if \p MO (a register operand) is a legal register for the
1030 /// given operand description.
1032 const MCOperandInfo &OpInfo,
1033 const MachineOperand &MO) const;
1034
1035 /// Legalize operands in \p MI by either commuting it or inserting a
1036 /// copy of src1.
1038
1039 /// Fix operands in \p MI to satisfy constant bus requirements.
1041
1042 /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
1043 /// be used when it is know that the value in SrcReg is same across all
1044 /// threads in the wave.
1045 /// \returns The SGPR register that \p SrcReg was copied to.
1047 MachineRegisterInfo &MRI) const;
1048
1051
1054 const TargetRegisterClass *DstRC,
1056 const DebugLoc &DL) const;
1057
1058 /// Legalize all operands in this instruction. This function may create new
1059 /// instructions and control-flow around \p MI. If present, \p MDT is
1060 /// updated.
1061 /// \returns A new basic block that contains \p MI if new blocks were created.
1063 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1064
1065 /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1066 /// was moved to VGPR. \returns true if succeeded.
1067 bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1068
1069 /// Replace the instructions opcode with the equivalent VALU
1070 /// opcode. This function will also move the users of MachineInstruntions
1071 /// in the \p WorkList to the VALU if necessary. If present, \p MDT is
1072 /// updated.
1073 void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const;
1074
1076 MachineInstr &Inst) const;
1077
1079 MachineBasicBlock::iterator MI) const override;
1080
1082 unsigned Quantity) const override;
1083
1084 void insertReturn(MachineBasicBlock &MBB) const;
1085 /// Return the number of wait states that result from executing this
1086 /// instruction.
1087 static unsigned getNumWaitStates(const MachineInstr &MI);
1088
1089 /// Returns the operand named \p Op. If \p MI does not have an
1090 /// operand named \c Op, this function returns nullptr.
1092 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1093
1096 unsigned OpName) const {
1097 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1098 }
1099
1100 /// Get required immediate operand
1101 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1102 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1103 return MI.getOperand(Idx).getImm();
1104 }
1105
1108
1109 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1110 bool isHighLatencyDef(int Opc) const override;
1111
1112 /// Return the descriptor of the target-specific machine instruction
1113 /// that corresponds to the specified pseudo or native opcode.
1114 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1115 return get(pseudoToMCOpcode(Opcode));
1116 }
1117
1118 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1119 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1120
1121 unsigned isLoadFromStackSlot(const MachineInstr &MI,
1122 int &FrameIndex) const override;
1123 unsigned isStoreToStackSlot(const MachineInstr &MI,
1124 int &FrameIndex) const override;
1125
1126 unsigned getInstBundleSize(const MachineInstr &MI) const;
1127 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1128
1129 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1130
1131 bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1132
1134 MachineBasicBlock *IfEnd) const;
1135
1137 MachineBasicBlock *LoopEnd) const;
1138
1139 std::pair<unsigned, unsigned>
1140 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1141
1143 getSerializableTargetIndices() const override;
1144
1147
1150
1153 const ScheduleDAG *DAG) const override;
1154
1156 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1157
1160 const ScheduleDAGMI *DAG) const override;
1161
1163 const MachineFunction &MF) const override;
1164
1165 bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1166
1169 const DebugLoc &DL, Register Src,
1170 Register Dst) const override;
1171
1174 const DebugLoc &DL, Register Src,
1175 unsigned SrcSubReg,
1176 Register Dst) const override;
1177
1178 bool isWave32() const;
1179
1180 /// Return a partially built integer add instruction without carry.
1181 /// Caller must add source operands.
1182 /// For pre-GFX9 it will generate unused carry destination operand.
1183 /// TODO: After GFX9 it should return a no-carry operation.
1186 const DebugLoc &DL,
1187 Register DestReg) const;
1188
1191 const DebugLoc &DL,
1192 Register DestReg,
1193 RegScavenger &RS) const;
1194
1195 static bool isKillTerminator(unsigned Opcode);
1196 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1197
1198 static bool isLegalMUBUFImmOffset(unsigned Imm) {
1199 return isUInt<12>(Imm);
1200 }
1201
1202 static unsigned getMaxMUBUFImmOffset();
1203
1204 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1205 Align Alignment = Align(4)) const;
1206
1207 /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1208 /// encoded instruction. If \p Signed, this is for an instruction that
1209 /// interprets the offset as signed.
1210 bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1211 uint64_t FlatVariant) const;
1212
1213 /// Split \p COffsetVal into {immediate offset field, remainder offset}
1214 /// values.
1215 std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1216 unsigned AddrSpace,
1217 uint64_t FlatVariant) const;
1218
1219 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1220 /// Return -1 if the target-specific opcode for the pseudo instruction does
1221 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1222 int pseudoToMCOpcode(int Opcode) const;
1223
1224 /// \brief Check if this instruction should only be used by assembler.
1225 /// Return true if this opcode should not be used by codegen.
1226 bool isAsmOnlyOpcode(int MCOp) const;
1227
1228 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1229 const TargetRegisterInfo *TRI,
1230 const MachineFunction &MF)
1231 const override;
1232
1233 void fixImplicitOperands(MachineInstr &MI) const;
1234
1238 int FrameIndex,
1239 LiveIntervals *LIS = nullptr,
1240 VirtRegMap *VRM = nullptr) const override;
1241
1242 unsigned getInstrLatency(const InstrItineraryData *ItinData,
1243 const MachineInstr &MI,
1244 unsigned *PredCost = nullptr) const override;
1245
1247 getInstructionUniformity(const MachineInstr &MI) const override final;
1248
1251
1252 const MIRFormatter *getMIRFormatter() const override {
1253 if (!Formatter.get())
1254 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1255 return Formatter.get();
1256 }
1257
1258 static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1259
1260 const TargetSchedModel &getSchedModel() const { return SchedModel; }
1261
1262 // Enforce operand's \p OpName even alignment if required by target.
1263 // This is used if an operand is a 32 bit register but needs to be aligned
1264 // regardless.
1265 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1266};
1267
1268/// \brief Returns true if a reg:subreg pair P has a TRC class
1270 const TargetRegisterClass &TRC,
1272 auto *RC = MRI.getRegClass(P.Reg);
1273 if (!P.SubReg)
1274 return RC == &TRC;
1275 auto *TRI = MRI.getTargetRegisterInfo();
1276 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1277}
1278
1279/// \brief Create RegSubRegPair from a register MachineOperand
1280inline
1282 assert(O.isReg());
1283 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1284}
1285
1286/// \brief Return the SubReg component from REG_SEQUENCE
1287TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1288 unsigned SubReg);
1289
1290/// \brief Return the defining instruction for a given reg:subreg pair
1291/// skipping copy like instructions and subreg-manipulation pseudos.
1292/// Following another subreg of a reg:subreg isn't supported.
1293MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1294 MachineRegisterInfo &MRI);
1295
1296/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1297/// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1298/// attempt to track between blocks.
1299bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1300 Register VReg,
1301 const MachineInstr &DefMI,
1302 const MachineInstr &UseMI);
1303
1304/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1305/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1306/// track between blocks.
1307bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1308 Register VReg,
1309 const MachineInstr &DefMI);
1310
1311namespace AMDGPU {
1312
1314 int getVOPe64(uint16_t Opcode);
1315
1317 int getVOPe32(uint16_t Opcode);
1318
1320 int getSDWAOp(uint16_t Opcode);
1321
1324
1327
1330
1333
1336
1339
1340 /// Check if \p Opcode is an Addr64 opcode.
1341 ///
1342 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1345
1348
1350 int getSOPKOp(uint16_t Opcode);
1351
1352 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1353 /// of a VADDR form.
1356
1357 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1358 /// of a SADDR form.
1361
1364
1365 /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1366 /// given an \p Opcode of an SS (SADDR) form.
1369
1370 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1371 /// of an SVS (SADDR + VADDR) form.
1374
1375 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1376 /// of an SV (VADDR) form.
1379
1380 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1381 /// of an SS (SADDR) form.
1384
1385 /// \returns earlyclobber version of a MAC MFMA is exists.
1388
1389 /// \returns v_cmpx version of a v_cmp instruction.
1392
1393 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1396 const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1397
1398} // end namespace AMDGPU
1399
1400namespace AMDGPU {
1402 // For sgpr to vgpr spill instructions
1405} // namespace AMDGPU
1406
1407namespace SI {
1408namespace KernelInputOffsets {
1409
1410/// Offsets in bytes from the start of the input buffer
1420 LOCAL_SIZE_Z = 32
1422
1423} // end namespace KernelInputOffsets
1424} // end namespace SI
1425
1426} // end namespace llvm
1427
1428#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Provides AMDGPU specific target descriptions.
AMDGPU specific overrides of MIRFormatter.
#define LLVM_READONLY
Definition: Compiler.h:208
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
StandardInstrumentations SI(Mod->getContext(), Debug, VerifyEach)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file implements a set that has insertion order iteration characteristics.
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:91
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:580
bool isInlineConstant(const APInt &Imm) const
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:710
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:526
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:404
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override
bool isNonUniformBranchInstr(MachineInstr &Instr) const
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:476
unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const override
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:520
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
static bool isNeverUniform(const MachineInstr &MI)
Definition: SIInstrInfo.h:833
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:982
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:634
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:747
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:588
uint64_t getDefaultRsrcDataFormat() const
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:444
InstructionUniformity getGenericInstructionUniformity(const MachineInstr &MI) const
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:853
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:809
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:584
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, Align Alignment=Align(4)) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const
Replace the instructions opcode with the equivalent VALU opcode.
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:516
void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, SlotIndexes *Indexes=nullptr) const
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:659
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:571
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1101
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:456
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:508
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
void insertReturn(MachineBasicBlock &MBB) const
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:597
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:388
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:775
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:468
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:484
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:416
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:873
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:702
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:625
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:552
static bool isMFMAorWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:735
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:639
static bool doesNotReadTiedSource(const MachineInstr &MI)
Definition: SIInstrInfo.h:837
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:432
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:723
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:817
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:793
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
bool isGWS(uint16_t Opcode) const
Definition: SIInstrInfo.h:538
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:928
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:480
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:739
bool isWave32() const
bool isHighLatencyDef(int Opc) const override
bool isBasicBlockPrologue(const MachineInstr &MI) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:492
void removeModOperands(MachineInstr &MI) const
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:556
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:593
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:743
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:420
static bool isGWS(const MachineInstr &MI)
Definition: SIInstrInfo.h:534
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1260
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:496
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:893
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1252
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:714
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:576
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:379
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:621
bool isBufferSMRD(const MachineInstr &MI) const
static bool isKillTerminator(unsigned Opcode)
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:217
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:530
void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, bool IsSCCLive, SlotIndexes *Indexes=nullptr) const
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1198
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:829
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:647
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:617
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:686
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:436
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:906
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
static bool isFoldableCopy(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isIgnorableUse(const MachineOperand &MO) const override
static bool isVINTERP(const MachineInstr &MI)
Definition: SIInstrInfo.h:751
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:500
bool expandPostRAPseudo(MachineInstr &MI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:392
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:472
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:797
InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const override final
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:566
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:488
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:996
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:886
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:440
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:678
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isMFMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:718
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:667
bool isLowLatencyInstruction(const MachineInstr &MI) const
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:781
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:771
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:690
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:424
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:400
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:464
bool isAlwaysGDS(uint16_t Opcode) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:504
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:825
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:767
void moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT, MachineInstr &Inst) const
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:452
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
bool isWMMA(uint16_t Opcode) const
Definition: SIInstrInfo.h:731
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:512
static unsigned getMaxMUBUFImmOffset()
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:651
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:655
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
static bool isWWMRegSpillOpcode(uint16_t Opcode)
Definition: SIInstrInfo.h:671
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:408
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:706
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:845
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:785
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:544
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:298
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:694
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:643
unsigned getVALUOp(const MachineInstr &MI) const
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void fixImplicitOperands(MachineInstr &MI) const
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:698
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1095
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:609
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
static bool isDualSourceBlendEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:601
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:629
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:663
static bool isWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:727
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
bool isVINTERP(uint16_t Opcode) const
Definition: SIInstrInfo.h:755
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool doesNotReadTiedSource(uint16_t Opcode) const
Definition: SIInstrInfo.h:841
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:682
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:412
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:428
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:560
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:213
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:396
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:805
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1114
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:911
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:759
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:448
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:548
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:801
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:763
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:821
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:789
LLVM_READONLY int commuteOpcode(unsigned Opc) const
uint64_t getScratchRsrcWords23() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:613
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:460
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool hasAnyModifiersSet(const MachineInstr &MI) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A vector that has set insertion semantics.
Definition: SetVector.h:57
SlotIndexes pass.
Definition: SlotIndexes.h:301
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:370
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1393
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1394
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1396
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:189
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:188
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1395
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1411
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1281
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:41
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1269
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
Definition: Uniformity.h:18
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Description of the encoding of one expression Op.
Utility to store machine instructions worklist.
Definition: SIInstrInfo.h:45
MachineInstr * top() const
Definition: SIInstrInfo.h:50
bool empty() const
Definition: SIInstrInfo.h:60
bool isDeferred(MachineInstr *MI)
SetVector< MachineInstr * > & getDeferredList()
Definition: SIInstrInfo.h:69
void insert(MachineInstr *MI)
A pair composed of a register and a sub-register index.