LLVM  14.0.0git
SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 class SIInstrInfo final : public AMDGPUGenInstrInfo {
39 private:
40  const SIRegisterInfo RI;
41  const GCNSubtarget &ST;
42  TargetSchedModel SchedModel;
43  mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
44 
45  // The inverse predicate should have the negative value.
46  enum BranchPredicate {
47  INVALID_BR = 0,
48  SCC_TRUE = 1,
49  SCC_FALSE = -1,
50  VCCNZ = 2,
51  VCCZ = -2,
52  EXECNZ = -3,
53  EXECZ = 3
54  };
55 
57 
58  static unsigned getBranchOpcode(BranchPredicate Cond);
59  static BranchPredicate getBranchPredicate(unsigned Opcode);
60 
61 public:
64  MachineOperand &SuperReg,
65  const TargetRegisterClass *SuperRC,
66  unsigned SubIdx,
67  const TargetRegisterClass *SubRC) const;
70  MachineOperand &SuperReg,
71  const TargetRegisterClass *SuperRC,
72  unsigned SubIdx,
73  const TargetRegisterClass *SubRC) const;
74 private:
75  void swapOperands(MachineInstr &Inst) const;
76 
77  std::pair<bool, MachineBasicBlock *>
78  moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
79  MachineDominatorTree *MDT = nullptr) const;
80 
81  void lowerSelect32(SetVectorType &Worklist, MachineInstr &Inst,
82  MachineDominatorTree *MDT = nullptr) const;
83 
84  void splitSelect64(SetVectorType &Worklist, MachineInstr &Inst,
85  MachineDominatorTree *MDT = nullptr) const;
86 
87  void lowerScalarAbs(SetVectorType &Worklist,
88  MachineInstr &Inst) const;
89 
90  void lowerScalarXnor(SetVectorType &Worklist,
91  MachineInstr &Inst) const;
92 
93  void splitScalarNotBinop(SetVectorType &Worklist,
94  MachineInstr &Inst,
95  unsigned Opcode) const;
96 
97  void splitScalarBinOpN2(SetVectorType &Worklist,
98  MachineInstr &Inst,
99  unsigned Opcode) const;
100 
101  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
102  MachineInstr &Inst, unsigned Opcode,
103  bool Swap = false) const;
104 
105  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
106  MachineDominatorTree *MDT = nullptr) const;
107 
108  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
109  unsigned Opcode,
110  MachineDominatorTree *MDT = nullptr) const;
111 
112  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
113  MachineDominatorTree *MDT = nullptr) const;
114 
115  void splitScalar64BitBCNT(SetVectorType &Worklist,
116  MachineInstr &Inst) const;
117  void splitScalar64BitBFE(SetVectorType &Worklist,
118  MachineInstr &Inst) const;
119  void movePackToVALU(SetVectorType &Worklist,
121  MachineInstr &Inst) const;
122 
123  void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
124  SetVectorType &Worklist) const;
125 
126  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
127  MachineInstr &SCCDefInst,
128  SetVectorType &Worklist,
129  Register NewCond = Register()) const;
130  void addSCCDefsToVALUWorklist(MachineOperand &Op,
131  SetVectorType &Worklist) const;
132 
133  const TargetRegisterClass *
134  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
135 
136  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
137  const MachineInstr &MIb) const;
138 
139  Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
140 
141 protected:
143  MachineOperand &Src0, unsigned Src0OpName,
144  MachineOperand &Src1, unsigned Src1OpName) const;
145 
147  unsigned OpIdx0,
148  unsigned OpIdx1) const override;
149 
150 public:
152  MO_MASK = 0xf,
153 
154  MO_NONE = 0,
155  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
157  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
160  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
162  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
163  MO_REL32 = 4,
165  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
167 
169 
172  };
173 
174  explicit SIInstrInfo(const GCNSubtarget &ST);
175 
177  return RI;
178  }
179 
180  const GCNSubtarget &getSubtarget() const {
181  return ST;
182  }
183 
185  AAResults *AA) const override;
186 
187  bool isIgnorableUse(const MachineOperand &MO) const override;
188 
189  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
190  int64_t &Offset1,
191  int64_t &Offset2) const override;
192 
194  const MachineInstr &LdSt,
196  bool &OffsetIsScalable, unsigned &Width,
197  const TargetRegisterInfo *TRI) const final;
198 
201  unsigned NumLoads, unsigned NumBytes) const override;
202 
203  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
204  int64_t Offset1, unsigned NumLoads) const override;
205 
207  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
208  bool KillSrc) const override;
209 
212  const DebugLoc &DL,
213  unsigned DestReg,
214  int64_t Value) const;
215 
217  unsigned Size) const;
218 
221  Register SrcReg, int Value) const;
222 
225  Register SrcReg, int Value) const;
226 
229  bool isKill, int FrameIndex,
230  const TargetRegisterClass *RC,
231  const TargetRegisterInfo *TRI) const override;
232 
235  int FrameIndex, const TargetRegisterClass *RC,
236  const TargetRegisterInfo *TRI) const override;
237 
238  bool expandPostRAPseudo(MachineInstr &MI) const override;
239 
240  // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
241  // instructions. Returns a pair of generated instructions.
242  // Can split either post-RA with physical registers or pre-RA with
243  // virtual registers. In latter case IR needs to be in SSA form and
244  // and a REG_SEQUENCE is produced to define original register.
245  std::pair<MachineInstr*, MachineInstr*>
247 
248  // Returns an opcode that can be used to move a value to a \p DstRC
249  // register. If there is no hardware instruction that can store to \p
250  // DstRC, then AMDGPU::COPY is returned.
251  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
252 
254  unsigned EltSize,
255  bool IsSGPR) const;
256 
258  bool IsIndirectSrc) const;
260  int commuteOpcode(unsigned Opc) const;
261 
263  inline int commuteOpcode(const MachineInstr &MI) const {
264  return commuteOpcode(MI.getOpcode());
265  }
266 
267  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
268  unsigned &SrcOpIdx2) const override;
269 
270  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
271  unsigned & SrcOpIdx1) const;
272 
273  bool isBranchOffsetInRange(unsigned BranchOpc,
274  int64_t BrOffset) const override;
275 
276  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
277 
279  MachineBasicBlock &NewDestBB,
280  const DebugLoc &DL,
281  int64_t BrOffset,
282  RegScavenger *RS = nullptr) const override;
283 
286  MachineBasicBlock *&TBB,
287  MachineBasicBlock *&FBB,
289  bool AllowModify) const;
290 
292  MachineBasicBlock *&FBB,
294  bool AllowModify = false) const override;
295 
297  int *BytesRemoved = nullptr) const override;
298 
301  const DebugLoc &DL,
302  int *BytesAdded = nullptr) const override;
303 
305  SmallVectorImpl<MachineOperand> &Cond) const override;
306 
309  Register TrueReg, Register FalseReg, int &CondCycles,
310  int &TrueCycles, int &FalseCycles) const override;
311 
315  Register TrueReg, Register FalseReg) const override;
316 
320  Register TrueReg, Register FalseReg) const;
321 
322  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
323  Register &SrcReg2, int64_t &CmpMask,
324  int64_t &CmpValue) const override;
325 
326  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
327  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
328  const MachineRegisterInfo *MRI) const override;
329 
331  unsigned Kind) const override;
332 
333  bool
335  const MachineInstr &MIb) const override;
336 
337  static bool isFoldableCopy(const MachineInstr &MI);
338 
340  MachineRegisterInfo *MRI) const final;
341 
342  unsigned getMachineCSELookAheadLimit() const override { return 500; }
343 
345  LiveVariables *LV) const override;
346 
348  const MachineBasicBlock *MBB,
349  const MachineFunction &MF) const override;
350 
351  static bool isSALU(const MachineInstr &MI) {
352  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
353  }
354 
355  bool isSALU(uint16_t Opcode) const {
356  return get(Opcode).TSFlags & SIInstrFlags::SALU;
357  }
358 
359  static bool isVALU(const MachineInstr &MI) {
360  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
361  }
362 
363  bool isVALU(uint16_t Opcode) const {
364  return get(Opcode).TSFlags & SIInstrFlags::VALU;
365  }
366 
367  static bool isVMEM(const MachineInstr &MI) {
368  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
369  }
370 
371  bool isVMEM(uint16_t Opcode) const {
372  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
373  }
374 
375  static bool isSOP1(const MachineInstr &MI) {
376  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
377  }
378 
379  bool isSOP1(uint16_t Opcode) const {
380  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
381  }
382 
383  static bool isSOP2(const MachineInstr &MI) {
384  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
385  }
386 
387  bool isSOP2(uint16_t Opcode) const {
388  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
389  }
390 
391  static bool isSOPC(const MachineInstr &MI) {
392  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
393  }
394 
395  bool isSOPC(uint16_t Opcode) const {
396  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
397  }
398 
399  static bool isSOPK(const MachineInstr &MI) {
400  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
401  }
402 
403  bool isSOPK(uint16_t Opcode) const {
404  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
405  }
406 
407  static bool isSOPP(const MachineInstr &MI) {
408  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
409  }
410 
411  bool isSOPP(uint16_t Opcode) const {
412  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
413  }
414 
415  static bool isPacked(const MachineInstr &MI) {
416  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
417  }
418 
419  bool isPacked(uint16_t Opcode) const {
420  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
421  }
422 
423  static bool isVOP1(const MachineInstr &MI) {
424  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
425  }
426 
427  bool isVOP1(uint16_t Opcode) const {
428  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
429  }
430 
431  static bool isVOP2(const MachineInstr &MI) {
432  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
433  }
434 
435  bool isVOP2(uint16_t Opcode) const {
436  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
437  }
438 
439  static bool isVOP3(const MachineInstr &MI) {
440  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
441  }
442 
443  bool isVOP3(uint16_t Opcode) const {
444  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
445  }
446 
447  static bool isSDWA(const MachineInstr &MI) {
448  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
449  }
450 
451  bool isSDWA(uint16_t Opcode) const {
452  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
453  }
454 
455  static bool isVOPC(const MachineInstr &MI) {
456  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
457  }
458 
459  bool isVOPC(uint16_t Opcode) const {
460  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
461  }
462 
463  static bool isMUBUF(const MachineInstr &MI) {
464  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
465  }
466 
467  bool isMUBUF(uint16_t Opcode) const {
468  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
469  }
470 
471  static bool isMTBUF(const MachineInstr &MI) {
472  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
473  }
474 
475  bool isMTBUF(uint16_t Opcode) const {
476  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
477  }
478 
479  static bool isSMRD(const MachineInstr &MI) {
480  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
481  }
482 
483  bool isSMRD(uint16_t Opcode) const {
484  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
485  }
486 
487  bool isBufferSMRD(const MachineInstr &MI) const;
488 
489  static bool isDS(const MachineInstr &MI) {
490  return MI.getDesc().TSFlags & SIInstrFlags::DS;
491  }
492 
493  bool isDS(uint16_t Opcode) const {
494  return get(Opcode).TSFlags & SIInstrFlags::DS;
495  }
496 
497  bool isAlwaysGDS(uint16_t Opcode) const;
498 
499  static bool isMIMG(const MachineInstr &MI) {
500  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
501  }
502 
503  bool isMIMG(uint16_t Opcode) const {
504  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
505  }
506 
507  static bool isGather4(const MachineInstr &MI) {
508  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
509  }
510 
511  bool isGather4(uint16_t Opcode) const {
512  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
513  }
514 
515  static bool isFLAT(const MachineInstr &MI) {
516  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
517  }
518 
519  // Is a FLAT encoded instruction which accesses a specific segment,
520  // i.e. global_* or scratch_*.
521  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
522  auto Flags = MI.getDesc().TSFlags;
524  }
525 
526  bool isSegmentSpecificFLAT(uint16_t Opcode) const {
527  auto Flags = get(Opcode).TSFlags;
529  }
530 
531  static bool isFLATGlobal(const MachineInstr &MI) {
532  return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
533  }
534 
535  bool isFLATGlobal(uint16_t Opcode) const {
536  return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
537  }
538 
539  static bool isFLATScratch(const MachineInstr &MI) {
540  return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
541  }
542 
543  bool isFLATScratch(uint16_t Opcode) const {
544  return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
545  }
546 
547  // Any FLAT encoded instruction, including global_* and scratch_*.
548  bool isFLAT(uint16_t Opcode) const {
549  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
550  }
551 
552  static bool isEXP(const MachineInstr &MI) {
553  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
554  }
555 
556  bool isEXP(uint16_t Opcode) const {
557  return get(Opcode).TSFlags & SIInstrFlags::EXP;
558  }
559 
560  static bool isAtomicNoRet(const MachineInstr &MI) {
561  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
562  }
563 
564  bool isAtomicNoRet(uint16_t Opcode) const {
565  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
566  }
567 
568  static bool isAtomicRet(const MachineInstr &MI) {
569  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
570  }
571 
572  bool isAtomicRet(uint16_t Opcode) const {
573  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
574  }
575 
576  static bool isAtomic(const MachineInstr &MI) {
577  return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
579  }
580 
581  bool isAtomic(uint16_t Opcode) const {
582  return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
584  }
585 
586  static bool isWQM(const MachineInstr &MI) {
587  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
588  }
589 
590  bool isWQM(uint16_t Opcode) const {
591  return get(Opcode).TSFlags & SIInstrFlags::WQM;
592  }
593 
594  static bool isDisableWQM(const MachineInstr &MI) {
595  return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
596  }
597 
598  bool isDisableWQM(uint16_t Opcode) const {
599  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
600  }
601 
602  static bool isVGPRSpill(const MachineInstr &MI) {
603  return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
604  }
605 
606  bool isVGPRSpill(uint16_t Opcode) const {
607  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
608  }
609 
610  static bool isSGPRSpill(const MachineInstr &MI) {
611  return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
612  }
613 
614  bool isSGPRSpill(uint16_t Opcode) const {
615  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
616  }
617 
618  static bool isDPP(const MachineInstr &MI) {
619  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
620  }
621 
622  bool isDPP(uint16_t Opcode) const {
623  return get(Opcode).TSFlags & SIInstrFlags::DPP;
624  }
625 
626  static bool isTRANS(const MachineInstr &MI) {
627  return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
628  }
629 
630  bool isTRANS(uint16_t Opcode) const {
631  return get(Opcode).TSFlags & SIInstrFlags::TRANS;
632  }
633 
634  static bool isVOP3P(const MachineInstr &MI) {
635  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
636  }
637 
638  bool isVOP3P(uint16_t Opcode) const {
639  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
640  }
641 
642  static bool isVINTRP(const MachineInstr &MI) {
643  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
644  }
645 
646  bool isVINTRP(uint16_t Opcode) const {
647  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
648  }
649 
650  static bool isMAI(const MachineInstr &MI) {
651  return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
652  }
653 
654  bool isMAI(uint16_t Opcode) const {
655  return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
656  }
657 
658  static bool isDOT(const MachineInstr &MI) {
659  return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
660  }
661 
662  bool isDOT(uint16_t Opcode) const {
663  return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
664  }
665 
666  static bool isScalarUnit(const MachineInstr &MI) {
667  return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
668  }
669 
670  static bool usesVM_CNT(const MachineInstr &MI) {
671  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
672  }
673 
674  static bool usesLGKM_CNT(const MachineInstr &MI) {
675  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
676  }
677 
678  static bool sopkIsZext(const MachineInstr &MI) {
679  return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
680  }
681 
682  bool sopkIsZext(uint16_t Opcode) const {
683  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
684  }
685 
686  /// \returns true if this is an s_store_dword* instruction. This is more
687  /// specific than than isSMEM && mayStore.
688  static bool isScalarStore(const MachineInstr &MI) {
689  return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
690  }
691 
692  bool isScalarStore(uint16_t Opcode) const {
693  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
694  }
695 
696  static bool isFixedSize(const MachineInstr &MI) {
697  return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
698  }
699 
700  bool isFixedSize(uint16_t Opcode) const {
701  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
702  }
703 
704  static bool hasFPClamp(const MachineInstr &MI) {
705  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
706  }
707 
708  bool hasFPClamp(uint16_t Opcode) const {
709  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
710  }
711 
712  static bool hasIntClamp(const MachineInstr &MI) {
713  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
714  }
715 
717  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
721  return MI.getDesc().TSFlags & ClampFlags;
722  }
723 
724  static bool usesFPDPRounding(const MachineInstr &MI) {
725  return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
726  }
727 
728  bool usesFPDPRounding(uint16_t Opcode) const {
729  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
730  }
731 
732  static bool isFPAtomic(const MachineInstr &MI) {
733  return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
734  }
735 
736  bool isFPAtomic(uint16_t Opcode) const {
737  return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
738  }
739 
740  bool isVGPRCopy(const MachineInstr &MI) const {
741  assert(MI.isCopy());
742  Register Dest = MI.getOperand(0).getReg();
743  const MachineFunction &MF = *MI.getParent()->getParent();
744  const MachineRegisterInfo &MRI = MF.getRegInfo();
745  return !RI.isSGPRReg(MRI, Dest);
746  }
747 
748  bool hasVGPRUses(const MachineInstr &MI) const {
749  const MachineFunction &MF = *MI.getParent()->getParent();
750  const MachineRegisterInfo &MRI = MF.getRegInfo();
751  return llvm::any_of(MI.explicit_uses(),
752  [&MRI, this](const MachineOperand &MO) {
753  return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
754  }
755 
756  /// Return true if the instruction modifies the mode register.q
757  static bool modifiesModeRegister(const MachineInstr &MI);
758 
759  /// Whether we must prevent this instruction from executing with EXEC = 0.
761 
762  /// Returns true if the instruction could potentially depend on the value of
763  /// exec. If false, exec dependencies may safely be ignored.
764  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
765 
766  bool isInlineConstant(const APInt &Imm) const;
767 
768  bool isInlineConstant(const APFloat &Imm) const {
769  return isInlineConstant(Imm.bitcastToAPInt());
770  }
771 
772  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
773 
775  const MCOperandInfo &OpInfo) const {
776  return isInlineConstant(MO, OpInfo.OperandType);
777  }
778 
779  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
780  /// be an inline immediate.
782  const MachineOperand &UseMO,
783  const MachineOperand &DefMO) const {
784  assert(UseMO.getParent() == &MI);
785  int OpIdx = MI.getOperandNo(&UseMO);
786  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
787  return false;
788  }
789 
790  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
791  }
792 
793  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
794  /// immediate.
795  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
796  const MachineOperand &MO = MI.getOperand(OpIdx);
797  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
798  }
799 
800  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
801  const MachineOperand &MO) const {
802  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
803  return false;
804 
805  if (MI.isCopy()) {
806  unsigned Size = getOpSize(MI, OpIdx);
807  assert(Size == 8 || Size == 4);
808 
809  uint8_t OpType = (Size == 8) ?
811  return isInlineConstant(MO, OpType);
812  }
813 
814  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
815  }
816 
817  bool isInlineConstant(const MachineOperand &MO) const {
818  const MachineInstr *Parent = MO.getParent();
819  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
820  }
821 
823  const MCOperandInfo &OpInfo) const {
824  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
825  }
826 
827  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
828  const MachineOperand &MO = MI.getOperand(OpIdx);
829  return MO.isImm() && !isInlineConstant(MI, OpIdx);
830  }
831 
832  // Returns true if this operand could potentially require a 32-bit literal
833  // operand, but not necessarily. A FrameIndex for example could resolve to an
834  // inline immediate value that will not require an additional 4-bytes; this
835  // assumes that it will.
836  bool isLiteralConstantLike(const MachineOperand &MO,
837  const MCOperandInfo &OpInfo) const;
838 
839  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
840  const MachineOperand &MO) const;
841 
842  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
843  /// This function will return false if you pass it a 32-bit instruction.
844  bool hasVALU32BitEncoding(unsigned Opcode) const;
845 
846  /// Returns true if this operand uses the constant bus.
848  const MachineOperand &MO,
849  const MCOperandInfo &OpInfo) const;
850 
851  /// Return true if this instruction has any modifiers.
852  /// e.g. src[012]_mod, omod, clamp.
853  bool hasModifiers(unsigned Opcode) const;
854 
855  bool hasModifiersSet(const MachineInstr &MI,
856  unsigned OpName) const;
857  bool hasAnyModifiersSet(const MachineInstr &MI) const;
858 
859  bool canShrink(const MachineInstr &MI,
860  const MachineRegisterInfo &MRI) const;
861 
863  unsigned NewOpcode) const;
864 
865  bool verifyInstruction(const MachineInstr &MI,
866  StringRef &ErrInfo) const override;
867 
868  unsigned getVALUOp(const MachineInstr &MI) const;
869 
870  /// Return the correct register class for \p OpNo. For target-specific
871  /// instructions, this will return the register class that has been defined
872  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
873  /// the register class of its machine operand.
874  /// to infer the correct register class base on the other operands.
876  unsigned OpNo) const;
877 
878  /// Return the size in bytes of the operand OpNo on the given
879  // instruction opcode.
880  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
881  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
882 
883  if (OpInfo.RegClass == -1) {
884  // If this is an immediate operand, this must be a 32-bit literal.
886  return 4;
887  }
888 
889  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
890  }
891 
892  /// This form should usually be preferred since it handles operands
893  /// with unknown register classes.
894  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
895  const MachineOperand &MO = MI.getOperand(OpNo);
896  if (MO.isReg()) {
897  if (unsigned SubReg = MO.getSubReg()) {
898  return RI.getSubRegIdxSize(SubReg) / 8;
899  }
900  }
901  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
902  }
903 
904  /// Legalize the \p OpIndex operand of this instruction by inserting
905  /// a MOV. For example:
906  /// ADD_I32_e32 VGPR0, 15
907  /// to
908  /// MOV VGPR1, 15
909  /// ADD_I32_e32 VGPR0, VGPR1
910  ///
911  /// If the operand being legalized is a register, then a COPY will be used
912  /// instead of MOV.
913  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
914 
915  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
916  /// for \p MI.
917  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
918  const MachineOperand *MO = nullptr) const;
919 
920  /// Check if \p MO would be a valid operand for the given operand
921  /// definition \p OpInfo. Note this does not attempt to validate constant bus
922  /// restrictions (e.g. literal constant usage).
924  const MCOperandInfo &OpInfo,
925  const MachineOperand &MO) const;
926 
927  /// Check if \p MO (a register operand) is a legal register for the
928  /// given operand description.
930  const MCOperandInfo &OpInfo,
931  const MachineOperand &MO) const;
932 
933  /// Legalize operands in \p MI by either commuting it or inserting a
934  /// copy of src1.
936 
937  /// Fix operands in \p MI to satisfy constant bus requirements.
939 
940  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
941  /// be used when it is know that the value in SrcReg is same across all
942  /// threads in the wave.
943  /// \returns The SGPR register that \p SrcReg was copied to.
945  MachineRegisterInfo &MRI) const;
946 
949 
952  const TargetRegisterClass *DstRC,
954  const DebugLoc &DL) const;
955 
956  /// Legalize all operands in this instruction. This function may create new
957  /// instructions and control-flow around \p MI. If present, \p MDT is
958  /// updated.
959  /// \returns A new basic block that contains \p MI if new blocks were created.
961  legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
962 
963  /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
964  /// was moved to VGPR. \returns true if succeeded.
965  bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
966 
967  /// Replace this instruction's opcode with the equivalent VALU
968  /// opcode. This function will also move the users of \p MI to the
969  /// VALU if necessary. If present, \p MDT is updated.
971  MachineDominatorTree *MDT = nullptr) const;
972 
974  MachineBasicBlock::iterator MI) const override;
975 
977  unsigned Quantity) const override;
978 
979  void insertReturn(MachineBasicBlock &MBB) const;
980  /// Return the number of wait states that result from executing this
981  /// instruction.
982  static unsigned getNumWaitStates(const MachineInstr &MI);
983 
984  /// Returns the operand named \p Op. If \p MI does not have an
985  /// operand named \c Op, this function returns nullptr.
987  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
988 
991  unsigned OpName) const {
992  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
993  }
994 
995  /// Get required immediate operand
996  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
997  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
998  return MI.getOperand(Idx).getImm();
999  }
1000 
1003 
1004  bool isLowLatencyInstruction(const MachineInstr &MI) const;
1005  bool isHighLatencyDef(int Opc) const override;
1006 
1007  /// Return the descriptor of the target-specific machine instruction
1008  /// that corresponds to the specified pseudo or native opcode.
1009  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1010  return get(pseudoToMCOpcode(Opcode));
1011  }
1012 
1013  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1014  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1015 
1016  unsigned isLoadFromStackSlot(const MachineInstr &MI,
1017  int &FrameIndex) const override;
1018  unsigned isStoreToStackSlot(const MachineInstr &MI,
1019  int &FrameIndex) const override;
1020 
1021  unsigned getInstBundleSize(const MachineInstr &MI) const;
1022  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1023 
1024  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1025 
1026  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1027 
1029  MachineBasicBlock *IfEnd) const;
1030 
1032  MachineBasicBlock *LoopEnd) const;
1033 
1034  std::pair<unsigned, unsigned>
1035  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1036 
1038  getSerializableTargetIndices() const override;
1039 
1042 
1045  const ScheduleDAG *DAG) const override;
1046 
1048  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1049 
1052  const ScheduleDAGMI *DAG) const override;
1053 
1054  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1055 
1058  const DebugLoc &DL, Register Src,
1059  Register Dst) const override;
1060 
1063  const DebugLoc &DL, Register Src,
1064  unsigned SrcSubReg,
1065  Register Dst) const override;
1066 
1067  bool isWave32() const;
1068 
1069  /// Return a partially built integer add instruction without carry.
1070  /// Caller must add source operands.
1071  /// For pre-GFX9 it will generate unused carry destination operand.
1072  /// TODO: After GFX9 it should return a no-carry operation.
1075  const DebugLoc &DL,
1076  Register DestReg) const;
1077 
1080  const DebugLoc &DL,
1081  Register DestReg,
1082  RegScavenger &RS) const;
1083 
1084  static bool isKillTerminator(unsigned Opcode);
1085  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1086 
1087  static bool isLegalMUBUFImmOffset(unsigned Imm) {
1088  return isUInt<12>(Imm);
1089  }
1090 
1091  /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1092  /// encoded instruction. If \p Signed, this is for an instruction that
1093  /// interprets the offset as signed.
1094  bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1095  uint64_t FlatVariant) const;
1096 
1097  /// Split \p COffsetVal into {immediate offset field, remainder offset}
1098  /// values.
1099  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1100  unsigned AddrSpace,
1101  uint64_t FlatVariant) const;
1102 
1103  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1104  /// Return -1 if the target-specific opcode for the pseudo instruction does
1105  /// not exist. If Opcode is not a pseudo instruction, this is identity.
1106  int pseudoToMCOpcode(int Opcode) const;
1107 
1108  /// \brief Check if this instruction should only be used by assembler.
1109  /// Return true if this opcode should not be used by codegen.
1110  bool isAsmOnlyOpcode(int MCOp) const;
1111 
1112  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1113  const TargetRegisterInfo *TRI,
1114  const MachineFunction &MF)
1115  const override;
1116 
1117  void fixImplicitOperands(MachineInstr &MI) const;
1118 
1120  ArrayRef<unsigned> Ops,
1121  MachineBasicBlock::iterator InsertPt,
1122  int FrameIndex,
1123  LiveIntervals *LIS = nullptr,
1124  VirtRegMap *VRM = nullptr) const override;
1125 
1126  unsigned getInstrLatency(const InstrItineraryData *ItinData,
1127  const MachineInstr &MI,
1128  unsigned *PredCost = nullptr) const override;
1129 
1130  const MIRFormatter *getMIRFormatter() const override {
1131  if (!Formatter.get())
1132  Formatter = std::make_unique<AMDGPUMIRFormatter>();
1133  return Formatter.get();
1134  }
1135 
1136  static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1137 
1138  const TargetSchedModel &getSchedModel() const { return SchedModel; }
1139 };
1140 
1141 /// \brief Returns true if a reg:subreg pair P has a TRC class
1143  const TargetRegisterClass &TRC,
1145  auto *RC = MRI.getRegClass(P.Reg);
1146  if (!P.SubReg)
1147  return RC == &TRC;
1148  auto *TRI = MRI.getTargetRegisterInfo();
1149  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1150 }
1151 
1152 /// \brief Create RegSubRegPair from a register MachineOperand
1153 inline
1155  assert(O.isReg());
1156  return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1157 }
1158 
1159 /// \brief Return the SubReg component from REG_SEQUENCE
1161  unsigned SubReg);
1162 
1163 /// \brief Return the defining instruction for a given reg:subreg pair
1164 /// skipping copy like instructions and subreg-manipulation pseudos.
1165 /// Following another subreg of a reg:subreg isn't supported.
1167  MachineRegisterInfo &MRI);
1168 
1169 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1170 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1171 /// attempt to track between blocks.
1172 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1173  Register VReg,
1174  const MachineInstr &DefMI,
1175  const MachineInstr &UseMI);
1176 
1177 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1178 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1179 /// track between blocks.
1180 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1181  Register VReg,
1182  const MachineInstr &DefMI);
1183 
1184 namespace AMDGPU {
1185 
1187  int getVOPe64(uint16_t Opcode);
1188 
1190  int getVOPe32(uint16_t Opcode);
1191 
1193  int getSDWAOp(uint16_t Opcode);
1194 
1196  int getDPPOp32(uint16_t Opcode);
1197 
1199  int getBasicFromSDWAOp(uint16_t Opcode);
1200 
1202  int getCommuteRev(uint16_t Opcode);
1203 
1205  int getCommuteOrig(uint16_t Opcode);
1206 
1208  int getAddr64Inst(uint16_t Opcode);
1209 
1210  /// Check if \p Opcode is an Addr64 opcode.
1211  ///
1212  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1214  int getIfAddr64Inst(uint16_t Opcode);
1215 
1217  int getMUBUFNoLdsInst(uint16_t Opcode);
1218 
1220  int getAtomicNoRetOp(uint16_t Opcode);
1221 
1223  int getSOPKOp(uint16_t Opcode);
1224 
1225  /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1226  /// of a VADDR form.
1228  int getGlobalSaddrOp(uint16_t Opcode);
1229 
1230  /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1231  /// of a SADDR form.
1233  int getGlobalVaddrOp(uint16_t Opcode);
1234 
1236  int getVCMPXNoSDstOp(uint16_t Opcode);
1237 
1238  /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1239  /// given an \p Opcode of an SS (SADDR) form.
1242 
1243  /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1244  /// of an SV (VADDR) form.
1247 
1248  /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1249  /// of an SS (SADDR) form.
1252 
1253  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1256  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1257 
1258 } // end namespace AMDGPU
1259 
1260 namespace SI {
1261 namespace KernelInputOffsets {
1262 
1263 /// Offsets in bytes from the start of the input buffer
1264 enum Offsets {
1274 };
1275 
1276 } // end namespace KernelInputOffsets
1277 } // end namespace SI
1278 
1279 } // end namespace llvm
1280 
1281 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SIInstrInfo::isIgnorableUse
bool isIgnorableUse(const MachineOperand &MO) const override
Definition: SIInstrInfo.cpp:132
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:28
llvm::AMDGPU::getVCMPXNoSDstOp
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
llvm::SIInstrInfo::isMIMG
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:503
llvm::SIInstrInfo::isMTBUF
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:475
llvm::SIInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SIInstrInfo.cpp:2416
llvm::SIInstrInfo::isAtomicRet
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:568
llvm::SIInstrInfo::insertNoops
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
Definition: SIInstrInfo.cpp:1614
llvm::SIInstrInfo::isFLAT
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:548
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
llvm::SIInstrInfo::isDPP
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:622
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:683
llvm::SIInstrInfo::isFLATGlobal
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:535
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::SIInstrInfo::insertNE
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1192
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SIInstrInfo::isDisableWQM
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:598
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:73
llvm::SIInstrInfo::swapSourceModifiers
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
Definition: SIInstrInfo.cpp:2074
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::SIInstrInfo::hasFPClamp
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:704
llvm::SIInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:3259
llvm::SIInstrInfo::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
Definition: SIInstrInfo.cpp:2736
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:82
llvm::AMDGPU::getFlatScratchInstSVfromSS
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
llvm::ARMII::VecSize
@ VecSize
Definition: ARMBaseInfo.h:417
llvm::SIInstrInfo::isSGPRSpill
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:610
llvm::SIInstrInfo::isSOP2
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:387
llvm::SIInstrInfo::isFixedSize
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:696
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2451
llvm::SIInstrInfo::isMAI
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:654
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:59
llvm::SIInstrInfo::getClampMask
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:716
llvm::getRegSubRegPair
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1154
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:53
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::AMDGPU::getAtomicNoRetOp
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
llvm::SIInstrInfo::usesLGKM_CNT
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:674
llvm::SIInstrInfo::usesVM_CNT
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:670
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SIInstrInfo::isVOP3
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:439
llvm::SIInstrInfo::hasVGPRUses
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:748
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y
@ GLOBAL_SIZE_Y
Definition: SIInstrInfo.h:1269
llvm::SIInstrInfo::getMovOpcode
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
Definition: SIInstrInfo.cpp:1205
llvm::SIInstrInfo::isSOPP
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:411
llvm::SIInstrInfo::isBufferSMRD
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7583
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:101
llvm::SIInstrInfo::getNumWaitStates
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
Definition: SIInstrInfo.cpp:1643
llvm::SIInstrInfo::MO_GOTPCREL32
@ MO_GOTPCREL32
Definition: SIInstrInfo.h:158
llvm::SIInstrInfo::isImmOperandLegal
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
Definition: SIInstrInfo.cpp:3510
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:29
llvm::SIInstrInfo::convertNonUniformLoopRegion
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
Definition: SIInstrInfo.cpp:7403
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:32
llvm::SIInstrInfo::isHighLatencyDef
bool isHighLatencyDef(int Opc) const override
Definition: SIInstrInfo.cpp:7223
llvm::SIInstrInfo::isDisableWQM
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:594
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:50
llvm::SIInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SIInstrInfo.cpp:2549
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SIInstrInfo::analyzeBranchImpl
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: SIInstrInfo.cpp:2373
llvm::SIInstrInfo::isScalarStore
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:688
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::SIInstrInfo::createPHIDestinationCopy
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
Definition: SIInstrInfo.cpp:7957
llvm::SIInstrInfo::isEXP
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:552
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:33
llvm::SIInstrInfo::isFoldableCopy
static bool isFoldableCopy(const MachineInstr &MI)
Definition: SIInstrInfo.cpp:2712
llvm::SIInstrInfo::moveToVALU
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Definition: SIInstrInfo.cpp:5787
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:36
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SIInstrInfo::modifiesModeRegister
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Definition: SIInstrInfo.cpp:3296
llvm::AMDGPU::getSOPKOp
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
llvm::SIInstrInfo::isSDWA
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:451
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::SIInstrInfo::isMUBUF
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:467
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:56
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:39
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:74
llvm::AMDGPU::getGlobalSaddrOp
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7263
TargetInstrInfo.h
llvm::SIInstrInfo::isVOP3P
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:634
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:88
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:40
llvm::SIInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV) const override
Definition: SIInstrInfo.cpp:3122
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SIInstrInfo::isAsmOnlyOpcode
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
Definition: SIInstrInfo.cpp:7715
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIInstrInfo::isVGPRSpill
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:602
llvm::SIInstrInfo::MO_MASK
@ MO_MASK
Definition: SIInstrInfo.h:152
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:63
llvm::SIInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
Definition: SIInstrInfo.cpp:7464
llvm::SIInstrInfo::getScratchRsrcWords23
uint64_t getScratchRsrcWords23() const
Definition: SIInstrInfo.cpp:7193
llvm::SIInstrInfo::MO_GOTPCREL
@ MO_GOTPCREL
Definition: SIInstrInfo.h:156
llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
Definition: SIInstrInfo.cpp:1321
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIInstrInfo::hasAnyModifiersSet
bool hasAnyModifiersSet(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:3566
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:55
llvm::SIInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: SIInstrInfo.cpp:2199
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SIInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: SIInstrInfo.cpp:1609
llvm::SIInstrInfo::isBasicBlockPrologue
bool isBasicBlockPrologue(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7510
llvm::SIInstrInfo::insertVectorSelect
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Definition: SIInstrInfo.cpp:1053
llvm::SIInstrInfo::isVOP1
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:427
llvm::SIInstrInfo::fixImplicitOperands
void fixImplicitOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7573
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:476
llvm::SIInstrInfo::isVOPC
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:459
llvm::AMDGPU::getVOPe64
LLVM_READONLY int getVOPe64(uint16_t Opcode)
llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
Definition: SIInstrInfo.cpp:3310
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:58
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:880
llvm::SIInstrInfo::isWave32
bool isWave32() const
Definition: SIInstrInfo.cpp:7992
llvm::SIInstrInfo::isVOPC
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:455
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::SIInstrInfo::canShrink
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: SIInstrInfo.cpp:3574
llvm::AMDGPU::getCommuteOrig
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:116
llvm::SIInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SIInstrInfo.cpp:659
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:154
llvm::SIInstrInfo::MO_GOTPCREL32_LO
@ MO_GOTPCREL32_LO
Definition: SIInstrInfo.h:159
llvm::SIInstrInfo::isMIMG
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:499
llvm::SIInstrInfo::isSOPK
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:403
llvm::SIInstrInfo::isAtomicNoRet
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:564
llvm::SIInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7289
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APInt &Imm) const
Definition: SIInstrInfo.cpp:3376
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::SIInstrInfo::isSOPC
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:391
llvm::SIInstrInfo::getSchedModel
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1138
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:41
llvm::SIInstrInfo::createPHISourceCopy
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Definition: SIInstrInfo.cpp:7972
llvm::SIInstrInfo::isNonUniformBranchInstr
bool isNonUniformBranchInstr(MachineInstr &Instr) const
Definition: SIInstrInfo.cpp:7374
llvm::SIInstrInfo::isMAI
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:650
llvm::SIInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:138
llvm::SIInstrInfo::isSOPK
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:399
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:85
llvm::AMDGPU::getFlatScratchInstSSfromSV
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIInstrInfo::isOperandLegal
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition: SIInstrInfo.cpp:4727
llvm::SIInstrInfo::hasIntClamp
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:712
llvm::AMDGPU::getDPPOp32
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
llvm::AMDGPU::getMUBUFNoLdsInst
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:44
llvm::AMDGPU::getVOPe32
LLVM_READONLY int getVOPe32(uint16_t Opcode)
AMDGPUMIRFormatter.h
llvm::SIInstrInfo::isVOP3
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:443
llvm::SIInstrInfo::isSegmentSpecificFLAT
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:526
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: SIInstrInfo.cpp:7451
OpName
Definition: R600Defines.h:62
llvm::SIInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: SIInstrInfo.cpp:7491
llvm::SIInstrInfo::isGather4
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:511
llvm::SIInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: SIInstrInfo.cpp:8031
llvm::SIInstrInfo::legalizeOperands
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
Definition: SIInstrInfo.cpp:5461
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:119
llvm::getVRegSubRegDef
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
Definition: SIInstrInfo.cpp:7833
llvm::SIInstrInfo::moveFlatAddrToVGPR
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
Definition: SIInstrInfo.cpp:5082
llvm::SIInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: SIInstrInfo.cpp:2176
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:57
llvm::SIInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
Definition: SIInstrInfo.cpp:2767
llvm::SIInstrInfo::sopkIsZext
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:678
llvm::SIInstrInfo::isVOP2
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:435
llvm::SIInstrInfo::getNamedOperand
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Definition: SIInstrInfo.cpp:7162
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:62
llvm::SIInstrInfo::hasModifiers
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
Definition: SIInstrInfo.cpp:3552
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::SIInstrInfo::isVOP3P
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:638
llvm::SIInstrInfo::isGather4
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:507
llvm::SIInstrInfo::MO_REL32
@ MO_REL32
Definition: SIInstrInfo.h:163
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1130
llvm::SIInstrInfo::legalizeGenericOperand
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
Definition: SIInstrInfo.cpp:5181
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:48
llvm::AMDGPU::getSDWAOp
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::SIInstrInfo::isScalarUnit
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:666
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::SIInstrInfo::MO_FAR_BRANCH_OFFSET
@ MO_FAR_BRANCH_OFFSET
Definition: SIInstrInfo.h:168
llvm::SI::KernelInputOffsets::NGROUPS_Z
@ NGROUPS_Z
Definition: SIInstrInfo.h:1267
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIInstrInfo::isVALU
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:363
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:68
llvm::SIInstrInfo::MO_ABS32_LO
@ MO_ABS32_LO
Definition: SIInstrInfo.h:170
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::SIInstrInfo::TargetOperandFlags
TargetOperandFlags
Definition: SIInstrInfo.h:151
llvm::SIInstrInfo::getAddNoCarry
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
Definition: SIInstrInfo.cpp:7516
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:122
llvm::SIInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:7249
llvm::SIInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: SIInstrInfo.cpp:110
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:768
llvm::SIInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7496
llvm::APFloat
Definition: APFloat.h:701
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:894
llvm::SIInstrInfo::MO_ABS32_HI
@ MO_ABS32_HI
Definition: SIInstrInfo.h:171
llvm::SIInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SIInstrInfo.cpp:2605
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:197
llvm::SIInstrInfo::isDPP
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:618
llvm::SIInstrInfo::isWQM
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:590
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:71
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:113
llvm::SIInstrInfo::isLowLatencyInstruction
bool isLowLatencyInstruction(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7217
TargetSchedule.h
llvm::SIInstrInfo::hasVALU32BitEncoding
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
Definition: SIInstrInfo.cpp:3540
llvm::SIInstrInfo::getNamedImmOperand
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:996
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::execMayBeModifiedBeforeAnyUse
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
Definition: SIInstrInfo.cpp:7901
uint64_t
llvm::SIInstrInfo::insertIndirectBranch
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
Definition: SIInstrInfo.cpp:2226
llvm::SIInstrInfo::hasFPClamp
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:708
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:34
llvm::SI::KernelInputOffsets::LOCAL_SIZE_X
@ LOCAL_SIZE_X
Definition: SIInstrInfo.h:1271
llvm::SIInstrInfo::getMIRFormatter
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1130
llvm::SIInstrInfo::buildExtractSubReg
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4628
llvm::SIInstrInfo::sopkIsZext
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:682
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:539
llvm::SIInstrInfo::isDS
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:489
llvm::SIInstrInfo::isDS
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:493
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2179
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:479
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::execMayBeModifiedBeforeUse
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
Definition: SIInstrInfo.cpp:7868
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIInstrInfo::isLegalFLATOffset
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
Definition: SIInstrInfo.cpp:7626
llvm::SIInstrInfo::legalizeOperandsFLAT
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5163
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:56
llvm::SIInstrInfo::isSOP2
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:383
llvm::SIInstrInfo::isScalarStore
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:692
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:101
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInstrInfo::MO_REL32_LO
@ MO_REL32_LO
Definition: SIInstrInfo.h:164
llvm::SIInstrInfo::isAlwaysGDS
bool isAlwaysGDS(uint16_t Opcode) const
Definition: SIInstrInfo.cpp:3286
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::SIInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:2215
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:795
llvm::SIInstrInfo::isVMEM
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:371
llvm::SIInstrInfo::isFPAtomic
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:732
llvm::SIInstrInfo::isSGPRSpill
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:614
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:35
llvm::SIInstrInfo::isPacked
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:415
llvm::SIInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1558
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:576
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::SIInstrInfo::isSOP1
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:375
llvm::SIInstrInfo::isSALU
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:351
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SIInstrInfo::insertReturn
void insertReturn(MachineBasicBlock &MBB) const
Definition: SIInstrInfo.cpp:1625
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::SIInstrInfo::mayAccessFlatAddressSpace
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7360
llvm::SIInstrInfo::isVOP1
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:423
llvm::SI::KernelInputOffsets::NGROUPS_Y
@ NGROUPS_Y
Definition: SIInstrInfo.h:1266
llvm::AMDGPU::RSRC_DATA_FORMAT
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1253
llvm::SIInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Definition: SIInstrInfo.cpp:436
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SIInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SIInstrInfo.cpp:2489
llvm::SIInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
Definition: SIInstrInfo.cpp:2563
llvm::SIInstrInfo::MO_REL32_HI
@ MO_REL32_HI
Definition: SIInstrInfo.h:166
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::SIInstrInfo::usesConstantBus
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
Definition: SIInstrInfo.cpp:3692
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SIInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3777
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:774
llvm::SIInstrInfo::isFixedSize
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:700
llvm::SIInstrInfo::isSDWA
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:447
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIInstrInfo::isSALU
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:355
llvm::SIInstrInfo::isVOP2
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:431
llvm::SIInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Definition: SIInstrInfo.cpp:8129
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:263
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:92
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:822
AMDGPUGenInstrInfo
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:463
llvm::SIInstrInfo::isAtomic
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:581
llvm::SIInstrInfo::isDOT
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:658
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:66
llvm::SIInstrInfo::isVINTRP
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:646
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::SIInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
Definition: SIInstrInfo.cpp:2124
llvm::SIInstrInfo::CreateTargetMIHazardRecognizer
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
Definition: SIInstrInfo.cpp:7479
llvm::SIInstrInfo::isKillTerminator
static bool isKillTerminator(unsigned Opcode)
Definition: SIInstrInfo.cpp:7552
llvm::AMDGPU::getCommuteRev
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1087
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::SIInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:1662
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:107
llvm::SIInstrInfo::legalizeOpWithMove
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
Definition: SIInstrInfo.cpp:4601
llvm::SIInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
Definition: SIInstrInfo.cpp:253
llvm::SIInstrInfo::isTRANS
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:630
llvm::SIInstrInfo::splitFlatOffset
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition: SIInstrInfo.cpp:7653
llvm::SIInstrInfo::convertNonUniformIfRegion
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
Definition: SIInstrInfo.cpp:7378
llvm::SIInstrInfo::isVGPRSpill
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:606
llvm::SIInstrInfo::getMCOpcodeFromPseudo
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1009
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SIInstrInfo::isAtomicNoRet
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:560
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::SIInstrInfo::legalizeOperandsVOP2
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition: SIInstrInfo.cpp:4822
llvm::SIInstrInfo::getMachineCSELookAheadLimit
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:342
llvm::SIInstrInfo::isSegmentSpecificFLAT
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:521
llvm::AMDGPU::getAddr64Inst
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
llvm::SIInstrInfo::getVALUOp
unsigned getVALUOp(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4449
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:367
llvm::getRegSequenceSubReg
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
Definition: SIInstrInfo.cpp:7796
llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SIInstrInfo.cpp:3040
llvm::SIInstrInfo::expandMovDPP64
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2018
llvm::SIInstrInfo::buildExtractSubRegOrImm
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4660
llvm::AMDGPU::getIfAddr64Inst
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
llvm::SIInstrInfo::isStackAccess
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7228
llvm::SIInstrInfo::getRegisterInfo
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:176
llvm::SIInstrInfo::getPreferredSelectRegClass
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
Definition: SIInstrInfo.cpp:1049
llvm::SIInstrInfo::isMTBUF
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:471
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIInstrInfo::isSMRD
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:483
llvm::SIInstrInfo::buildShrunkInst
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
Definition: SIInstrInfo.cpp:3647
llvm::SIInstrInfo::isFLATScratch
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:543
llvm::SIInstrInfo::getDSShaderTypeValue
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
Definition: SIInstrInfo.cpp:8048
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y
@ LOCAL_SIZE_Y
Definition: SIInstrInfo.h:1272
llvm::SIInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SIInstrInfo.cpp:7994
llvm::SIInstrInfo::SIInstrInfo
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:66
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
llvm::SIInstrInfo::isDOT
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:662
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::AMDGPU::RSRC_TID_ENABLE
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1256
llvm::SIInstrInfo::usesFPDPRounding
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:728
llvm::SIInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SIInstrInfo.cpp:2459
llvm::SIInstrInfo::legalizeOperandsSMRD
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5063
llvm::SI::KernelInputOffsets::NGROUPS_X
@ NGROUPS_X
Definition: SIInstrInfo.h:1265
llvm::SIInstrInfo::getDefaultRsrcDataFormat
uint64_t getDefaultRsrcDataFormat() const
Definition: SIInstrInfo.cpp:7171
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(unsigned Opc) const
Definition: SIInstrInfo.cpp:974
llvm::AMDGPU::getBasicFromSDWAOp
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:817
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:29
llvm::SIInstrInfo::isSOPP
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:407
llvm::SIInstrInfo::isLegalRegOperand
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
Definition: SIInstrInfo.cpp:4689
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z
@ GLOBAL_SIZE_Z
Definition: SIInstrInfo.h:1270
llvm::SIInstrInfo::usesFPDPRounding
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:724
llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1255
llvm::SIInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
Definition: SIInstrInfo.cpp:479
llvm::SIInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
Definition: SIInstrInfo.cpp:8070
llvm::SIInstrInfo::isFLATGlobal
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:531
llvm::SIInstrInfo::MO_GOTPCREL32_HI
@ MO_GOTPCREL32_HI
Definition: SIInstrInfo.h:161
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z
@ LOCAL_SIZE_Z
Definition: SIInstrInfo.h:1273
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:72
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:104
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:359
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:75
llvm::SIInstrInfo::isLiteralConstantLike
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.cpp:3477
llvm::SIInstrInfo::isFPAtomic
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:736
llvm::SIInstrInfo::isWQM
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:586
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:827
llvm::SIInstrInfo::getNamedOperand
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:990
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:45
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:47
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:144
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X
@ GLOBAL_SIZE_X
Definition: SIInstrInfo.h:1268
llvm::SIInstrInfo::isLegalVSrcOperand
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
Definition: SIInstrInfo.cpp:4716
llvm::SIInstrInfo::getOpRegClass
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Definition: SIInstrInfo.cpp:4583
llvm::SIInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1419
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:110
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SIInstrInfo::materializeImmediate
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
Definition: SIInstrInfo.cpp:992
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:70
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::SIInstrInfo::readlaneVGPRToSGPR
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
Definition: SIInstrInfo.cpp:5021
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::SIInstrInfo::isVGPRCopy
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:740
llvm::SIInstrInfo::isSGPRStackAccess
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:7241
llvm::SIInstrInfo::isEXP
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:556
llvm::SIInstrInfo::isTRANS
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:626
llvm::SIInstrInfo::isAtomicRet
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:572
llvm::SIInstrInfo::getSubtarget
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:180
llvm::SIInstrInfo::isPacked
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:419
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:515
llvm::SIInstrInfo::insertEQ
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1179
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:54
llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1254
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1264
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:800
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::isOfRegClass
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1142
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:49
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:95
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIInstrInfo::getRegClass
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:4551
llvm::SIInstrInfo::hasModifiersSet
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:3560
llvm::SIInstrInfo::mayReadEXEC
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
Definition: SIInstrInfo.cpp:3351
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SIInstrInfo::getKillTerminatorFromPseudo
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Definition: SIInstrInfo.cpp:7562
SIRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SIInstrInfo::isSOPC
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:395
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:145
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIInstrInfo::getIndirectGPRIDXPseudo
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
Definition: SIInstrInfo.cpp:1220
llvm::SIInstrInfo::pseudoToMCOpcode
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Definition: SIInstrInfo.cpp:7735
llvm::AMDGPU::getGlobalVaddrOp
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isVINTRP
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:642
llvm::SIInstrInfo::isSOP1
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:379
llvm::SIInstrInfo::legalizeOperandsVOP3
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Definition: SIInstrInfo.cpp:4934
SetVector.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
AMDGPUBaseInfo.h
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:781
llvm::SIInstrInfo::getInstBundleSize
unsigned getInstBundleSize(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7277