Go to the documentation of this file.
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
43 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
46 enum BranchPredicate {
58 static unsigned getBranchOpcode(BranchPredicate
Cond);
59 static BranchPredicate getBranchPredicate(
unsigned Opcode);
77 std::pair<bool, MachineBasicBlock *>
92 unsigned Opcode)
const;
96 unsigned Opcode)
const;
100 bool Swap =
false)
const;
128 getDestEquivalentVGPRClass(
const MachineInstr &Inst)
const;
130 bool checkInstOffsetsDoNotOverlap(
const MachineInstr &MIa,
142 unsigned OpIdx1)
const override;
184 int64_t &Offset2)
const override;
189 bool &OffsetIsScalable,
unsigned &
Width,
194 unsigned NumLoads,
unsigned NumBytes)
const override;
197 int64_t Offset1,
unsigned NumLoads)
const override;
201 bool KillSrc)
const override;
207 int64_t
Value)
const;
210 unsigned Size)
const;
238 std::pair<MachineInstr*, MachineInstr*>
251 bool IsIndirectSrc)
const;
261 unsigned &SrcOpIdx2)
const override;
264 unsigned & SrcOpIdx1)
const;
267 int64_t BrOffset)
const override;
282 bool AllowModify)
const;
287 bool AllowModify =
false)
const override;
290 int *BytesRemoved =
nullptr)
const override;
295 int *BytesAdded =
nullptr)
const override;
303 int &TrueCycles,
int &FalseCycles)
const override;
316 unsigned Kind)
const override;
508 auto Flags =
MI.getDesc().TSFlags;
513 auto Flags =
get(Opcode).TSFlags;
707 return MI.getDesc().TSFlags & ClampFlags;
739 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
771 int OpIdx =
MI.getOperandNo(&UseMO);
772 if (!
MI.getDesc().OpInfo || OpIdx >=
MI.getDesc().NumOperands) {
788 if (!
MI.getDesc().OpInfo || OpIdx >=
MI.getDesc().NumOperands)
795 uint8_t OpType = (
Size == 8) ?
849 unsigned NewOpcode)
const;
862 unsigned OpNo)
const;
884 return RI.getSubRegIdxSize(
SubReg) / 8;
959 unsigned Quantity)
const override;
980 return MI.getOperand(Idx).getImm();
1016 std::pair<unsigned, unsigned>
1066 return isUInt<12>(Imm);
1073 uint64_t FlatVariant)
const;
1079 uint64_t FlatVariant)
const;
1106 unsigned *PredCost =
nullptr)
const override;
1109 if (!Formatter.get())
1110 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1111 return Formatter.get();
1143 MachineRegisterInfo &
MRI);
1150 const MachineInstr &
DefMI,
1151 const MachineInstr &
UseMI);
1158 const MachineInstr &
DefMI);
1221 namespace KernelInputOffsets {
1241 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
bool isMIMG(uint16_t Opcode) const
bool isMTBUF(uint16_t Opcode) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isAtomicRet(const MachineInstr &MI)
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
bool isFLAT(uint16_t Opcode) const
bool isDPP(uint16_t Opcode) const
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
bool isFLATGlobal(uint16_t Opcode) const
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
bool isDisableWQM(uint16_t Opcode) const
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
MachineInstrBuilder & UseMI
static bool hasFPClamp(const MachineInstr &MI)
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
static bool isSGPRSpill(const MachineInstr &MI)
bool isSOP2(uint16_t Opcode) const
static bool isFixedSize(const MachineInstr &MI)
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isMAI(uint16_t Opcode) const
uint64_t getClampMask(const MachineInstr &MI) const
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
static bool usesLGKM_CNT(const MachineInstr &MI)
static bool usesVM_CNT(const MachineInstr &MI)
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
static bool isVOP3(const MachineInstr &MI)
bool hasVGPRUses(const MachineInstr &MI) const
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
bool isSOPP(uint16_t Opcode) const
bool isBufferSMRD(const MachineInstr &MI) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
bool isHighLatencyDef(int Opc) const override
static bool isDisableWQM(const MachineInstr &MI)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isScalarStore(const MachineInstr &MI)
const TargetRegisterInfo * getTargetRegisterInfo() const
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
static bool isEXP(const MachineInstr &MI)
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Represents one node in the SelectionDAG.
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
bool isSDWA(uint16_t Opcode) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isMUBUF(uint16_t Opcode) const
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isVOP3P(const MachineInstr &MI)
bool isFoldableCopy(const MachineInstr &MI) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
static bool isVGPRSpill(const MachineInstr &MI)
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
uint64_t getScratchRsrcWords23() const
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool hasAnyModifiersSet(const MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned const TargetRegisterInfo * TRI
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool isBasicBlockPrologue(const MachineInstr &MI) const override
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
bool isVOP1(uint16_t Opcode) const
void fixImplicitOperands(MachineInstr &MI) const
A pair composed of a register and a sub-register index.
bool isVOPC(uint16_t Opcode) const
LLVM_READONLY int getVOPe64(uint16_t Opcode)
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
static bool isVOPC(const MachineInstr &MI)
This holds information about one operand of a machine instruction, indicating the register class for ...
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool isMIMG(const MachineInstr &MI)
bool isSOPK(uint16_t Opcode) const
bool isAtomicNoRet(uint16_t Opcode) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isInlineConstant(const APInt &Imm) const
static bool isSOPC(const MachineInstr &MI)
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
bool isNonUniformBranchInstr(MachineInstr &Instr) const
static bool isMAI(const MachineInstr &MI)
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
static bool isSOPK(const MachineInstr &MI)
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
static bool hasIntClamp(const MachineInstr &MI)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
bool isVOP3(uint16_t Opcode) const
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isGather4(uint16_t Opcode) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
static bool sopkIsZext(const MachineInstr &MI)
bool isVOP2(uint16_t Opcode) const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool isVOP3P(uint16_t Opcode) const
static bool isGather4(const MachineInstr &MI)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
APInt bitcastToAPInt() const
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static bool isScalarUnit(const MachineInstr &MI)
bool isVALU(uint16_t Opcode) const
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
bool isInlineConstant(const APFloat &Imm) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isDPP(const MachineInstr &MI)
bool isWQM(uint16_t Opcode) const
bool isLowLatencyInstruction(const MachineInstr &MI) const
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Provide an instruction scheduling machine model to CodeGen passes.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
bool hasFPClamp(uint16_t Opcode) const
const MIRFormatter * getMIRFormatter() const override
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool sopkIsZext(uint16_t Opcode) const
uint8_t OperandType
Information about the type of the operand.
static bool isFLATScratch(const MachineInstr &MI)
static bool isDS(const MachineInstr &MI)
bool isDS(uint16_t Opcode) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
static bool isSMRD(const MachineInstr &MI)
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
OperandType
Operands are tagged with one of the values of this enum.
static bool isSOP2(const MachineInstr &MI)
bool isScalarStore(uint16_t Opcode) const
TargetInstrInfo::RegSubRegPair RegSubRegPair
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAlwaysGDS(uint16_t Opcode) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
bool isVMEM(uint16_t Opcode) const
static bool isFPAtomic(const MachineInstr &MI)
bool isSGPRSpill(uint16_t Opcode) const
@ MO_LONG_BRANCH_BACKWARD
static bool isPacked(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isAtomic(const MachineInstr &MI)
static bool isSOP1(const MachineInstr &MI)
static bool isSALU(const MachineInstr &MI)
Class for arbitrary precision integers.
void insertReturn(MachineBasicBlock &MBB) const
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
static bool isVOP1(const MachineInstr &MI)
const uint64_t RSRC_DATA_FORMAT
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
SmallVector< MachineOperand, 4 > Cond
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
StringRef - Represent a constant reference to a string, i.e.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
bool isFixedSize(uint16_t Opcode) const
static bool isSDWA(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool isSALU(uint16_t Opcode) const
static bool isVOP2(const MachineInstr &MI)
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
static bool isMUBUF(const MachineInstr &MI)
bool isAtomic(uint16_t Opcode) const
static bool isDOT(const MachineInstr &MI)
bool isVINTRP(uint16_t Opcode) const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
static bool isKillTerminator(unsigned Opcode)
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
static bool isLegalMUBUFImmOffset(unsigned Imm)
bool expandPostRAPseudo(MachineInstr &MI) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
bool isTRANS(uint16_t Opcode) const
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
bool isVGPRSpill(uint16_t Opcode) const
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Should compile to something r4 addze r3 instead we get
static bool isAtomicNoRet(const MachineInstr &MI)
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
unsigned getMachineCSELookAheadLimit() const override
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Iterator for intrusive lists based on ilist_node.
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
unsigned getVALUOp(const MachineInstr &MI) const
static bool isVMEM(const MachineInstr &MI)
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
const SIRegisterInfo & getRegisterInfo() const
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
static bool isMTBUF(const MachineInstr &MI)
bool isSMRD(uint16_t Opcode) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
bool isFLATScratch(uint16_t Opcode) const
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
SIInstrInfo(const GCNSubtarget &ST)
bool isDOT(uint16_t Opcode) const
const uint64_t RSRC_TID_ENABLE
bool usesFPDPRounding(uint16_t Opcode) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
uint64_t getDefaultRsrcDataFormat() const
LLVM_READONLY int commuteOpcode(unsigned Opc) const
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
bool isInlineConstant(const MachineOperand &MO) const
static bool isSOPP(const MachineInstr &MI)
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
static bool usesFPDPRounding(const MachineInstr &MI)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
static bool isFLATGlobal(const MachineInstr &MI)
static bool isVALU(const MachineInstr &MI)
MachineInstrBuilder MachineInstrBuilder & DefMI
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
bool isFPAtomic(uint16_t Opcode) const
static bool isWQM(const MachineInstr &MI)
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
A SetVector that performs no allocations if smaller than a certain size.
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isVGPRCopy(const MachineInstr &MI) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
bool isEXP(uint16_t Opcode) const
static bool isTRANS(const MachineInstr &MI)
bool isAtomicRet(uint16_t Opcode) const
const GCNSubtarget & getSubtarget() const
bool isPacked(uint16_t Opcode) const
static bool isFLAT(const MachineInstr &MI)
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
LLVM Value Representation.
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Itinerary data supplied by a subtarget to be used by a target.
bool isSOPC(uint16_t Opcode) const
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
static bool isVINTRP(const MachineInstr &MI)
bool isSOP1(uint16_t Opcode) const
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Wrapper class representing physical registers. Should be passed by value.
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
unsigned getInstBundleSize(const MachineInstr &MI) const