LLVM  13.0.0git
SIInstrInfo.h
Go to the documentation of this file.
1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 class SIInstrInfo final : public AMDGPUGenInstrInfo {
39 private:
40  const SIRegisterInfo RI;
41  const GCNSubtarget &ST;
42  TargetSchedModel SchedModel;
43  mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
44 
45  // The inverse predicate should have the negative value.
46  enum BranchPredicate {
47  INVALID_BR = 0,
48  SCC_TRUE = 1,
49  SCC_FALSE = -1,
50  VCCNZ = 2,
51  VCCZ = -2,
52  EXECNZ = -3,
53  EXECZ = 3
54  };
55 
57 
58  static unsigned getBranchOpcode(BranchPredicate Cond);
59  static BranchPredicate getBranchPredicate(unsigned Opcode);
60 
61 public:
64  MachineOperand &SuperReg,
65  const TargetRegisterClass *SuperRC,
66  unsigned SubIdx,
67  const TargetRegisterClass *SubRC) const;
70  MachineOperand &SuperReg,
71  const TargetRegisterClass *SuperRC,
72  unsigned SubIdx,
73  const TargetRegisterClass *SubRC) const;
74 private:
75  void swapOperands(MachineInstr &Inst) const;
76 
77  std::pair<bool, MachineBasicBlock *>
78  moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
79  MachineDominatorTree *MDT = nullptr) const;
80 
81  void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
82  MachineDominatorTree *MDT = nullptr) const;
83 
84  void lowerScalarAbs(SetVectorType &Worklist,
85  MachineInstr &Inst) const;
86 
87  void lowerScalarXnor(SetVectorType &Worklist,
88  MachineInstr &Inst) const;
89 
90  void splitScalarNotBinop(SetVectorType &Worklist,
91  MachineInstr &Inst,
92  unsigned Opcode) const;
93 
94  void splitScalarBinOpN2(SetVectorType &Worklist,
95  MachineInstr &Inst,
96  unsigned Opcode) const;
97 
98  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
99  MachineInstr &Inst, unsigned Opcode,
100  bool Swap = false) const;
101 
102  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
103  MachineDominatorTree *MDT = nullptr) const;
104 
105  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
106  unsigned Opcode,
107  MachineDominatorTree *MDT = nullptr) const;
108 
109  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
110  MachineDominatorTree *MDT = nullptr) const;
111 
112  void splitScalar64BitBCNT(SetVectorType &Worklist,
113  MachineInstr &Inst) const;
114  void splitScalar64BitBFE(SetVectorType &Worklist,
115  MachineInstr &Inst) const;
116  void movePackToVALU(SetVectorType &Worklist,
118  MachineInstr &Inst) const;
119 
120  void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
121  SetVectorType &Worklist) const;
122 
123  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
124  MachineInstr &SCCDefInst,
125  SetVectorType &Worklist) const;
126 
127  const TargetRegisterClass *
128  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
129 
130  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
131  const MachineInstr &MIb) const;
132 
133  Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
134 
135 protected:
137  MachineOperand &Src0, unsigned Src0OpName,
138  MachineOperand &Src1, unsigned Src1OpName) const;
139 
141  unsigned OpIdx0,
142  unsigned OpIdx1) const override;
143 
144 public:
146  MO_MASK = 0xf,
147 
148  MO_NONE = 0,
149  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
151  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
154  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
156  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
157  MO_REL32 = 4,
159  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
161 
164 
167  };
168 
169  explicit SIInstrInfo(const GCNSubtarget &ST);
170 
172  return RI;
173  }
174 
175  const GCNSubtarget &getSubtarget() const {
176  return ST;
177  }
178 
180  AAResults *AA) const override;
181 
182  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
183  int64_t &Offset1,
184  int64_t &Offset2) const override;
185 
187  const MachineInstr &LdSt,
189  bool &OffsetIsScalable, unsigned &Width,
190  const TargetRegisterInfo *TRI) const final;
191 
194  unsigned NumLoads, unsigned NumBytes) const override;
195 
196  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
197  int64_t Offset1, unsigned NumLoads) const override;
198 
200  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
201  bool KillSrc) const override;
202 
205  const DebugLoc &DL,
206  unsigned DestReg,
207  int64_t Value) const;
208 
210  unsigned Size) const;
211 
214  Register SrcReg, int Value) const;
215 
218  Register SrcReg, int Value) const;
219 
222  bool isKill, int FrameIndex,
223  const TargetRegisterClass *RC,
224  const TargetRegisterInfo *TRI) const override;
225 
228  int FrameIndex, const TargetRegisterClass *RC,
229  const TargetRegisterInfo *TRI) const override;
230 
231  bool expandPostRAPseudo(MachineInstr &MI) const override;
232 
233  // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
234  // instructions. Returns a pair of generated instructions.
235  // Can split either post-RA with physical registers or pre-RA with
236  // virtual registers. In latter case IR needs to be in SSA form and
237  // and a REG_SEQUENCE is produced to define original register.
238  std::pair<MachineInstr*, MachineInstr*>
240 
241  // Returns an opcode that can be used to move a value to a \p DstRC
242  // register. If there is no hardware instruction that can store to \p
243  // DstRC, then AMDGPU::COPY is returned.
244  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
245 
246  const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
247  unsigned EltSize,
248  bool IsSGPR) const;
249 
250  const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
251  bool IsIndirectSrc) const;
253  int commuteOpcode(unsigned Opc) const;
254 
256  inline int commuteOpcode(const MachineInstr &MI) const {
257  return commuteOpcode(MI.getOpcode());
258  }
259 
260  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
261  unsigned &SrcOpIdx2) const override;
262 
263  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
264  unsigned & SrcOpIdx1) const;
265 
266  bool isBranchOffsetInRange(unsigned BranchOpc,
267  int64_t BrOffset) const override;
268 
269  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
270 
272  MachineBasicBlock &NewDestBB,
273  const DebugLoc &DL,
274  int64_t BrOffset,
275  RegScavenger *RS = nullptr) const override;
276 
279  MachineBasicBlock *&TBB,
280  MachineBasicBlock *&FBB,
282  bool AllowModify) const;
283 
285  MachineBasicBlock *&FBB,
287  bool AllowModify = false) const override;
288 
290  int *BytesRemoved = nullptr) const override;
291 
294  const DebugLoc &DL,
295  int *BytesAdded = nullptr) const override;
296 
298  SmallVectorImpl<MachineOperand> &Cond) const override;
299 
302  Register TrueReg, Register FalseReg, int &CondCycles,
303  int &TrueCycles, int &FalseCycles) const override;
304 
308  Register TrueReg, Register FalseReg) const override;
309 
313  Register TrueReg, Register FalseReg) const;
314 
316  unsigned Kind) const override;
317 
318  bool
320  const MachineInstr &MIb) const override;
321 
322  bool isFoldableCopy(const MachineInstr &MI) const;
323 
325  MachineRegisterInfo *MRI) const final;
326 
327  unsigned getMachineCSELookAheadLimit() const override { return 500; }
328 
330  MachineInstr &MI,
331  LiveVariables *LV) const override;
332 
334  const MachineBasicBlock *MBB,
335  const MachineFunction &MF) const override;
336 
337  static bool isSALU(const MachineInstr &MI) {
338  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
339  }
340 
341  bool isSALU(uint16_t Opcode) const {
342  return get(Opcode).TSFlags & SIInstrFlags::SALU;
343  }
344 
345  static bool isVALU(const MachineInstr &MI) {
346  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
347  }
348 
349  bool isVALU(uint16_t Opcode) const {
350  return get(Opcode).TSFlags & SIInstrFlags::VALU;
351  }
352 
353  static bool isVMEM(const MachineInstr &MI) {
354  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
355  }
356 
357  bool isVMEM(uint16_t Opcode) const {
358  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
359  }
360 
361  static bool isSOP1(const MachineInstr &MI) {
362  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
363  }
364 
365  bool isSOP1(uint16_t Opcode) const {
366  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
367  }
368 
369  static bool isSOP2(const MachineInstr &MI) {
370  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
371  }
372 
373  bool isSOP2(uint16_t Opcode) const {
374  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
375  }
376 
377  static bool isSOPC(const MachineInstr &MI) {
378  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
379  }
380 
381  bool isSOPC(uint16_t Opcode) const {
382  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
383  }
384 
385  static bool isSOPK(const MachineInstr &MI) {
386  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
387  }
388 
389  bool isSOPK(uint16_t Opcode) const {
390  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
391  }
392 
393  static bool isSOPP(const MachineInstr &MI) {
394  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
395  }
396 
397  bool isSOPP(uint16_t Opcode) const {
398  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
399  }
400 
401  static bool isPacked(const MachineInstr &MI) {
402  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
403  }
404 
405  bool isPacked(uint16_t Opcode) const {
406  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
407  }
408 
409  static bool isVOP1(const MachineInstr &MI) {
410  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
411  }
412 
413  bool isVOP1(uint16_t Opcode) const {
414  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
415  }
416 
417  static bool isVOP2(const MachineInstr &MI) {
418  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
419  }
420 
421  bool isVOP2(uint16_t Opcode) const {
422  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
423  }
424 
425  static bool isVOP3(const MachineInstr &MI) {
426  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
427  }
428 
429  bool isVOP3(uint16_t Opcode) const {
430  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
431  }
432 
433  static bool isSDWA(const MachineInstr &MI) {
434  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
435  }
436 
437  bool isSDWA(uint16_t Opcode) const {
438  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
439  }
440 
441  static bool isVOPC(const MachineInstr &MI) {
442  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
443  }
444 
445  bool isVOPC(uint16_t Opcode) const {
446  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
447  }
448 
449  static bool isMUBUF(const MachineInstr &MI) {
450  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
451  }
452 
453  bool isMUBUF(uint16_t Opcode) const {
454  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
455  }
456 
457  static bool isMTBUF(const MachineInstr &MI) {
458  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
459  }
460 
461  bool isMTBUF(uint16_t Opcode) const {
462  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
463  }
464 
465  static bool isSMRD(const MachineInstr &MI) {
466  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
467  }
468 
469  bool isSMRD(uint16_t Opcode) const {
470  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
471  }
472 
473  bool isBufferSMRD(const MachineInstr &MI) const;
474 
475  static bool isDS(const MachineInstr &MI) {
476  return MI.getDesc().TSFlags & SIInstrFlags::DS;
477  }
478 
479  bool isDS(uint16_t Opcode) const {
480  return get(Opcode).TSFlags & SIInstrFlags::DS;
481  }
482 
483  bool isAlwaysGDS(uint16_t Opcode) const;
484 
485  static bool isMIMG(const MachineInstr &MI) {
486  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
487  }
488 
489  bool isMIMG(uint16_t Opcode) const {
490  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
491  }
492 
493  static bool isGather4(const MachineInstr &MI) {
494  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
495  }
496 
497  bool isGather4(uint16_t Opcode) const {
498  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
499  }
500 
501  static bool isFLAT(const MachineInstr &MI) {
502  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
503  }
504 
505  // Is a FLAT encoded instruction which accesses a specific segment,
506  // i.e. global_* or scratch_*.
507  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
508  auto Flags = MI.getDesc().TSFlags;
510  }
511 
512  bool isSegmentSpecificFLAT(uint16_t Opcode) const {
513  auto Flags = get(Opcode).TSFlags;
515  }
516 
517  static bool isFLATGlobal(const MachineInstr &MI) {
518  return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
519  }
520 
521  bool isFLATGlobal(uint16_t Opcode) const {
522  return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
523  }
524 
525  static bool isFLATScratch(const MachineInstr &MI) {
526  return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
527  }
528 
529  bool isFLATScratch(uint16_t Opcode) const {
530  return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
531  }
532 
533  // Any FLAT encoded instruction, including global_* and scratch_*.
534  bool isFLAT(uint16_t Opcode) const {
535  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
536  }
537 
538  static bool isEXP(const MachineInstr &MI) {
539  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
540  }
541 
542  bool isEXP(uint16_t Opcode) const {
543  return get(Opcode).TSFlags & SIInstrFlags::EXP;
544  }
545 
546  static bool isAtomicNoRet(const MachineInstr &MI) {
547  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
548  }
549 
550  bool isAtomicNoRet(uint16_t Opcode) const {
551  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
552  }
553 
554  static bool isAtomicRet(const MachineInstr &MI) {
555  return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
556  }
557 
558  bool isAtomicRet(uint16_t Opcode) const {
559  return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
560  }
561 
562  static bool isAtomic(const MachineInstr &MI) {
563  return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
565  }
566 
567  bool isAtomic(uint16_t Opcode) const {
568  return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
570  }
571 
572  static bool isWQM(const MachineInstr &MI) {
573  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
574  }
575 
576  bool isWQM(uint16_t Opcode) const {
577  return get(Opcode).TSFlags & SIInstrFlags::WQM;
578  }
579 
580  static bool isDisableWQM(const MachineInstr &MI) {
581  return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
582  }
583 
584  bool isDisableWQM(uint16_t Opcode) const {
585  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
586  }
587 
588  static bool isVGPRSpill(const MachineInstr &MI) {
589  return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
590  }
591 
592  bool isVGPRSpill(uint16_t Opcode) const {
593  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
594  }
595 
596  static bool isSGPRSpill(const MachineInstr &MI) {
597  return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
598  }
599 
600  bool isSGPRSpill(uint16_t Opcode) const {
601  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
602  }
603 
604  static bool isDPP(const MachineInstr &MI) {
605  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
606  }
607 
608  bool isDPP(uint16_t Opcode) const {
609  return get(Opcode).TSFlags & SIInstrFlags::DPP;
610  }
611 
612  static bool isTRANS(const MachineInstr &MI) {
613  return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
614  }
615 
616  bool isTRANS(uint16_t Opcode) const {
617  return get(Opcode).TSFlags & SIInstrFlags::TRANS;
618  }
619 
620  static bool isVOP3P(const MachineInstr &MI) {
621  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
622  }
623 
624  bool isVOP3P(uint16_t Opcode) const {
625  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
626  }
627 
628  static bool isVINTRP(const MachineInstr &MI) {
629  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
630  }
631 
632  bool isVINTRP(uint16_t Opcode) const {
633  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
634  }
635 
636  static bool isMAI(const MachineInstr &MI) {
637  return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
638  }
639 
640  bool isMAI(uint16_t Opcode) const {
641  return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
642  }
643 
644  static bool isDOT(const MachineInstr &MI) {
645  return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
646  }
647 
648  bool isDOT(uint16_t Opcode) const {
649  return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
650  }
651 
652  static bool isScalarUnit(const MachineInstr &MI) {
653  return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
654  }
655 
656  static bool usesVM_CNT(const MachineInstr &MI) {
657  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
658  }
659 
660  static bool usesLGKM_CNT(const MachineInstr &MI) {
661  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
662  }
663 
664  static bool sopkIsZext(const MachineInstr &MI) {
665  return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
666  }
667 
668  bool sopkIsZext(uint16_t Opcode) const {
669  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
670  }
671 
672  /// \returns true if this is an s_store_dword* instruction. This is more
673  /// specific than than isSMEM && mayStore.
674  static bool isScalarStore(const MachineInstr &MI) {
675  return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
676  }
677 
678  bool isScalarStore(uint16_t Opcode) const {
679  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
680  }
681 
682  static bool isFixedSize(const MachineInstr &MI) {
683  return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
684  }
685 
686  bool isFixedSize(uint16_t Opcode) const {
687  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
688  }
689 
690  static bool hasFPClamp(const MachineInstr &MI) {
691  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
692  }
693 
694  bool hasFPClamp(uint16_t Opcode) const {
695  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
696  }
697 
698  static bool hasIntClamp(const MachineInstr &MI) {
699  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
700  }
701 
702  uint64_t getClampMask(const MachineInstr &MI) const {
703  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
707  return MI.getDesc().TSFlags & ClampFlags;
708  }
709 
710  static bool usesFPDPRounding(const MachineInstr &MI) {
711  return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
712  }
713 
714  bool usesFPDPRounding(uint16_t Opcode) const {
715  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
716  }
717 
718  static bool isFPAtomic(const MachineInstr &MI) {
719  return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
720  }
721 
722  bool isFPAtomic(uint16_t Opcode) const {
723  return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
724  }
725 
726  bool isVGPRCopy(const MachineInstr &MI) const {
727  assert(MI.isCopy());
728  Register Dest = MI.getOperand(0).getReg();
729  const MachineFunction &MF = *MI.getParent()->getParent();
730  const MachineRegisterInfo &MRI = MF.getRegInfo();
731  return !RI.isSGPRReg(MRI, Dest);
732  }
733 
734  bool hasVGPRUses(const MachineInstr &MI) const {
735  const MachineFunction &MF = *MI.getParent()->getParent();
736  const MachineRegisterInfo &MRI = MF.getRegInfo();
737  return llvm::any_of(MI.explicit_uses(),
738  [&MRI, this](const MachineOperand &MO) {
739  return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
740  }
741 
742  /// Return true if the instruction modifies the mode register.q
743  static bool modifiesModeRegister(const MachineInstr &MI);
744 
745  /// Whether we must prevent this instruction from executing with EXEC = 0.
747 
748  /// Returns true if the instruction could potentially depend on the value of
749  /// exec. If false, exec dependencies may safely be ignored.
750  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
751 
752  bool isInlineConstant(const APInt &Imm) const;
753 
754  bool isInlineConstant(const APFloat &Imm) const {
755  return isInlineConstant(Imm.bitcastToAPInt());
756  }
757 
758  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
759 
761  const MCOperandInfo &OpInfo) const {
762  return isInlineConstant(MO, OpInfo.OperandType);
763  }
764 
765  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
766  /// be an inline immediate.
768  const MachineOperand &UseMO,
769  const MachineOperand &DefMO) const {
770  assert(UseMO.getParent() == &MI);
771  int OpIdx = MI.getOperandNo(&UseMO);
772  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
773  return false;
774  }
775 
776  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
777  }
778 
779  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
780  /// immediate.
781  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
782  const MachineOperand &MO = MI.getOperand(OpIdx);
783  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
784  }
785 
786  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
787  const MachineOperand &MO) const {
788  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
789  return false;
790 
791  if (MI.isCopy()) {
792  unsigned Size = getOpSize(MI, OpIdx);
793  assert(Size == 8 || Size == 4);
794 
795  uint8_t OpType = (Size == 8) ?
797  return isInlineConstant(MO, OpType);
798  }
799 
800  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
801  }
802 
803  bool isInlineConstant(const MachineOperand &MO) const {
804  const MachineInstr *Parent = MO.getParent();
805  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
806  }
807 
809  const MCOperandInfo &OpInfo) const {
810  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
811  }
812 
813  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
814  const MachineOperand &MO = MI.getOperand(OpIdx);
815  return MO.isImm() && !isInlineConstant(MI, OpIdx);
816  }
817 
818  // Returns true if this operand could potentially require a 32-bit literal
819  // operand, but not necessarily. A FrameIndex for example could resolve to an
820  // inline immediate value that will not require an additional 4-bytes; this
821  // assumes that it will.
822  bool isLiteralConstantLike(const MachineOperand &MO,
823  const MCOperandInfo &OpInfo) const;
824 
825  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
826  const MachineOperand &MO) const;
827 
828  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
829  /// This function will return false if you pass it a 32-bit instruction.
830  bool hasVALU32BitEncoding(unsigned Opcode) const;
831 
832  /// Returns true if this operand uses the constant bus.
834  const MachineOperand &MO,
835  const MCOperandInfo &OpInfo) const;
836 
837  /// Return true if this instruction has any modifiers.
838  /// e.g. src[012]_mod, omod, clamp.
839  bool hasModifiers(unsigned Opcode) const;
840 
841  bool hasModifiersSet(const MachineInstr &MI,
842  unsigned OpName) const;
843  bool hasAnyModifiersSet(const MachineInstr &MI) const;
844 
845  bool canShrink(const MachineInstr &MI,
846  const MachineRegisterInfo &MRI) const;
847 
849  unsigned NewOpcode) const;
850 
851  bool verifyInstruction(const MachineInstr &MI,
852  StringRef &ErrInfo) const override;
853 
854  unsigned getVALUOp(const MachineInstr &MI) const;
855 
856  /// Return the correct register class for \p OpNo. For target-specific
857  /// instructions, this will return the register class that has been defined
858  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
859  /// the register class of its machine operand.
860  /// to infer the correct register class base on the other operands.
862  unsigned OpNo) const;
863 
864  /// Return the size in bytes of the operand OpNo on the given
865  // instruction opcode.
866  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
867  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
868 
869  if (OpInfo.RegClass == -1) {
870  // If this is an immediate operand, this must be a 32-bit literal.
872  return 4;
873  }
874 
875  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
876  }
877 
878  /// This form should usually be preferred since it handles operands
879  /// with unknown register classes.
880  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
881  const MachineOperand &MO = MI.getOperand(OpNo);
882  if (MO.isReg()) {
883  if (unsigned SubReg = MO.getSubReg()) {
884  return RI.getSubRegIdxSize(SubReg) / 8;
885  }
886  }
887  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
888  }
889 
890  /// Legalize the \p OpIndex operand of this instruction by inserting
891  /// a MOV. For example:
892  /// ADD_I32_e32 VGPR0, 15
893  /// to
894  /// MOV VGPR1, 15
895  /// ADD_I32_e32 VGPR0, VGPR1
896  ///
897  /// If the operand being legalized is a register, then a COPY will be used
898  /// instead of MOV.
899  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
900 
901  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
902  /// for \p MI.
903  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
904  const MachineOperand *MO = nullptr) const;
905 
906  /// Check if \p MO would be a valid operand for the given operand
907  /// definition \p OpInfo. Note this does not attempt to validate constant bus
908  /// restrictions (e.g. literal constant usage).
910  const MCOperandInfo &OpInfo,
911  const MachineOperand &MO) const;
912 
913  /// Check if \p MO (a register operand) is a legal register for the
914  /// given operand description.
916  const MCOperandInfo &OpInfo,
917  const MachineOperand &MO) const;
918 
919  /// Legalize operands in \p MI by either commuting it or inserting a
920  /// copy of src1.
922 
923  /// Fix operands in \p MI to satisfy constant bus requirements.
925 
926  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
927  /// be used when it is know that the value in SrcReg is same across all
928  /// threads in the wave.
929  /// \returns The SGPR register that \p SrcReg was copied to.
931  MachineRegisterInfo &MRI) const;
932 
935 
938  const TargetRegisterClass *DstRC,
940  const DebugLoc &DL) const;
941 
942  /// Legalize all operands in this instruction. This function may create new
943  /// instructions and control-flow around \p MI. If present, \p MDT is
944  /// updated.
945  /// \returns A new basic block that contains \p MI if new blocks were created.
947  legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
948 
949  /// Replace this instruction's opcode with the equivalent VALU
950  /// opcode. This function will also move the users of \p MI to the
951  /// VALU if necessary. If present, \p MDT is updated.
953  MachineDominatorTree *MDT = nullptr) const;
954 
956  MachineBasicBlock::iterator MI) const override;
957 
959  unsigned Quantity) const override;
960 
961  void insertReturn(MachineBasicBlock &MBB) const;
962  /// Return the number of wait states that result from executing this
963  /// instruction.
964  static unsigned getNumWaitStates(const MachineInstr &MI);
965 
966  /// Returns the operand named \p Op. If \p MI does not have an
967  /// operand named \c Op, this function returns nullptr.
969  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
970 
973  unsigned OpName) const {
974  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
975  }
976 
977  /// Get required immediate operand
978  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
979  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
980  return MI.getOperand(Idx).getImm();
981  }
982 
983  uint64_t getDefaultRsrcDataFormat() const;
984  uint64_t getScratchRsrcWords23() const;
985 
986  bool isLowLatencyInstruction(const MachineInstr &MI) const;
987  bool isHighLatencyDef(int Opc) const override;
988 
989  /// Return the descriptor of the target-specific machine instruction
990  /// that corresponds to the specified pseudo or native opcode.
991  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
992  return get(pseudoToMCOpcode(Opcode));
993  }
994 
995  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
996  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
997 
998  unsigned isLoadFromStackSlot(const MachineInstr &MI,
999  int &FrameIndex) const override;
1000  unsigned isStoreToStackSlot(const MachineInstr &MI,
1001  int &FrameIndex) const override;
1002 
1003  unsigned getInstBundleSize(const MachineInstr &MI) const;
1004  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1005 
1006  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1007 
1008  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1009 
1011  MachineBasicBlock *IfEnd) const;
1012 
1014  MachineBasicBlock *LoopEnd) const;
1015 
1016  std::pair<unsigned, unsigned>
1017  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1018 
1020  getSerializableTargetIndices() const override;
1021 
1024 
1027  const ScheduleDAG *DAG) const override;
1028 
1030  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1031 
1032  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1033 
1036  const DebugLoc &DL, Register Src,
1037  Register Dst) const override;
1038 
1041  const DebugLoc &DL, Register Src,
1042  unsigned SrcSubReg,
1043  Register Dst) const override;
1044 
1045  bool isWave32() const;
1046 
1047  /// Return a partially built integer add instruction without carry.
1048  /// Caller must add source operands.
1049  /// For pre-GFX9 it will generate unused carry destination operand.
1050  /// TODO: After GFX9 it should return a no-carry operation.
1053  const DebugLoc &DL,
1054  Register DestReg) const;
1055 
1058  const DebugLoc &DL,
1059  Register DestReg,
1060  RegScavenger &RS) const;
1061 
1062  static bool isKillTerminator(unsigned Opcode);
1063  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1064 
1065  static bool isLegalMUBUFImmOffset(unsigned Imm) {
1066  return isUInt<12>(Imm);
1067  }
1068 
1069  /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1070  /// encoded instruction. If \p Signed, this is for an instruction that
1071  /// interprets the offset as signed.
1072  bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1073  uint64_t FlatVariant) const;
1074 
1075  /// Split \p COffsetVal into {immediate offset field, remainder offset}
1076  /// values.
1077  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1078  unsigned AddrSpace,
1079  uint64_t FlatVariant) const;
1080 
1081  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1082  /// Return -1 if the target-specific opcode for the pseudo instruction does
1083  /// not exist. If Opcode is not a pseudo instruction, this is identity.
1084  int pseudoToMCOpcode(int Opcode) const;
1085 
1086  /// \brief Check if this instruction should only be used by assembler.
1087  /// Return true if this opcode should not be used by codegen.
1088  bool isAsmOnlyOpcode(int MCOp) const;
1089 
1090  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1091  const TargetRegisterInfo *TRI,
1092  const MachineFunction &MF)
1093  const override;
1094 
1095  void fixImplicitOperands(MachineInstr &MI) const;
1096 
1098  ArrayRef<unsigned> Ops,
1099  MachineBasicBlock::iterator InsertPt,
1100  int FrameIndex,
1101  LiveIntervals *LIS = nullptr,
1102  VirtRegMap *VRM = nullptr) const override;
1103 
1104  unsigned getInstrLatency(const InstrItineraryData *ItinData,
1105  const MachineInstr &MI,
1106  unsigned *PredCost = nullptr) const override;
1107 
1108  const MIRFormatter *getMIRFormatter() const override {
1109  if (!Formatter.get())
1110  Formatter = std::make_unique<AMDGPUMIRFormatter>();
1111  return Formatter.get();
1112  }
1113 
1114  static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1115 };
1116 
1117 /// \brief Returns true if a reg:subreg pair P has a TRC class
1119  const TargetRegisterClass &TRC,
1121  auto *RC = MRI.getRegClass(P.Reg);
1122  if (!P.SubReg)
1123  return RC == &TRC;
1124  auto *TRI = MRI.getTargetRegisterInfo();
1125  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1126 }
1127 
1128 /// \brief Create RegSubRegPair from a register MachineOperand
1129 inline
1131  assert(O.isReg());
1132  return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1133 }
1134 
1135 /// \brief Return the SubReg component from REG_SEQUENCE
1137  unsigned SubReg);
1138 
1139 /// \brief Return the defining instruction for a given reg:subreg pair
1140 /// skipping copy like instructions and subreg-manipulation pseudos.
1141 /// Following another subreg of a reg:subreg isn't supported.
1143  MachineRegisterInfo &MRI);
1144 
1145 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1146 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1147 /// attempt to track between blocks.
1148 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1149  Register VReg,
1150  const MachineInstr &DefMI,
1151  const MachineInstr &UseMI);
1152 
1153 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1154 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1155 /// track between blocks.
1156 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1157  Register VReg,
1158  const MachineInstr &DefMI);
1159 
1160 namespace AMDGPU {
1161 
1163  int getVOPe64(uint16_t Opcode);
1164 
1166  int getVOPe32(uint16_t Opcode);
1167 
1169  int getSDWAOp(uint16_t Opcode);
1170 
1172  int getDPPOp32(uint16_t Opcode);
1173 
1175  int getBasicFromSDWAOp(uint16_t Opcode);
1176 
1178  int getCommuteRev(uint16_t Opcode);
1179 
1181  int getCommuteOrig(uint16_t Opcode);
1182 
1184  int getAddr64Inst(uint16_t Opcode);
1185 
1186  /// Check if \p Opcode is an Addr64 opcode.
1187  ///
1188  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1190  int getIfAddr64Inst(uint16_t Opcode);
1191 
1193  int getMUBUFNoLdsInst(uint16_t Opcode);
1194 
1196  int getAtomicNoRetOp(uint16_t Opcode);
1197 
1199  int getSOPKOp(uint16_t Opcode);
1200 
1202  int getGlobalSaddrOp(uint16_t Opcode);
1203 
1205  int getVCMPXNoSDstOp(uint16_t Opcode);
1206 
1209 
1212 
1213  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1214  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1215  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1216  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1217 
1218 } // end namespace AMDGPU
1219 
1220 namespace SI {
1221 namespace KernelInputOffsets {
1222 
1223 /// Offsets in bytes from the start of the input buffer
1224 enum Offsets {
1234 };
1235 
1236 } // end namespace KernelInputOffsets
1237 } // end namespace SI
1238 
1239 } // end namespace llvm
1240 
1241 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:65
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::AMDGPU::getVCMPXNoSDstOp
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:49
llvm::SIInstrInfo::isMIMG
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:489
llvm::SIInstrInfo::isMTBUF
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:461
llvm::SIInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SIInstrInfo.cpp:2365
llvm::SIInstrInfo::isAtomicRet
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:554
llvm::SIInstrInfo::insertNoops
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
Definition: SIInstrInfo.cpp:1610
llvm::SIInstrInfo::isFLAT
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:534
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:50
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:59
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
llvm::SIInstrInfo::isDPP
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:608
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:672
llvm::SIInstrInfo::isFLATGlobal
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:521
llvm
Definition: AllocatorList.h:23
llvm::SIInstrInfo::insertNE
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1200
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SIInstrInfo::isDisableWQM
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:584
llvm::SIInstrInfo::swapSourceModifiers
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
Definition: SIInstrInfo.cpp:2036
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::SIInstrInfo::hasFPClamp
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:690
llvm::SIInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:3196
llvm::SIInstrInfo::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
Definition: SIInstrInfo.cpp:2682
llvm::SIInstrInfo::isSGPRSpill
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:596
llvm::SIInstrInfo::isSOP2
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:373
llvm::SIInstrInfo::isFixedSize
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:682
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2375
llvm::SIInstrInfo::isMAI
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:640
llvm::SIInstrInfo::getClampMask
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:702
llvm::getRegSubRegPair
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1130
llvm::SIInstrInfo::MO_LONG_BRANCH_FORWARD
@ MO_LONG_BRANCH_FORWARD
Definition: SIInstrInfo.h:162
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::AMDGPU::getAtomicNoRetOp
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
llvm::SIInstrInfo::usesLGKM_CNT
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:660
llvm::SIInstrInfo::usesVM_CNT
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:656
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SIInstrInfo::isVOP3
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:425
llvm::SIInstrInfo::hasVGPRUses
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:734
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y
@ GLOBAL_SIZE_Y
Definition: SIInstrInfo.h:1229
llvm::SIInstrInfo::getMovOpcode
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
Definition: SIInstrInfo.cpp:1213
llvm::SIInstrInfo::isSOPP
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:397
llvm::SIInstrInfo::isBufferSMRD
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7289
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:100
llvm::SIInstrInfo::getNumWaitStates
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
Definition: SIInstrInfo.cpp:1639
llvm::SIInstrInfo::MO_GOTPCREL32
@ MO_GOTPCREL32
Definition: SIInstrInfo.h:152
llvm::SIInstrInfo::isImmOperandLegal
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
Definition: SIInstrInfo.cpp:3445
llvm::SIInstrInfo::convertNonUniformLoopRegion
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
Definition: SIInstrInfo.cpp:7123
llvm::SIInstrInfo::isHighLatencyDef
bool isHighLatencyDef(int Opc) const override
Definition: SIInstrInfo.cpp:6940
llvm::SIInstrInfo::isDisableWQM
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:580
llvm::SIInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SIInstrInfo.cpp:2495
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:97
llvm::SIInstrInfo::analyzeBranchImpl
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: SIInstrInfo.cpp:2322
llvm::SIInstrInfo::isScalarStore
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:674
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::SIInstrInfo::createPHIDestinationCopy
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
Definition: SIInstrInfo.cpp:7611
llvm::SIInstrInfo::isEXP
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:538
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:81
llvm::SIInstrInfo::moveToVALU
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
Definition: SIInstrInfo.cpp:5635
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SIInstrInfo::modifiesModeRegister
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Definition: SIInstrInfo.cpp:3233
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:109
llvm::AMDGPU::getSOPKOp
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
llvm::SIInstrInfo::isSDWA
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:437
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SIInstrInfo::isMUBUF
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:453
llvm::AMDGPU::getGlobalSaddrOp
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
llvm::SIInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:6980
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:61
TargetInstrInfo.h
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:64
llvm::SIInstrInfo::isVOP3P
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:620
llvm::SIInstrInfo::isFoldableCopy
bool isFoldableCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:2658
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:46
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SIInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
Definition: SIInstrInfo.cpp:3060
llvm::SIInstrInfo::isAsmOnlyOpcode
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
Definition: SIInstrInfo.cpp:7369
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::SIInstrInfo::isVGPRSpill
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:588
llvm::SIInstrInfo::MO_MASK
@ MO_MASK
Definition: SIInstrInfo.h:146
llvm::SIInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
Definition: SIInstrInfo.cpp:7184
llvm::SIInstrInfo::getScratchRsrcWords23
uint64_t getScratchRsrcWords23() const
Definition: SIInstrInfo.cpp:6910
llvm::SIInstrInfo::MO_GOTPCREL
@ MO_GOTPCREL
Definition: SIInstrInfo.h:150
llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
Definition: SIInstrInfo.cpp:1329
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:29
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:41
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SIInstrInfo::hasAnyModifiersSet
bool hasAnyModifiersSet(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:3501
llvm::SIInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: SIInstrInfo.cpp:2161
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SIInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: SIInstrInfo.cpp:1605
llvm::SIInstrInfo::isBasicBlockPrologue
bool isBasicBlockPrologue(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7216
llvm::SIInstrInfo::insertVectorSelect
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Definition: SIInstrInfo.cpp:1061
llvm::SIInstrInfo::isVOP1
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:413
llvm::SIInstrInfo::fixImplicitOperands
void fixImplicitOperands(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7279
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:464
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:33
llvm::SIInstrInfo::isVOPC
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:445
llvm::AMDGPU::getVOPe64
LLVM_READONLY int getVOPe64(uint16_t Opcode)
llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
Definition: SIInstrInfo.cpp:3247
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:866
llvm::SIInstrInfo::isWave32
bool isWave32() const
Definition: SIInstrInfo.cpp:7646
llvm::SIInstrInfo::isVOPC
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:441
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::SIInstrInfo::canShrink
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: SIInstrInfo.cpp:3509
llvm::AMDGPU::getCommuteOrig
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
llvm::SIInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SIInstrInfo.cpp:667
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:148
llvm::SIInstrInfo::MO_GOTPCREL32_LO
@ MO_GOTPCREL32_LO
Definition: SIInstrInfo.h:153
llvm::SIInstrInfo::isMIMG
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:485
llvm::SIInstrInfo::isSOPK
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:389
llvm::SIInstrInfo::isAtomicNoRet
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:550
llvm::SIInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7006
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APInt &Imm) const
Definition: SIInstrInfo.cpp:3313
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::SIInstrInfo::isSOPC
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:377
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:37
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:34
llvm::SIInstrInfo::createPHISourceCopy
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Definition: SIInstrInfo.cpp:7626
llvm::SIInstrInfo::isNonUniformBranchInstr
bool isNonUniformBranchInstr(MachineInstr &Instr) const
Definition: SIInstrInfo.cpp:7094
llvm::SIInstrInfo::isMAI
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:636
llvm::SIInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Definition: SIInstrInfo.cpp:129
llvm::SIInstrInfo::isSOPK
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:385
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::AMDGPU::getFlatScratchInstSSfromSV
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIInstrInfo::isOperandLegal
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition: SIInstrInfo.cpp:4658
llvm::SIInstrInfo::hasIntClamp
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:698
llvm::AMDGPU::getDPPOp32
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
llvm::AMDGPU::getMUBUFNoLdsInst
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
llvm::AMDGPU::getVOPe32
LLVM_READONLY int getVOPe32(uint16_t Opcode)
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:26
AMDGPUMIRFormatter.h
llvm::SIInstrInfo::isVOP3
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:429
llvm::SIInstrInfo::isSegmentSpecificFLAT
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:512
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: SIInstrInfo.cpp:7171
OpName
Definition: R600Defines.h:62
llvm::SIInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: SIInstrInfo.cpp:7197
llvm::SIInstrInfo::isGather4
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:497
llvm::SIInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: SIInstrInfo.cpp:7685
llvm::SIInstrInfo::legalizeOperands
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
Definition: SIInstrInfo.cpp:5309
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:47
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:66
llvm::getVRegSubRegDef
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
Definition: SIInstrInfo.cpp:7487
llvm::SIInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: SIInstrInfo.cpp:2138
llvm::SIInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
Definition: SIInstrInfo.cpp:2713
llvm::SIInstrInfo::sopkIsZext
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:664
llvm::SIInstrInfo::isVOP2
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:421
llvm::SIInstrInfo::getNamedOperand
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
Definition: SIInstrInfo.cpp:6879
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:52
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:115
llvm::SIInstrInfo::hasModifiers
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
Definition: SIInstrInfo.cpp:3487
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:284
llvm::SIInstrInfo::isVOP3P
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:624
llvm::SIInstrInfo::isGather4
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:493
llvm::SIInstrInfo::MO_REL32
@ MO_REL32
Definition: SIInstrInfo.h:157
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::SIInstrInfo::legalizeGenericOperand
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
Definition: SIInstrInfo.cpp:5029
llvm::AMDGPU::getSDWAOp
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:75
llvm::SIInstrInfo::isScalarUnit
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:652
llvm::SI::KernelInputOffsets::NGROUPS_Z
@ NGROUPS_Z
Definition: SIInstrInfo.h:1227
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIInstrInfo::isVALU
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:349
llvm::SIInstrInfo::MO_ABS32_LO
@ MO_ABS32_LO
Definition: SIInstrInfo.h:165
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::SIInstrInfo::TargetOperandFlags
TargetOperandFlags
Definition: SIInstrInfo.h:145
llvm::SIInstrInfo::getAddNoCarry
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
Definition: SIInstrInfo.cpp:7222
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:55
llvm::SIInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SIInstrInfo.cpp:6966
llvm::SIInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: SIInstrInfo.cpp:108
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:754
llvm::SIInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: SIInstrInfo.cpp:7202
llvm::APFloat
Definition: APFloat.h:701
llvm::SIInstrInfo::getOpSize
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:880
llvm::SIInstrInfo::MO_ABS32_HI
@ MO_ABS32_HI
Definition: SIInstrInfo.h:166
llvm::SIInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SIInstrInfo.cpp:2551
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:128
llvm::SIInstrInfo::isDPP
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:604
llvm::SIInstrInfo::isWQM
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:576
llvm::SIInstrInfo::isLowLatencyInstruction
bool isLowLatencyInstruction(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:6934
TargetSchedule.h
llvm::SIInstrInfo::hasVALU32BitEncoding
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
Definition: SIInstrInfo.cpp:3475
llvm::SIInstrInfo::getNamedImmOperand
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:978
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::execMayBeModifiedBeforeAnyUse
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
Definition: SIInstrInfo.cpp:7555
llvm::SIInstrInfo::insertIndirectBranch
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
Definition: SIInstrInfo.cpp:2188
llvm::SIInstrInfo::hasFPClamp
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:694
llvm::SI::KernelInputOffsets::LOCAL_SIZE_X
@ LOCAL_SIZE_X
Definition: SIInstrInfo.h:1231
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:27
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:42
llvm::SIInstrInfo::getMIRFormatter
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1108
llvm::SIInstrInfo::buildExtractSubReg
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4559
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:106
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:67
llvm::SIInstrInfo::sopkIsZext
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:668
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:68
llvm::SIInstrInfo::isFLATScratch
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:525
llvm::SIInstrInfo::isDS
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:475
llvm::SIInstrInfo::isDS
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:479
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2075
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:465
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::execMayBeModifiedBeforeUse
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
Definition: SIInstrInfo.cpp:7522
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIInstrInfo::isLegalFLATOffset
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
Definition: SIInstrInfo.cpp:7302
llvm::SIInstrInfo::legalizeOperandsFLAT
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:5014
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:57
llvm::SIInstrInfo::isSOP2
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:369
llvm::SIInstrInfo::isScalarStore
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:678
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:25
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:101
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInstrInfo::MO_REL32_LO
@ MO_REL32_LO
Definition: SIInstrInfo.h:158
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:38
llvm::SIInstrInfo::isAlwaysGDS
bool isAlwaysGDS(uint16_t Opcode) const
Definition: SIInstrInfo.cpp:3223
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:22
llvm::SIInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:2177
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:781
llvm::SIInstrInfo::isVMEM
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:357
llvm::SIInstrInfo::isFPAtomic
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:718
llvm::SIInstrInfo::isSGPRSpill
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:600
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:28
llvm::SIInstrInfo::MO_LONG_BRANCH_BACKWARD
@ MO_LONG_BRANCH_BACKWARD
Definition: SIInstrInfo.h:163
llvm::SIInstrInfo::isPacked
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:401
llvm::SIInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1554
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:562
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:40
llvm::SIInstrInfo::isSOP1
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:361
llvm::SIInstrInfo::isSALU
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:337
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:88
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::SIInstrInfo::insertReturn
void insertReturn(MachineBasicBlock &MBB) const
Definition: SIInstrInfo.cpp:1621
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::AMDGPU::getFlatScratchInstSTfromSS
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::SIInstrInfo::mayAccessFlatAddressSpace
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:7080
llvm::SIInstrInfo::isVOP1
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:409
llvm::SI::KernelInputOffsets::NGROUPS_Y
@ NGROUPS_Y
Definition: SIInstrInfo.h:1226
llvm::AMDGPU::RSRC_DATA_FORMAT
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1213
llvm::SIInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Definition: SIInstrInfo.cpp:444
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::SIInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SIInstrInfo.cpp:2435
llvm::SIInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
Definition: SIInstrInfo.cpp:2509
llvm::SIInstrInfo::MO_REL32_HI
@ MO_REL32_HI
Definition: SIInstrInfo.h:160
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::SIInstrInfo::usesConstantBus
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
Definition: SIInstrInfo.cpp:3627
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::SIInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3712
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:760
llvm::SIInstrInfo::isFixedSize
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:686
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:43
llvm::SIInstrInfo::isSDWA
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:433
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SIInstrInfo::isSALU
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:341
llvm::SIInstrInfo::isVOP2
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:417
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:256
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:808
AMDGPUGenInstrInfo
llvm::SIInstrInfo::isMUBUF
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:449
llvm::SIInstrInfo::isAtomic
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:567
llvm::SIInstrInfo::isDOT
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:644
llvm::SIInstrInfo::isVINTRP
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:632
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:362
llvm::SIInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
Definition: SIInstrInfo.cpp:2086
llvm::SIInstrInfo::isKillTerminator
static bool isKillTerminator(unsigned Opcode)
Definition: SIInstrInfo.cpp:7258
llvm::AMDGPU::getCommuteRev
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
llvm::SIInstrInfo::isLegalMUBUFImmOffset
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1065
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:112
llvm::SIInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:1648
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SIInstrInfo::legalizeOpWithMove
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
Definition: SIInstrInfo.cpp:4532
llvm::SIInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
Definition: SIInstrInfo.cpp:244
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:32
llvm::SIInstrInfo::isTRANS
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:616
llvm::SIInstrInfo::splitFlatOffset
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition: SIInstrInfo.cpp:7319
llvm::SIInstrInfo::convertNonUniformIfRegion
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
Definition: SIInstrInfo.cpp:7098
llvm::SIInstrInfo::isVGPRSpill
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:592
llvm::SIInstrInfo::getMCOpcodeFromPseudo
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:991
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SIInstrInfo::isAtomicNoRet
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:546
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SIInstrInfo::legalizeOperandsVOP2
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition: SIInstrInfo.cpp:4753
llvm::SIInstrInfo::getMachineCSELookAheadLimit
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:327
llvm::SIInstrInfo::isSegmentSpecificFLAT
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:507
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::AMDGPU::getAddr64Inst
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:48
llvm::SIInstrInfo::getVALUOp
unsigned getVALUOp(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4380
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:353
llvm::getRegSequenceSubReg
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
Definition: SIInstrInfo.cpp:7450
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:78
llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SIInstrInfo.cpp:2986
llvm::SIInstrInfo::expandMovDPP64
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Definition: SIInstrInfo.cpp:1980
llvm::SIInstrInfo::buildExtractSubRegOrImm
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Definition: SIInstrInfo.cpp:4591
llvm::AMDGPU::getIfAddr64Inst
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
llvm::SIInstrInfo::isStackAccess
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:6945
llvm::SIInstrInfo::getRegisterInfo
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:171
llvm::SIInstrInfo::getPreferredSelectRegClass
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
Definition: SIInstrInfo.cpp:1057
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:103
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:56
llvm::SIInstrInfo::isMTBUF
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:457
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIInstrInfo::isSMRD
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:469
llvm::SIInstrInfo::buildShrunkInst
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
Definition: SIInstrInfo.cpp:3582
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:94
llvm::SIInstrInfo::isFLATScratch
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:529
llvm::SIInstrInfo::getDSShaderTypeValue
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
Definition: SIInstrInfo.cpp:7702
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y
@ LOCAL_SIZE_Y
Definition: SIInstrInfo.h:1232
llvm::SIInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SIInstrInfo.cpp:7648
llvm::SIInstrInfo::SIInstrInfo
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:64
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::SIInstrInfo::isDOT
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:648
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::AMDGPU::RSRC_TID_ENABLE
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1216
llvm::SIInstrInfo::usesFPDPRounding
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:714
llvm::SIInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SIInstrInfo.cpp:2408
llvm::SIInstrInfo::legalizeOperandsSMRD
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
Definition: SIInstrInfo.cpp:4994
llvm::SI::KernelInputOffsets::NGROUPS_X
@ NGROUPS_X
Definition: SIInstrInfo.h:1225
llvm::SIInstrInfo::getDefaultRsrcDataFormat
uint64_t getDefaultRsrcDataFormat() const
Definition: SIInstrInfo.cpp:6888
llvm::SIInstrInfo::commuteOpcode
LLVM_READONLY int commuteOpcode(unsigned Opc) const
Definition: SIInstrInfo.cpp:982
llvm::AMDGPU::getBasicFromSDWAOp
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:803
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:30
llvm::SIInstrInfo::isSOPP
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:393
llvm::SIInstrInfo::isLegalRegOperand
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
Definition: SIInstrInfo.cpp:4620
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z
@ GLOBAL_SIZE_Z
Definition: SIInstrInfo.h:1230
llvm::SIInstrInfo::usesFPDPRounding
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:710
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:21
llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1215
llvm::SIInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
Definition: SIInstrInfo.cpp:487
llvm::SIInstrInfo::isFLATGlobal
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:517
llvm::SIInstrInfo::MO_GOTPCREL32_HI
@ MO_GOTPCREL32_HI
Definition: SIInstrInfo.h:155
llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z
@ LOCAL_SIZE_Z
Definition: SIInstrInfo.h:1233
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:345
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::SIInstrInfo::isLiteralConstantLike
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.cpp:3412
llvm::SIInstrInfo::isFPAtomic
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:722
llvm::SIInstrInfo::isWQM
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:572
llvm::SIInstrInfo::isLiteralConstant
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:813
llvm::SIInstrInfo::getNamedOperand
const LLVM_READONLY MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:972
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X
@ GLOBAL_SIZE_X
Definition: SIInstrInfo.h:1228
llvm::SIInstrInfo::isLegalVSrcOperand
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
Definition: SIInstrInfo.cpp:4647
llvm::SIInstrInfo::getOpRegClass
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Definition: SIInstrInfo.cpp:4514
llvm::SIInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SIInstrInfo.cpp:1421
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SIInstrInfo::materializeImmediate
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
Definition: SIInstrInfo.cpp:1000
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::SIInstrInfo::readlaneVGPRToSGPR
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
Definition: SIInstrInfo.cpp:4952
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::SIInstrInfo::isVGPRCopy
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:726
llvm::SIInstrInfo::isSGPRStackAccess
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Definition: SIInstrInfo.cpp:6958
llvm::SIInstrInfo::isEXP
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:542
llvm::SIInstrInfo::isTRANS
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:612
llvm::SIInstrInfo::isAtomicRet
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:558
llvm::SIInstrInfo::getSubtarget
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:175
llvm::SIInstrInfo::isPacked
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:405
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:501
llvm::SIInstrInfo::insertEQ
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
Definition: SIInstrInfo.cpp:1187
llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1214
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1224
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:786
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::isOfRegClass
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1118
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIInstrInfo::getRegClass
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Definition: SIInstrInfo.cpp:4482
llvm::SIInstrInfo::hasModifiersSet
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.cpp:3495
llvm::SIInstrInfo::mayReadEXEC
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
Definition: SIInstrInfo.cpp:3288
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:63
llvm::SIInstrInfo::getKillTerminatorFromPseudo
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
Definition: SIInstrInfo.cpp:7268
SIRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SIInstrInfo::isSOPC
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:381
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:51
llvm::SIInstrInfo::getIndirectGPRIDXPseudo
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
Definition: SIInstrInfo.cpp:1228
llvm::SIInstrInfo::pseudoToMCOpcode
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Definition: SIInstrInfo.cpp:7389
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:85
llvm::SIInstrInfo::isVINTRP
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:628
llvm::SIInstrInfo::isSOP1
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:365
llvm::SIInstrInfo::legalizeOperandsVOP3
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Definition: SIInstrInfo.cpp:4865
SetVector.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
AMDGPUBaseInfo.h
llvm::SIInstrInfo::isInlineConstant
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:767
llvm::SIInstrInfo::getInstBundleSize
unsigned getInstBundleSize(const MachineInstr &MI) const
Definition: SIInstrInfo.cpp:6994