|
LLVM 22.0.0git
|
This file defines a class for holding ownership of various simulated hardware units. More...
#include "llvm/MCA/Context.h"#include "llvm/MCA/HardwareUnits/RegisterFile.h"#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"#include "llvm/MCA/HardwareUnits/Scheduler.h"#include "llvm/MCA/Stages/DispatchStage.h"#include "llvm/MCA/Stages/EntryStage.h"#include "llvm/MCA/Stages/ExecuteStage.h"#include "llvm/MCA/Stages/InOrderIssueStage.h"#include "llvm/MCA/Stages/MicroOpQueueStage.h"#include "llvm/MCA/Stages/RetireStage.h"Go to the source code of this file.
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::mca |
This file defines a class for holding ownership of various simulated hardware units.
A Context also provides a utility routine for constructing a default out-of-order pipeline with fetch, dispatch, execute, and retire stages.
Definition in file Context.cpp.