LLVM 19.0.0git
RetireStage.h
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1//===---------------------- RetireStage.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines the retire stage of a default instruction pipeline.
11/// The RetireStage represents the process logic that interacts with the
12/// simulated RetireControlUnit hardware.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
17#define LLVM_MCA_STAGES_RETIRESTAGE_H
18
24
25namespace llvm {
26namespace mca {
27
28class RetireStage final : public Stage {
29 // Owner will go away when we move listeners/eventing to the stages.
31 RegisterFile &PRF;
32 LSUnitBase &LSU;
33
34 RetireStage(const RetireStage &Other) = delete;
35 RetireStage &operator=(const RetireStage &Other) = delete;
36
37public:
39 : RCU(R), PRF(F), LSU(LS) {}
40
41 bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
42 Error cycleStart() override;
43 Error cycleEnd() override;
44 Error execute(InstRef &IR) override;
45 void notifyInstructionRetired(const InstRef &IR) const;
46};
47
48} // namespace mca
49} // namespace llvm
50
51#endif // LLVM_MCA_STAGES_RETIRESTAGE_H
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
Legalize the Machine IR a function s Machine IR
Definition: Legalizer.cpp:81
#define F(x, y, z)
Definition: MD5.cpp:55
This file defines a register mapping file class.
This file simulates the hardware responsible for retiring instructions.
This file defines the SmallVector class.
This file defines a stage.
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:720
Abstract base interface for LS (load/store) units in llvm-mca.
Definition: LSUnit.h:190
Manages hardware register files, and tracks register definitions for register renaming purposes.
Definition: RegisterFile.h:83
Error cycleEnd() override
Called once at the end of each cycle.
Definition: RetireStage.cpp:44
void notifyInstructionRetired(const InstRef &IR) const
Definition: RetireStage.cpp:60
Error cycleStart() override
Called once at the start of each cycle.
Definition: RetireStage.cpp:25
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: RetireStage.cpp:49
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Definition: RetireStage.h:41
RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
Definition: RetireStage.h:38
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...