LLVM  15.0.0git
RetireStage.h
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1 //===---------------------- RetireStage.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines the retire stage of a default instruction pipeline.
11 /// The RetireStage represents the process logic that interacts with the
12 /// simulated RetireControlUnit hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
17 #define LLVM_MCA_STAGES_RETIRESTAGE_H
18 
19 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MCA/Stages/Stage.h"
24 
25 namespace llvm {
26 namespace mca {
27 
28 class RetireStage final : public Stage {
29  // Owner will go away when we move listeners/eventing to the stages.
30  RetireControlUnit &RCU;
31  RegisterFile &PRF;
32  LSUnitBase &LSU;
33 
34  RetireStage(const RetireStage &Other) = delete;
35  RetireStage &operator=(const RetireStage &Other) = delete;
36 
37 public:
39  : RCU(R), PRF(F), LSU(LS) {}
40 
41  bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
42  Error cycleStart() override;
43  Error cycleEnd() override;
44  Error execute(InstRef &IR) override;
45  void notifyInstructionRetired(const InstRef &IR) const;
46 };
47 
48 } // namespace mca
49 } // namespace llvm
50 
51 #endif // LLVM_MCA_STAGES_RETIRESTAGE_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::mca::RetireStage
Definition: RetireStage.h:28
llvm::mca::RetireControlUnit
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
Definition: RetireControlUnit.h:36
RetireControlUnit.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::mca::RetireStage::RetireStage
RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
Definition: RetireStage.h:38
llvm::mca::LSUnitBase
Abstract base interface for LS (load/store) units in llvm-mca.
Definition: LSUnit.h:193
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:751
LSUnit.h
llvm::mca::RetireStage::notifyInstructionRetired
void notifyInstructionRetired(const InstRef &IR) const
Definition: RetireStage.cpp:60
llvm::mca::RetireStage::execute
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: RetireStage.cpp:49
llvm::mca::RetireStage::cycleEnd
Error cycleEnd() override
Called once at the end of each cycle.
Definition: RetireStage.cpp:44
llvm::mca::RetireStage::cycleStart
Error cycleStart() override
Called once at the start of each cycle.
Definition: RetireStage.cpp:25
Stage.h
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:720
llvm::mca::Stage
Definition: Stage.h:27
llvm::mca::RegisterFile
Manages hardware register files, and tracks register definitions for register renaming purposes.
Definition: RegisterFile.h:83
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
llvm::mca::RetireStage::hasWorkToComplete
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Definition: RetireStage.h:41
SmallVector.h
RegisterFile.h
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236