LLVM  14.0.0git
InOrderIssueStage.h
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1 //===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// InOrderIssueStage implements an in-order execution pipeline.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H
15 #define LLVM_MCA_STAGES_INORDERISSUESTAGE_H
16 
19 #include "llvm/MCA/SourceMgr.h"
20 #include "llvm/MCA/Stages/Stage.h"
21 
22 namespace llvm {
23 namespace mca {
24 class LSUnit;
25 class RegisterFile;
26 
27 struct StallInfo {
28  enum class StallKind {
29  DEFAULT,
31  DISPATCH,
32  DELAY,
33  LOAD_STORE,
35  };
36 
38  unsigned CyclesLeft;
40 
41  StallInfo() : IR(), CyclesLeft(), Kind(StallKind::DEFAULT) {}
42 
43  StallKind getStallKind() const { return Kind; }
44  unsigned getCyclesLeft() const { return CyclesLeft; }
45  const InstRef &getInstruction() const { return IR; }
46  InstRef &getInstruction() { return IR; }
47 
48  bool isValid() const { return (bool)IR; }
49  void clear();
50  void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
51  void cycleEnd();
52 };
53 
54 class InOrderIssueStage final : public Stage {
55  const MCSubtargetInfo &STI;
56  RegisterFile &PRF;
57  ResourceManager RM;
58  CustomBehaviour &CB;
59  LSUnit &LSU;
60 
61  /// Instructions that were issued, but not executed yet.
62  SmallVector<InstRef, 4> IssuedInst;
63 
64  /// Number of instructions issued in the current cycle.
65  unsigned NumIssued;
66 
67  StallInfo SI;
68 
69  /// Instruction that is issued in more than 1 cycle.
70  InstRef CarriedOver;
71  /// Number of CarriedOver uops left to issue.
72  unsigned CarryOver;
73 
74  /// Number of instructions that can be issued in the current cycle.
75  unsigned Bandwidth;
76 
77  /// Number of cycles (counted from the current cycle) until the last write is
78  /// committed. This is taken into account to ensure that writes commit in the
79  /// program order.
80  unsigned LastWriteBackCycle;
81 
82  InOrderIssueStage(const InOrderIssueStage &Other) = delete;
83  InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
84 
85  /// Returns true if IR can execute during this cycle.
86  /// In case of stall, it updates SI with information about the stalled
87  /// instruction and the stall reason.
88  bool canExecute(const InstRef &IR);
89 
90  /// Issue the instruction, or update the StallInfo.
91  Error tryIssue(InstRef &IR);
92 
93  /// Update status of instructions from IssuedInst.
94  void updateIssuedInst();
95 
96  /// Continue to issue the CarriedOver instruction.
97  void updateCarriedOver();
98 
99  /// Notifies a stall event to the Stage listener. Stall information is
100  /// obtained from the internal StallInfo field.
101  void notifyStallEvent();
102 
103  void notifyInstructionIssued(const InstRef &IR,
104  ArrayRef<ResourceUse> UsedRes);
105  void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
106  ArrayRef<unsigned> UsedRegs);
107  void notifyInstructionExecuted(const InstRef &IR);
108  void notifyInstructionRetired(const InstRef &IR,
109  ArrayRef<unsigned> FreedRegs);
110 
111  /// Retire instruction once it is executed.
112  void retireInstruction(InstRef &IR);
113 
114 public:
116  CustomBehaviour &CB, LSUnit &LSU);
117 
118  unsigned getIssueWidth() const;
119  bool isAvailable(const InstRef &) const override;
120  bool hasWorkToComplete() const override;
121  Error execute(InstRef &IR) override;
122  Error cycleStart() override;
123  Error cycleEnd() override;
124 };
125 
126 } // namespace mca
127 } // namespace llvm
128 
129 #endif // LLVM_MCA_STAGES_INORDERISSUESTAGE_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
ResourceManager.h
llvm::mca::StallInfo::getStallKind
StallKind getStallKind() const
Definition: InOrderIssueStage.h:43
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::mca::StallInfo::getInstruction
const InstRef & getInstruction() const
Definition: InOrderIssueStage.h:45
llvm::mca::ResourceManager
A resource manager for processor resource units and groups.
Definition: ResourceManager.h:311
llvm::mca::LSUnit
Default Load/Store Unit (LS Unit) for simulated processors.
Definition: LSUnit.h:401
llvm::mca::StallInfo::isValid
bool isValid() const
Definition: InOrderIssueStage.h:48
llvm::mca::StallInfo::StallKind
StallKind
Definition: InOrderIssueStage.h:28
SourceMgr.h
llvm::mca::StallInfo::StallKind::REGISTER_DEPS
@ REGISTER_DEPS
llvm::mca::StallInfo::clear
void clear()
Definition: InOrderIssueStage.cpp:24
llvm::mca::InOrderIssueStage
Definition: InOrderIssueStage.h:54
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::mca::InOrderIssueStage::cycleEnd
Error cycleEnd() override
Called once at the end of each cycle.
Definition: InOrderIssueStage.cpp:424
CustomBehaviour.h
llvm::mca::StallInfo::StallKind::CUSTOM_STALL
@ CUSTOM_STALL
llvm::mca::StallInfo::update
void update(const InstRef &Inst, unsigned Cycles, StallKind SK)
Definition: InOrderIssueStage.cpp:30
llvm::mca::CustomBehaviour
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
Definition: CustomBehaviour.h:56
llvm::mca::StallInfo
Definition: InOrderIssueStage.h:27
Stage.h
llvm::mca::StallInfo::StallKind::DEFAULT
@ DEFAULT
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:686
llvm::mca::InOrderIssueStage::hasWorkToComplete
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Definition: InOrderIssueStage.cpp:56
llvm::ArrayRef< ResourceUse >
llvm::mca::StallInfo::Kind
StallKind Kind
Definition: InOrderIssueStage.h:39
llvm::mca::Stage
Definition: Stage.h:27
llvm::mca::InOrderIssueStage::isAvailable
bool isAvailable(const InstRef &) const override
Returns true if it can execute IR during this cycle.
Definition: InOrderIssueStage.cpp:60
llvm::mca::StallInfo::cycleEnd
void cycleEnd()
Definition: InOrderIssueStage.cpp:36
llvm::mca::RegisterFile
Manages hardware register files, and tracks register definitions for register renaming purposes.
Definition: RegisterFile.h:83
llvm::mca::StallInfo::IR
InstRef IR
Definition: InOrderIssueStage.h:37
llvm::mca::InOrderIssueStage::execute
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: InOrderIssueStage.cpp:199
llvm::mca::StallInfo::CyclesLeft
unsigned CyclesLeft
Definition: InOrderIssueStage.h:38
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::mca::StallInfo::StallInfo
StallInfo()
Definition: InOrderIssueStage.h:41
llvm::mca::StallInfo::StallKind::DISPATCH
@ DISPATCH
llvm::mca::StallInfo::StallKind::LOAD_STORE
@ LOAD_STORE
llvm::mca::StallInfo::getInstruction
InstRef & getInstruction()
Definition: InOrderIssueStage.h:46
llvm::mca::StallInfo::StallKind::DELAY
@ DELAY
llvm::mca::StallInfo::getCyclesLeft
unsigned getCyclesLeft() const
Definition: InOrderIssueStage.h:44
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::mca::InOrderIssueStage::getIssueWidth
unsigned getIssueWidth() const
Definition: InOrderIssueStage.cpp:52
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1195
llvm::mca::InOrderIssueStage::cycleStart
Error cycleStart() override
Called once at the start of each cycle.
Definition: InOrderIssueStage.cpp:382