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18 #ifndef LLVM_MCA_STAGES_DISPATCHSTAGE_H
19 #define LLVM_MCA_STAGES_DISPATCHSTAGE_H
50 unsigned DispatchWidth;
51 unsigned AvailableEntries;
60 bool canDispatch(
const InstRef &
IR)
const;
63 void notifyInstructionDispatched(
const InstRef &
IR,
87 #endif // LLVM_MCA_STAGES_DISPATCHSTAGE_H
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
This is an optimization pass for GlobalISel generic memory operations.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F)
Error cycleStart() override
Called once at the start of each cycle.
Statically lint checks LLVM IR
An InstRef contains both a SourceMgr index and Instruction pair.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Manages hardware register files, and tracks register definitions for register renaming purposes.
Lightweight error class with error context and mandatory checking.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Generic base class for all target subtargets.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.