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16 #ifndef LLVM_MCA_HARDWAREUNITS_REGISTERFILE_H
17 #define LLVM_MCA_HARDWAREUNITS_REGISTERFILE_H
40 unsigned WriteBackCycle;
45 static const unsigned INVALID_IID;
49 : IID(INVALID_IID), WriteBackCycle(), WriteResID(), RegisterID(),
73 return Write &&
Other.Write && Write ==
Other.Write;
93 struct RegisterMappingTracker {
98 const unsigned NumPhysRegs;
100 unsigned NumUsedPhysRegs;
105 const unsigned MaxMoveEliminatedPerCycle;
113 unsigned NumMoveEliminated;
116 bool AllowZeroMoveEliminationOnly;
118 RegisterMappingTracker(
unsigned NumPhysRegisters,
119 unsigned MaxMoveEliminated = 0U,
120 bool AllowZeroMoveElimOnly =
false)
121 : NumPhysRegs(NumPhysRegisters), NumUsedPhysRegs(0),
122 MaxMoveEliminatedPerCycle(MaxMoveEliminated), NumMoveEliminated(0U),
123 AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly) {}
144 using IndexPlusCostPairTy = std::pair<unsigned, unsigned>;
165 struct RegisterRenamingInfo {
166 IndexPlusCostPairTy IndexPlusCost;
169 bool AllowMoveElimination;
170 RegisterRenamingInfo()
171 : IndexPlusCost(std::make_pair(0U, 1U)), RenameAs(0U), AliasRegID(0U),
172 AllowMoveElimination(
false) {}
187 using RegisterMapping = std::pair<WriteRef, RegisterRenamingInfo>;
190 std::vector<RegisterMapping> RegisterMappings;
196 unsigned CurrentCycle;
217 void allocatePhysRegs(
const RegisterRenamingInfo &Entry,
222 void freePhysRegs(
const RegisterRenamingInfo &Entry,
229 void initialize(
const MCSchedModel &SM,
unsigned NumRegs);
233 unsigned NumRegs = 0);
270 unsigned PRFIndex)
const;
312 #endif // LLVM_MCA_HARDWAREUNITS_REGISTERFILE_H
This is an optimization pass for GlobalISel generic memory operations.
unsigned getElapsedCyclesFromWriteBack(const WriteRef &WR) const
bool tryEliminateMoveOrSwap(MutableArrayRef< WriteState > Writes, MutableArrayRef< ReadState > Reads)
void removeRegisterWrite(const WriteState &WS, MutableArrayRef< unsigned > FreedPhysRegs)
RAWHazard checkRAWHazards(const MCSubtargetInfo &STI, const ReadState &RS) const
const WriteState * getWriteState() const
MCPhysReg getRegisterID() const
WriteState * getWriteState()
An instruction propagated through the simulated instruction pipeline.
A register file descriptor.
unsigned getSourceIndex() const
unsigned getNumRegisterFiles() const
bool hasUnknownCycles() const
bool operator==(const WriteRef &Other) const
unsigned isAvailable(ArrayRef< MCPhysReg > Regs) const
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
A possibly irreducible generalization of a Loop.
Tracks register operand latency in cycles.
RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, unsigned NumRegs=0)
A reference to a register write.
unsigned getWriteBackCycle() const
bool canEliminateMove(const WriteState &WS, const ReadState &RS, unsigned PRFIndex) const
bool hasKnownWriteBackCycle() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isAvailable() const
Returns true if this register write has been executed, and the new register value is therefore availa...
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned getWriteResourceID() const
void onInstructionExecuted(Instruction *IS)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const
Manages hardware register files, and tracks register definitions for register renaming purposes.
void collectWrites(const MCSubtargetInfo &STI, const ReadState &RS, SmallVectorImpl< WriteRef > &Writes, SmallVectorImpl< WriteRef > &CommittedWrites) const
void addRegisterWrite(WriteRef Write, MutableArrayRef< unsigned > UsedPhysRegs)
Machine model for scheduling, bundling, and heuristics.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Generic base class for all target subtargets.
Tracks uses of a register definition (e.g.
void notifyExecuted(unsigned Cycle)
Optional< std::vector< StOtherPiece > > Other