LLVM  15.0.0git
MCInstrDesc.cpp
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1 //===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/MC/MCInstrDesc.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 
18 using namespace llvm;
19 
21  const MCRegisterInfo &RI) const {
22  if (isBranch() || isCall() || isReturn() || isIndirectBranch())
23  return true;
24  unsigned PC = RI.getProgramCounter();
25  if (PC == 0)
26  return false;
27  if (hasDefOfPhysReg(MI, PC, RI))
28  return true;
29  return false;
30 }
31 
33  const MCRegisterInfo *MRI) const {
34  if (const MCPhysReg *ImpDefs = ImplicitDefs)
35  for (; *ImpDefs; ++ImpDefs)
36  if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
37  return true;
38  return false;
39 }
40 
41 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
42  const MCRegisterInfo &RI) const {
43  for (int i = 0, e = NumDefs; i != e; ++i)
44  if (MI.getOperand(i).isReg() &&
45  RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
46  return true;
47  if (variadicOpsAreDefs())
48  for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
49  if (MI.getOperand(i).isReg() &&
50  RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
51  return true;
52  return hasImplicitDefOfPhysReg(Reg, &RI);
53 }
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Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:304
MCInstrDesc.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrDesc::isIndirectBranch
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:308
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:201
MCInst.h
llvm::MCRegisterInfo::isSubRegisterEq
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:568
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:32
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:200
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:285
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MCRegisterInfo.h
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::MCInstrDesc::hasDefOfPhysReg
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
Definition: MCInstrDesc.cpp:41
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrDesc::mayAffectControlFlow
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
Definition: MCInstrDesc.cpp:20
uint16_t
llvm::MCRegisterInfo::getProgramCounter
MCRegister getProgramCounter() const
Return the register which is the program counter.
Definition: MCRegisterInfo.h:442
llvm::MCInstrDesc::isReturn
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:273
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:207